IBM 25CPC710 Manuals

Page 1 of 8 Version 1.0 11/08/01 Abstract This Application Note describes the differences between the CPC710-100+ (DD2) and the CPC710 (DD3.x) versions of the PowerPC Dual PCI/Memory Controller companion chip. The purpose of this note is to provide designers with an overview of the changes and point out performance enhancements and potential programming changes. For a detailed understanding of the operation of the CPC710-133, please refer to the User’s Manual. For a detailed understanding of the physical pin out and electrical specifications, please refer to the Data Sheet. Overview The IBM25CPC710 DD3.x is a host bridge that interfaces a PowerPC 60x bus with system memory (SDRAM) and two independent PCI interfaces. It provides arbitration for one to four processors and supports up to two levels of pipelining per processor with 64-byte buffers (maximum of 6 buffers). Use of external slave devices on the 60x bus is also supported and requires additional external logic. The CPC710 DD3.x supports 60x bus speeds of up to 133MHz at 2.5V. Of course, given signal quality issues with higher bus speeds it is not recommended that the CPU bus run at 133Mhz in configurations that include more than 2 CPUs. The bridge’s two way interleaved memory controller supports SDRAM at 100 or 133 MHz; both single bank and dual bank, PC100, PC133 and registered DIMMs are supported. The memory controller design requires the use of an external multiplexer and two physical DIMMs. The bridge contains two PCI host bus bridges: one provides an interface for a 32-bit, 33 MHz PCI bus for standard and native I/O. This bus supports either 3.3V or 5V logic level devices, and allows attachment of up to 2MB of boot ROM (and up to 256MB of extended boot ROM). The other PCI interface supports a 32- or 64-bit, 33 or 66 MHz PCI bus for high data throughput, but supports only 3.3V logic level devices. This is a change from the previous revision. Burst and non-burst data transfers to memory from the PCI (bridge acts as target on PCI bus) and from memory to the PCI (bridge acts as master on PCI bus) are supported; data transfers directly between PCI-32 and PCI-64 are not supported. This is a change from the previous revision. A single channel DMA controller provides support for large data transfers between memory and the PCI busses. DMA to and from the CPU bus to memory, or between PCI-32 and PCI-64 is not supported. This is a change from the previous revision. IBM25CPC710 Bridge Chip: Enhancements and Changes in the DD3.x revisions November 8, 2001 Version 1.0 PowerPCTM Applications IBM Microelectronics Research Triangle Park, NC [email protected] http://www.chips.ibm.com