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Cat. No. W450-E1-06
1
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CP1H CPU Unit
3
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Unit Versions of CP-series CPU Units
6
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TABLE OF CONTENTS
11
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About this Manual:
15
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Read and Understand this Manual
19
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SUITABILITY FOR USE
20
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CHANGE IN SPECIFICATIONS
21
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Operating Environment Precautions
26
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Conformance to EC Directives
30
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Features and System Configuration
35
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Features and Main Functions
36
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for CJ-series Special
49
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When serial communications are req
50
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Maximum Normal I/O Points
52
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CP-series Expansion Units
53
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System Expansion with CJ-series Units
55
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Expansion I/O Units
56
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Restrictions on System Configuration
57
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■ Restrictions for the Ambient Temperature
58
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Connecting Programming Devices
59
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X and XA CPU Units
70
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Y CPU Units
71
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Functions Common to All Models
72
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Easy-to-read “Block Box”
74
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Nomenclature and Specifications
75
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Part Names and Functions
76
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DIP Switch for Operation Settings
82
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Maximum number of function block definitions: 128
84
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Unit version 1.0 and earli
85
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I/O Specifications for XA and X CPU Units
87
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Setting Input Functions in
88
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Interrupt Inputs and
91
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Transistor Outputs (Sinking or Sourcing)
93
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(1) The fuse cannot be replaced by the user.
94
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Analog I/O Specifications
96
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I/O Specifications for Y CPU Units
97
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High-speed Counter Inputs
99
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Special Pulse Outputs
102
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CP-series Expansion I/O Unit I/O Specifications
104
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■ Output Load Current and Ambient Temperature
106
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CP1H CPU Unit Operation
108
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CPU Unit Operation
116
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CPU Unit Operating Modes
121
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Power OFF Operation
123
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Computing the Cycle Time
125
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Installation and Wiring
137
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Installation and Wiring Precautions
139
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• To ensure safe access for opera
140
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DIN Track Installation
142
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Routing Wiring Ducts
144
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Wiring CP1H CPU Units
150
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Lower Terminal Block
159
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Example I/O Wiring for Y CPU Units
160
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Pulse Input Connection Examples
161
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Pulse Output Connection Examples
162
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Connection Example 2
164
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Analog Input Terminal Block
165
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CP-series Expansion I/O Unit Wiring
167
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I/O Memory Allocation
175
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Overview of I/O Memory Area
176
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I/O Area and I/O Allocations
184
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Built-in Analog I/O Area (XA CPU Units Only)
191
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Data Link Area
192
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CPU Bus Unit Area
193
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Special I/O Unit Area
194
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Serial PLC Link Area
195
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Internal I/O Area
197
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Auxiliary Area (A)
198
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Timers and Counters
199
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Data Memory Area (D)
202
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CPU Bus Units (D30000 to D31599)
204
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4-15-2 Precautions for Using Index Registers
209
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Limitations when Using Index Registers
210
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4-17 Task Flags
213
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Using the Condition Flags
214
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Saving and Loading Condition Flag Status
215
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Basic CP1H Functions
217
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Overview of CP1H Interrupt Functions
218
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Creating an Interrupt
219
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Input Terminal Arrangement
223
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Setting the Input Functions in the PLC Setup
224
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Scheduled Interrupt Interval Setting
231
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Writing the Scheduled
232
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Scheduled interrupt 2 is executed every 30.5 ms.
233
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X/XA CPU Units
235
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(All CP1H CPU Units)
237
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Contents of the
238
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New PV Setting in NV and NV+1
239
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Auxiliary Area Data
244
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Counter Input Modes
245
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Lower and Upper Limits of the Range
247
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Select high-speed counter 0 to 3.
249
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■ I/O Allocation
255
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■ PLC Setup
256
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■ Creating the Ladder Program
257
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Pausing Input Signal Counting (Gate Function)
260
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Pulse Frequency Conversion
261
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Pulse Output Specifications
264
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Pulse Output Modes
265
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Pulse Output Terminal Allocations
266
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■ Setting Input Functions in the PLC Setup
268
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■ Input Terminal Block Arrangement
270
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CIO 1 00
271
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Auxiliary Area Data Allocation (All Models)
272
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Stopping a Pulse Output
274
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Independent Mode (Positioning)
275
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tion and tar-
278
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Relationship between the
281
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Make the following settings in the PLC Setup.
285
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Changing the Pulse Output PV
288
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■ Limit Input Signal Setting
290
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Using Reversal Mode 1
298
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Using Reversal Mode 2
299
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Specifying the Origin
300
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Origin Input Signal
303
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Origin Search Examples
304
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CIO 100 00
305
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Moves the motor to the origin position from an
306
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SET PULSES: PULS(886)
312
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Bits 0 to 3
315
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0001 to FFFF hex (1 to 65,535 Hz)
316
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PV READ: PRV(881)
318
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PULSE WITH VARIABLE
319
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The following tables show when a second pulse c
320
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Restrictions on the PWM(891) Outputs
322
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Scheduled Interrupt Time Unit Setting
324
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Scheduled Interrupt Task 0 (Interrupt Task 2)
325
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■ System Configuration
330
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The system is returned to the original position.
334
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Palletize: Two-axis Multipoint Positioning
340
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■ DM Area Settings
344
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Positioning to C
347
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Limit Input Setting
350
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Feeding Wrapping Material: Interrupt Feeding
351
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Cyclic Task Program
353
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The quick-response inputs can read pulses with
354
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Analog I/O (XA CPU Units)
357
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The CP1H CPU Units support the following
372
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1:N NT links
373
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No-protocol communications enable sending and rec
374
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Message Frame Formats
375
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CPU Unit Serial Gateway Function Specifications
381
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Complete Link Method
385
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Related Auxiliary Area Flags for Serial Port 1
387
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Related Auxiliary Area Flags for Serial Port 2
388
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1:N NT Links
389
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Host Link Communications
390
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Host Link Commands
391
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CIO AREA WRITE
392
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Analog Adjuster and External Analog Setting Input
394
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7-Segment LED Display
396
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Memory Cassette Functions
400
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CPU Unit DIP Switch
412
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Failure Diagnosis Functions
415
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Auxiliary Area Flags and Words
420
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Analog Input Units
423
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Analog Output Units
432
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Analog I/O Units
440
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Temperature Sensor Units
463
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CompoBus/S I/O Link Units
478
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DeviceNet I/O Link Units
484
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LCD Option Board
491
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Installation and Removing
495
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Screen Transition Example in the Monitor Mode
498
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Displaying I/O Memory
500
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LCD Option Board Function
501
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Symptom at Power ON or during Operation
550
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Deleting EEPROM Error
551
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Ethernet Option Board
553
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Ethernet Option Board Function Guide
554
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Compatibility and Speed
557
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Devices Required for Cons
558
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FINS Communications Service Specifications
560
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Overview of FINS Communication Service
561
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Attach the label here to show IP address
562
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Comparison with Previous Models
563
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Installation and Initial Setup
564
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DM Area Allocation
573
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FINS/TCP and FINS/UDP Port Number
574
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IP Address Table
575
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FINS/ TCP Port Settings
576
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Web Browser Setup and Display
577
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9-11 Trouble Shooting
588
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No routing table entry (send
589
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01 to FE
590
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9-11-3 Error Status
592
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9-12 Sample Application
593
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CX-Programmer’s Change PLC Dialog Box
594
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Network Settings (Network Tab)
595
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Routing Table Settings and Transfer to Each PLC
597
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Program Transfer, Trial Operation, and Debugging
599
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10-1 Program Transfer
600
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Trial Operation and Debugging
601
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Error Classification and Confirmation
608
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■ Fatal Errors
613
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11-2-1 Error Processing Flowchart
614
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11-2-3 Fatal Errors
615
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■ Reference Information
616
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11-2-4 CPU Errors
620
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Errors Created with for FAL Instructions
621
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PLC Setup Errors
622
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Special I/O Unit Errors
623
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11-2-6 Other Errors
624
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11-3 Error Log
625
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Troubleshooting Unit Errors
626
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Inspection and Maintenance
629
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Replacing User-serviceable Parts
632
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Name and appearance
636
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CP-series Expansion I/O Units
637
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CJ-series Special I/O Units
639
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CJ-series CPU Bus Units
640
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Installation and Wiring Products
641
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X, XA, and Y CPU Units
643
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CP1W-CIF01/CIF11/CIF12 Option Boards
644
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CP1W-DAM01 LCD Option Board
645
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CP1W/CPM1A-MAD11 Analog I/O Units
648
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CPM1A-DRT21 DeviceNet I/O Link Unit
649
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Products Related to Using CJ-series Units
650
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CJ-series Special I/O Units and CPU Bus Units
651
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Auxiliary Area Allocations by Function
653
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Auxiliary Area Allocations by Address
673
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PLC Memory Addresses
719
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Connections to Serial Communications Option Boards
721
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Startup Hold Settings
747
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Settings: CPU Unit Settings
748
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Timings: Time and Interrupt Settings
749
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Input Constant Settings
750
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Serial Port 1 Settings
751
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NT Link (1:N): 1:N NT Links
752
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PC Link (Slave)
754
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Serial Port 2 Settings
755
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NT Link (1:N)
756
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Peripheral Service Settings
759
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Use high speed counter 2
760
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Interrupt Input Settings
761
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Origin Return Settings
763
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Pulse Output 1 Settings
764
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Pulse Output 2 Settings
767
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Pulse Output 3 Settings
770
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DA 0CH/DA 1CH: Analog Output Settings
773
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At start of operation
774
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FINS Protection Settings
775
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Specifications for External Power
777
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Specifications for External Power Supply Expansion
778
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absolute pulse outputs, 246
779
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pin 6 status, 619
780
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I/O Hold Bit, xxx
781
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related flags/bits, 625
782
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variable duty ratio pulse outputs
784
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Control Devices Division H.Q.
787
