Texas Instruments CLC520 Manuals

CLC520 CLC520 Amplifier with Voltage Controlled Gain, AGC +Amp Literature Number: SNOS861C CLC520 Amplifier with Voltage Controlled Gain, AGC +Amp General Description The CLC520 is a wideband DC-coupled amplifier with volt- age controlled gain (AGC). The amplifier has a high imped- ance, differential signal input; a high bandwidth, gain control input; and a single-ended voltage output. Signal channel performance is outstanding with 160MHz small signal band- width, 0.5 degree linear phase deviation (to 60MHz) and 0.04% signal nonlinearity at 4VPP output. Gain control is very flexible and easy to use. Maximum gain may be set over a nominal range of 2 to 100 with one external resistor. In addition, the gain control input provides more than 40dB of voltage controlled gain adjustment from the maximum gain setting. For example, a CLC520 may be set for a maximum gain of 2 (or 6dB) for a voltage controlled gain range from 40dB to less than 34dB. Alternatively, the CLC520 could be set for a maximum gain of 100 or (40dB) for a voltage controlled gain range from 40dB to less than 0dB. The gain control bandwidth of 100MHz is superb for AGC/ ALC loop stabilization. And since the gain is minimum with a zero volt input and maximum with a +2 volt input, driving the control input is easy. Finally, the CLC520 differential inputs, and ground refer- enced voltage output take the trouble out of designing DC-coupled AGC circuits for display normalizers; signal lev- eling automatic circuits; etc. Enhanced Solutions (Military/Aerospace) SMD Number: 5962-91694 Space level versions also available. For more information, visit http://www.national.com/mil Features n 160MHz, −3dB bandwidth n 2000V/µsec slew rate n 0.04% signal nonlinearity at 4VPP output n −43dB feedthrough at 30MHz n User adjustable gain range n Differential voltage input and single-ended voltage output Applications n Wide bandwidth AGC systems n Automatic signal leveling n Video signal processing n Voltage controlled filters n Differential amplifier n Amplitude modulation Gain vs. Vg 01275640 01275639 Gain vs. Vg Connection Diagram 01275629 Pinout DIP & SOIC May 2001 CLC520 Amplifier with Voltage Controlled Gain, AGC +Amp © 2001 National Semiconductor Corporation DS012756 www.national.com Ordering Information Package Temperature Range Industrial Part Number Package Marking NSC Drawing 14-pin plastic DIP −40˚C to +85˚C CLC520AJP CLC520AJP N14A 14-pin plastic SOIC −40˚C to +85˚C CLC520AJE CLC520AJE M14A CLC520 www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) ±7V IOUT Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... 60mA Common Mode Input Voltage ±VCC VIN Differential Input Voltage 10V Vg Differential Input Voltage ±VCC Vref Differential Input Voltage ±VCC Junction Temperature +150˚C Operating Temperature Range −40˚C to +85˚C Storage Temperature Range −65˚C to +150˚C Lead Solder Duration (+300˚C) 10 sec ESD (human body model) 500V Operating Ratings Thermal Resistance Package (θJC) (θJA) MDIP 55˚C/W 105˚C/W SOIC 45˚C/W 120˚C/W Electrical Characteristics AV = +10, VCC = ±5V, RL = 100Ω, Rf = 1kΩ, Rg = 182Ω, Vg = +2V; unless specified Symbol Parameter Conditions Typ Max/Min (Note 2) Units Ambient Temperature CLC520AJ +25˚C −40˚C +25˚C +85˚C Frequency Domain Response SSBW -3dB Bandwidth VOUT <0.5VPP 160 >110 >120 >120 MHz SSBW VOUT <0.5VPP (AJE only) 140 >90 >100 >100 MHz LSBW VOUT<4.0VPP 140 >85 >100 >100 MHz -3dB Bandwidth VOUT <0.5VPP SBWC Gain Control Channel VIN = +0.2V, Vg = +1VDC 100 >80 >80 >80 MHz Gain Flatness VOUT< 0.5VPP GFPL Peaking 0.1MHz to 30MHz 0 <0.4 <0.3 <0.4 dB GFPH Peaking 0.1MHz to 20MHz 0 <0.7 <0.5 <0.7 dB GFRL Rolloff 0.1MHz to 30MHz 0.1 <0.4 <0.3 <0.4 dB GFRH Rolloff 0.1MHz to 60MHz 0.5 <1.3 <1 <1.3 dB LPD Linear Phase Deviation 0.1MHz to 60MHz 0.5 <1.2 <1 <1.2 deg FDTH Feedthrough Vg = 0V, VIN = -22dBm -38 <-31 <-31 <-31 dB TRS Rise and Fall Time 0.5V Step 2.5 <3.7 <3 <3 ns TRL 4.0V Step 3.7 <5 <5 <5 ns TS Settling Time to ±0.1% 2.0V Step 12 <18 <18 <18 ns OS Overshoot 0.5V Step 0 <15 <15 <15 % SR Slew Rate 4V Step 2000 >1450 >1450 >1450 V/µsec HD2 2nd Harmonic Distortion 2VPP, 20MHz −47 <−40 <−40 <−35 dBc HD3 3rd Harmonic Distortion 2VPP, 20MHz −60 <−50 <−50 <−45 dBc Equivalent Output Noise (÷10 for input noise) (Note 3) SNF Noise floor 1MHz to 200MHz −132 <−130 <−130 <−129 dBm (1Hz) INV Integrated noise 1MHz to 200MHz 800 <1000 <1000 <1100 µV DG Differential Gain (Note 4) at 3.58MHz 0.15 % DP Differential PIase (Note 4) at 3.58MHz 0.15 deg Static, DC Performance SGNL Integral Signal Nonlinearity VOUT = 4VPP 0.04 <0.1 <0.1 <0.2 % Gain Accuracy Rf = 1kΩ, Rg = 182Ω GACCU For Nominal Max Gain = 20dB ±0 <±1.0 <±0.5 <±0.5 dB VOS Output Offset Voltage (Note 5) 40 <150 <120 <150 mV DVOS Average Temperature Coefficient 100 <400 – <300 µV/˚C CLC520 www.national.com 3