Roland SDE-1000 Service Notes

LED SLB-26URS RED (15029132) LEDSLB-26UR5 RED (15029132) pPot K1611008FE-100KB (13219361) LEDGL9ND2 Knob ORN RED/GRN (2247025900) (15029148) PHOTO SDE-3000 SPECIFICATIONS Button '(2247053700) LEDSLB-26YYHLYEL (1S029159) LED GL-9HD12 RED (15029152) L- LED SLB 26GG5F GRN (15029158) Display panel (2221071300) Button (2247054700) Control panel (2221031100) Button \ LED GL-3AR1 RED (2247054200) \ (15029110) Button Button Fluorescent display FIP16A5R (2247054300) (2247057700) (15029710) Button (2247054100) Power Switch SDG A 3P (13129124) Button (2247024000) Rear GND terminal (13459123) Rear panel (2221031300) Pot. EVH-6PA361B54 (13219214) Knob (2247023900) Jack HU 531701-100 (13449240) 6 \ Bushing BU4801 (12369511) Jack HLJ 531701-010 (13449238) ISDE-10001 Front LEDSLB-26YYHLYEL (15029159) LED SLB-26UR5 RED (15029132) Pot. K1611008FE 100KD (13219361) Knob ORN (2247025900) Pot. K1611008FE 50KB (13219360) Knob GRN (2247026000) Pot. K1611008FE 50KA (13219359) Knob BLU (2247026200) Button (2247054500) Jack HLJ 5317 01-030 (13449239) LEDGL-9HD12 RED (15029152) Button (2247053500) Switch SUF-12 (13129338) Display panel (2221071400) LED SLB 26GG5F GRN (15029158) Pot. K1611008FE 50KB (13219360) Knob YE L (2247026100) Pot. K1611008FE 50KB (13219360) Knob BLU (2247026200) Button (2247053700) Button (2247053800) Fluorescent display LED GL-3AR1 RED FIP5A8B (15029110) (15029709) \ \ Conrol panel (2221031200) Power Switch SDGA 3P (13129124) Button (2247024000) Button (2247054000) Rear GND terminal (13459123) Bushing BU4801 (12369511)

M4 internal tooth 3x8 BLK binding 3x6 BLK binding 4x12 BLK oval 3x8 BLK binding f 4x12 BLK oval (1000): SDE-1000, (3000): SDE-3000 Control panel 2221031200 2221031100 -Display panel 2221071400 2221071300 -Fluorescent display 15029709 FIP5A8B 15029710 (4)-Switch board 7411608005 7411708005 (s) -PCB holder 221903JB01 Q*y~ Button assembly 2247090300 2247090100 FIP16A5R (1000) (3000) (1000) (3000) (1000) (3000) (1000) (3000) (1000) (3000) &■ ^7 J—Button assembly 2247090200 Button BLK 2247024000 •-Cushion 2226022200 (jo}-LED holder 2219031900 ^Jy-Joint A 2215040100 (12)— Connection rod 2214020700 (m- Joint B 2215040200 (i4)— Line cord strain relief 12369410 1702B (3000) -Main board 7411606032 7411706026 'li 5}-Push switch 13129338 -Button WHT 12470514 -Push switch 13129337 -Push switch 13129124 --Power board 7411609000 7411709000 • - Insulation sheet 2216052701 --GND terminal 13459123 SUF-12 SUE-12 SDGA3P

(pcb 2291058201) (pcb 2291058300) (pcb 2291058400) (pcb 2291057901) (pcb 2291058000) (pcb 2291058100) (pcb 2291058500) Fuses, Fuse labels, capacitor Cl excluded. Specify model and line voltage when ordering for complete assy. RAM board (pcb 2291083800) Analog SW board (pcb 2291091900) Substitutive for HI-302 and HI-303. No replaceable part. See P.20. (SDE-1000) (SDE-1000) (SDE-1000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) POTENTIOMETER 13219361 13299101 K1611008FE 100KB EVT-R4SA00B14 trimmer

CPU 64K D-RAM Transistor array 7-Segments decoder Quad 2 Input NOR Quad 2 Input NAND Inverter Dual D-Flip-Flop Comparators Voltage detector LED Driver OP Amp OP Amp Three Terminal Voltage Regulator Hex O.C. Inverters Hex O.C. Buffers VCO Compandor OP AMP Analog Switch Three Terminal Voltage Regulator Quad 2 Input NAND Dual D-Flip-Flop 2 to 1 Data Selectors 4 bit Binary Full Adders Dual D-Flip-Flop Triple 2-channel Multiplexer Dual Voltage Comparator D/A Converter Quad Analog Switch Dual Analog Switch Dual Analog Switch OP Amp OP Amp VCA 4 to 16 Line Decoder (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) 15019125 15019251 15019236 15019525 15029132 15029159 15029158 15029152 15029110 15019103 15019557 15019209T0 15029148 15029111 150192490X 1SS-133 1N4007 W-02 RD5.6EB-2 SLB-26UR5 SLB-26YYHL SLB-26GG5F GL-9HD12 GL-3AR1 1S-2473 RD15EB-3 S5500G GL-9ND2 GL-3PG1 KV1226X or KV1226Y (150192490Y) Rectifier Bridge Zener LED RED LED YEL LED GRN LED RED LED RED Zener LED RED/GRN LED GRN Varicap (SDE-1000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000)

Polypropylene ±1% (SDE-1000) set of pair, selected (SDE-1000) Polypropylene ±1% (SDE-3000) Tantalum bead (SDE-3000) Electro (SDE-3000) Electro (SDE-3000) Bi-polar, electro (SDE-3000) OTHERS 12389718 PX-1 11.0MHz Xtal 2216031201 Insulation spacer (vinyl sheet) 2216052701 Insulation sheet (fibre, L-shaped) 2214020700 Connection rod 2215040100 Joint A 2215040200 Joint B 13439127 Connector housing 5045-11A IIP .13439157 Connector housing 5045-13A 13P 2341043200 Connector wiring assy IIP 2341043300 Connector wiring assy 13P 12569111 CR1/3N 3V Lithium Battery 2226022200 Cushion 2225021001 Shield board (metal, L-shaped) 2225021100 Shield board (metal, flat) 2225011200 Shield sheet (foiled paper) 2216031300 Insulation spacer (vinyl chloride) 13439120 Connector housing 5045-04A 4P 13439123 Connector housing 5045-07A 7P 13429143 Connector-housing EMC-S0760 7P 2341017100 Connector wiring assy 4P 2341018000 Connector wiring assy 7P 2341030700 Connector wiring assy 7P 2225021501 Shield board (metal, U-shaped) 13439125 Connector housing 5045-090A 9A 13429145 Connector housing EMCS0960 9P 2341043400 Connector wiring assy 9P 2341030300 Connector wiring assy 9P 13439514 Connector PS-30 SD-S4TS1-1 30P female 13439516 Connector PS-30 PA-S4T1-A1 30P male 2215050900 Spacer 13mmL HEX threaded 13459123 GND terminal 12369511 Cord bushing BU4801 12369410 Line cord strain relief 1702B PS board LED board SW board LED board (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-1000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000) (SDE-3000)

audio signals are stored by means of PCM (Pulse Coded Modulation) method. The delay unit first samples the input audio signal to have a series of discrete values of the signal amplitude at point. Each of sampled pulses is digitalized and stored into RAM cells as a binary coded data which, when a specified time passed, is read, restored to analog value, then injected into audio path as a delayed signal. The process can well be compared to that of conventional tape echo machine as shown in Fig. 1. RAM cells correspond to the tape and the RAM accessing to a Record/Play back head. In operation R/P head first functions as a playback head and will read a group of RAM cells being in touch with, then quickly changes to a recording head to record digital data being fed from the A/D converter into the same cells. The head steps to the next cell group and repeats the read and write opera tions, then to the third, fourth and so on continuously until the time deter mined by DELAY TIME button comes. When the delay time has passed, the head leaves the remaining cells unused and jumps to the first cell group where it reads the previously stored data and writes the new data. The number of cell groups the head can see is based on DELAY TIME setting and the travel ling speed of the head slows down one-half when in TIME X2 mode. In other words, the length of the tape varies with Delay Time and the speed with Delay Time Range (also X1—X1.5 setting and MOD rate). The following description breaks major circuits down into Analog and Digital, starting with SDE-1000 circuits most of which are also found in SDE-3000, then goes through the circuits featuring SDE-3000. One major difference be tween two models are their time delay ranges: SDE-3000 four times the SDE- 1000 in RAM memory capacity. RAM MEMORY CELLS SDE-1000 See P. 13 for SDE-3000 Fig. 1 HEAD AMP The Head Amp interfaces the unit wih a variety of input signals so that the unit can operate with adequate signal * noise and without execessive limiting across the dynamic range of the signa Although this amp has a gain range of 1 to 24, VR-6 (INPUT ATT) attenuass the delay signal as it is rotated from FCW position to CCW. The unit's overll gain is unity at FCW. NOTE: Minor modifications are madeon SDE-1000 head amp and associated circuits to provide more headroom without sacrificing tonal quality and sound level. Refer to Engineering Chage in SDE-1000 section in this manual. FEEDBACK/MIXING The delay signal is mixed again with aiew direct signal when 0V is placed on Q51 gate, and out of the delay line whn -14V is on the gate. PREEMPHASIS This stage boosts higher frequency corents to provide a good S/N ratio. GAIN: unity at 1kHz and 2.5 at 10kH INPUT jack 1 kHz TP-2 TIME X2 OFF TP-2 TIME X2 ON 0.2 ms/div LPF-1 An 'Anti-aliasing filter including tw filters of different cutoff point. Only one filter is connected to the next stge at a time. Pressing TIME X2 switch causes the Control Logic (IC14, etc to place a ground to the gate of 027 and -14V to Q28, limiting the filir's output bandwidth within 10Hz- 8kHz. Disengaging the X2 switch corlucts Q28 and cuts off Q27, extending the bandwidth to 17kHz. Control Lgic also cuts off both FETs for 7 sec after power is first applied to the un; and during HOLD ON mode or while Delay Time button is manuplated. * Aliasing — The type of distortioi that is found in "sampled" signal pro cessing system when the signal has frtjuency components which exceed half the sampling frequency. COMPRESSOR This stage logarithmically reduces trudynamic range of the signal before it is digitalized. NOTE: For detailed descriptions olS/H, A/D, D/A, Main Controller and RAM, see corresponding sections in S E-3000 description. SAMPLE & HOLD ICs 5A and 5B, together with C13 extract a portion of the input signal at SAH rate. The sampled audio is fed through Q8 to pin 2 of IC2 where it is compared with 12 step voltages on pin 3 to have its analog voltage repre sented by digital code through A/D conversion. NOTE: SAH rate is constant regardless of DELAY TIME setting, but varies when TIME X2, DELAY TIME X1/X1.5 or MODULATION is enabled. A/D CONVERTER The A/D Converter employed here is of Successive Approximation consisting of SAR (Successive Approximation Registers in IC12, Main Controller), ICs 3 and 4 which boost TTL compatible to 12V, RM-1 ladder resistor which adds a corresponding analog weight to individual bit, Q9 and Q10 follower and comparator IC2. In operation, SAR first sets the highest bit (MSB) register to H (1) whose output is, after given the highest voltage at RM-1, compared with sampled audio at IC2 input. If MSB is larger than the sampled audio, it is reset to L(0) by a H from IC2 (D IN). If smaller, kept set and applied once more together with the second highest bit register output (H) that is one-half the highest in voltage. The process repeats for MSBs while the combination of SAR outputs is approaching to the sampled audio level. During the process, D IN is also transferred to RAMs IC9-IC11 to record H or L of all the bits which, when grouped into 12 bits, are the data of the sampled portion of audio input signal.

system serve as D/A converter. RAM stored 12-bit data is transferred in time sequence (3 bits parallel x 4 times) from each RAM OUT pin to IC12 where they are so arranged that they are fed simultaneously via D11-D10, ICs 3,4, RM-1, Q9 and Q10 to S/H IC5C and IC5D. EXPANDER One half IC15 NE570 exponentially amplifies delayed audio to restore it to the original dynamic range. LPF-2 The configuration analogues to LPF-1, providing 19kHz bandwidth when Q48 is ON, or 9.5kHz when Q49 is selected by TIME X2 switch. Being an interporating filter, it smoothes staircase-like out of the waveform. As just for LPF-1, mute signals are applied from Control Logic IC14. DE-EMPHASIS IC29 and associated components reduce higher frequency components in the delay line to compensate for preemphasis, restoring the overall frequency res ponse to flat. PHASE SELECTOR Q45, when conducted, change IC28 into an inverter, reversing the delay out put phase with respect to the direct signal. DELAY PHASE "OFF" INPUT MIXED OUT jack INPUT MIXED OUT jack DELAY OUT (VR4) at CENTER MAIN CONTROLLER IC12 63H-101 a specially designed gate array for controlling digital delay system. It clocks most of delay related sequences such as A/D, D/A, S/H, RAM accessing, etc. in time with clocks generated at the internal timing gene rator which in turn is clocked on MSCK delivered from CLOCK Generator IC23. With TIME X2 button activated IC12 has an H on RNG 1 pin and slows down all timing sequences by one-half except REFRESH cycle. The clock fre quency can be varied by the external voltages to be applied on FC pin or PA pin. As the name implies, IC12 Main Controller is the heart of the Delay Line. All the delay circuits will not work correctly should the Main Controller fail to receive adequate clocks from IC23. IC12 PIN DESCRIPTION SAH & RNG 1 SAH determines the rate of sampling being performed at IC5 which gates on a high SAH. When TIME X2 is engaged, RNG 1 turns from L to H, lengthening SAH intervals from 22.9/is to 45.8/us DIN D IN accepts a series of H or L from the comparator IC2, resetting register(s) in SAR on H to omit it from the subsequent comparisons. DOUT These Hs and Ls on D IN are also transferred to RAMs (IC9-IC11) and stored as a set of 12-bit data which represint the amplitude of a portion of input signal (sampled audio) being fed to I(2 pin 2. D0-D11 During A/D conversion cycle these pins represent comparison data from internal SAR. During D/A cycle, sinultaneously output 12-bit RAM stored data which have been read from eaci RAM in time sequence (3-bits x 4) and temporarily buffered in internal threi registers. A0-A7 These pins feed RAMs with addresses: Refresh, Row and Column. Since the number of RAM cells involved in data storage is varied with DELAY TIME setting, the numbers of Row and Column addresses are also changed accord ingly while Refresh addresses are issued for all the RAM cells. RS(RAS) 16 Falling edges of RAS (Row Address Strobe) enable each RAM to latch Row address (W/R cycle) or Refresh address into its designated cells. CAS1-CAS3 RAMs IC9—IC11 latch Column addresses on negative edges of cocurrent Column Address Strobes (CAS1CAS3) which also serve as Chip select, and read memory cell respectively. The data read are routed to the RAM D OUT (pin 14) while related CAS is low. DATA & SHI FT (SIFT) As mentioned in general descriptio, RAM cells used for sound memory received at SHIFT rate. The DATAIs a serial stream of 16 bits and'vti change between: , 16 bits—, MSB LSB 0000 000 at 0ms setting am 0011 111 at maximum settg 11 (SDE-3000) The DATA/SHIFT are transmit^ only after DELAY TIME or PRESf button is released. The DATA is accompanied by sevel mute signals to cancel unwantl signals. MUTE A: active low when DEL/ TIME button is mai- plated. MUTE B: active low while PREST is pressed. To shorten the Mute periods, TIC X2, MOD., and X1.5 are disabled. CPU . (IC21) IC17 P20(DATA) P21 (SHIFT) P22(X1.5INH) P23 (MUTE A) ^ P23 (MUTE B) Q2(TIMEX2) - Q4 (MOD) Interruption(s) for Switch scan and LED/numerical displays. MINIM L TIME/MEMORY DELAY TIME DATA

IC12 (SDE-1000)/IC31 (SDE-3000) CO CO A A CO CO CO CM CO If) 00 in s CO in in in CO in CM in — o in in 5 00 t A TIMING GENERATOR DIVIDE BY 216 A CM A g V in u o V CO (O 00 CO CO CO DATA SELECTORS DATA SELECTORS ***REHASH COUNTER ck PRESETTABLE ADDRESS COUNTER *>ck ADDRESS COUNTER t T T T T T f T T T T T T DATA SELECTORS SHIFT REGISTERS ck D-FLIP-FLOPS in CO A 5 CO CO A i RAM BANK SELECTOR SET CO O) A CO SEL DATA SELECTORS V oo o q V Q V o CM CM CM CO CM in CM G V oo CM CM Q V 8 CO CM CO

IC12 (SDE-1000)/IC31 (SDE-3000) MSCK SAH DIN D 11 D10 D 9 D 8 D 7 D 6 D 5 D A D 3 D 2 D 1 D 0 DOUT A0-A7 R/W MODEt RS16-64 J REFRESH MODE-i RS16-64 J CAS 1 CAS 2 CAS 3 I I I R/W MODE-i wr -I RAM 1 RAM 2 RAM 3 DB 0 -l OFFSET DAT/ DB 1-1 «*»«** DB 2 RASFORCOMfWCINQRAM DB 3 CAS FOR OOMPWCING RAM DB DB 5 DB 6 DB 7 R/W MODE RS16-64 REFRESH MODE RS16-64 DB 2

The frequency of Clock Generator is as follows (approx): 2.7MHz at Normal 1.7MHz at TIME X1.5 2.7M-3.3MHZ at MOD max. 1.7M-2MHz at TIME X1.5/M0D max. MSCK - Clocks the internal Timing Generator that times the most of digital circuits. HDCK - The frequency of HDCK is MSCK or 43Hz at normal mode. Used by the CPU as a time base for calibrating Delay Time display. The CPU fails to read switches and jacks if HDCK period is outside 7m-50ms. RAM 1-RAM 3 12-bit data read from three RAMs are fed through these pins to internal three shift registers for temporary storage. All the buffered bits are placed on D0-D11 at a time to form a 12-bit parallel data to be applied to D/A con verter for reproducing a part of delay signal. During HOLD ON the A/D converter remains active but cannot receive input signal. The comparator output is inhibited from being written into RAMs. CONTROL SIGNALS IN DIFFE RENT MODES RAMs(IC9-IC11) Record the results of Successive Approximation, from MSB (D11) to LSB (DO), sharing 12 bits - 4 specific bits for each as shown in the table at the beginning of General Description. CPU The CPU is provided with a battery backup to retain switch, delay time and preset settings. TO - Decides the operation mode of the CPU: +5V-- 0V-- SDE-1000 - SDE-3000 T1 — Receives Clock pulses through IC12 HDCK pin. The clock serves as a time base to enable the CPU to calibrate Delay Time Display and is ignored by the CPU when Modulation is ON and MOD Foot control jack disengaged. (See HDCK, Main Controller.) P20 (DATA) - Send memory access control data after every delay time P21 (SHIFT) - settings (see DATA/SHIFT, Main Controller). P23 - P10 - P11 P12 - P13 - P14 - P15 P16 P24 P2'7 DB7 DBO DB3 DB4 - DB5 NOTE: Becomes "L" for muting. (See timing chart in DATA, SHIFT, Main Controller.) Read SW1-SW10 through the matrix in combination with P24- P27 and DB7. Input from PRESET SHIFT jack. A rising edge of this input steps PRESET memory. MODULATION FOOT CONTROL jack input. With MODULATION ON and this input at low, CPU ignores T1 input. For example, rotation of DELAY TIME X1-X1.5does not change TIME display. HOLD jack input. When H, readings of TIME UP or DOWN and PRESET memory are inhibited. PLAY MATE jack input. Active rising edge. Rising edge from this pin latches the following logic codes made by DB0-DB3 into Analog Control IC17. TIME X2, DELAY PHASE, MOD and FEEDBACK Output of switch scan signals which are read through P10 and P11. Besides Control signals for IC17, these pins deliver numerical data to fluorescent display via IC18 7-seg-decoder. DB6: Dot Point signal. Send LED lighting signals. When P10, P11, P12 and P15 pins receive signals almost at the same time, the CPU gives priority to the signal first read. Example: PRESET SHIFT and Front Panel switches are disabled when PLAY MATE has been activated. 10

illlllillll Hill Iflttliliiillil— CORRECTION PAGE 10 MSCK, HDCK & CLOCK GENERATOR The frequency of Clock Generator is as follows (approx): 2.7MHz at Normal 1.7MHz at TIME X1.5 2.7M-3.3MHz at MOD max. 1.7M-2M MSCK — Clocks the internal Timing Generato MSCK times the most of digital circuits. ^ "' i i HDCK - The frequency of HDCK is\M^J>br 43Hz at normal mode. Used by the CPU as a time base for calibrating Delay Time display. The CPU fails to read switches and jacks if HDCK period is outside 7m-50ms. Switch KBF1O9O6(13169621) SDE-3000 7411708005 o rr~i r~n i i i [ i i m

For other circuits not described, refer to those in SDE-1000. HEAD AMP Has a gain range of 2dB(1.26) to 30dB(31.6). DELAY OUT/PHASE SELECT This stage has 9.9dB gain. When TR78 is conducted, the delay out is 180° out of the direct signal. MIXED OUT Changes its gain with UNIGAIN settings: 7dBwithUNIGAINat +4dB -3dB with UNIGAIN at -20dB CVIN Level shifts 0 to +12V inputs to ±4V. INV OUT Level shifts ±4V inputs to 0 to +12V. MOD DEPTH Controls the amplitude of CV from CV IN or LFO with 0 to +5V coming via IC27Afrom RM8.. CV LINEARIZER The output voltage at IC49A pin 1 is normally 0V. Has a unique voltage response curve to compensate for nonlinear V/C charac teristic of D62 varicap in VCO circuit. IC31 MAIN CONTROLLER DBO, DB1 Address offset data fx companding RAMs. (See COMPANDING RAMs.) DB4 Strobe . Latches data from companding RAMs into IC32 on rising edge. DB5, DB6 Signals D/Aor A/D cycle. Cycle DB5 DB6 D/A H L A/D L H DATA COMPANDING Audio signals are digitalized with a 12-bit Analog to Digital Converter before stored into RAM. In ordinary D/A conversion, the number of significant digits decreases as input signal level decreases, lowering relative resolution. The reason is well illustrated by comparing A/D system to a voltmeter. Suppose the voltages ranging from IV to 100V are read with 100V scale, smaller voltages cannot be read accurately. The meter has to be switched down to lower ranges to allow the pointer stay around the middle of the scale. The same concept, named companding, is applied to SDE-3000 A/D conversion circuits. Companding Input Signal Q Peak Hold IC2, IC3 Comparator IC6, IC7 isr ■ RAMs IC1 I IC12 Companding RAMs IC41 IC43 Fig. 2 The ideal companding system will work as follows: With 100V, 10V and IV input applied to the comparator (IC8) at different time, the D/A converter outputs the same successive voltages which are attenuated by IC10 by 1, 10 and 100'respectively before comparison. Conse quently, the A/D converter has a higher resolution 100 times that of direct conversion at 1V input. The same procedure takes place, when RAM stored data are D/Aed as a delay signal, to correctly restore the voltage to the origi nal level. Examples of companding effects are shown in the photos below. Note that waveforms at TP-1 will change drastically as the input varies in level, especially at a border of ranges where companding system works even for one waveform cycle of low frequencies. These phenomenons should be made familiar to the eye of observer to avoid misjudging. INPUT 100Hz TP-1 5V/div ■ A/D cycle - D/A cycle (RAM stored data) INPUT 40Hz, +5dBm IC8 pin 2 2V/div TP-1 10V/div 5ms/div INPUT 40Hz, +5dBm IC8 pin 2 2V/div TP-1 10V/div 5 /is/div 11

The positive and negative peaks of a samped signal are peak-held and detected at IC6 and IC7 respectively, resulting in a logic code as shown in the table below. The code is latched into IC33 at SAH rate, passes through IC34 (data selector) on "L" DB5 (A/D cycle), and through ICs 35C and D and reaches pins 6 and 9 of IC10 D/A attenuator. IC10 switches ON or OFF its analog gates to provide for correct D/A output level. This logic code is also sent through IC33 to companding RAMs IC41 and IC43 while A/Ded input signal data is sent from comparator IC8 to RAM board via IC31. In other words, audio input is stored into two locations with different information separated—meter's pointer deflection reading into IC1— IC12 on the RAM board, and meter range into companding RAMs. COMPANDING RAMs (IC41 and 43) As shown in the Main Controller Timing Chart (see RAM1-RAM3) and RAM table, A/D data for a sampled signal is stored into three RAMs (in the same R'S section) four times starting from MSB 3 bits (D11-D9). On the contrary, companding data is stored into IC41 and IC43 once for the signal. However, since the same addresses are used for both RAM groups, companding RAMs cannot make use of the remaining three addresses if suit able modification is made on them. IC31 issues address-offset data from DBO and DB1 to IC38 and IC36 (Address Adder) which adds 0 to 3 as the memory banks change from RS16 to RS32, RS32 to RS48 and so on. INPUT 100Hz IC41 (IC43) DIN TP-1 1C41T1C33) DOUT When in delay mode (D/A cycle, IC31 DB5=H and DB6=L), companding data is latched into IC32 on rising edge of DB4, selected by IC34 (pin 1=H), gated by IC35C and D, then routed to IG10. With this companding data applied IC10 determines the range of analog voltage from D/A converter IC15 and IC14, restoring RAMs (IC1-IC12) stored data to the original signal level. RAMs IC1-IC12 on RAM BOAHD As mentioned earlier, during success ve approximation of a sampled signal, comparison results are stored into th ee RAMs, being designated by RS-, in 3 bits parallel x 4 serial format to represent the signal in 12 bit data. RAMs used for storing are always from those in RS16 (ICs 12, 8 and 4) to RS64 (ICs 9, 5 and 1) depending on delay title settings. In short delay settings those RAMs of RS16 are repeatedly used while those in RS64 are left out of storing. This concept becomes important when troubleshooting RAMs. (Refer to the table on P.13). CONTROL SIGNALS IN DIFFERENT MODES Irrelevant to Power-ON mute sue as MUTE A and MUTE B. All "0 ing Power-ON MUTE periods. dur DIAGNOZING DELAY SOUND - Isolating Defective RAM - ►For SDE-1000, see para. 5 and 6. ►Also see P.22 for failure examples. When a trouble is found in the delay sound, the circuits first to be checked will be those shown in the block diagram (Fig. 2, P.11). They are closely related to each other. Of these, companding circuit effects to both A/D and D/A conversions and the D/A converter becomes a part of A/D converter during A/D cycle. However, the most difficult to point out is a RAM since 14 RAMs are involved in the delay line. Consequently, this section describes fault isolation procedure on the assumption that a specific RAM is defective. Before going into RAM sections, other related circuits must be checked for proper function. These checkings also give hints for troubleshooting associ ated circuits. NOTE: The number of RAM cells engaged in sound delay are dependent on delay time and the level of input signal while companding circuit acts with changes in input sound level. Unless otherwise directed DELAY TIME should be set at the longest and the input signal level varied widely when checking. USE MONITOR for help checking irregular sound. 1. BRIEF CHECKING With relatively large signal applied to the unit's input jack, observe TP-1 (IC14 pin 6); Adjust the scope to display the waveform similar to that in the photo below. Check steps of A/D cycle traces for 1/2-changes in voltage. If not, widely vary the input level and check whether companding circuit is ill affecting. When A/D conversion seems defective, proceed to para. 5. 2. DISCONNECTING COMPANDING CIRCUIT Companding circuit affects to both A/D and D/A converters. Disconnect the companding when checking the both circuits. a. Disolder and remove the ground lead of R165 connecting to pin 6 of IC10. b. Jumper wire across pin 6 of IC14 (TP-1) and pin 2 of IC8 to bypass IC10. If companding circuit seems defective, proceed to the next para. 12

TP-1 Freed from comDandinq effect 3. COMPANDING CIRCUIT When companding circuit seems malfunctioning, track the logic code from peak hold output to IC10 (see the table in "Peak Hold and Comparator" in the Circuit De scription, SDE-3000). During a tracking the input signal must be set at a level for unchanged code. Then change input level for another logic code. Verify the identical code throughout A/D and D/A cycles. If a difference exists, check RAMs IC41 and IC43. 4. ISOLATING RAM GROUPs (RS16-RS64) When delay time at which defective sound is reproduced is determined, it is easier to point out the RAM group containing the ill cell by referring to the table on the right. The DELAY DISPLAY can be a great help to measure the time when abnormal sound occurs on the border of two RAM groups. a. With MODULATION OFF, set TIME to the maximum. b. Adjust DELAY TIME (X1-X1.5) on the rear panel for 1600ms display. c. With MODULATION DEPTH "0", push MOD to ON. d. Re-set TIME to around suspective time. For example, if a noise pops closely at the middle of the delay time, set TIME for 800ms. If the noise disappears, failure may be located anywhere in a RAM of RS48. Some errors may exist in relationship between the delay time and the RAM address increment (+1ms). In this critical case, refer to the next para. It is difficult to detect failure in lower bits, also proceed to the next para. 5. ALL "1" & ALL "0" CHECKS Using sine wave as a test signal has adverse effects, that is, data in conversion system, RAM memory, etc. vary status from time to time as the input changes in level. When DC voltage at constant level is applied as an input signal, these data bits will stay at "1" or "0" at least for a certain period. P.B.HJR.H. READ/ WRITE POINTER RS 64 18k WORD RS 16 16k WORD I IC36. IC38 Companding RAMS IC41. IC43 RS 32 16k WORD A/D staircase must step by 1/2 in amplitude. If not, or uncertain because of lower bits, check suspective bit(s) onD11-D0of IC31. The waveform (and sound) will be disturbed at the moment when defective bit is reproduced. Check for jitter or glitch (pulse) at TP-1. If doubtful, proceed to para 6. 6. PINPOINTING DEFECTIVE RAM Set DELAY TIME for 1600ms (see para. 4). Feed D IN of IC31 with +5V or 0V (para. 5). Connect scope to the bus of RAMs including suspective RAM. If the RAM is not defined yet, may have to be re peated for the other 2 buses. For confirmation, first disconnect suspective RAM's D OUT by cutting off the pattern to the bus, then observe the RAM D OUT directly. Ideally, this can be accomplished by applying DC volt ages (of max. or min. that can be accomodated by A/D system) to the input of the comparator IC8. Alternative to this is pulling up or down of D IN (IC31 pin 31). a. Disconnect D42 cathode from TR97 (circuit dia. F-22). b. A staircase "A" as shown in the figure will be seen at TP-1. c. Connect a length of wire to D42 anode (or DIN of IC31) and touch the other end of the wire to ground point. A reversed waveform "B" will appear. D/A cycle is also inverted when the delay time comes; its amplitude being equal to that at the end of A/D cycle. Oil ,D10.D9, 08. , 06 , D5 , D4 , D3 . D2 , Dl DO 13

Earier SDE-1000's have factory-modifications on INPUT Switch, Head Amp, Expander and Compressor as shown in the table below. The modifications add the following features (one by one) to the unit when it is used with UNI- GAIN set in -20dBm. * Greater Delay circuit headroom with better balance of Direct/Delay sounds in volume. * Higher frequency response of the Delay line. * Greater S/N ratio in Delay sound. When need arises to implement one o1 the aboves to a given unit with serial number prior to 374800, the final values in the bottom of list should be ap plied since these improvements closely elate to each other. Exceptions are R271 and R272 whichcan be solely implemented for reduc ing noise from compander. NOTE: Changed parts are mounted ii place on the parts side of the PCBs of 2291058202 and subsequent versions. LOCATIONS R39, R42(SW1 A) R45(SW1B)/R108(IC8)/R224, C114(Q55) C124(VR6-SW1A) R40(SW1C)/R145, R272(IC15 pin 5)/ R271(IC15pin 12) C48(Q13-Q18) R1890C30 pin 2)/R260(Q57)/R58, R6KQ18-JK3) Cut pattern here and bridge with 1k (R272) Cut pattern here and bridge with 1k (R271) 14

1-1. Set UNIGAIN (Rear panel) to -20dBm. 1-2. Connect audio generator (AG) to INPUT jack and set AG for -20dBm, 1kHzf sine. 2. DELAY TIME 1-3. Set RT8 at the point where +3dB LED just com pletely fades out. MVTATT FEEDBACK DELAY OUT SRoland -OFF 2-1. Set DELAY TIME (VR1, Rear panel) to XI. 2-2. Press and hold DELAY TIME button until DELAY TIME display reads maximum value. 3. COMPRESSOR LEVEL LINEARITY 2-3. Adjust RT6 for 379 ± 1ms reading. 2-4. Repeat step 2-2. If the reading changes, readjust RT6for379±1ms. WUTATT FEEDBACK 06LAV OUT (BRoland -OFF 3-1. Set DELAY TIME (Rear panel) to X1 and UNI GAIN to-20dBm. 3-2. Connect AG to INPUT jack and set for -10dBm, 1kHz, sine. 3-3. Adjust DELAY OUT (VR4) for -10dBm reading. 4. COMPRESSOR TOTAL HARMONIC DISTORTION 3-4. Reset AG to -60dBm. Adjust RT1 for -60 ± 0.5dBm reading. 3-5. VR4 and RT1 interact Repeat from 3-2 through 3-4. TEST POINT: TP2 (connect to oscilloscope - - DC coupling) 4-1. Set DELAY TIME to X1 and UNIGAIN to -20 dBm. 4-2. Connect AG to INPUT jack and set for 1kHz, sine, burst tone (4-0-4 cycles). Adjust AG output level so OFF that the first bottoms (a) are at +1V on the scope. 4-3. Adjust RT2 for straight DC level. 4-4. Set scope V IN to AC coupling. 4-5. Repeatedly rotating INPUT ATT over its full travel, fine adjust RT2 for minimum DC drift. Adjust scope VAR as necessary. SDE-1000/3000 6. EXPANDER TOTAL HARMONIC DISTORTION TEST POINT: DELAY OUT (connect to scope - - DC coupling) 5-1. Set DELAY TIME to X1 and UNIGAIN to -20dBm. 5-2. Feed the same signal as for 4-2. 5-3. Adjust RT3 for straight DC line. 5-4. Set scope V IN to AC coupling. 6. FREQUENCY RESPONSE OFF 5-5. Repeatedly rotating INPUT ATT over its full travel, fine adjust RT3 for minimum DC drift. Adjust scope VAR as necessary. 5-6. Connect amplifier/speaker to DELAY OUT and check for pop or rumble noise. If noticeable, check for absence of R271 and R272 (see table on the fac ing page) which are effective to the problem. ■"Fl/TATT FEEDBACK DELAY OUT TUSSTj SH^Roland □ -OFF TEST POINT: DELAY OUT (connect to AC voltmeter) 6-1. Set DELAY TIME to X1 and UNIGAIN to -20 dBm. 6-2. Connect AG to INPUT jack and set AG output for -20dBm, 1kHz, sine. 6-3. Adjust INPUT ATT for -30dBm reading. 7. FEEDBACK 6-4. Reset AG to 8.5kHz. Adjust RT4 for -30.2dBm reading. 6-5. Press DELAY TIME X2 (ON). Reset AG to400Hz, -30dBm. 6-6. Adjust INPUT ATT for -30dBm reading. 6-7. Reset AG to 5kHz, -30dBm. Adjust VR5 for -30.2dBm reading. T ATT FEEDBACK DELAY OUT OFF- BRoland • <** i I ON TEST POINT: DELAY OUT (connect to scope) 7-1. Set DELAY TIME to X1 and UNIGAIN to -20 dBm. 7-2. Apply a signal (e.g. -30dBm, 1kHz, sine) to INPUT jack for an instant and adjust RT7 for continual re peats at a level. 7-3. Verify decaying repeats with FEEDBACK at 7.5. 15

iw? SDE-1000 f Itt^tt > 0*"0 0 I ® ® ® ® ® ® - S S 2 g s LED BOARD 7411607001 (pcb 2291058300) View from foil side MAIN BOARD 7411606031 (pcb 2291058201) See P.19 for POWEFSUPPLY BOARD ^r^PPIpl|J||m^ 1/"' il^V'^a"' ©C5s'.*—- ^#111 Ml tV kaftM»\ X •xPi»_9*» ; 16

PT RATING IDC. fit*** • 1&6V » ? #tttmA IQOfeF 1N VtJ-VtJ t1V«OOmA«IODtF f IN UNLESS OHCRWISE SPEDFIEO ALL <*0> TflANSiSTORS ON MAIN eOtitOARE 2SAII6 UNLESS OTHERWISE 8FEOFIED ALL NPN TRANSISTORS ON MAM BOARD ARE 2SC26O3 UNLESS OTHERWISE SPEOFCD ALL DIODES ARE ISSI33 MT-74116060 MAIN BOARD SWITCH BOARD t 1 1 1 1 r N >■ X 5 > T T 1—" CO OC O ii \ 1—r~"—r tn CO CM in —I—T —r~~i r c c c c c

I IC5i1,12,13,16.17 I I I I ?** I R2ir | 33K I f^i8 39K 2SC2603 ♦7 I -t8 I — IT— — LED BOARD 7411707001 (pdb 22910581000) View from fort side SWITCH BOARD 7411708005 (pcb 2291058100) View from foil side S T U V w X Y t

tCt?:NJM00t r r ll^ain Board MT41^O6o1 10 :D46 11 :t49 n or a :W«29 » :*27 19 ;*•!? »? tar 0 : Y*2? 19 j H29 10 :U*29 11 :U-39 12 t P-59S 13 :U-5* M :V21 IB :V-21 0 >U20 17 if «22 0 1O24 00 !ft«38 01 ;8iJ8 02 tft-SB 03 :M0 04 :M41 1t» :t4l 100 :28 49A:U29 498 :O27 50A:W^4 908 :X29 81 :T49 VII U22 SW1B:M2 SW1C.1 :O3 Sf SW2A.B:B-2 8W2O:I? "' ,0 [tWV OUT. | n tFO c c 18 ♦ * '• •

B C D E F G H I J K L M N O P a R 8 t ■ U V w X ■ Y z RAM BOARD 7411711002 (pcb 2291083800) View from foil side ui as $lslE tstmiJMki o POWER SUPPLY BOARD 7411709000 (pcb22d1058500) Common to SOE tOOO and SOE^OOO f mm. Fuie label*. Capacitor Ci wsto&BA. Specify modal and line voltage when ordering lot complete my. SDE-1000/SDE-3QMJtit i. h ■■■?'.;. 19

|TOP VIEW) NClT 01 •1 J * JL u 11)04 pot «1 1*1 v- . DUAL SPOT HI-303 ft HI-307 o$ 01 ot ANALOG SWITCH BOARD 22*1091900 Temtiorarily used for SN 372900-396099 - Substitute for ICB HI-302 and IC10 MI-303 - _ Analog Swrtteh Board 2291091900 1* aqulwrient to Hl-303 and H14102 In operation and H Stalled on «m* un»U baetu» ^^r^"^^; When the PCB needs replacing, use ty. *o A OrO OOO Tr: 9SCfMBm TSCIIMBtw 7SC9603 01-04: IS1473

■■ 'I IEW) ) ) ) o o SDE-3000 ADJUSTMENT 1. VOLTAGES CHECK IC24 4514 8.'tltv8 Front Panel S i;^l"®fdp 2. INPUT LEVEL METER OFF 2-1 Set UNIGAIN (Rear panel) to +4dBm. 2-2. Connect audio generator (AG) to INPUT Jack and set AG output for +4dBm, 1kHz, sine. 3. VCO 3-1. Set DELAY TIME (Rear panel) to XI. 3-2. Press and hold DELAY TIME button until TIME display reads maximum value. 4. LFORATE TEST POINT: MODULATION CV INV OUT (connect to oscilloscope) 4.1. Press and hold RATE button until RATE display . • reads 09. 4-2. Adjust VR7 for lOOms/cycle. 5. FREQUENCY RESPONSE 23. Set VR2«t the point where +3dBm LED Juttcom pletely fedes out. 3-3. Press TIME X2 (ON). 34. Adjust LI for 301011ms reading. NOTE: A TIME display change delays 1 tec behind a coll adjustment. ov 100m* □ =:• TEST POINT: DELAY OUT (connect to AC voltmeter) 8-1. Set UNIGAIN (Rear panel) to 44dBm and OELAY Set AO lor -lOdBm. 82. Connect AO 1kHi. sine. B-3. Adjust INPUT ATT lor -10dBm reading. 6. FEEDBACK &4.. Reset AG to 8.6kHt. Adjust VR4 for -10.2dBm rereading. 8-6. Press DELAY TIME X2 (ON). Reset AO lor «OW"«. - reiSm. B4. Adjust INPUT ATT for -lOdBm reading. B-7. Reset AG to -10dBm, BkHf. Adjuit VRB for -10.2d.Bm reading. -ALL OFF 8-1. Sat DELAY TIME to X1. 82.Turn VR3 fully clockwise. All INPUT level LEOs wUMIflhtupftom-20to-t6. 8-3. Gradually reverse VR3 until 48 and +3 LEDs 90 off completely. 7. D/A OFFSET TEST POINT: TP-1 (connect to scope, Y-axb or V IN-DCcouple) Connect TP-2 to X-axis or EXT TRIG. >1*S«t UNIGAIN to -20dBm and DELAY TIME to ^ AG to INPUT lack. Set AG for -IBdBm. UjQHt.slne. ^scope's VOLTS/DIVA/AR to show a pattern te^Nl In the photo. "A" Is on the center 6-4, Oonflrwtht following:. FEEDBACK M\ at SI. +3 *nd -HI light asaln i « VWth FEEDBACK M\ . Wlfh FEEDBACK 79, ail level LEDs go o« one by

22 SW2 UNIGAIN(SUF-12) +4dBm -20dBm i3> t: 'o ' ; u ;E F' C on t ;o ;A b OFF SW1 BYPASS(SUE-12) Top View SW1 BYPASS(SUE-12) -20dBm +4dBm ° :F e: °: ,o .d c: o, r6 ;B a! o ! b" o :o • d o1 t 'O ' F1. - OFF ON SW2 UNIGAIN(SUF12) Bottom View 21

—No data on one RAM pin of Main Controller- SDE-1000 INPUT -18dBm 1kHz RAM1 defective RAM17& IC28 pin6 5V/div TP-3 5V/div 0.2ms/div SDE-3000 INPUT -10dBm 1kHz All RAMs intact TP-1 TR45/TR50 emitter RAM1 (IC11) INPUT -18dBm 1kHz TP-3 5V/div IC16 pin6 2V/div 0.2ms/div TP-3 5V/div TP-1 20V/div 5/is/div INPUT -10dBm 1kHz TP-1 TR45/TR50 emitter 0.2ms/div TP-1 TP-2 5Ms/div UM1 (IC11) RAM1 RAM2 (IC10) RAM2 RAM3 (IC9) RAM3 22