Analog Devices AD604 Operation & User’s Manual

Variable Gain Amplifier AD604 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved. FEATURES Ultralow input noise at maximum gain 0.80 nV/√Hz, 3.0 pA/√Hz 2 independent linear-in-dB channels Absolute gain range per channel programmable 0 dB to 48 dB (preamplifier gain = 14 dB) through 6 dB to 54 dB (preamplifier gain = 20 dB) ±1.0 dB gain accuracy Bandwidth: 40 MHz (−3 dB) Input resistance: 300 kΩ Variable gain scaling: 20 dB/V through 40 dB/V Stable gain with temperature and supply variations Single-ended unipolar gain control Power shutdown at lower end of gain control Drive ADCs directly APPLICATIONS Ultrasound and sonar time-gain controls High performance AGC systems Signal measurement FUNCTIONAL BLOCK DIAGRAM OUTx VOCM PAOx PAIx +DSXx –DSXx VGNx VREF AFA FIXED GAIN AMPLIFIER 34.4dB PRECISION PASSIVE INPUT ATTENUATOR PROGRAMMABLE ULTRALOW NOISE PREAMPLIFIER G = 14dB TO 20dB DIFFERENTIAL ATTENUATOR R-1.5R LADDER NETWORK 0dB TO –48.4dB GAIN CONTROL AND SCALING 00540-001 Figure 1. GENERAL DESCRIPTION The AD604 is an ultralow noise, very accurate, dual-channel, linear-in-dB variable gain amplifier (VGA) optimized for time- based variable gain control in ultrasound applications; however, it supports any application requiring low noise, wide bandwidth, variable gain control. Each channel of the AD604 provides a 300 kΩ input resistance and unipolar gain control for ease of use. User-determined gain ranges, gain scaling (dB/V), and dc level shifting of output further optimize performance. Each channel of the AD604 uses a high performance preamplifier that provides an input-referred noise voltage of 0.8 nV/√Hz. The very accurate linear-in-dB response of the AD604 is achieved with the differential input exponential amplifier (DSX-AMP) architecture. Each DSX-AMP comprises a variable attenuator of 0 dB to 48.36 dB followed by a high speed fixed-gain amplifier. The attenuator is a 7-stage R-1.5R ladder network. The attenuation between tap points is 6.908 dB and 48.36 dB for the ladder network. The equation for the linear-in-dB gain response is G (dB) = (Gain Scaling (dB/V) × VGN (V)) + (Preamp Gain (dB) – 19 dB) Preamplifier gains between 5 and 10 (14 dB and 20 dB) provide overall gain ranges per channel of 0 dB through 48 dB and 6 dB through 54 dB. The two channels of the AD604 can be cascaded to provide greater levels of gain range by bypassing the preamplifier of the second channel. However, in multiple channel systems, cascading the AD604 with other devices in the AD60x VGA family that do not include a preamplifier may provide a more efficient solution. The AD604 provides access to the output of the preamplifier, allowing for external filtering between the preamplifier and the differential attenuator stage. Note that scale factors up to 40 dB/V are achievable with reduced accuracy for scales above 30 dB/V. The gain scales linearly in decibels with control voltages of 0.4 V to 2.4 V with the 20 dB/V scale. Below and above this gain control range, the gain begins to deviate from the ideal linear-in-dB control law. The gain control region below 0.1 V is not used for gain control. When the gain control voltage is <50 mV, the amplifier channel is powered down to 1.9 mA. The AD604 is available in 24-lead SSOP, SOIC, and PDIP packages and is guaranteed for operation over the −40°C to +85°C temperature range. www. BDTI C. com/ADI

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 13 Preamplifier ................................................................................. 14 Differential Ladder (Attenuator) .............................................. 15 AC Coupling ............................................................................... 16 Gain Control Interface ............................................................... 16 Active Feedback Amplifier (Fixed-Gain Amp) ...................... 16 Applications Information .............................................................. 18 Ultralow Noise AGC Amplifier with 82 dB to 96 dB Gain Range .................................................................................. 19 Ultralow Noise, Differential Input-Differential Output VGA ................................................................................ 21 Medical Ultrasound TGC Driving the AD9050, a 10-Bit, 40 MSPS ADC............................................................................. 22 Evaluation Board ............................................................................ 24 Using the Preamplifier ............................................................... 24 DSX Input Connections ............................................................ 24 Preamplifier Gain ....................................................................... 25 Outputs ........................................................................................ 25 DC Operating Conditions ......................................................... 25 Evaluation Board Artwork and Schematic ............................. 26 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 29 REVISION HISTORY 10/08—Rev. D to Rev. E Changes to Figure 1 .......................................................................... 1 Changes to Figure 37 ...................................................................... 13 Changes to Figure 41 ...................................................................... 15 Changes to Evaluation Board Model Name ................................ 24 Changes to Ordering Guide .......................................................... 29 1/08—Rev. C to Rev. D Changes to AC Coupling Section ................................................. 16 Changes to Applications Information Section ............................ 18 Changes to An Ultralow Noise AGC Amplifier with 82 dB to 96 dB Gain Range Section ............................................................. 19 Changes to Figure 55 and Figure 56 ............................................. 24 Changes to Cascaded DSX Section and Outputs Section ......... 25 Changes to Figure 57 to Figure 60 ................................................ 26 Changes to Figure 61 and Table 6 ................................................. 27 Changes to Ordering Guide .......................................................... 29 3/07—Rev. B to Rev. C Added Evaluation Board Section ................................................. 24 Added Evaluation Board Artwork and Schematics Section ..... 26 Changes to Ordering Guide .......................................................... 29 12/06—Rev. A to Rev. B Changes to General Description .................................................... 1 Changes to Figure 54 ...................................................................... 23 Changes to Ordering Guide .......................................................... 25 1/04—Rev. 0 to Rev. A Changes to Specifications .................................................................2 Changes to Absolute Maximum Ratings ........................................3 Changes to Ordering Guide .............................................................3 Changes to Figure 1 Caption............................................................5 Changes to Figure 11 Caption .........................................................6 Changes to Figure 17 .........................................................................6 Changes to Figure 51 ...................................................................... 17 Updated Outline Dimensions ....................................................... 18 10/96—Revision 0: Initial Version www. BDTI C. com/ADI

SPECIFICATIONS Each amplifier channel at TA = 25°C, VS = ±5 V, RS = 50 Ω, RL = 500 Ω, CL = 5 pF, VREF = 2.50 V (scaling = 20 dB/V), 0 dB to 48 dB gain range (preamplifier gain = 14 dB), VOCM = 2.5 V, C1 and C2 = 0.1 μF (see Figure 37), unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Preamplifier Input Resistance 300 kΩ Input Capacitance 8.5 pF Input Bias Current −27 mA Peak Input Voltage Preamplifier gain = 14 dB ±400 mV Preamplifier gain = 20 dB ±200 mV Input Voltage Noise VGN = 2.9 V, RS = 0 Ω Preamplifier gain = 14 dB 0.8 nV/√Hz Preamplifier gain = 20 dB 0.73 nV/√Hz Input Current Noise Independent of gain 3.0 pA/√Hz Noise Figure RS = 50 Ω, f = 10 MHz, VGN = 2.9 V 2.3 dB RS = 200 Ω, f = 10 MHz, VGN = 2.9 V 1.1 dB DSX Input Resistance 175 Ω Input Capacitance 3.0 pF Peak Input Voltage 2.5 ± 2 V Input Voltage Noise VGN = 2.9 V 1.8 nV/√Hz Input Current Noise VGN = 2.9 V 2.7 pA/√Hz Noise Figure RS = 50 Ω, f = 10 MHz, VGN = 2.9 V 8.4 dB RS = 200 Ω, f = 10 MHz, VGN = 2.9 V 12 dB Common-Mode Rejection Ratio f = 1 MHz, VGN = 2.65 V −20 dB OUTPUT CHARACTERISTICS −3 dB Bandwidth Constant with gain 40 MHz Slew Rate VGN = 1.5 V, output = 1 V step 170 V/μs Output Signal Range RL ≥ 500 Ω 2.5 ± 1.5 V Output Impedance f = 10 MHz 2 Ω Output Short-Circuit Current ±40 mA Harmonic Distortion VGN = 1 V, VOUT = 1 V p-p HD2 f = 1 MHz −54 dBc HD3 f = 1 MHz −67 dBc HD2 f = 10 MHz −43 dBc HD3 f = 10 MHz −48 dBc Two-Tone Intermodulation Distortion (IMD) VGN = 2.9 V, VOUT = 1 V p-p f = 1 MHz −74 dBc f = 10 MHz −71 dBc Third-Order Intercept f = 10 MHz, VGN = 2.65 V, VOUT = 1 V p-p, input referred −12.5 dBm 1 dB Compression Point f = 1 MHz, VGN = 2.9 V, output referred 15 dBm Channel-to-Channel Crosstalk VOUT = 1 V p-p, f = 1 MHz, Channel 1: VGN = 2.65 V, inputs shorted, Channel 2: VGN = 1.5 V (mid gain) −30 dB Group Delay Variation 1 MHz < f < 10 MHz, full gain range ±2 ns VOCM Input Resistance 45 kΩ www. BDTI C. com/ADI

Parameter Conditions Min Typ Max Unit ACCURACY Absolute Gain Error 0 dB to 3 dB 0.25 V < VGN < 0.400 V −1.2 +0.75 +3 dB 3 dB to 43 dB 0.400 V < VGN < 2.400 V −1.0 ±0.3 +1.0 dB 43 dB to 48 dB 2.400 V < VGN < 2.65 V −3.5 −1.25 +1.2 dB Gain Scaling Error 0.400 V < VGN < 2.400 V ±0.25 dB/V Output Offset Voltage VREF = 2.500 V, VOCM = 2.500 V −50 ±30 +50 mV Output Offset Variation VREF = 2.500 V, VOCM = 2.500 V 30 50 mV GAIN CONTROL INTERFACE Gain Scaling Factor VREF = 2.5 V, 0.4 V < VGN < 2.4 V 19 20 21 dB/V VREF = 1.67 V 30 dB/V Gain Range Preamplifier gain = 14 dB 0 to 48 dB Preamplifier gain = 20 dB 6 to 54 dB Input Voltage (VGN) Range 20 dB/V, VREF = 2.5 V 0.1 to 2.9 V Input Bias Current −0.4 μA Input Resistance 2 MΩ Response Time 48 dB gain change 0.2 μs VREF Input Resistance 10 kΩ POWER SUPPLY Specified Operating Range One complete channel ±5 V One DSX only 5 V Power Dissipation One complete channel 220 mW One DSX only 95 mW Quiescent Supply Current VPOS, one complete channel 32 36 mA VPOS, one DSX only 19 23 mA VNEG, one preamplifier only −15 −12 mA Powered Down VPOS, VGN < 50 mV, one channel 1.9 3.0 mA VNEG, VGN < 50 mV, one channel −150 μA Power-Up Response Time 48 dB gain change, VOUT = 2 V p-p 0.6 μs Power-Down Response Time 0.4 μs www. BDTI C. com/ADI

ABSOLUTE MAXIMUM RATINGS Table 2. Parameter1, 2 Rating Supply Voltage ±VS Pin 17 to Pin 20 (with Pin 16, Pin 22 = 0 V) ±6.5 V Input Voltages Pin 1, Pin 2, Pin 11, Pin 12 VPOS/2 ± 2 V continuous Pin 4, Pin 9 ±2 V Pin 5, Pin 8 VPOS, VNEG Pin 6, Pin 7, Pin 13, Pin 14, Pin 23, Pin 24 VPOS, 0 V Internal Power Dissipation PDIP (N) 2.2 W SOIC (RW) 1.7 W SSOP (RS) 1.1 W Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering 60 sec 300°C θJA3 AD604AN 105°C/W AD604AR 73°C/W AD604ARS 112°C/W θJC3 AD604AN 35°C/W AD604AR 38°C/W AD604ARS 34°C/W 1 Pin 1, Pin 2, Pin 11 to Pin 14, Pin 23, and Pin 24 are part of a single-supply circuit. The part is likely to suffer damage if any of these pins are accidentally connected to VN. 2 When driven from an external low impedance source. 3 Using MIL-STD-883 test method G43-87 with a 1S (2-layer) test board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION www. BDTI C. com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –DSX1 1 +DSX1 2 PAO1 3 FBK1 4 VGN1 24 VREF 23 OUT1 22 GND1 21 PAI1 5 COM1 6 COM2 7 VPOS 20 VNEG 19 VNEG 18 PAI2 8 VPOS 17 FBK2 9 GND2 16 PAO2 10 OUT2 15 +DSX2 11 VOCM 14 –DSX2 12 VGN2 13 AD604 TOP VIEW (Not to Scale) 00540-002 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 –DSX1 Channel 1 Negative Signal Input to DSX1. 2 +DSX1 Channel 1 Positive Signal Input to DSX1. 3 PAO1 Channel 1 Preamplifier Output. 4 FBK1 Channel 1 Preamplifier Feedback Pin. 5 PAI1 Channel 1 Preamplifier Positive Input. 6 COM1 Channel 1 Signal Ground. When this pin is connected to positive supply, Preamplifier 1 shuts down. 7 COM2 Channel 2 Signal Ground. When this pin is connected to positive supply, Preamplifier 2 shuts down. 8 PAI2 Channel 2 Preamplifier Positive Input. 9 FBK2 Channel 2 Preamplifier Feedback Pin. 10 PAO2 Channel 2 Preamplifier Output. 11 +DSX2 Channel 2 Positive Signal Input to DSX2. 12 –DSX2 Channel 2 Negative Signal Input to DSX2. 13 VGN2 Channel 2 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive voltage increases gain. 14 VOCM Input to this pin defines the common mode of the output at OUT1 and OUT2. 15 OUT2 Channel 2 Signal Output. 16 GND2 Ground. 17 VPOS Positive Supply. 18 VNEG Negative Supply. 19 VNEG Negative Supply. 20 VPOS Positive Supply. 21 GND1 Ground. 22 OUT1 Channel 1 Signal Output. 23 VREF Input to this pin sets gain scaling for both channels to 2.5 V = 20 dB/V and 1.67 V = 30 dB/V. 24 VGN1 Channel 1 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive voltage increases gain. www. BDTI C. com/ADI

VGN (V) –10 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, G (preamplifier) = 14 dB, VREF = 2.5 V (20 dB/V scaling), f = 1 MHz, RL = 500 Ω, CL = 5 pF, TA = 25°C, and VSS = ±5 V. GAIN SCALING (dB/V) 40.0 37.5 32.5 30.0 25.0 20.0 22.5 27.5 35.0 50 20 40 30 10 0 GAIN (dB) 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3 CURVES –40°C, +25°C, +85°C 00540-003 Figure 3. Gain vs. VGN for Three Temperatures VGN (V) 60 50 40 30 20 10 0 –10 GAIN (dB) –20 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 G (PREAMP) = +20dB (+6dB TO +54dB) DSX ONLY (–14dB TO +34dB) G (PREAMP) = +14dB (0dB TO +48dB) 00540-004 Figure 4. Gain vs. VGN for Different Preamplifier Gains VGN (V) –10 50 20 40 30 10 0 GAIN (dB) 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 ACTUAL ACTUAL 20dB/V VREF = 2.5V 30dB/V VREF = 1.67V 00540-005 Figure 5. Gain vs. VGN for Different Gain Scalings ACTUAL VREF (V) THEORETICAL 1.25 1.50 1.75 2.00 2.25 2.50 00540-006 VGN (V) GAIN ERROR (dB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 Figure 6. Gain Scaling vs. VREF 0.2 0.7 1.2 1.7 2.2 2.7 +25°C –40°C +85°C 00540-007 Figure 7. Gain Error vs. VGN VGN (V) GAIN ERROR (dB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0.2 0.7 1.2 1.7 2.2 2.7 FREQ = 5MHz FREQ = 1MHz FREQ = 10MHz 00540-008 Figure 8. Gain Error vs. VGN at Different Frequencies www. BDTI C. com/ADI

VGN (V) GAIN ERROR (dB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 FREQUENCY (Hz) GAIN (dB) 50 40 –50 30 20 10 0 –10 –20 –30 –40 100k 1M 10M 100M 0.2 0.7 1.2 1.7 2.2 2.7 20dB/V VREF = 2.5V 30dB/V VREF = 1.67V 00540-009 Figure 9. Gain Error vs. VGN for Two Gain Scaling Values DELTA GAIN (dB) PERCENTAGE 25 20 15 10 5 0 –1.0 –0.8 –0.6 –0.4 –0.2 0.1 0.3 0.5 0.7 0.9 N = 50 VGN1 = 1.0V VGN2 = 1.0V ΔG(dB) = G(CH1) – G(CH2) 00540-010 Figure 10. Gain Match; VGN1 = VGN2 = 1.0 V DELTA GAIN (dB) PERCENTAGE 25 20 15 10 5 0 –1.0 –0.8 –0.6 –0.4 –0.2 0.1 0.3 0.5 0.7 0.9 N = 50 VGN1 = 2.50V VGN2 = 2.50V ΔG(dB) = G(CH1) – G(CH2) 00540-011 Figure 11. Gain Match; VGN1 = VGN2 = 2.50 V VGN = 2.9V VGN = 2.5V VGN = 1.5V VGN = 0.5V VGN = 0.1V VGN = 0V 00540-012 VGN (V) 2.55 Figure 12. AC Response for Various Values of VGN VOCM = 2.5V 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.45 2.46 2.47 –40°C +25°C +85°C VOUT (V) 0.2 0.7 1.2 1.7 2.2 2.7 00540-013 210 Figure 13. Output Offset vs. VGN for Three Temperatures VGN (V) 190 170 150 130 110 90 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 NOISE (nV/ Hz) –40°C +25°C +85°C 00540-014 Figure 14. Output Referred Noise vs. VGN for Three Temperatures www. BDTI C. com/ADI

1000 1 0.1 10 1 0.1 VGN = 2.9V VGN (V) 100 10 NOISE (nV/ Hz) 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 00540-015 Figure 15. Input Referred Noise vs. VGN 900 850 800 750 700 650 600 TEMPERATURE (°C) NOISE (pV/ Hz) VGN = 2.9V –40 –20 0 20 40 60 80 90 00540-016 FREQUENCY (Hz) 740 Figure 16. Input Referred Noise vs. Temperature 770 745 760 765 750 755 VGN = 2.9V 100k 1M 10M NOISE (pV/ Hz) 7 00540-01 Figure 17. Input Referred Noise vs. Frequency RSOURCE (Ω) 1 10 100 1k NOISE (nV/ Hz) RSOURCE ALONE 00540-018 NOISE FIGURE (dB) 16 11 1 10k 100 1k 6 15 14 13 12 10 9 8 7 5 3 4 2 Figure 18. Input Referred Noise vs. RSOURCE VGN = 2.9V 10 1 RSOURCE (Ω) 00540-019 NOISE FIGURE (dB) 40 20 Figure 19. Noise Figure vs. RSOURCE VGN (V) 0 RS = 240Ω 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 00 35 30 25 15 10 5 540-020 Figure 20. Noise Figure vs. VGN www. BDTI C. com/ADI

–20 2 FREQUENCY (Hz) HARMONIC DISTORTION (dBc) –40 –50 –70 –60 –45 –55 –65 100k 1M 10M 100M VO = 1V p-p VGN = 1V HD3 HD2 00540-021 Figure 21. Harmonic Distortion vs. Frequency VGN (V) HARMONIC DISTORTION (dBc) –30 –60 –80 –40 –50 –70 –35 –65 –45 –55 –75 VO = 1V p-p HD2 (10MHz) HD3 (1MHz) HD3 (10MHz) HD2 (1MHz) 0.5 0.9 1.3 1.7 2.1 2.5 2.9 00540-022 Figure 22. Harmonic Distortion vs. VGN –20 –50 HARMONIC DISTORTION (dBc) –80 –30 –40 –70 –60 50Ω 500Ω DUT RS RSOURCE (Ω) 0 50 100 150 200 250 VO = 1V p-p VGN = 1V HD3 (10MHz) HD2 (1MHz) HD3 (1MHz) HD2 (10MHz) 3 00540-02 FREQUENCY (MHz) –90 –120 Figure 23. Harmonic Distortion vs. RSOURCE VO = 1V p-p VGN = 1V –30 –80 –100 –110 –60 –70 –40 –50 9.96 9.98 10.00 10.02 10.04 POUT (dBm) 00540-024 VGN (V) 5 –15 –35 Figure 24. Intermodulation Distortion 0 –5 –10 –20 –30 –25 10MHz 1MHz INPUT SIGNAL LIMIT 800mV p-p PIN (dBm) 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 00540-025 IP3 (dBm) 25 20 Figure 25. 1 dB Compression vs. VGN VGN (V) –15 5 0 –5 –10 15 10 f = 1MHz f = 10MHz VO = 1V p-p 0.4 0.9 1.4 1.9 2.4 2.9 00540-026 Figure 26. Third-Order Intercept vs. VGN www. BDTI C. com/ADI

100ns/DIV 400mV/DIV 2V –2V 253ns 1.253µs VO = 2V p-p VGN = 1.5V 00540-027 Figure 27. Large Signal Pulse Response 100ns/DIV 40mV/DIV 200 –200 253ns 1.253µs VO = 200mV p-p VGN = 1.5V TRIG'D 00540-028 Figure 28. Small Signal Pulse Response 10 0% 100 90 2.9V VGN (V) 0V 200ns 500mV 00540-029 500mV Figure 29. Power-Up/Power-Down Response 10 0% 100 90 100ns 500mV 500mV 2.9V 0.1V VGN (V) 00540-030 FREQUENCY (Hz) CROSSTALK (dB) –30 –10 –20 –40 –50 –60 0 –70 Figure 30. Gain Response 100k 1M 10M 100M VGN2 = 0.1V VGN2 = 1.5V VGN2 = 2V VGN2 = 2.9V VGN1 = 1V VOUT1 = 1V p-p VIN2 = GND 00540-031 CMRR (dB) –50 –10 –20 –30 –40 0 Figure 31. Crosstalk (Channel 1 to Channel 2) vs. Frequency FREQUENCY (Hz) –60 100k 1M 10M 100M VGN = 2.9V VGN = 2.5V VGN = 2V VGN = 0.1V 00540-032 Figure 32. DSX Common-Mode Rejection Ratio vs. Frequency www. BDTI C. com/ADI

FREQUENCY (Hz) 1M 1k 1 100k 10k 100 10 1k 10k 100k 1M 10M 100M INPUT IMPEDANCE (Ω) 00540-033 25.8 Figure 33. Input Impedance vs. Frequency 27.6 27.2 26.8 26.6 26.2 26.4 27.0 27.4 26.0 TEMPERATURE (°C) –40 –20 0 20 40 60 80 90 00540-034 SUPPLY CURRENT (mA) 40 20 0 35 30 25 15 10 5 INPUT BIAS CURRENT (µA) Figure 34. Input Bias Current vs. Temperature PREAMP (±IS) AD604 (+IS) DSX (+IS) +IS (VGN = 0) +IS (AD604) = +IS (PA) + +IS (DSX) –IS (AD604) = –IS (PA) TEMPERATURE (°C) –40 –20 0 20 40 60 80 90 00540-035 Figure 35. Supply Current (One Channel) vs. Temperature FREQUENCY (Hz) 20 14 8 10 12 16 18 6 DELAY (ns) VGN = 0.1V VGN = 2.9V 100k 1M 10M 100M 00540-036 Figure 36. Group Delay vs. Frequency www. BDTI C. com/ADI

THEORY OF OPERATION The AD604 is a dual-channel VGA with an ultralow noise preamplifier. Figure 37 shows the simplified block diagram of one channel. Each identical channel consists of a preamplifier with gain setting resistors (R5, R6, and R7) and a single-supply X-AMP® (hereafter called DSX, differential single-supply X-AMP) made up of the following: • A precision passive attenuator (differential ladder). • A gain control block. • A VOCM buffer with supply splitting resistors (R3 and R4). • An active feedback amplifier (AFA) with gain setting resistors (R1 and R2). To understand the active-feedback amplifier topology, refer to the AD830 data sheet. The AD830 is a practical implementation of the idea. The preamplifier is powered by a ±5 V supply, while the DSX uses a single +5 V supply. The linear-in-dB gain response of the AD604 can generally be described by G (dB) = Gain Scaling (dB/V) × Gain Control (V) + (Preamp Gain (dB) − 19 dB) (1) Each channel provides between 0 dB to 48.4 dB and 6 dB to 54.4 dB of gain, depending on the user-determined preamplifier gain. The center 40 dB of gain is exactly linear-in-dB while the gain error increases at the top and bottom of the range. The gain of the preamplifier is typically either 14 dB or 20 dB but can be set to intermediate values by a single external resistor (see the Preamplifier section for details). The gain of the DSX can vary from −14 dB to +34.4 dB, as determined by the gain control voltage (VGN). The VREF input establishes the gain scaling; the useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF voltage of 2.5 V and 1.25 V, respectively. For example, if the preamp gain is set to 14 dB and VREF is set to 2.50 V (to establish a gain scaling of 20 dB/V), the gain equation simplifies to G (dB) = 20 (dB/V) × VGN (V) – 5 dB The desired gain can then be achieved by setting the unipolar gain control (VGN) to a voltage within its nominal operating range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is monotonic for a complete gain control voltage range of 0.1 V to 2.9 V. Maximum gain can be achieved at a VGN of 2.9 V. The inputs VREF and VOCM are common to both channels. They are decoupled to ground, minimizing interchannel crosstalk. For the highest gain scaling accuracy, VREF should have an external low impedance voltage source. For low accuracy 20 dB/V applications, the VREF input can be decoupled with a capacitor to ground. In this mode, the gain scaling is determined by the midpoint between VPOS and GND; therefore, care should be taken to control the supply voltage to 5 V. The input resistance looking into the VREF pin is 10 kΩ ± 20%. The DSX portion of the AD604 is a single-supply circuit, and the VOCM pin is used to establish the dc level of the midpoint of this portion of the circuit. The VOCM pin only needs an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 V, GND); however, the VOCM can be adjusted to other voltage levels if the dc common-mode level of the output is important to the user (for example, see the section entitled Medical Ultrasound TGC Driving the AD9050, a 10-Bit, 40 MSPS ADC). The input resistance looking into the VOCM pin is 45 kΩ ± 20%. VGNx PAIx FBKx C1 –DSXx EXT. COMx VPOS VOCM C3 C2 OUTx 175Ω G1 Ao G2 EXT. 175Ω R4 200kΩ R3 200kΩ VREF DISTRIBUTED GM GAIN CONTROL DIFFERENTIAL ATTENUATOR R1 820Ω R2 20Ω +DSXx PAOx R7 40Ω R5 32Ω R6 8Ω 00540-037 Figure 37. Simplified Block Diagram of a Single Channel of the AD604 www. BDTI C. com/ADI

PREAMPLIFIER The input capability of the following single-supply DSX (2.5 ± 2 V for a +5 V supply) limits the maximum input voltage of the preamplifier to ±400 mV for the 14 dB gain configuration or ±200 mV for the 20 dB gain configuration. The preamplifier gain can be programmed to 14 dB or 20 dB by either shorting the FBK1 node to PAO1 (14 dB) or by leaving the FBK1 node open (20 dB). These two gain settings are very accurate because they are set by the ratio of the on-chip resistors. Any intermediate gain can be achieved by connecting the appropriate resistor value between PAO1 and FBK1 according to Equation 2 and Equation 3. ( ) 6 6 5 || 7 R R R R R V V G EXT OUT + + = = IN ( ) [ ] ( ) ( ) (2) 6 5 6 7 7 6 5 6 R R G R R R R R G R REXT + + × − × + − × = (3) Because the internal resistors have an absolute tolerance of ±20%, the gain can be in error by as much as 0.33 dB when REXT is 30 Ω, where it is assumed that REXT is exact. Figure 38 shows how the preamplifier is set to gains of 14 dB, 17.5 dB, and 20 dB. The gain range of a single channel of the AD604 is 0 dB to 48 dB when the preamplifier is set to 14 dB (Figure 38a), 3.5 dB to 51.5 dB for a preamp gain of 17.5 dB (Figure 38b), and 6 dB to 54 dB for the highest preamp gain of 20 dB (Figure 38c). FBK1 PAO1 COM1 PAI1 FBK1 PAO1 COM1 PAI1 FBK1 PAO1 PAI1 COM1 R6 8Ω R5 32Ω R7 40Ω a. PREAMP GAIN = 14dB b. PREAMP GAIN = 17.5dB R10 40Ω R7 40Ω R5 32Ω R6 8Ω R7 c. PREAMP GAIN = 20dB 40Ω R5 32Ω R6 8Ω 00540-038 20 19 10 GAIN 17 Figure 38. Preamplifier Gain Programmability For a preamplifier gain of 14 dB, the −3 dB small signal bandwidth of the preamplifier is 130 MHz. When the gain is at its maximum of 20 dB, the bandwidth is reduced by half to 65 MHz. Figure 39 shows the ac response for the three preamp gains shown in Figure 38. Note that the gain for an REXT of 40 Ω should be 17.5 dB, but the mismatch between the internal resistors and the external resistor causes the actual gain for this particular preamplifier to be 17.7 dB. The −3 dB small signal bandwidth of one complete channel of the AD604 (preamplifier and DSX) is 40 MHz and is independent of gain. To achieve optimum specifications, power and ground manage- ment are critical to the AD604. Large dynamic currents result because of the low resistances needed for the desired noise performance. Most of the difficulty is with the very low gain setting resistors of the preamplifier that allow for a total input referred noise, including the DSX, as low as 0.8 nV/√Hz. The consequently large dynamic currents have to be carefully handled to maintain performance even at large signal levels. OPEN (dB) 16 18 15 14 13 12 11 SHORT 40Ω 50Ω 40Ω 150Ω 8Ω IN 32Ω 100M 10M 1M 100k FREQUENCY (Hz) REXT VIN 00540-039 Figure 39. AC Response for Preamplifier Gains of 14 dB, 17.5 dB, and 20 dB The preamplifier uses a dual ±5 V supply to accommodate large dynamic currents and a ground referenced input. The preamplifier output is also ground referenced and requires a common-mode level shift into the single-supply DSX. The two external coupling capacitors (C1 and C2 in Figure 37) connected to the PAO1 and +DSXx, and –DSXx, nodes and ground, respectively, perform this function (see the AC Coupling section). In addition, they eliminate any offset that would otherwise be introduced by the preamplifier. It should be noted that an offset of 1 mV at the input of the DSX is amplified by 34.4 dB (× 52.5) when the gain control voltage is at its maximum; this equates to 52.5 mV at the output. AC coupling is consequently required to keep the offset from degrading the output signal range. The gain-setting preamplifier feedback resistors are small enough (8 Ω and 32 Ω) that even an additional 1 Ω in the ground connection at Pin COM1 (the input common-mode reference) seriously degrades gain accuracy and noise performance. This node is sensitive, and careful attention is necessary to minimize the ground impedance. All connections to the COM1 node should be as short as possible. The preamplifier, including the gain setting resistors, has a noise performance of 0.71 nV/√Hz and 3 pA/√Hz. Note that a significant portion of the total input referred voltage noise is due to the feedback resistors. The equivalent noise resistance presented by R5 and R6 in parallel is nominally 6.4 Ω, which contributes 0.33 nV/√Hz to the total input referred voltage noise. www. BDTI C. com/ADI

12 11 10 A unique circuit technique is used to interpolate continuously among the tap points, thereby providing continuous attenuation from 0 dB to −48.36 dB. The ladder network, together with the interpolation mechanism, can be considered a voltage-controlled potentiometer. The larger portion of the input referred voltage noise comes from the amplifier with 0.63 nV/√Hz. The current noise is independent of gain and depends only on the bias current in the input stage of the preamplifier, which is 3 pA/√Hz. The preamplifier can drive 40 Ω (the nominal feedback resistors) and the following 175 Ω ladder load of the DSX with low distortion. For example, at 10 MHz and 1 V at the output, the preamplifier has less than −45 dB of second and third harmonic distortion when driven from a low (25 Ω) source resistance. Because the DSX circuit uses a single voltage power supply, the input biasing is provided by the VOCM buffer driving the MID node (see Figure 41). Without internal biasing, the user would have to dc bias the inputs externally. If not done carefully, the biasing network can introduce additional noise and offsets. By providing internal biasing, the user is relieved of this task and only needs to ac-couple the signal into the DSX. Note that the input to the DSX is still fully differential if driven differentially; that is, Pin +DSXx and Pin −DSXx see the same signal but with opposite polarity (see the Ultralow Noise, Differential Input- Differential Output VGA section). In applications that require more than 48 dB of gain range, two AD604 channels can be cascaded. Because the preamplifier has a limited input signal range and consumes over half (120 mW) of the total power (220 mW), and its ultralow noise is not necessary after the first AD604 channel, a shutdown mechanism that disables only the preamplifier is provided. To shut down the preamplifier, connect the COM1 pin and/or COM2 pin to the positive supply; the DSX is unaffected. For additional details, refer to the Applications Information section. What changes is the load seen by the driver; it is 175 Ω when each input is driven single-ended but 350 Ω when driven differentially. This is easily explained by thinking of the ladder network as two 175 Ω resistors connected back-to-back with the middle node, MID, being biased by the VOCM buffer. A differential signal applied between the +DSXx and −DSXx nodes results in zero current into the MID node, but a single- ended signal applied to either input, +DSXx or –DSXx, while the other input is ac-grounded causes the current delivered by the source to flow into the VOCM buffer via the MID node. 9 8 1 2 3 4 7 6 5 13 15 14 16 24 23 22 21 20 19 18 17 AD604 –DSX1 +DSX1 PAI1 FBK1 PAO1 COM1 COM2 PAI2 FBK2 VGN1 VREF VPOS GND1 OUT1 VNEG VNEG VPOS GND2 PAO2 +DSX2 –DSX2 OUT2 VOCM VGN2 The ladder resistor value of 175 Ω provides the optimum balance between the load driving capability of the preamplifier and the noise contribution of the resistors. An advantage of the X-AMP architecture is that the output referred noise is constant vs. gain over most of the gain range. Figure 41 shows that the tap resistance is equal for all taps after only a few taps away from the inputs. The resistance seen looking into each tap is 54.4 Ω, which makes 0.95 nV/√Hz of Johnson noise spectral density. Because there are two attenuators, the overall noise contribution of the ladder network is √2 times 0.95 nV/√Hz or 1.34 nV/√Hz, a large fraction of the total DSX noise. The balance of the DSX circuit components contributes another 1.2 nV/√Hz, which together with the attenuator produces 1.8 nV/√Hz of total DSX input referred noise. 00540-040 Figure 40. Shutdown of Preamplifiers Only DIFFERENTIAL LADDER (ATTENUATOR) The attenuator before the fixed-gain amplifier of the DSX is realized by a differential 7-stage R-1.5R resistive ladder network with an untrimmed input resistance of 175 Ω single-ended or 350 Ω differential. The signal applied at the input of the ladder network is attenuated by 6.908 dB per tap; thus, the attenuation at the first tap is 0 dB, at the second, 13.816 dB, and so on, all the way to the last tap where the attenuation is 48.356 dB (see Figure 41). R R –6.908dB 1.5R R R –13.82dB R R R R R R R R R R –20.72dB –27.63dB –34.54dB –41.45dB –48.36dB +DSXx MID –DSXx NOTES 1. R = 96Ω 2. 1.5R = 144Ω 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 175Ω 1.5R 175Ω 00540-041 Figure 41. R-1.5R Dual Ladder Network www. BDTI C. com/ADI

GAIN CONTROL VOLTAGE (VGN) 5 0 –5 AC COUPLING The DSX portion of the AD604 is a single-supply circuit and, therefore, its inputs need to be ac-coupled to accommodate ground-based signals. External Capacitors C1 and C2 in Figure 37 level shift the ground referenced preamplifier output from ground to the dc value established by VOCM (nominal 2.5 V). C1 and C2, together with the 175 Ω looking into each of the DSX inputs (+DSXx and −DSXx), act as high-pass filters with corner frequencies depending on the values chosen for C1 and C2. As an example, for values of 0.1 μF at C1 and C2, combined with the 175 Ω input resistance at each side of the differential ladder of the DSX, the −3 dB high-pass corner is 9.1 kHz. If the AD604 output needs to be ground referenced, another ac coupling capacitor is required for level shifting. This capacitor also eliminates any dc offsets contributed by the DSX. With a nominal load of 500 Ω and a 0.1 μF coupling capacitor, this adds a high-pass filter with −3 dB corner frequency at about 3.2 kHz. The choice for all three of these coupling capacitors depends on the application. They should allow the signals of interest to pass unattenuated while, at the same time, they can be used to limit the low frequency noise in the system. GAIN CONTROL INTERFACE The gain control interface provides an input resistance of approximately 2 MΩ at VGN1 and gain scaling factors from 20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V, respectively. The gain scales linearly in decibels for the center 40 dB of gain range, which for VGN is equal to 0.4 V to 2.4 V for the 20 dB/V scale and 0.2 V to 1.2 V for the 40 dB/V scale. Figure 42 shows the ideal gain curves for a nominal preamplifier gain of 14 dB, which are described by the following equations: G (20 dB/V) = 20 × VGN – 5, VREF = 2.500 V (4) G (20 dB/V) = 30 × VGN – 5, VREF = 1.666 V (5) G (20 dB/V) = 40 × VGN – 5, VREF = 1.250 V (6) 20 40 35 30 25 15 10 50 45 GAIN (dB) 30dB/V 40dB/V 20dB/V 0.5 1.0 1.5 2.0 2.5 3.0 00540-042 LINEAR-IN-dB RANGE OF AD604 WITH PREAMPLIFIER SET TO 14dB Figure 42. Ideal Gain Curves vs. VGN From these equations, it can be seen that all gain curves intercept at the same −5 dB point; this intercept is +6 dB higher (+1 dB) if the preamplifier gain is set to +20 dB or +14 dB lower (−19 dB) if the preamplifier is not used at all. Outside the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 dB of range. For a given gain scaling, VREF can be calculated as shown in Equation 7. Scale Gain VREF dB/V 20 V 500 .2 × = (7) Usable gain control voltage ranges are 0.1 V to 2.9 V for the 20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN voltages of less than 0.1 V are not used for gain control because below 50 mV the channel (preamplifier and DSX) is powered down. This can be used to conserve power and, at the same time, to gate off the signal. The supply current for a powered- down channel is 1.9 mA; the response time to power the device on or off is less than 1 μs. ACTIVE FEEDBACK AMPLIFIER (FIXED-GAIN AMP) To achieve single-supply operation and a fully differential input to the DSX, an active feedback amplifier (AFA) is used. The AFA is an op amp with two gm stages; one of the active stages is used in the feedback path (therefore the name), while the other is used as a differential input. Note that the differential input is an open-loop gm stage that requires it to be highly linear over the expected input signal range. In this design, the gm stage that senses the voltages on the attenuator is a distributed one; for example, there are as many gm stages as there are taps on the ladder network. Only a few of them are on at any one time, depending on the gain control voltage. The AFA makes a differential input structure possible because one of its inputs (G1) is fully differential; this input is made up of a distributed gm stage. The second input (G2) is used for feedback. The output of G1 is some function of the voltages sensed on the attenuator taps, which is applied to a high-gain amplifier (A0). Because of negative feedback, the differential input to the high-gain amplifier has to be zero; this in turn implies that the differential input voltage to G2 times gm2 (the transconductance of G2) has to be equal to the differential input voltage to G1 times gm1 (the transconductance of G1). Therefore, the overall gain function of the AFA is 2 R 2 R 1 R g g V V m2 m1 ATTEN OUT + × = (8) where: VOUT is the output voltage. VATTEN is the effective voltage sensed on the attenuator. (R1 + R2)/R2 = 42 gm1/gm2 = 1.25 The overall gain is thus 52.5 (34.4 dB). www. BDTI C. com/ADI

The AFA offers the following additional features: • The ability to invert the signal by switching the positive and negative inputs to the ladder network • The possibility of using DSX1 input as a second signal input • Fully differential high-impedance inputs when both preamplifiers are used with one DSX (the other DSX could still be used alone) • Independent control of the DSX common-mode voltage Under normal operating conditions, it is best to connect a decoupling capacitor to VOCM, in which case, the common- mode voltage of the DSX is half the supply voltage, which allows for maximum signal swing. Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be used as another signal input, the only limitation being the rather low slew rate of the VOCM buffer. If the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the DSX; again, this is done for level shifting and to eliminate any dc offsets contributed by the DSX (see the AC Coupling section). www. BDTI C. com/ADI

12 APPLICATIONS INFORMATION The basic circuit in Figure 43 shows the connections for one channel of the AD604. The signal is applied at Pin 5. RGN is normally 0, in which case the preamplifier is set to a gain of 5 (14 dB). When FBK1 is left open, the preamplifier is set to a gain of 10 (20 dB), and the gain range shifts up by 6 dB. The ac coupling capacitors before −DSX1 and +DSX1 should be selected according to the required lower cutoff frequency. In this example, the 0.1 μF capacitors, together with the 175 Ω seen looking into each of the DSXx input pins, provide a −3 dB high-pass corner of about 9.1 kHz. The upper cutoff frequency is determined by the bandwidth of the channel, which is 40 MHz. Note that the signal can be simply inverted by connecting the output of the preamplifier to −DSX1 instead of +DSX1; this is due to the fully differential input of the DSX. 11 10 9 8 1 2 3 4 7 6 5 13 16 15 14 24 23 22 21 20 19 18 17 AD604 VGN RGN +2.5V +5V –5V OUT –DSX1 +DSX1 PAI1 FBK1 PAO1 COM1 COM2 PAI2 FBK2 PAO2 +DSX2 VGN1 VREF VPOS GND1 OUT1 VNEG VNEG VPOS GND2 OUT2 VOCM 0.1µF 0.1µF VIN 0.1µF RL 500Ω 3 –DSX2 VGN2 0.1µF 00540-04 Figure 43. Basic Connections for a Single Channel In Figure 43, the output is ac-coupled for optimum performance. For dc coupling, as shown in Figure 52, the capacitor can be eliminated if VOCM is biased at the same 3.3 V common-mode voltage as the analog-to-digital converter, AD9050. VREF requires a voltage of 1.25 V to 2.5 V, with between 40 dB/V and 20 dB/V gain scaling, respectively. Voltage VGN controls the gain; its nominal operating range is from 0.25 V to 2.65 V for 20 dB/V gain scaling and 0.125 V to 1.325 V for 40 dB/V scaling. When VGNx is grounded, the channel powers down and disables its output. COM1 is the main signal ground for the preamplifier and needs to be connected with as short a connection as possible to the input ground. Because the internal feedback resistors of the preamplifier are very small for noise reasons (8 Ω and 32 Ω nominally), it is of utmost importance to keep the resistance in this connection to a minimum. Furthermore, excessive inductance in this connection can lead to oscillations. Because of the ultralow noise and wide bandwidth of the AD604, large dynamic currents flow to and from the power supply. To ensure the stability of the part, careful attention to supply decoupling is required. A large storage capacitor in parallel with a smaller high-frequency capacitor connected at the supply pins, together with a ferrite bead coming from the supply, should be used to ensure high-frequency stability. To provide for additional flexibility, COM1 can be used to disable the preamplifier. When COM1 is connected to VP, the preamplifier is off, yet the DSX portion can be used independently. This may be of value when cascading the two DSX stages in the AD604. In this case, the first DSX output signal with respect to noise is large and using the second preamplifier at this point would waste power (see Figure 44). www. BDTI C. com/ADI

VG 13 16 15 14 19 18 17 24 23 22 21 20 12 11 10 9 8 1 2 3 4 7 6 5 AD604 –5V +5V VREF RF OUT –5V +5V 8 7 6 5 1 2 3 4 AD711 NC OUT AD835 +5V –5V –5V +5V 2 VSET (<0V) –DSX1 +DSX1 PAI1 FBK1 PAO1 COM1 COM2 PAI2 FBK2 PAO2 +DSX2 –DSX2 VGN1 VREF VPOS GND1 OUT1 VNEG VNEG VPOS GND2 OUT2 VOCM VGN2 FB FB +5V –5V ALL SUPPLY PINS ARE DECOUPLED AS SHOWN. 1V OFFS NULL C1 0.1µF C2 0.1µF VIN (MAX 800mV p-p) R1 49.9Ω C3 0.1µF C4 0.1µF C7 0.1µF C6 0.56µF R2 453Ω R3 1kΩ C7 0.33µF V1 = VIN × G R4 2kΩ C8 0.33µF 8 7 6 5 1 2 3 4 C9 0.33µF R5 2kΩ R6 2kΩ – (A)2 IF V1 = A × cos (wt) Y1 Y2 VN Z X1 X2 VP W – (V1)2 LOW- PASS FILTER R7 1kΩ C10 1µF C11 1µF R8 2kΩ +VS –VS OFFS NULL C12 0.1µF C13 0.1µF 00540-044 Figure 44. AGC Amplifier with 82 dB of Gain Range ULTRALOW NOISE AGC AMPLIFIER WITH 82 dB TO 96 dB GAIN RANGE Figure 44 shows an implementation of an AGC amplifier with 82 dB of gain range using a single AD604. The signal is applied to connector VIN and, because the signal source is 50 Ω, a terminating resistor (R1) of 49.9 Ω is added. The signal is then amplified by 14 dB (Pin FBK1 shorted to PAO1) through the Channel 1 preamplifier and is further processed by the Channel 1 DSX. Next, the signal is applied directly to the Channel 2 DSX. The second preamplifier is powered down by connecting its COM2 pin to the positive supply as explained in the Preamplifier section. C1 and C2 level shift the signal from the preamplifier into the first DSX and, at the same time, eliminate any offset contribution of the preamplifier. C3 and C4 have the same offset cancellation purpose for the second DSX. Each set of capacitors, combined with the 175 Ω input resistance of the corresponding DSX, provides a high-pass filter with a −3 dB corner frequency of about 9.1 kHz. VOCM is decoupled to ground by a 0.1 μF capacitor, while VREF can be externally provided; in this application, the gain scale is set to 20 dB/V by applying 2.500 V. Because each DSX amplifier operates from a single 5 V supply, the output is ac-coupled via C6 and C7. The output signal can be monitored at the connector labeled RF OUT. Figure 45 and Figure 46 show the gain range and gain error for the AD604 connected as shown in Figure 44. The gain range is −14 dB to +82 dB; the useful range is 0 dB to +82 dB if the RF output amplitude is controlled to ±400 mV (+2 dBm). The main limitation on the lower end of the signal range is the input capability of the preamplifier. This limitation can be overcome by adding an attenuator in front of the preamplifier, but that would defeat the advantage of the ultralow noise preamplifier. It should be noted that the second preamplifier is not used because its ultralow noise and the associated high-power consumption are overkill after the first DSX stage. It is disabled in this application by connecting the COM2 pin to the positive supply. Nevertheless, the second preamplifier can be used, if so desired, and the useful gain range increases by 14 dB to encompass 0 dB to 96 dB of gain. For the same +2 dBm output, this allows signals as small as −94 dBm to be measured. To achieve the highest gains, the input signal must be band- limited to reduce the noise; this is especially true if the second preamplifier is used. If the maximum signal at OUT2 of the AD604 is limited to ±400 mV (+2 dBm), the input signal level at the AGC threshold is +25 μV rms (−79 dBm). The circuit as shown in Figure 44 has about 40 MHz of noise bandwidth; the 0.8 nV/√Hz of input referred voltage noise spectral density of the AD604 results in an rms noise of 5.05 μV in the 40 MHz bandwidth. www. BDTI C. com/ADI

The 50 Ω termination resistor, in parallel with the 50 Ω source resistance of the signal generator, forms an effective resistance of 25 Ω as seen by the input of the preamplifier, creating 4.07 μV of rms noise at a bandwidth of 40 MHz. The noise floor of this channel is consequently 6.5 μV rms, the rms sum of these two main noise sources. The minimum detectable signal (MDS) for this circuit is +6.5 μV rms (−90.7 dBm). Generally, the measured signal should be about a factor of three larger than the noise floor, in this case 19.5 μV rms. Note that the 25 μV rms signal that this AGC circuit can correct for is just slightly above the MDS. Of course, the sensitivity of the input can be improved by band-limiting the signal; if the noise bandwidth is reduced by a factor of four to 10 MHz, the noise floor of the AGC circuit with a 50 Ω termination resistor drops to +3.25 μV rms (−96.7 dBm). Further noise improvement can be achieved by an input matching network or by transformer coupling of the input signal. VGN (V) –30 90 80 70 60 20 50 40 30 –20 –10 0 10 GAIN (dB) f = 1MHz 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 00540-045 Figure 45. Cascaded Gain vs. VGN (Based on Figure 44) VGN (V) –4 –3 4 3 2 1 0 –1 –2 GAIN ERROR (dB) f = 1MHz 0.2 0.7 1.2 1.7 2.2 2.7 00540-046 Figure 46. Cascaded Gain Error vs. VGN (Based on Figure 44) The descriptions of the detector circuitry functions, comprising a squarer, a low-pass filter, and an integrator, follow. At this point, it is necessary to make some assumptions about the input signal. The following explanation of the detector circuitry presumes an amplitude modulated RF carrier where the modulating signal is at a much lower frequency than the RF signal. The AD835 multiplier functions as the detector by squaring the output signal presented to it by the AD604. A low-pass filter following the squaring operation removes the RF signal component at twice the incoming signal frequency, while passing the low frequency AM information. The following integrator with a time constant of 2 ms set by R8 and C11 integrates the error signal presented by the low-pass filter and changes VG until the error signal is equal to VSET. For example, if the signal presented to the detector is V1 = A × cos(ωt) as indicated in Figure 44, the output of the squarer is −(V1)2/1 V. The reason for all the minus signs in the detection circuitry is the necessity of providing negative feedback in the control loop; actually, if VSET becomes greater than 0 V, the control loop provides positive feedback. Squaring A × cos(ωt) results in two terms, one at dc and one at 2ω; the following low- pass filter passes only the −(A)2/2 dc term. This dc voltage is now forced equal to the voltage, VSET, by the control loop. The squarer, together with the low-pass filter, functions as a mean- square detector. As should be evident by controlling the value of VSET, the amplitude of the voltage V1 can be set at the input of the AD835; if VSET equals −80 mV, the AGC output signal amplitude is ±400 mV. Figure 47 shows the control voltage, VGN, vs. the input power at frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at an output regulated level of 2 dBm (800 mV p-p). The AGC threshold is evident at a PIN of about −79 dBm; the highest input power that can still be accommodated is about +3 dBm. At this level, the output starts being distorted because of clipping in the preamplifier. 4.5 4.0 0.5 3.5 3.0 1.0 2.5 2.0 1.5 CONTROL VOLTAGE (V) 1MHz 10MHz 00540-047 PIN (dBm) –80 –70 –60 –50 –40 –30 –20 –10 0 10 Figure 47. Control Voltage vs. Input Power of the Circuit in Figure 44 As previously mentioned, the second preamplifier can be used to extend the range of the AGC circuit in Figure 44. Figure 48 shows the modifications that must be made to Figure 46 to achieve 96 dB of gain and dynamic range. Because of the extremely high gain, the bandwidth must be limited to reject some of the noise. Furthermore, limiting the bandwidth helps suppress high- frequency oscillations. The added components act as a low-pass filter and dc block (C5 decouples the 2.5 V common-mode output of the first DSX). The ferrite bead has an impedance of about 5 Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at 100 MHz. The bead, combined with R2 and C6, forms a 1 MHz low-pass filter. www. BDTI C. com/ADI

At 1 MHz, the attenuation is about −0.2 dB, increasing to −6 dB at 10 MHz and −28 dB at 100 MHz. Signals less than approximately 1 MHz are not significantly affected. 2 Figure 49 shows the control voltage vs. the input power at 1 MHz to the circuit shown in Figure 48; note that the AGC threshold is at −95 dBm. The output signal level is set to 800 mV p-p by applying −80 mV to the VSET connector. 12 11 10 9 8 1 2 3 4 7 6 5 13 16 15 14 24 23 22 21 20 19 18 17 AD604 FB –DSX1 +DSX1 PAI1 FBK1 PAO1 COM1 COM2 PAI2 FBK2 PAO2 +DSX2 –DSX2 VGN1 VREF VPOS GND1 OUT1 VNEG VNEG VPOS GND2 OUT2 VOCM VGN2 C5 0.1µF R2 499Ω C6 560pF C3 0.1µF FAIR-RITE #2643000301 00540-048 Figure 48. Modifications of the AGC Amplifier to Create 96 dB of Gain Range 4.5 4.0 0 3.5 3.0 1.0 2.5 2.0 1.5 CONTROL VOLTAGE (V) 1MHz 0.5 PIN (dBm) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 00540-049 13 16 15 14 19 18 17 24 23 22 21 20 Figure 49. Control Voltage vs. Input Power of the Circuit in Figure 48 ULTRALOW NOISE, DIFFERENTIAL INPUT- DIFFERENTIAL OUTPUT VGA Figure 50 shows how to use both preamplifiers and DSXs to create a high impedance, differential input-differential output VGA. This application takes advantage of the differential inputs to the DSXs. Note that the input is not truly differential in the sense that the common-mode voltage needs to be at ground to achieve maximum input signal swing. This has largely to do with the limited output swing capability of the output drivers of the preamplifiers; they clip around ±2.2 V due to having to drive an effective load of about 30 Ω. If a different input common-mode voltage needs to be accommodated, ac coupling (as in Figure 48) is recommended. The differential gain range of this circuit runs from 6 dB to 54 dB, which is 6 dB higher than each individual channel of the AD604 because the DSX inputs now see twice the signal amplitude compared with when they are driven single-ended. 12 11 10 9 8 1 2 3 4 7 6 5 AD604 FB FB +5V –5V ALL SUPPLY PINS ARE DECOUPLED AS SHOWN. +5V –5V –5V +5V VG VREF VOUT+ VOUT VIN+ VIN– – –DSX1 +DSX1 PAI1 FBK1 PAO1 COM1 COM2 PAI2 FBK2 PAO2 +DSX2 –DSX2 VGN1 VREF VPOS GND1 OUT1 VNEG VNEG VPOS GND2 OUT2 VOCM VGN2 C13 0.1µF C12 0.1µF C1 0.1µF C2 0.1µF C4 0.1µF C3 0.1µF C5 0.1µF C7 0.1µF R1 453Ω R2 453Ω C6 0.1µF 00540-050 Figure 50. Ultralow Noise, Differential Input-Differential Output VGA Figure 51 displays the output signals VOUT+ and VOUT− after a −20 dB attenuator formed between the 453 Ω resistors shown in Figure 50 and the 50 Ω loads presented by the oscilloscope plug-in. R1 and R2 are inserted to ensure a nominal load of 500 Ω at each output. The differential gain of the circuit is set to 20 dB by applying a control voltage, VGN, of 1 V; the gain scaling is 20 dB/V for a VREF of 2.500 V; the input frequency is 10 MHz, and the differential input amplitude is 100 mV p-p. The resulting differential output amplitude is 1 V p-p as can be seen on the scope photo when reading the vertical scale as 200 mV/div. 100 90 10 0% 20ns 20mV 20mV NOTES 1. THE OUTPUT AFTER 10× ATTENUATER FORMED BY 453ΩTOGETHER WITH 50Ω OF 7A24 PLUG-IN. –500mV ACTUAL VOUT +500mV 00540-054 Figure 51. Output of VGA in Figure 50 for VGN = 1 V www. BDTI C. com/ADI

MEDICAL ULTRASOUND TGC DRIVING THE AD9050, A 10-BIT, 40 MSPS ADC The AD604 is an ideal candidate for the time gain control (TGC) amplifier that is required in medical ultrasound systems to limit the dynamic range of the signal that is presented to the ADC. Figure 52 shows a schematic of an AD604 driving an AD9050 in a typical medical ultrasound application. The gain is controlled by means of a digital byte that is input to an AD7226 DAC that outputs the analog gain control signal. The output common-mode voltage of the AD604 is set to VPOS/2 by means of an internal voltage divider. The VOCM pin is bypassed with a 0.1 μF capacitor to ground. The DSX output is optionally filtered and then buffered by an AD9631 op amp, a low distortion, low noise amplifier. The op amp output is ac-coupled into the self-biasing input of an AD9050 ADC that is capable of outputting 10 bits at a 40 MSPS sampling rate. 20 27 28 26 22 14 13 10 15 16 17 18 19 24 25 3 4 9 6 5 AD9050 COMP VREFIN VREFOUT REFBP AINB D8 D5 D6 D7 D4 D3 ENCODE OR AIN D2 D1 (LSB) D0 VDD 13 16 15 14 18 17 24 23 22 21 20 19 12 11 10 9 8 7 1 2 3 4 6 5 AD604 1kΩ CLK J2 12 11 20 19 18 17 16 15 14 13 10 9 8 1 2 3 4 7 6 5 AD7226 AGND VREF VSS DGND DB6 DB5 DB4 A1 A0 DB1 DB2 DB3 VREF +15V DIGITAL GAIN CONTROL FILTER 2 AD9631 3 6 OPTIONAL –IN –DSX1 +DSX1 PAI1 FBK1 PAO1 COM1 VGN1 VREF VPOS GND1 OUT1 VNEG 1kΩ 1kΩ 0.1µF 0.1µF ANALOG INPUT 0.1µF 0.1µF A/D OUTPUT (MSB) D9 +IN OUT COM2 PAI2 FBK2 PAO2 +DSX2 –DSX2 VNEG VPOS GND2 OUT2 VOCM VGN2 50Ω 50Ω 100Ω VDD 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF DB7 (MSB) VOUTA VOUTB VOUTC VOUTD VDD DB0 (LSB) WR 00540-051 +5V 0.1µF –5V 0.1µF Figure 52. TGC Circuit for Medical Ultrasound Application www. BDTI C. com/ADI

13 16 15 14 19 18 17 24 23 22 21 20 12 11 10 9 8 1 2 3 4 7 6 5 AD604 +5V –5V IN1 VREF OUT1 VOCM VG1 VG2 OUT2 NOTE 2 NOTE 3 NOTE 3 IN2 PAO2 PAO1 –DSX1 +DSX1 PAI1 FBK1 PAO1 COM1 COM2 PAI2 FBK2 PAO2 +DSX2 –DSX2 VGN1 VREF VPOS GND1 OUT1 VNEG VNEG VPOS GND2 OUT2 VOCM VGN2 OPTIONAL R3 RGN C6 0.1µF C3 0.1µF C1 0.1µF R2 RGN C4 0.1µF C2 5pF R1 500Ω C5 0.1µF C12 0.1µF C11 0.1µF C10 0.1µF C9 0.1µF C8 5pF R4 500Ω 0.1µF C7 0.1µF NOTES 1. PAO1 AND PAO2 ARE USED TO MEASURE PREAMPS. 2. RGN = 0 NOMINALLY; PREAMP GAIN = 5, RGN = OPEN; PREAMP GAIN = 10. 3. WHEN M IN SERIES. 0540-052 EASURING BW WITH 50ΩSPECTRUM ANALYZER, USE 450Ω 0 Figure 53. Basic Test Board PAI OUT R A HP3577B 450Ω 50Ω HP11636B POWER SPLITTER 0.1µF 49.9Ω AD604 DUT 00540-053 Figure 54. Setup for Gain Measurements www. BDTI C. com/ADI

EVALUATION BOARD 2 Figure 55 is a photograph of the AD604 evaluation board assembly. Multiple input connections, test points, jumper selectable options, and on-board trims offer convenience when configuring the AD604 in various operating modes. The evaluation board requires only a dual 5 V supply capable of 200 mA or higher to operate both channels. Prior to shipment, the evaluation board is fully tested. Users need only attach power supply leads and the appropriate test equipment to the board. Because of this flexibility, not all component positions on the board are populated when the board is shipped. Installing or changing additional parts is optional. The AD604-EVALZ is fabricated on a 4-layer board with inner power and ground layers. The AD604 is a stable, trouble-free device; however, as with all high-frequency integrated circuits, power and ground planes help to ensure consistency in performance. 00540-05 00540-056 5 Figure 56. AD604 Evaluation Board—Component Side Silk Screen DSX INPUT CONNECTIONS The DSX inputs can be connected in single-ended or differential configurations. SMA connectors are provided for each of the inputs and are labeled CHx VGA IN (+) and CHx VGA IN (−). JP6 and JP15 select between the preamplifier outputs and the DSX inputs. For direct drive of the Channel 1 VGA, insert a jumper in the top position of JP6. For direct drive of the Channel 2 VGA, insert a jumper in JP14 and verify that there are no jumpers in JP12 and JP13. Refer to the schematic shown in Figure 61 for circuit details. Differential DSX Inputs Differential inputs are possible using both polarities of the VGA SMA connectors and appropriate jumpers. Inserting a jumper in the lower position of JP5 selects the negative input of Channel 1. A jumper in the top position of JP6 selects the positive input of Channel 1. A jumper in the JP16 rightmost position selects the negative input of Channel 2, and a jumper in JP14 selects the positive input. Verify that there are no jumpers in JP15 or JP13. Figure 55. AD604 Evaluation Board Assembly USING THE PREAMPLIFIER To use the preamplifiers, simply connect a signal source to CH1 PREAMP IN and/or CH2 PREAMP IN via the SMA connectors. Referring to the schematic in Figure 61, the input lines are terminated with 50 Ω resistors at locations R7 and R8. Because the VGA section of the AD604 uses a single 5 V supply, the DSX inputs are ac-coupled. Decoupling capacitors are provided on the evaluation board. To enable the preamplifiers, insert jumpers in the JP8 and JP9 rightmost positions; this connects COM1 and COM2 to ground. Power down the preamplifiers by inserting jumpers in the JP8 and JP9 leftmost positions. The DSX input impedance is approximately 200 Ω. Optional 66.5 Ω resistors can be installed across the inputs at positions R5, R6, R9, and R10 to establish a 50 Ω terminating load. www. BDTI C. com/ADI

Connecting the DSX Inputs to the Preamplifiers To connect the DSX inputs to the preamplifiers, install jumpers in the JP6 lower position and in JP15. Verify that the jumpers in JP13 and JP14 are removed. Cascaded DSX To channel-cascade the two channels, insert a jumper in JP13. The resulting single-channel gain range is 96 dB. Verify that JP14 and JP15 are removed. The gains of cascaded VGAs can be controlled independently or in common. For common control, insert a jumper in the top position of JP4. To use the trimmer as a gain control, insert a jumper in JP1. For external control, remove JP1 and connect a signal source at VGN1 or VGN2 test loop. PREAMPLIFIER GAIN Jumpers in JP7 and JP12 select between two preamplifier gains: 14 dB and 20 dB. Intermediate gains are derived by installing resistors in the R11 and R12 positions. The 14 dB and 20 dB preset gains are accurate due to close matching of thin film resistors. The gain accuracy after installing external resistors is subject to inherent tolerance of absolute accuracy. OUTPUTS The DSX outputs are available on OUT1 and OUT2 SMA connectors and are series terminated with decoupling capacitors and 49.9 Ω series resistors. These components can be replaced to accommodate other output impedances. DC OPERATING CONDITIONS Table 4 lists the trimmers and their functions provided for convenient dc level adjustments of gain, reference voltage, and output common-mode voltage. Table 5 lists the jumpers and their functions. Table 4. Trimmer Functions Trimmer Function R1 Gain of Channel 1 R2 Reference voltage adjustment R3 Output common-mode voltage adjustment R4 Channel 2 gain adjustment Table 5. Jumpers Jumper No. Function 1 Connects R1 gain adjust wiper to VGN1. 2 Connects R2 reference voltage trimmer to VREF input. 3 Connects common-mode voltage trimmer to VOCM. 4 Connects VGN2 to R4 Channel 2 gain trimmer or to VGN1 or common gain adjustment. 5 Connects –DSX1 to CH1 VGA IN (−) or to ground. 6 Connects +DSX1 (ac-coupled) to preamplifier output of Channel 1 or to the CH 1 VGA IN (+) SMA connector. 7 When open, the Preamp 1 gain is 20 dB; Preamp 1 gain is 14 dB when a shunt is installed. 8 Shunt in left position disables Preamp 1; shunt in rightmost position enables Preamp 1. 9 Shunt in left position disables Preamp 2; shunt in rightmost position enables Preamp 2. 12 When open, the Preamp 2 gain is 20 dB; Preamp 2 gain is 14 dB when a shunt is installed. 13 Cascades DSX2 with DSX 1 when a jumper is inserted. 14 Connects +DSX2 (ac-coupled) to preamplifier output of Channel 2 or to the CH 2 VGA IN (+) SMA connector. 15 Connects +DSX2 (ac-coupled) to preamplifier output of Channel 2. 16 Connects –DSX2 to CH2 VGA IN (−) or to ground. www. BDTI C. com/ADI

0-057 2 EVALUATION BOARD ARTWORK AND SCHEMATIC 00540-059 Figure 59. Internal Ground Plane 0054 0054 Figure 57. Component Side Copper 00540-058 Figure 58. Secondary Side Copper 0-060 Figure 60. Internal Power Plane www. BDTI C. com/ADI

R12 –DSX1 PAO1 OUT1 VREF VGN1 +DSX1 15 4 3 2 1 13 14 16 17 18 19 20 10 7 9 8 6 5 C8 0.1µF C9 0.1µF C7 0.1µF C14 0.1µF C13 0.1µF C2 0.1µF C4 0.1µF C6 0.1µF 12 11 24 23 22 21 FBK1 PAI1 COM1 COM2 PAO2 +DSX2 FBK2 PAI2 OUT2 VGN2 VOCM GND2 VPOS VNEG GND1 VNEG AD604 U1 R5 JP7 R6 +DSX1 R11 –DSX1 PAO1 PAI1 +5V JP6 JP8 JP9 C10 0.1µF C11 0.1µF R10 JP12 R9 –DSX2 PAO2 R8 49.9Ω R7 49.9Ω PAI2 JP15 JP14 JP13 VGN2 C12 1nF R4 1kΩ +5V JP4 A B GN2 ADJ VOCM R3 1kΩ +5V JP3 A B VOCM ADJ +5V –5V –5V +5V OUT2 OUT1 R13 49.9Ω R2 10kΩ R1 10kΩ +5V +5V JP2 C5 1nF JP1 GN1 ADJ A B VGN1 JP5 JP16 A B C3 10µF 10V C1 10µF 10V + + J1 CH1 VGA IN (–) J2 CH1 VGA IN (+) J7 CH2 VGA IN (+) J8 CH1 VGA IN (–) J5 CH 1 PREAMP IN J6 CH 2 PREAMP IN NOTES 1. PARTS IN GRAY ARE NOT INSTALLED. VREF GND1 GND2 GND3 GND4 GND +DSX2 –DSX2 VPOS J4 OUT2 VREF ADJ R14 49.9Ω J3 OUT1 00540-061 Figure 61. Evaluation Board Schematic Table 6. Bill of Materials Qty. Type Description Reference Designator Manufacturer Part Number 1 Test loop Red +5 V Components Corp. TP-104-01-02 1 Test loop Blue −5 V Components Corp. TP-104-01-06 5 Test loop Black GND, GND1, GND2, GND3, GND4 Components Corp. TP-104-01-00 14 Test loop Purple +DSX1, +DSX2, −DSX1, −DSX2, OUT1, OUT2, PAI1, PAI2, PAO1, PAO2, VGN1, VGN2, VOCM, VREF Components Corp. TP-104-01-07 2 Capacitor Tantalum 10 μF, 10 V, A size C1, C3 Nichicon F931A106MAA 10 Capacitor 0.1 μF, 50 V, 20%, 0805 C2, C4, C6, C7, C8, C9, C10, C11, C13, C14 Panasonic PCC1840CT-ND 2 Capacitor SM, 1000 pF, 50 V, 0805 C5, C12 Panasonic ECU-V1H102KBN 8 Connector SMA FEM PC Mount, RA J1, J2, J3, J4, J5, J6, J7, J8 Amphenol 901-143-6RFX 8 Header 0.1” center 2-pin JP1, JP2, JP3, JP7, JP12, JP13, JP14, JP15 Berg 69157-2 6 Header 0.1” center 3-pin JP4, JP5, JP6, JP8, JP9, JP16 Molex 22-11-2032 4 Trimmer 10 kΩ, 1/4" SM R1, R2, R3, R4 Bourns 3361P-1-103G 4 Resistor 49.9 Ω, 1%, 1/10 W, 0805 R7, R8, R13, R14 Panasonic ERJ-6ENF49R9 1 Integrated circuit 40 MHz dual low noise VGA U1 Analog Devices, Inc. AD604AR 10 Jumper Mini jumper; install in headers at JP1, JP2, JP3, JP4 lower, JP5 lower, JP6 lower, JP8 right, JP9 right, JP15, JP16 left www. BDTI C. com/ADI

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. COMPLIANT TO JEDEC STANDARDS MS-001 071006-A OUTLINE DIMENSIONS 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) BSC 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) MAX SEATING PLANE 0.015 (0.38) MIN 0.005 (0.13) MIN 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) MAX 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) GAUGE PLANE 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) Figure 62. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45° 1.27 (0.0500) 0.40 (0.0157) COPLANARITY 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 8° 0° 24 13 12 1 1.27 (0.0500) BSC COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 060706-A Figure 63. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) www. BDTI C. com/ADI

COMPLIANT TO JEDEC STANDARDS MO-150-AG 060106-A 24 13 12 1 8.50 8.20 7.90 8.20 7.80 7.40 5.60 5.30 5.00 SEATING PLANE 0.05 MIN 0.65 BSC 2.00 MAX 0.38 0.22 COPLANARITY 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8° 4° 0° Figure 64. 24-Lead Shrink Small Outline Package [SSOP] (RS-24) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD604AN −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD604ANZ1 −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD604AR −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD604AR-REEL −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD604ARZ1 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD604ARZ-RL1 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD604ARS −40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP] RS-24 AD604ARS-REEL −40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP] RS-24 AD604ARS-REEL7 −40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP] RS-24 AD604ARSZ1 −40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP] RS-24 AD604ARSZ-RL1 −40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP] RS-24 AD604ARSZ-R71 −40°C to +85°C 24-Lead Shrink Small Outline Package [SSOP] RS-24 AD604-EVALZ1 Evaluation Board 1 Z = RoHS Compliant Part. www. BDTI C. com/ADI

NOTES ©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00540-0-10/08(E) www. BDTI C. com/ADI