Altera Stratix IV GX Reference Manual

Components and Interfaces Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation J2.116 LVDS RX bit 10n or CMOS bit 51 HSMB_RX_D_N10 LVDS or 2.5-V F6 J2.119 LVDS TX bit 11 or CMOS bit 52 HSMB_TX_D_P11 K9 J2.120 LVDS RX bit 11 or CMOS bit 53 HSMB_RX_D_P11 G5 J2.121 LVDS TX bit 11n or CMOS bit 54 HSMB_TX_D_N11 J9 J2.122 LVDS RX bit 11n or CMOS bit 55 HSMB_RX_D_N11 F5 J2.125 LVDS TX bit 12 or CMOS bit 56 HSMB_TX_D_P12 H7 J2.126 LVDS RX bit 12 or CMOS bit 57 HSMB_RX_D_P12 F7 J2.127 LVDS TX bit 12n or CMOS bit 58 HSMB_T ...

General User Input/Output Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation Table 2–22 lists the crystal oscillators component references and manufacturing information. General User Input/Output This section describes the user I/O interface to the FPGA, including the push-buttons, DIP switches, status LEDs, and character LCD. User-Defined Push-Button Switches The development board includes four user-defined push-button switches: three general switches and one CPU reset. For information on the system and safe ...

Memory Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation DDR3 Top Port The DDR3 top port consists of a single DDR3 devices, providing 128 Mbyte with a 16-bit data bus. The board supports addressing for up to 4 times the memory if larger devices become available. This memory interface is designed to run between 300 MHz, the minimum frequency for DDR3, and 533 MHz for a maximum theoretical bandwidth of over 68.2 Gbps. The internal bus in the FPGA is typically 2 or 4 times the width at full rate or half rate resp ...

2–53 Memory November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual Table 2–49 lists the DDR3 component reference and manufacturing information. QDRII+ Top Port 0 The QDRII+ top port 0 consists of a single QDRII+ burst-of-4 SRAM, providing 4 Mbyte with an 18-bit read data bus and an 18-bit write data bus. This memory interface is designed to run between 120 MHz, the minimum frequency for this device, and 400 MHz for a maximum theoretical bandwidth of over 14.4 Gbps for reading and 14.4 Gbps for writing. The internal bu ...

2–19 Configuration, Status, and Setup Elements November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual Table 2–14 lists the JTAG control DIP switch component references and manufacturing information. PCI Express Control DIP switch The PCI Express control DIP switch is provided to enable or disable the different configurations. Table 2–15 shows the switch controls and descriptions. Table 2–16 lists the PCI Express control DIP switch component reference and manufacturing information. Reset Configuration Push-Button S ...

Memory Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation Table 2–51 lists the QDRII+ top port 0 component reference and manufacturing information. QDRII+ Top Port 1 The QDRII+ top port 1 consists of a single QDRII+ burst-of-4 SRAM, providing 4 Mbyte with an 18-bit read data bus and an 18-bit write data bus. This memory interface is designed to run between 120 MHz, the minimum frequency for this device, and 400 MHz for a maximum theoretical bandwidth of over 14.4 Gbps for reading and 14.4 Gbps for writing. Th ...

2–49 Memory November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual U5, U12, U18, U24 pin P3 Address bus DDR3BOT_A2 1.5-V SSTL Class I AH14 U5, U12, U18, U24 pin P7 Address bus DDR3BOT_A1 AG15 U5, U12, U18, U24 pin N3 Address bus DDR3BOT_A0 AK13 U5, U12, U18, U24 pin M3 Bank address bus DDR3BOT_BA2 AE15 U5, U12, U18, U24 pin M3 Bank address bus DDR3BOT_BA1 AD15 U5, U12, U18, U24 pin M3 Bank address bus DDR3BOT_BA0 AF14 U5, U12, U18, U24 pin J3 Row address select DDR3BOT_RASn AW21 U5, U12, U18, U24 pin K3 Column address s ...