Intel i960 Design Manual

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel® i960® RM/RN I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Other brands and names are the property of their respective owners. *

Contents 1.0 Introduction...................................................................................................................................9 2.0 Intel® 80960RM/RN Processor Ball Map......................................................................................9 2.1 Intel® 80960RM/RN Processor PBGA Signal Ball Map.................................................10 3.0 Routing Guidelines .....................................................................................................................11 3.1 Trace Length Limits .......................................................................................................11 4.0 Intel® 80960RM/RN Processor Memory Subsystem ..................................................................12 4.1 ROM, SRAM, or Flash Guidelines.................................................................................12 4.1.1 Layout Guidelines..........................................................................................................13 4.1.2 Wait State Profiles .........................................................................................................13 4.2 SDRAM Guidelines........................................................................................................14 4.2.1 Layout Guidelines..........................................................................................................15 4.2.2 SDRAM Clocking and Clock Buffer Specifications ........................................................20 4.2.3 SDRAM Power Failure Guidelines.................................................................................23 4.2.4 System Assumptions .....................................................................................................23 4.2.5 External Logic Required for Power Failure....................................................................23 5.0 Interrupt Routing.........................................................................................................................25 5.1 Intel® 80960RM/RN Processor Implementation on a MotherBoard...............................25 5.2 Intel® 80960RM/RN Processor Implementation on an Add-in Card ..............................26 6.0 Clocking Guidelines....................................................................................................................27 6.1 Layout Guidelines for Add-in Cards...............................................................................27 6.2 Layout Guidelines for Motherboards..............................................................................28 6.3 Clock Vendors ...............................................................................................................29 7.0 Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................30 8.0 Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................32 9.0 Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations.......................................34 9.1 Providing 3.3 V in a 5 V System ....................................................................................34 9.2 Choosing a Power Source.............................................................................................36 9.3 PCI Adapter Card Power Source...................................................................................37 9.4 VCC5REF Pin Requirement (VDIFF).................................................................................37 9.5 VCCPLL Pins Requirement..............................................................................................38 9.6 Pullups and Pulldown Resistors ....................................................................................38 9.7 FAIL# .............................................................................................................................39 10.0 Processor Power Supply Decoupling .........................................................................................40 10.1 High Frequency Decoupling ..........................................................................................40 10.2 Bulk Decoupling Capacitance........................................................................................41 11.0 Intel® 80960RM/RN Processor Based Reference Design..........................................................42 12.0 Debug Connector Recommendations.........................................................................................43 12.1 PBGA Sockets and Headers .........................................................................................43 12.2 Logic Analyzer Connectivity...........................................................................................45 *

12.3 JTAG Connector and Test Interface..............................................................................48 12.3.1 Intel® i960® RM/RN I/O Processor JTAG Emulator.....................................................48 12.3.2 Intel® i960® RM/RN I/O Processor Target Debug Interface Connector.......................48 12.3.3 Connecting The Emulator To The Target ......................................................................50 12.3.4 Other Tools....................................................................................................................51 13.0 Design for Manufacturability .......................................................................................................52 14.0 Thermal Solutions.......................................................................................................................53 14.1 Thermal Recommendations ..........................................................................................53 14.2 3-Dimensional View: Processor with Heat Sink Attached..............................................54 14.3 PCB Heatsink Hole Dimensions ....................................................................................55 14.4 Clearances of PCI Board and Components ..................................................................57 14.5 Heat Sink Information ....................................................................................................58 14.5.1 Socket Information.........................................................................................................58 14.5.2 Socket-Header Vendor ..................................................................................................58 14.5.3 Burn-in Socket Vendor ..................................................................................................58 14.5.4 Shipping Tray Vendor....................................................................................................59 14.5.5 Logic Analyzer Interposer Vendor .................................................................................59 14.5.6 JTAG Emulator Vendor .................................................................................................59 15.0 References .................................................................................................................................60 15.1 Related Documents .......................................................................................................60 15.2 Electronic Information....................................................................................................60 A Intel® i960® RM I/O Processor Schematics ..............................................................................61 B Intel® IQ80960RM Board Bill of Material ....................................................................................72 C Intel® i960® RN I/O Processor Schematics ..............................................................................76 D Intel® IQ80960RN Board Bill of Material.....................................................................................88 E Intel® IQ80960RM/RN SDRAM Battery Backup PLD Equations................................................92 F Intel® 80960RM/RN Processor PBGA Signal Ball Map..............................................................93 *

Figures 2-1 540L H-PBGA Diagram (Bottom View).......................................................................................10 3-2 Examples of Stubless and Short Stub Traces ............................................................................11 4-3 4 Mbyte Flash Memory System ..................................................................................................13 4-4 Dual-Bank SDRAM Memory Subsystem ....................................................................................15 4-5 SDRAM DIMM Layout Topology #1............................................................................................17 4-6 SDRAM DIMM Layout Topology #2............................................................................................17 4-7 Address and Control Topology for Two Discrete SDRAM Devices ............................................18 4-8 Address and Control Topology for Four or More Discrete SDRAM Devices ..............................18 4-9 Data and DQM Topology for Discrete SDRAM Devices.............................................................19 4-10 Clocking for a Dual-Bank SDRAM DIMM ...................................................................................20 4-11 Clock Routing for a Two Device SDRAM Subsystem.................................................................22 4-12 External Power Failure State Machine .......................................................................................23 4-13 External Power Failure Logic in the System...............................................................................24 5-14 Example Secondary PCI Connector Interrupt Routing ...............................................................26 6-15 PCI Add-in Card Example Configuration ....................................................................................27 6-16 Motherboard Example Configuration..........................................................................................28 9-17 Creating a Power “Island”...........................................................................................................35 9-18 Power Supply Circuit ..................................................................................................................36 9-19 Recommended Power Supply Connection Layout .....................................................................36 9-20 VCC5REF Current-Limiting Resistor .............................................................................................37 9-21 VCCPLL Low-Pass Filter ..............................................................................................................38 9-22 Recommended FAIL# Circuit......................................................................................................39 10-23 High-Frequency Capacitor Values and Layout...........................................................................41 12-24 540L PBGA Header....................................................................................................................43 12-25 540L PBGA Socket.....................................................................................................................44 12-26 Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View.............................................46 12-27 Packard-Hughes Direct Mount (Flex Tape) Interposer - Side View............................................46 12-28 Flex Tape Interposer Application (Add-In Card) .........................................................................47 12-29 Flex Tape Interposer (Top View) ................................................................................................47 12-30 Flex Tape Interposer (Side View) ...............................................................................................47 12-31 JTAG Emulator Connector (Top View) .......................................................................................48 14-32 Conceptual 3-D View of Processor with a Heat Sink..................................................................54 14-33 Hole Dimensions for Passive Heatsink.......................................................................................55 14-34 Board Level Keep Out Areas......................................................................................................56 14-35 Clearances of PCI Board and Components................................................................................57 15-36 Decoupling and 3.3 V Power Schematic ....................................................................................62 15-37 Primary PCI Interface Schematic................................................................................................63 15-38 Memory Controller Schematic ....................................................................................................64 15-39 Flash ROM, UART and LEDs Schematic ...................................................................................65 15-40 Logic Analyzer I/F Schematic .....................................................................................................66 15-41 SDRAM 168-Pin DIMM Schematic.............................................................................................67 15-42 Secondary PCI/80960 Core Schematic......................................................................................68 15-43 Secondary PCI Bus 1/2 Schematic.............................................................................................69 15-44 Secondary PCI Bus 3/4 Schematic.............................................................................................70 15-45 Battery Monitor Schematic..........................................................................................................71 15-46 Decoupling and 3.3 V Power Schematic ....................................................................................77 15-47 Primary PCI Interface Schematic................................................................................................78 15-48 Memory Controller Schematic ....................................................................................................79 15-49 Flash ROM, UART and LEDs Schematic ...................................................................................80 *

15-50 Logic Analyzer I/F Schematic .....................................................................................................81 15-51 SDRAM 168-Pin DIMM Schematic.............................................................................................82 15-52 Secondary PCI/80960 Core Schematic......................................................................................83 15-53 Secondary PCI Bus 1/2 Schematic ............................................................................................84 15-54 Secondary PCI Bus 3/4 Schematic ............................................................................................85 15-55 SPCI Pull-Ups Schematic...........................................................................................................86 15-56 Battery/Monitor Schematic .........................................................................................................87 *

Tables 4-1 Flash Interface Signals ...............................................................................................................12 4-2 ROM, SRAM, or Flash Wait State Profile Programming.............................................................13 4-3 SDRAM Interface Signals...........................................................................................................14 4-4 Drive Strength Programmability Options ....................................................................................16 4-5 DCLKIN Routing and Loading Requirements.............................................................................21 4-6 SDRAM Clock Buffer Information ...............................................................................................22 5-7 Intel® 80960RM/RN Processor Interrupt Routing Signals ..........................................................25 6-8 Low Skew Clock Buffer Information............................................................................................29 7-9 Memory Controller, Core and JTAG Signals ..............................................................................30 7-10 I2C Bus Signals...........................................................................................................................30 7-11 PCI Signals.................................................................................................................................30 8-12 Memory Controller, Core and JTAG Signals ..............................................................................32 8-13 I2C Bus Signals...........................................................................................................................32 8-14 PCI Signals.................................................................................................................................32 9-15 VDIFF Specification for Dual-Power Supply Requirements (3.3 V, 5 V)......................................37 12-16 Logic Analyzer Header Definitions (Mictor) ................................................................................45 12-17 i960® RM/RN I/O Processor Debug Connector Wiring...............................................................49 12-18 i960® RM/RN I/O Processor with PC-1149.1/100F (cable P/N AS01090025-Ax) ......................50 12-19 i960® RM/RN I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx) ......................51 14-20 H-PBGA Package Characteristics ..............................................................................................53 14-21 Heat Sink Vendors and Contacts................................................................................................58 14-22 Socket-Header Vendor ...............................................................................................................58 14-23 Burn-in Socket Vendor................................................................................................................58 14-24 Shipping Tray Vendor.................................................................................................................59 14-25 Logic Analyzer Interposer Vendor ..............................................................................................59 14-26 JTAG Emulator Vendor...............................................................................................................59 15-27 Related Documentation ..............................................................................................................60 15-28 Electronic Information.................................................................................................................60 B-1 Intel® IQ80960RM Bill of Materials .............................................................................................72 D-1 Intel® IQ80960RN Bill of Materials .............................................................................................88 F-1 540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor..................................93 F-2 540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor ..................................98 *

Revision History Rev Date Description of Changes 004 04/2002 • Changed “Thermal Recommendations” section. 003 08/2000 • Added schematics. 002 06/2000 • Updated Trademarks and Branding. • Updated vendor tables. • Minor text rewrites. • Updated Pinout tables. 1.0 06/1998 • Added reference schematics. • Added debug connector recommendations section. • Added more detailed heat-sink drawings. • Updated heat-sink vendor table. 0.9 12/10/97 Original Document *

Introduction 1.0 Introduction This design guide addresses design considerations for designing with either the Intel® i960® RN I/O processor or the Intel® i960® RM I/O processor. Where necessary and applicable, differences in design constraints between the two processors is clarified. The i960 RN I/O Processor is an Intel I/O processor supporting both 64-bit and 32-bit PCI operation. The i960 RM I/O Processor is an Intel I/O processor only supporting 32-bit PCI operation. 2.0 Intel® 80960RM/RN Processor Ball Map Intel® i960® RM/RN I/O processor signals, by design, are located on the PBGA package to simplify signal routing and system implementation. Figure 2-1 shows the RM/RN I/O processor major signal sections. To simplify routing and minimize the number of cross traces, keep this layout in mind when placing components in your system. Individual signals within the respective groups have also been laid out to minimize signal crossings. For detailed signal descriptions refer to the Tuzigoot Processor Target Specification document. Contact your Intel sales representative to obtain a copy of the document. *

Intel® 80960RM/RN Processor Ball Map 10 Design Guide 2.1 Intel® 80960RM/RN Processor PBGA Signal Ball Map Table F-1 and Table F-2 detail the ballout for the 80960RM and 80960RN processor, respectively. See Appendix F. Figure 2-1. 540L H-PBGA Diagram (Bottom View) T AL AK AJ AH AG AF AE AD AC AB AA Y W V U AM R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 T AL AK AJ AH AG AF AE AD AC AB AA Y W V U AM R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Secondary PCI Bus Signals Memory Controller and Miscellaneous Signals Primary PCI Bus Signals Memory Controller Signals *

Routing Guidelines 3.0 Routing Guidelines The order in which signals are routed first and last varies from designer to designer. Some prefer to route all clock signals first, while others prefer to route all high speed bus signals first. Either order can be used, provided the guidelines listed here are followed. Route the RM/RN I/O processor address/data and control signals using a “daisy chain” topology. This topology assumes that no stubs are used to connect any devices on the net. Figure 3-2 shows two possible techniques to achieve a stubless trace. When it is not possible to apply one of these two techniques due to congestion, a very short stub is allowed — preferably not to exceed 250 mils. 3.1 Trace Length Limits For add-in cards, trace lengths from the top of the card edge connector to the RM/RN I/O processor are as follows: • The maximum trace length for all 32-bit interface signals should not exceed 1.5 inches for 32-bit and 64-bit cards. This includes all signals except those listed as ‘Signal Pins’, ‘Interrupt Pins’, and ‘JTAG Pins’ as per PCI Local Bus Specification, Revision 2.1. • The trace length of the additional signals used in the 64-bit extension are limited to 2 inches on all 64-bit cards. • The trace length for the PCI CLK signal is 2.5 inches ± 0.1 inch for 32-bit and 64-bit cards and should be routed to only a single load. Figure 3-2. Examples of Stubless and Short Stub Traces <250 mils Stubless Short Stub *

Intel® 80960RM/RN Processor Memory Subsystem 12 Design Guide 4.0 Intel® 80960RM/RN Processor Memory Subsystem The RM/RN I/O processor integrates a memory controller to provide a direct interface between the RM/RN I/O processor and its local memory subsystem. The memory controller supports: • Up to 16 Mbytes of 8-bit Flash, ROM, or SRAM • Between 8 and 128 Mbytes of 64-bit synchronous DRAM (SDRAM) • Between 4 and 64 Mbytes of 32-bit synchronous DRAM for low cost solutions • Single-bit error correction, double-bit and nibble detection support (ECC) The Flash interface provides an 8-bit data bus, 23-bit address bus, and control to support up to two 64 Mbit Bulk-Erase or Boot-Block Flash devices. The Flash devices provide storage for the RM/RN I/O processor initialization code. The memory controller provides a separate SDRAM interface from the Flash interface. The SDRAM interface consists of a 66 MHz, 64-bit wide data path to support 528 Mbytes/sec throughput. An 8-bit Error Correction Code (ECC) across each 64-bit word improves system reliability. • The memory controller supports two banks of SDRAM in the form of a single two-bank dual inline memory module (DIMM) or two single-bank DIMMs. • The memory controller supports a 32-bit SDRAM data interface. This mode enables lower-cost solutions at the cost of system bandwidth. • The memory controller responds to internal bus memory accesses within its programmed address range and issues the memory request to either the Flash or SDRAM interface. The memory controller provides four chip enables to the memory subsystem. Two chip enables service the SDRAM subsystem (one per bank) and two service the Flash devices. Note: If the design does not follow the listed guidelines, then it is very important that the design be simulated. Even if the guidelines are followed it is still recommended that the design be simulated for proper signal integrity, flight time, and cross talk. 4.1 ROM, SRAM, or Flash Guidelines The RM/RN I/O processor memory controller provides an interface to two banks of static memory ranging from 64 Kbytes to 16 Mbytes. This memory may be SRAM, ROM, or Flash. Optionally, one of the banks may be dedicated to a UART device. Table 4-1 defines all Flash interface signals. Table 4-1. Flash Interface Signals Pin Name Description RCE[1:0]# Chip Enable - Asserted for all transactions to the Flash device. RWE# Write Enable - Controls the Flash input data buffers. ROE# Output Enable - Asserted for reads, deasserted for writes. Controls the Flash output data buffers for write transactions. RAD[16:0] Address/Data bus - Capable of supporting 16 Mbit of Flash (2Mx8). The data bus is multiplexed on RAD[16:9]. RALE Address Latch Enable - Indicates the transfer of a physical address. RALE is asserted during a Flash address cycle and deasserted before the beginning of the data cycle. *

Intel® 80960RM/RN Processor Memory Subsystem 4.1.1 Layout Guidelines Figure 4-3 illustrates how two Flash devices would interface to the RM/RN I/O processor with the memory controller. The Flash subsystem requires an external latch for address and data demultiplexing on RAD[16:3]. The data is multiplexed on RAD[16:9]. Flash signal loading should not exceed 50 pF. If the system conforms to I2O specification, then a minimum 16 Mbit Flash such as Intel’s 28F016SA is suggested. All traces between the RM/RN I/O processor and Flash/SRAM should not exceed 8 inches. 4.1.2 Wait State Profiles Table 4-2 summarizes various wait state profiles of SRAM and writable non-volatile memory devices. Figure 4-3. 4 Mbyte Flash Memory System Latch Latch RALE RAD[16:0] ROE# RWE# RCE0# RCE1# 80960RM/RN A[20:0] OE# WE# DQ[7:0] CE# Intel 28F016-70 16 Mbit Flash A[20:0] OE# WE# DQ[7:0] CE# Intel 28F016-70 16 Mbit Flash RAD[2:0] A[2:0] A[8:3] A[22:17] A[16:9] DQ[7:0] RAD[8:3] RAD[16:9] Table 4-2. ROM, SRAM, or Flash Wait State Profile Programming Device Speed Address-to-Data Wait States Recovery Wait States ≤ 55 ns 4 0 ≤ 115 ns 8 4 ≤ 175 ns 12 4 *

Intel® 80960RM/RN Processor Memory Subsystem 14 Design Guide 4.2 SDRAM Guidelines The RM/RN I/O processor memory controller supports up to two banks of 66 MHz, 72-bit SDRAM. The memory controller supports 16 Mbit or 64 Mbit technology offering up to 128 Mbytes of ECC protected memory. For low-cost solutions, the memory controller provides a 32-bit SDRAM interface offering up to 64 Mbytes of memory. Table 4-3 shows the SDRAM interface signals. Table 4-3. SDRAM Interface Signals Pin Name Description DCLKOUT SDRAM Clock Out - This is the clock to the off-chip SDRAM clock buffer driven by the RM/RN I/O processor. Section 4.2.2 describes the SDRAM clocking strategy. DCLKIN SDRAM Clock In - This is the clock returning from the off-chip SDRAM clock buffer. Section 4.2.2 describes the SDRAM clocking strategy. SCKE[1:0] Clock enables - One clock after SCKE[1:0] is deasserted, the data is latched on DQ[63:0] and SCB[7:0]. The burst counters within the SDRAM device are not incremented. Deasserting this signal places the SDRAM in self-refresh mode. For normal operation, SCKE[1:0] must be asserted. SDQM[7:0] Data Mask - On a write, these signals disable the data on a byte-by-byte basis, thus preventing certain bytes from being written. On a read, two clocks after asserting SDQM[7:0] the output data bytes from the SDRAM device are disabled. SCE[1:0]# Chip Select - Must be asserted for all transactions to the SDRAM device. One per bank. SWE# Write Enable - Controls the SDRAM data input buffers. Asserting SWE# causes the data on DQ[63:0] and SCB[7:0] to be written into the SDRAM devices. SBA[1:0] SDRAM Bank Selects - Controls which of the internal SDRAM banks to read or write. For 16 Mbit devices (2 banks), only SBA[0] is used while 64 Mbit devices use SBA[1:0]. SA[10] Address bit 10 - If high during a read or write command, then auto-precharge occurs after the command. During a row-activate command, this bit is part of the address. SA[11:0] Address bits 11 through 0 - Indicates the row or column to access depending on the state of SRAS# and SCAS#. SRAS# Row Address Strobe - Indicates that the current address on SA[11:0] is the row. SCAS# Column Address Strobe - Indicates that the current address on SA[11:0] is the column. DQ[63:0] Data Bus - 64-bit wide data bus. SCB[7:0] ECC Bus - 8-bit error correction code which accompanies the data on DQ[63:0]. *

Intel® 80960RM/RN Processor Memory Subsystem 4.2.1 Layout Guidelines The SDRAM subsystem may be implemented with: • up to two banks directly connected on the printed circuit board (32, 64, or 72 bits wide) • up to two 168-pin DIMM sockets (64-bit data bus with or without ECC) • up to two 144-pin SO-DIMM sockets (64-bit data bus without ECC) The memory controller supports either one dual-bank DIMM or two single-bank DIMMs. The 4-Clock 66 MHz 72-bit ECC Unbuffered SDRAM DIMM Specification requires four clock inputs. Figure 4-4 illustrates how two banks of 16 Mbits SDRAM would interface with the RM/RN I/O processor memory controller. SBA[1] is only connected for 64 Mbit SDRAM devices. For the clock routing, refer to Figure 4-10. Figure 4-4. Dual-Bank SDRAM Memory Subsystem DQ[63:0] SCB[7:0] SRAS# SCAS# SWE# SA[10:0] SBA[0] SBA[1] SDQM[7:0] SCKE SCE0# SCE1# 80960RM/RN DQ[63:0] CB[7:0] RAS# CAS# WE# A[10:0] BA0 DQM[7:0] CKE[1:0] CS[3:0]# SDRAM DIMM using 16 Mbit devices DQ[63:0] CB[7:0] RAS# CAS# WE# A[10:0] BA0 DQM[7:0] CKE[1:0] CS[3:0]# SDRAM DIMM using 16 Mbit devices *

Intel® 80960RM/RN Processor Memory Subsystem 16 Design Guide The drive strengths for the SDRAM signals are independently programmable using the SDCR register. Table 4-4 lists some example SDRAM configurations and how the SDCR should be programmed. The RM/RN I/O processor determines the SDRAM configuration with the Serial Presence Detect EEROM (SPD) located on the DIMM. The I2C bus interfaces the RM/RN I/O processor with the SPD. Specific SDRAM signal topologies have been validated for 66 MHz operation. Figure 4-5 through Figure 4-9 illustrate the proven topologies and are recommended. Proper signal integrity analysis should verify any other signal topologies. To minimize crosstalk, SDRAM signal routing should use a minimum of 4 mils spacing and 4 mils trace width. SDRAM clocks (out of the buffer) should use a minimum of 12 mils spacing and 6 mils trace width. Table 4-4. Drive Strength Programmability Options Bus Width Memory Size1 (Mbytes) Form Factor Bank 0 Bank 1 SDCR[3] (DQ) SDCR[4] (CKE0) SDCR[5] (CKE1) SDCR[6] (DQM) SDCR[7] (SA[11:0]) 32 4 On-board 2x1M16 None 0 0 02 0 0 8 4x2M8 0 0 02 0 0 64 8 4x1M16 0 0 02 0 0 16 8X2M8 0 1 02 0 1 8 1 Single-si ded DIMM 4x1M16 0 0 02 0 0 16 8x2M8 0 1 02 0 1 16 1 Double-si ded DIMM 4x1M16 4x1M16 1 0 0 1 1 32 8x2M8 8x2M8 1 1 1 1 1 16 2 Single-si ded DIMMs 4x1M16 4x1M16 1 0 0 1 1 32 4x1M16 8x2M8 1 0 1 1 1 24 8x2M8 4x1M16 1 1 0 1 1 32 8x2M8 8x2M8 1 1 1 1 1 72 16 On-board 9x2M8 None 0 1 02 0 1 16 1 Single-si ded DIMM 9x2M8 0 1 02 0 1 32 1 Double-si ded DIMM 9x2M8 9x2M8 1 1 1 1 1 32 2 Single-si ded DIMMs 9x2M8 9x2M8 1 1 1 1 1 NOTES: 1. The Memory Size column is based on 16 Mbit SDRAM technology. If 64 Mbit SDRAM is populated, then the size will increase appropriately. Each bank’s technology may be programmed independently. 2. If one SDRAM bank is unpopulated, then the corresponding SCKE and SCE is unconnected. *

Intel® 80960RM/RN Processor Memory Subsystem Figure 4-5. SDRAM DIMM Layout Topology #1 Figure 4-6. SDRAM DIMM Layout Topology #2 DIMM DIMM Intel® 80960RM/RN I/O Processor 1 to 8 inches 0 to 0.6 inches Trace Lengths apply for all SDRAM signals except the clock Address, Data and Control 1 to 8 inches SCE[0], SCKE[0] 1 to 8 inches SCE[1], SCKE[1] D IM M 0 In te l® 8 0 9 6 0 R M /R N I/O P ro c e s s o r T ra c e L e n g th s a p p ly fo r a ll S D R A M s ig n a ls e xc e p t th e c lo c k D IM M 1 T ra c e s fro m th e p ro c e s s o r to D IM M 0 m u s t b e 1 to 8 in c h e s T ra c e s fro m th e p ro c e s s o r to D IM M 1 m u s t b e 1 to 8 in c h e s *

Intel® 80960RM/RN Processor Memory Subsystem 18 Design Guide Figure 4-7. Address and Control Topology for Two Discrete SDRAM Devices Figure 4-8. Address and Control Topology for Four or More Discrete SDRAM Devices SDRAM0 Intel® 80960RM/RN I/O Processor SDRAM1 Signals must be 3 to 9.5 inches from the processor and each SDRAM device Applicable to all signals except DQ[63:0], SCB[7:0], and SDQM[7:0]. Address and Control S D R A M 0 In te l® 8 0 9 6 0 R M /R N I/O P ro c e s s o r S D R A M 1 0 to 0.8 inches S D R A M 2 1 to 8 in c h e s 0 to 0.8 inches 0 to 0 .5 in c h 0 to 0 .5 in c h 0 to 0 .5 in c h A p p lic a b le to a ll s ig n a ls e x c e p t D Q [6 3 :0 ], S C B [7 :0 ], a n d S D Q M [7 :0 ]. *

Intel® 80960RM/RN Processor Memory Subsystem The address and control signals for the SDRAM subsystem include SA[11:0], SCAS#, SCE[1:0]#, SCKE[1:0], SRAS#, and SWE#. The SDRAM data signals include DQ[63:0], and SCB[7:0]. Figure 4-9. Data and DQM Topology for Discrete SDRAM Devices S D R A M 0 In te l® 8 0 9 6 0 R M /R N I/O P ro c e s s o r 1 0 o h m s + /- 5 % S D R A M 1 S D Q [6 3 :0 ], S C B [7 :0 ] D a ta s ig n a ls m u s t b e 3 to 8 in c h e s fro m th e p ro c e s s o r a n d e a c h S D R A M d e v ic e 1 0 o h m s + /- 5 % R e s is to rs m u s t b e w ith in 0 .5 in c h e s fro m th e S D R A M d e v ic e S D Q M [7 :0 ] S D Q M s ig n a ls m u s t b e 3 to 9 .5 in c h e s fro m th e p ro c e s s o r a n d e a c h S D R A M d e v ic e *

Intel® 80960RM/RN Processor Memory Subsystem 20 Design Guide 4.2.2 SDRAM Clocking and Clock Buffer Specifications The MCU provides one clock (DCLKOUT) to the SDRAM memory subsystem with a 66 MHz frequency. The 72-bit, 2-bank SDRAM DIMM specification requires four clocks to distribute the loading across eighteen x8 SDRAM components. The board designer must buffer DCLKOUT external to the RM/RN I/O processor with a Texas Instruments CDC318 or equivalent buffer. Refer to Figure 4-10 for the clock routing diagram. External resistors and capacitors are required for proper signal integrity and clock skew management. Note: Any single SDRAM bank will use two clock buffer outputs. Four clock buffer outputs are used only when two SDRAM banks are populated. Figure 4-10. Clocking for a Dual-Bank SDRAM DIMM Intel® 80960RM/RN I/O Processor Clock Buffer SDRAM DIMM DCLKOUT Clock0 DCLKIN 35 ohms +/- 5% 25 ohms +/- 5% X pF 30 ohms +/- 5% Clock1 30 ohms +/- 5% Clock2 30 ohms +/- 5% Clock3 30 ohms +/- 5% Traces from the processor to the resistor must be within 0.5 inches. Traces from the clock buffer to the resistors must be within 0.5 inches. Traces from the processor to the capacitor must be within 0.5 inches. 30 ohms +/- 5% *

Intel® 80960RM/RN Processor Memory Subsystem DCLKOUT and the clock buffer outputs may be between 1 and 8 inches. Each of the four clock buffer outputs must be equal in length. Refer to Table 4-5 for the DCLKIN trace length and capacitance requirements. DCLKIN requires an external capacitor to match the loading seen on the other clock buffer outputs. Traces from the processor to the capacitor must be within 0.5 inches. The DCLKIN trace length must be equal to the clock buffer output trace length plus the additional length specified in Table 4-5. Note: The 66 MHz Unbuffered 168-Pin SDRAM DIMM requires four clock inputs. The lumped capacitance value required on DCLKIN is 18 pf in this reference design. Table 4-5. DCLKIN Routing and Loading Requirements Memory Configuration Additional DCLKIN Trace Length DCLKIN Capacitance 168-pin SDRAM DIMM 4.5 +/- 0.1 inches 18 pF 144-pin SO-DIMM 3.4 +/- 0.1 inches 8.2 pF Two discrete SDRAM devices 1.3 +/- 0.1 inches 3.3 pF Four discrete SDRAM devices 4.5 +/- 0.1 inches 12 pF Eight discrete SDRAM devices 4.5 +/- 0.1 inches 12 pF Nine discrete SDRAM devices 4.5 +/- 0.1 inches 18 pF *

Intel® 80960RM/RN Processor Memory Subsystem 22 Design Guide Any memory configuration using four or more discrete SDRAM components directly on the board must adhere to the same routing requirements specified in the 4-Clock 66 MHz 72-bit ECC Unbuffered SDRAM DIMM Specification. Figure 4-11 illustrates the routing requirements for the SDRAM input clock when the configuration uses two SDRAM components. Suggested clock driver components are listed in Table 4-6. This is neither an endorsement nor a warranty of the performance of the listed product and company. Figure 4-11. Clock Routing for a Two Device SDRAM Subsystem Clock Buffer Clock 30 ohms +/- 5% SDRAM 1Mx16 SDRAM 1Mx16 1 to 8 inches 0.4 inches 0.7 inches 0.7 inches Traces from the processor to the resistor must be within 0.5 inches Table 4-6. SDRAM Clock Buffer Information Manufacturer Part Number Cypress CY2310NZPVC-1 Motorola MPC9140SD Pericom P16C182 Pericom P16C180V *

Intel® 80960RM/RN Processor Memory Subsystem 4.2.3 SDRAM Power Failure Guidelines SDRAM technology provides a simple way of enabling data preservation through the self-refresh command. When the memory controller issues this command, the SDRAM refreshes itself autonomously with internal logic and timers. The SDRAM device remains in self-refresh mode as long as: • The device continues to be powered. • SCKE is held low until the memory controller is ready to control the SDRAM once again. The board design should ensure power to the SDRAM subsystem with an adequate battery backup and a reliable method for switching between system power and battery power. The memory controller is responsible for deasserting SCKE[1:0] when issuing the self-refresh command however, while power gradually drops, SCKE[1:0] MUST remain deasserted regardless of the state of Vcc powering the RM/RN I/O processor. 4.2.4 System Assumptions The board design should ensure that P_RST# is asserted to the RM/RN I/O processor when at least 1 ms of reliable power is remaining. This is required so that the memory controller can execute its power-failure state machine in response to the assertion of P_RST#. 4.2.5 External Logic Required for Power Failure Refer to Figure for a state machine of the external logic required for power failure mode. Actual implementations may vary. This state machine can be implemented in a programmable logic device illustrated in Figure 4-13. Figure 4-12. External Power Failure State Machine PULLCKE = 0 PULLCKE = 1 SCKEout P_RST# *

Intel® 80960RM/RN Processor Memory Subsystem 24 Design Guide The implementation illustrated in Figure 4-13 requires that all external logic be powered by Vbatt. The edge detect state machine activates the pull-down when the MCU deasserts SCKE[1:0]. As long as Vbatt is active, SCKE[1:0] is held low. Once the memory controller is reset, the rising edge of P_RST# deactivates the pull-down. The memory controller will reliably control SCKE[1:0] at this point, driving it low. The pull-down is activated within the PLD device. Refer to the IQ80960RM/RN schematics in Appendix E for details. Note: Figure 4-13 shows logic for one of the SCKE signals. The loading of this signal is large enough so that two signals are required (one per SDRAM bank) and the above logic should be replicated for each SCKE[1:0]. Figure 4-13. External Power Failure Logic in the System Memory Controller Address, Data, and Control SDRAM Subsystem P_RST# PULLCKE SCKE[0] SCKEout External PLD *

Interrupt Routing 5.0 Interrupt Routing As stated in the PCI Local Bus Specification, Revision 2.1 and the PCI-to-PCI Bridge Architecture Specification, Revision 1.0, interrupt routing is system-specific. In general, the BIOS maps the device’s interrupt line to the RM/RN I/O processor’s secondary bus INTx line. The IDSEL address originates from the RM/RN I/O processor’s secondary address bus and connects to the device’s IDSEL pin or PCI connector slots. Table 5-7 provides interrupt routing for devices with a single interrupt pin. Multifunction devices, which have more than one interrupt pin, would follow the interrupt routing guidelines shown in Figure 5-14. In this case, replace the connector with the multifunction device. Secondary Address lines S_AD[25:16] can be configured for public devices or private devices depending on the Secondary ID Select Register (SISR). S_AD[31:26] are for public devices only. When PCI connectors are present on the RM/RN I/O processor’s secondary bus, the interrupts rotate on the subsequent PCI connectors as shown in Figure 5-14. 5.1 Intel® 80960RM/RN Processor Implementation on a MotherBoard When implementing the RM/RN I/O processor onto a motherboard, you must adhere to the Device ID address and interrupt routing scheme used on the primary side of the PCI bus which is dependent on the individual motherboard implementation. Table 5-7. Intel® 80960RM/RN Processor Interrupt Routing Signals Device’s IDSEL Signal Pin Device Interrupt Signal S_AD16, 20, 24, 28 INTA# S_AD17, 21, 25, 29 INTB# S_AD18, 22, 26, 30 INTC# S_AD19, 23, 27, 31 INTD# *

Interrupt Routing 26 Design Guide 5.2 Intel® 80960RM/RN Processor Implementation on an Add-in Card When designing the RM/RN I/O processor into an add-in card, refer to Figure 5-14 for Device ID address and interrupt routing. Figure 5-14. Example Secondary PCI Connector Interrupt Routing INTA# INTB# INTC# INTD# IDSEL Secondary PCI Connector 1 S_INTA# S_INTB# S_INTC# S_INTD# S_INTD:A# S_AD31:0 S_AD16 INTA# INTB# INTC# INTD# IDSEL Secondary PCI Connector 2 S_INTB# S_INTC# S_INTD# S_INTA# S_AD17 INTA# INTB# INTC# INTD# IDSEL Secondary PCI Connector 3 S_INTC# S_INTD# S_INTA# S_INTB# S_AD18 INTA# INTB# INTC# INTD# IDSEL Secondary PCI Connector 4 S_INTD# S_INTA# S_INTB# S_INTC# S_AD19 Intel® 80960RM/RN Processor NOTE: Secondary PCI Bus interrupt signals “rotate” on subsequent PCI connectors. *

Clocking Guidelines 6.0 Clocking Guidelines RM/RN I/O processor uses P_CLK (synchronous clock) input for clocking. All AC timings on the primary PCI bus and the secondary PCI bus are referenced to the P_CLK input. The system must provide clocks for any devices on the secondary PCI bus and ensure that system level goals for clock skew and jitter are met. 6.1 Layout Guidelines for Add-in Cards A PCI edge connector provides a singular PCI clock which must only be connected to one load on the add-in card. Add-in cards which contain the RM/RN I/O processor should use a low skew, low jitter clock driver/buffer to make multiple copies of the PCI clock for the RM/RN I/O processor and any devices on the secondary PCI bus. See Figure 6-15. Such clock driver/buffer devices are widely available (typically from Cypress, Motorola, National Semiconductor, etc.) The PCI bus specification allows a maximum PCI clock skew of 2 ns between any two devices connected on the PCI bus. To minimize skew on the primary PCI bus, place the clock driver device as close as possible to the PCI edge connector. Trace lengths from the PCI edge connector to the clock driver (“A” in Figure 6-15), and from the clock driver to the RM/RN I/O processor P_CLK input (“B” in Figure 6-15) must be as short as physically possible (max length 2.5 inches). For the secondary PCI bus, allowable skew is 2 ns between the RM/RN I/O processor P_CLK input and any device on the secondary PCI bus. This allows the trace lengths from the clock driver to the secondary PCI clock inputs (“C” and “D” in Figure 6-15) to be longer than the trace to the RM/RN I/O processor P_CLK input to accommodate layout. In general, keep these secondary clock routes shorter than eight inches to provide a skew of less than 2 ns. Figure 6-15. PCI Add-in Card Example Configuration B Secondary PCI Device PLL Clock Secondary 80960RM/RN P_CLK PCI Device P_CLK D C A from Edge Connector PCLK0 PCLK1 PCLK2 See notes 1,2 NOTES: 1. Trace length between source component and resistor must be <1 inch. 2. All resistor values are 22 Ohms. Generator *

Clocking Guidelines 28 Design Guide 6.2 Layout Guidelines for Motherboards For motherboard implementations, the designer has much more flexibility with PCI clocking, primarily related to controlling the central clock resources. Skew requirements for the motherboard are more stringent due to the uncertainty of having PCI edge connectors on the secondary bus. For motherboard implementation designs, it is best to choose a central clocking resource with enough PCI clock outputs to drive all PCI devices in the system, including the RM/RN I/O processor and any PCI devices on the secondary bus. All trace lengths should be equalized to both the primary and secondary PCI devices. If it is not possible to find a central clock resource with enough clock outputs for your design, then use a clock buffer/driver for the secondary PCI bus as shown in Figure 6-16. To minimize skew for these designs, use the following equation for trace length (see Figure 6-16): Equation 6-1. A = B + C + F = B + D + F - 2.5 Inches The total trace length must be under 18 inches. Also, since implementations can be varied, each design must be simulated to meet specifications as per PCI Local Bus Specification, Revision 2.1. To minimize skew, clocks to connectors should be 2.5 inches shorter than traces routed to motherboard devices. Figure 6-16. Motherboard Example Configuration B PLL Secondary PCI Device Central Clock Resource PCI DEVICE Secondary PCI Connector D Primary PCI Connector PCI DEVICE P_CLK PCLKO PCLK1 PCLK2 C D A See notes 1,2,3,4 NOTES: 1. Trace length between source component and resistor must be <1 inch. 2. All resistor values are 22 Ohms. 3. To minimize skew, trace length A = B + C = B + D - 2.5 inches. 2.5” 2.5” Clock Generator 80960RM/RN 4. F is the length of the feedback path in the clock generator. FB PCLK3 *

Clocking Guidelines 6.3 Clock Vendors The low-skew clock buffer components in Table 6-8 are suggested. This is neither an endorsement nor a warranty of the performance of the listed product and/or company. Table 6-8. Low Skew Clock Buffer Information Manufacturer Part Number Cypress W217 (new) Cypress CY7B9910 *

Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors 30 Design Guide 7.0 Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 7-9 through Table 7-11 identify the signals that require pull-up and/or pull-down resistors and the recommended resistor values. Table 7-9. Memory Controller, Core and JTAG Signals Signal Resistor Value (in Ohms) Pull-up or Pull-down Comments RAD[6]/RST_MODE# 1.5K Pull-down1 Dependent on which reset mode is desired. This signal has an internal pull-up. RAD[4]/STEST 2.7K Pull-up or Pull-down Pull-up to enable RAD[4]/STEST, pull-down to disable. RAD[3]/RETRY 1.5K Pull-down1 Dependent on which reset mode is desired. This signal has an internal pull-up. RAD[2]/32BITMEM_EN# 1.5K Pull-down2 Pull-down for 32-bit SDRAM protocol. This signal has an internal pull-up. RAD[1]/32BITPCI_EN# 1.5K Pull-down3 Pull-down for 32-bit SPCI bus protocol. This signal has an internal pull-up. NMI# 2.7K Pull-up TRST# 1.5K Pull-down Alternatively this signal may be tied to P_RST#. NOTES: 1. Pull-down only if other than default Reset Mode is required. 2. Pull-down only if the memory controller is required to support the 32-bit SDRAM protocol for access to SDRAM memory. 3. Pull-down only if the secondary PCI bus is required to function as a 32-bit bus. Table 7-10. I2C Bus Signals Signal Resistor value (in Ohms) Pull-up or Pull-down Comments SCL 2.7K pull-up When I2C unit is not used SDA 2.7K pull-up When I2C unit is not used Table 7-11. PCI Signals (Sheet 1 of 2) Signal Resistor value (in Ohms) Pull-up or Pull-down Comments S_SERR# 2.7K pull-up On Secondary Bus S_TRDY# 2.7K pull-up On Secondary Bus S_LOCK# 2.7K pull-up On Secondary Bus S_PERR# 2.7K pull-up On Secondary Bus S_DEVSEL# 2.7K pull-up On Secondary Bus *

Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors S_ FRAME# 2.7K pull-up On Secondary Bus S_ STOP# 2.7K pull-up On Secondary Bus S_ IRDY# 2.7K pull-up On Secondary Bus S_ INTA# 2.7K pull-up On Secondary Bus S_ INTB# 2.7K pull-up On Secondary Bus S_ INTC# 2.7K pull-up On Secondary Bus S_ INTD# 2.7K pull-up On Secondary Bus XINT4# 2.7K pull-up On Secondary Bus XINT5# 2.7K pull-up On Secondary Bus S_ REQ0# 2.7K pull-up On Secondary Bus S_ REQ1# 2.7K pull-up On Secondary Bus S_ REQ2# 2.7K pull-up On Secondary Bus S_ REQ3# 2.7K pull-up On Secondary Bus S_ REQ4# 2.7K pull-up On Secondary Bus S_ REQ5# 2.7K pull-up On Secondary Bus S_AD[63:32] 2.7K pull-up On Secondary Bus S_C/BE[7:4]# 2.7K pull-up On Secondary Bus S_PAR64 2.7K pull-up On Secondary Bus S_REQ64# 2.7K pull-up On Secondary Bus S_ACK64# 2.7K pull-up On Secondary Bus Table 7-11. PCI Signals (Sheet 2 of 2) Signal Resistor value (in Ohms) Pull-up or Pull-down Comments *

Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors 32 Design Guide 8.0 Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors Table 8-12 through Table 8-14 identify the signals that require pull-up and/or pull-down resistors and the recommended resistor values. Table 8-12. Memory Controller, Core and JTAG Signals Signal Resistor Value (in Ohms) Pull-up or Pull-down Comments RAD[6]/RST_MODE# 1.5K Pull-down1 Dependent on which reset mode is desired. This signal has an internal pull-up. RAD[4]/STEST 2.7K Pull-up or Pull-down Pull-up to enable RAD[4]/STEST, pull-down to disable. RAD[3]/RETRY 1.5K Pull-down1 Dependent on which reset mode is desired. This signal has an internal pull-up. RAD[2]/32BITMEM_EN# 1.5K Pull-down2 Pull-down for 32-bit SDRAM protocol. This signal has an internal pull-up. RAD[1]/32BITPCI_EN# 1.5K Pull-down3 Pull-down for 32-bit SPCI bus protocol. This signal has an internal pull-up. NMI# 2.7K Pull-up TRST# 1.5K Pull-down Alternatively this signal may be tied to P_RST#. NOTES: 1. Pull-down only if other than default Reset Mode is required. 2. Pull-down only if the memory controller is required to support the 32-bit SDRAM protocol for access to SDRAM memory. 3. Pull-down only if the secondary PCI bus is required to function as a 32-bit bus. Table 8-13. I2C Bus Signals Signal Resistor value (in Ohms) Pull-up or Pull-down Comments SCL 2.7K pull-up When I2C unit is not used SDA 2.7K pull-up When I2C unit is not used Table 8-14. PCI Signals (Sheet 1 of 2) (Sheet 1 of 2) Signal Resistor value (in Ohms) Pull-up or Pull-down Comments S_SERR# 2.7K pull-up On Secondary Bus S_TRDY# 2.7K pull-up On Secondary Bus S_LOCK# 2.7K pull-up On Secondary Bus S_PERR# 2.7K pull-up On Secondary Bus S_DEVSEL# 2.7K pull-up On Secondary Bus *

Intel® 80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors S_ FRAME# 2.7K pull-up On Secondary Bus S_ STOP# 2.7K pull-up On Secondary Bus S_ IRDY# 2.7K pull-up On Secondary Bus S_ INTA# 2.7K pull-up On Secondary Bus S_ INTB# 2.7K pull-up On Secondary Bus S_ INTC# 2.7K pull-up On Secondary Bus S_ INTD# 2.7K pull-up On Secondary Bus XINT4# 2.7K pull-up On Secondary Bus XINT5# 2.7K pull-up On Secondary Bus S_ REQ0# 2.7K pull-up On Secondary Bus S_ REQ1# 2.7K pull-up On Secondary Bus S_ REQ2# 2.7K pull-up On Secondary Bus S_ REQ3# 2.7K pull-up On Secondary Bus S_ REQ4# 2.7K pull-up On Secondary Bus S_ REQ5# 2.7K pull-up On Secondary Bus Table 8-14. PCI Signals (Sheet 2 of 2) (Sheet 2 of 2) Signal Resistor value (in Ohms) Pull-up or Pull-down Comments *

Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations 34 Design Guide 9.0 Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations 9.1 Providing 3.3 V in a 5 V System In most system board designs, the 5 V system power supply is routed to board components through a dedicated board layer. With the requirement of a 3.3 V supply for the RM/RN I/O processor, it is not necessary to add a completely new power supply layer to the circuit board. It is possible to create a 3.3 V “island” around the processor in the existing power supply plane. Figure 9-17 shows a recommended “island” layout. The RM/RN I/O processor 5 V-tolerant input buffers and TTL-compatible outputs allow the processor to interface with existing TTL-compatible external logic, without requiring extra components. Thus, the processor runs at 3.3 V and the system logic can run at 3.3 V or 5 V. Other important considerations are: • The “island” must be large enough to include the processor, the required power supply decoupling capacitance, and the necessary connection to the 3.3 V source. • To minimize signal degradation, the gap between the 3.3 V island and the 5 V plane should be kept to a minimum: typical gap size is about 0.02 inches. • Minimize the number of traces routed across the power plane gap, since each crossing introduces signal degradation due to the impedance discontinuity that occurs at the gap. For traces that must cross the gap, route them on the side of the board next to the ground plane to reduce or eliminate the signal degradation caused by crossing the gap. If this is not possible, then route the trace to cross the gap at a right angle (90 degrees). • Use liberal decoupling capacitance between the 5 V plane and the 3.3 V island. Decoupling the island reduces impedance discontinuity. *

Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations Figure 9-17. Creating a Power “Island” 3.3V island Gap in Plane Connection Point for 3.3V Source 5V Plane *

Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations 36 Design Guide 9.2 Choosing a Power Source The primary concern that must be addressed when selecting a power source is the maximum load current requirement. The processor power supply must maintain correct voltage regulation at a current of 5.0 A for the RM/RN I/O processor. Two options for supplying 3.3 V to the processor are: • Add a 3.3 V tap to the primary system power supply • Use on-board secondary regulation to derive 3.3 V from the 5 V system power supply For on-board secondary regulation, a linear voltage regulator performs adequately for most designs as shown in Figure 9-18. If low heat or power dissipation is a design goal, then the higher complexity and cost of a switching regulator may be warranted. Switching regulators offer better efficiency, thereby lowering regulator power consumption and heat. Figure 9-19 shows recommended layouts for power supply or linear regulator connection to the 3.3 V “island.” Figure 9-18. Power Supply Circuit +5V VIN VOUT 3.3V Intel® VCC 10 µF 10 µF Linear Regulator 80960RM/RN I/O Processor 100 MHz / 3.3 V Figure 9-19. Recommended Power Supply Connection Layout 3.3V Regulator (upright) and Heatsink Use a wide trace to power supply connector 3.3V Supply Using Linear Regulator 3.3V Supply Using System Power Supply *

Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations 9.3 PCI Adapter Card Power Source Currently, PCI Adapter card vendors cannot rely on the PCI connector to provide 3.3V. Hence, any adapter card designed with the RM/RN I/O processor must design an on-board 3.3V regulator for the processor power supply. 9.4 VCC5REF Pin Requirement (VDIFF) In mixed voltage systems that drive RM/RN I/O processor inputs in excess of 3.3V, the VCC5REF pin must be connected to the system’s 5V supply. To limit current flow into the VCC5REF pin, there is a limit to the voltage differential between the VCC5REF pin and the other VCC pins. The voltage differential between the VCC5REF pin and its 3.3V VCC pins should never exceed 2.25V. Meeting this requirement ensures proper operation and guarantees component reliability. This limit applies to power-up, power-down, and steady-state operation. Table 9-15 outlines this requirement. If the voltage difference requirements cannot be met due to system design limitations, an alternate solution may be employed. As shown in Figure 9-20, a 100 ohm 0.5W series resistor may be used to limit the current into the VCC5REF pin. This resistor ensures that current drawn by the VCC5REF pin does not exceed the maximum rating for this pin. This resistor is not necessary in systems that can guarantee the VDIFF specification. Also, in 3.3V-only systems and systems that drive pins from 3.3V logic, connect the VCC5REF pin directly to the 3.3V VCC plane. Table 9-15. VDIFF Specification for Dual-Power Supply Requirements (3.3 V, 5 V) Sym Parameter Min Max Unit Notes VDIFF VCC5-VCC Difference 2.25 V VCC5REF input should not exceed VCC by more than 2.25V during power-up and power-down, or during steady-state operation. Figure 9-20. VCC5REF Current-Limiting Resistor +5V (±0.25V) VCC5REF Pin 100 Ω (±5%, 0.5 W) *

Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations 38 Design Guide 9.5 VCCPLL Pins Requirement To reduce clock skew on the processor, the VCCPLL pin for the Phase Lock Loop (PLL) circuit is isolated on the pinout. The low-pass filter, shown in Figure 9-21, reduces noise induced clock jitter and its effects on timing relationships in system designs. The trace lengths between the 4.7 µF capacitor, the 0.01 µF capacitor, and VCCPLL must be as short as possible. There are three VCCPLL pins on the RM/RN I/O processor: VCCPLL1, VCCPLL2 and VCCPLL3. Each pin requires a low-pass filter. Providing just one low-pass filter and tying it to all three VCCPLL inputs is not recommended. 9.6 Pullups and Pulldown Resistors RM/RN I/O processor inputs which require a pull-up should have the pullup resistor tied to the appropriate supply voltage. In a 3.3V only design, the resistor should be tied to the 3.3V supply. In a design where the RM/RN I/O processor interface to components operating at 5V, the resistors can be tied to either the 3.3V power island or the 5V supply. Figure 9-21. VCCPLL Low-Pass Filter 10Ω, 5%, 1/8W VCC (Board Plane) VCCPLL (Processor input pin) 0.01µF 4.7µF + *

Intel® 80960RM/RN Processor 5 V and 3.3 V Design Considerations 9.7 FAIL# Many applications use a light emitting diode (LED) to indicate when the FAIL# pin is low (active). However, when an RM/RN I/O processor is in the design, and the FAIL# pin is high (inactive) at 3.3 V, the LED can still be forward biased enough to glow. To ensure the LED extinguishes when FAIL# goes high, Intel recommends the circuit shown in Figure 9-22. The two diodes dissipate about 1.4 V, so the LED voltage drops too low to glow when the FAIL# pin goes high. Use a low current LED that can operate at 3-5 mA. This design works whether VCC is 5 V or 3.3 V nominal. An alternative is to eliminate the diodes and power the LED from the 3.3 V VCC supply of the RM/RN I/O processor. Figure 9-22. Recommended FAIL# Circuit VCC 1N4002, or Equivalent 390 Ω, 10%, 0.125 W LED ~3.1 - 4.1V 80960RM/RN FAIL# *

Processor Power Supply Decoupling 40 Design Guide 10.0 Processor Power Supply Decoupling Processor power supply decoupling is critical for reliable operation. With the 3.3 V ready system, two areas of concern are described in Section 10.1 and Section 10.2: • High frequency decoupling, necessitated by the processor’s high speed operation • Low frequency decoupling, necessitated by the processor’s power saving features 10.1 High Frequency Decoupling Decoupling capacitors reduce voltage spikes by supplying extra current needed during switching. Decoupling is especially critical on the RM/RN I/O processor because of its 100 MHz internal operation. A reliable design will include a minimum of thirty-two 0.1 µF surface mount ceramic chip capacitors between power and ground, evenly distributed, around the processor. The capacitors must be placed as close to the processor as possible, attached directly to the power and ground planes, otherwise circuit board inductance will significantly reduce their effectiveness. Figure 10-23 is an example of how to place high frequency capacitors on the back (solder) side of the motherboard or add-in card. The BGA package in Figure 10-23 is shown for reference only; normally it is not be visible from the back side. The outline around the BGA package is the 3.3 V power island which is only needed on mixed voltage designs. When the design does not permit components on the back side of the PCB, place the decoupling capacitors around the perimeter on the component side of the PCB. Inadequate high frequency decoupling results in unreliable or inconsistent program behavior. These failures are often intermittent, and are difficult to diagnose and debug. *

Processor Power Supply Decoupling 10.2 Bulk Decoupling Capacitance Bulk, or low-frequency decoupling is needed on the RM/RN I/O processor. If the processor is on a separate power plane “island”, it is necessary to place capacitance on the processor “island.” For bulk decoupling, place two 47 mF surface mount capacitors in parallel, directly between the power and ground planes. Place the capacitors close to the processor, within the power “island”. If other 3.3V components are on the PCB, then the two 47 mF capacitors may be omitted since the other components would have bulk decoupling capacitors. However, the value and number of capacitors required is dependent on the individual board design and layout characteristics. Figure 10-23. High-Frequency Capacitor Values and Layout Legend: = 0.1 µF Capacitor *

Intel® 80960RM/RN Processor Based Reference Design 42 Design Guide 11.0 Intel® 80960RM/RN Processor Based Reference Design See Appendix A through Appendix D for schematics and bill of material. OrCAD libraries for the RM/RN I/O processor are available and can be supplied upon request. *

Debug Connector Recommendations 12.0 Debug Connector Recommendations This section describes debug hardware and connectors developed for the RM/RN I/O processor. This includes sockets, headers, logic analyzer interposer, Mictor* signal cross reference lists and JTAG emulator debug connector/pin assignments. 12.1 PBGA Sockets and Headers Figure 12-24 and Figure 12-25 illustrate surface mount sockets and headers available for the RM/RN I/O processor. See Table 14-22 for socket and header vendor information. Figure 12-24. 540L PBGA Header A5858-02 .05 Chamfer .060 inch Top View Side View .158 inch .062 inch 1.67 inch *

Debug Connector Recommendations 44 Design Guide Figure 12-25. 540L PBGA Socket A5857-02 .05 inch Chamfer .062 inch .062 inch .312 inch .667 inch .812 inch .193 inch .050 inch .125 inch .340 inch 1.674 inch Top View Side View *

Debug Connector Recommendations 12.2 Logic Analyzer Connectivity The Mictor connector is the common connector used by the RM/RN I/O processor for logic analysis connectivity. The Cyclone evaluation board developed for the 80960RM/RN integrates five Mictor connectors to route the appropriate signals for logic analysis and probing. See Table 12-16. A removable interposer is also available for designs that may not have the available board space for Mictor connectors. See Figure 12-26, Figure 12-27 and Figure 12-28. Refer to Table 14-25 for logic analyzer interposer vendor information. Table 12-16 is the signal cross-reference list for the RM/RN I/O processor and associated Mictor connectors for the Cyclone board and the flex tape interposer. Pins1,2,37 and 38 are not used. Table 12-16. Logic Analyzer Header Definitions (Mictor) PIN Cyclone J9 Cyclone J11 Cyclone J12 Cyclone J10 Cyclone J8 Interposer J2 Interposer J3 Interposer J4 Interposer J5 Interposer J1 3 N/C SDRAMCLK N/C N/C N/C 4 DQ15 SDQM7 DQ31 N/C RAD15 5 DQ14 SDQM6 DQ30 N/C RAD14 6 DQ13 SDQM5 DQ29 N/C RAD13 7 DQ12 SDQM4 DQ28 N/C RAD12 8 DQ11 SDQM3 DQ27 N/C RAD11 9 DQ10 SDQM2 DQ26 N/C RAD10 10 DQ9 SDQM1 DQ25 N/C RAD9 11 DQ8 SDQM0 DQ24 N/C RAD8 12 DQ7 SCB7 DQ23 N/C RAD7 13 DQ6 SCB6 DQ22 N/C RAD6 14 DQ5 SCB5 DQ21 N/C RAD5 15 DQ4 SCB4 DQ20 N/C RAD4 16 DQ3 SCB3 DQ19 SCE0# RAD3 17 DQ2 SCB2 DQ18 SCE1# RAD2 18 DQ1 SCB1 DQ17 SBA1 RAD1 19 DQ0 SCB0 DQ16 SBA0 RAD0 20 DQ32 SA0 DQ48 SREQ0# RAD16 21 DQ33 SA1 DQ49 SREQ1# N/C 22 DQ34 SA2 DQ50 SREQ2# N/C 23 DQ35 SA3 DQ51 SREQ3# RALE 24 DQ36 SA4 DQ52 SREQ4# RCE0# 25 DQ37 SA5 DQ53 SREQ5# RCE1# 26 DQ38 SA6 DQ54 SGNT0# ROE# 27 DQ39 SA7 DQ55 SGNT1# RWE# 28 DQ40 SA8 DQ56 SGNT2# N/C 29 DQ41 SA9 DQ57 SGNT3# N/C 30 DQ42 SA10 DQ58 SGNT4# N/C 31 DQ43 SA11 DQ59 SGNT5# N/C 32 DQ44 N/C DQ60 N/C N/C 33 DQ45 SWE# DQ61 N/C N/C 34 DQ46 SCAS# DQ62 N/C N/C 35 DQ47 SRAS# DQ63 N/C N/C 36 N/C N/C N/C P_PCICLK RALE *

Debug Connector Recommendations 46 Design Guide Figure 12-26. Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View Figure 12-27. Packard-Hughes Direct Mount (Flex Tape) Interposer - Side View A5880-01 1.91 inch 4.59 inch Pin #1 J3 Packard-Hughes Interconnect Direct Mount Interposer J4 J5 J2 J1 Flex Tape Socket Mictor* Connectors 1 38 * Other brands and names are the property of their respective owners. A5881-01 Header J3 Packard-Hughes Interconnect Direct Mount Interposer J4 J5 J2 J1 Flex Tape Socket ~.35 inch ~.25 inch Mictor Connector *

Debug Connector Recommendations Figure 12-28. Flex Tape Interposer Application (Add-In Card) Figure 12-29. Flex Tape Interposer (Top View) Figure 12-30. Flex Tape Interposer (Side View) A5882-01 312 mm Add-in Card Motherboard PCI Connector Flex Tape Interposer Mictor connector Side View Top view of Flex Tape Interposer Pin #1 J8 J7 J6 J5 J3 *

Debug Connector Recommendations 48 Design Guide 12.3 JTAG Connector and Test Interface 12.3.1 Intel® i960® RM/RN I/O Processor JTAG Emulator The JTAG emulator for the i960® RM/RN I/O processor is designed to provide a convenient and non-intrusive means of debugging. The JTAG emulator is connected to the processor by means of a simple 16-pin connector. The hardware provided with the JTAG emulator can also be used (with additional software) to test opens and shorts on the processor without the necessity for any additional circuitry, other than a single 16-pin connector once it has been installed onto the PCB. A JTAG emulator provides a designer the ability to download code, read data from registers, single-step the processor, insert breakpoints (both hardware and software) and perform full source level debugging without the need of an intrusive monitor program or a bulky hardware pod. 12.3.2 Intel® i960® RM/RN I/O Processor Target Debug Interface Connector The i960 microprocessor target should have a 16-pin, two row header connector. Use 3M part number 2516-6002UG or equivalent. The header is made from a keyed plastic shroud with two rows of 8 pins and the spacing between adjacent pins and between the two rows is 0.100”. The header pin assignment is illustrated in Figure 12-31. Figure 12-31. JTAG Emulator Connector (Top View) 1 2 15 16 0.1” 0.1” *

Debug Connector Recommendations Figure 12-17 describes the interconnections required between the target debug interface connector and the pins/balls of the i960 RM/RN I/O processor family. Table 12-17. i960® RM/RN I/O Processor Debug Connector Wiring Header Pin i960® RM/RN I/O Processor Ball/Direction Signal Name Recommended Target Resistor 1 C11 TRST# 1KΩ pull-down 2 GND 3 A12 TDI 1KΩ pull-up 4 GND 5 E11 TDO 6 GND 7 B11 TMS 1KΩ pull-up 8 GND 9 C12 TCK 1KΩ pull-up 10 GND 11 A21 LCDINIT# 1KΩ pull-up 12 GND 13 A11 I_RST# 14 GND 15 PWRVLD Connected to VCC through 1KΩ series resistor 16 GND *

Debug Connector Recommendations 50 Design Guide 12.3.3 Connecting The Emulator To The Target The emulation software uses the first Test Access Port (TAP) on the PC-1149.1/100F boundary-scan controller card to control the i960 RM/RN I/O processor. A cable should be connected from the boundary-scan controller to the i960 RM/RN I/O processor target debug interface connector as shown in the following tables. A cable built to one of the following specifications is supplied with the corresponding emulator. Table 12-18. i960® RM/RN I/O Processor with PC-1149.1/100F (cable P/N AS01090025-Ax) PC-1149.1/100F Signal Name PC-1149.1/100F Pin Target Signal Name Target Debug Header Pin TRST# 1 TRST# 1 GND 2 GND 2 TDO12 3 TDI 3 GND 4 GND 4 TDI12 5 TDO 5 GND 6 GND 6 TMS1 7 TMS 7 GND 8 GND 8 TCK12 (see note) 9 TCK 9 GND 10 GND 10 TMS3 25 LCDINIT#/ RSTIN# 11 GND 12 GND 12 SENSE# 13 I_RST/ RSTOUT# 13 GND 14 GND 14 T_OFF# (see note) 11 PWRVLD 15 GND 16 GND 16 NOTE: Connected to target through 33Ω series resistor. *

Debug Connector Recommendations 12.3.4 Other Tools Other tools are available that are designed to complement the i960 family of JTAG emulators. These include a full complement of boundary-scan hardware and software for testing the 80960RM/RN for opens, shorts, and other manufacturing defects once it has been installed onto the target board. In addition, Corelis has available a preprocessor (PI-PCI32/64) for use with the HP family of logic analyzers that allows a designer to examine the full complement of signals on the PCI bus including all the boundary-scan signals. Since 80960RM/RN designs typically incorporate PCI connectivity, this tool has been proven particularly effective in troubleshooting designs utilizing the 80960RM/RN. Table 12-19. i960® RM/RN I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx) PCMCIA-1149.1 Signal Name PCMCIA-1149.1 Pin Target Signal Name Target Debug Header Pin TRST# 8 TRST# 1 GND 9 GND 2 TDO1 7 TDI 3 GND 5 GND 4 TDI1 6 TDO 5 GND 3 GND 6 TMS1 4 TMS 7 GND 1 GND 8 TCK1 (see note) 2 TCK 9 GND 11 GND 10 PIO_0 17 LCDINIT#/ RSTIN# 11 GND 13 GND 12 PIO_1 18 I_RST/ RSTOUT# 13 GND 25 GND 14 PIO_2 (see note) 19 PWRVLD 15 - No Connection GND 16 NOTE: Connected to target through 33Ω series resistor. *

Design for Manufacturability 52 Design Guide 13.0 Design for Manufacturability The RM/RN I/O processor is offered in a high-thermal BGA (H-PBGA) package. PBGA packaging is explained extensively in the Intel® Packaging Databook (Order Number 240800). *

Thermal Solutions 14.0 Thermal Solutions In general, three factors affect the thermal performance of the BGA: package and board materials, package geometry and use environment. The H-PBGA package utilizes a heat spreader or slug across the top of the package to dissipate heat efficiently. Environmental conditions play a critical role in the thermal performance of PBGAs. Ambient conditions, junction and case temperatures, the device’s placement and orientation on a board, in conjunction with the volume and temperature of air flowing past the unit present a broad range of possible thermal solutions. The profiles of the H-PBGA package are characterized in Table 14-20. 14.1 Thermal Recommendations Refer to the thermal sections of the Intel® 80960 RM I/O Processor Datasheet (273156), the Intel® 80960 RN I/O Processor Datasheet (273157), and the Intel® 80960 RS I/O Processor Datasheet (273328) and to the thermal section of the Thermal Data for the 540-Lead PBGA Package Application Note (273390). Table 14-20. H-PBGA Package Characteristics Description Criteria Die Junction temperature 110° C Case Temperature (maximum) 90° Ca a. Case temperature is dependent on the ambient temperature and airflow surrounding the processor. Refer to the application note “Thermal Data for the 540-Lead PBGA Package” for more information. Ambient temperature up to 55° C Airflow (on motherboard) from system fan up to 50 LFM (worst case) Airflow (on add-in card) 0 LFM (worst case) Passive heatsink dimensions Acceptable flange adds 5 mm per side on hole direction of fan Clip = 45 mm x 45 mm < 11 mm (thickness) Flange type =55 mm x 45 mm <11 mm (thickness) with pins. Maximum heatsink thickness <11 mm Clip Hole Pattern 4 holes (3.175 mm diameter), 48.4632 x 34.798 mm rectangular (see Figure 14-33 and Figure 14-34) Heatsink Flatness From center of heatsink to 1/2 inch in x and y directions, 2 mils maximum *

Thermal Solutions 54 Design Guide 14.2 3-Dimensional View: Processor with Heat Sink Attached To assist the board designer in component placement, hole placement and dimensions, Figure 14-33 and Figure 14-34 detail specifics. Figure 14-33 details dimensions for board designs requiring a Passive Heat Sink. Figure 14-32. Conceptual 3-D View of Processor with a Heat Sink Push Pins Heatsink Flange Single-fan Active Heatsink Customer’s Board Heat Slug BGA Package *

Thermal Solutions 14.3 PCB Heatsink Hole Dimensions Figure 14-33. Hole Dimensions for Passive Heatsink A5860-03 Outline of Passive Heat Sink 34.798 mm 45 mm 55 mm Package: 42.5 mm x 42.5 mm 48.4632 mm 4 Holes of diameter 3.175 ± 0.0508 mm 5.10 mm 2.98 mm REF 25.4 mm Top View Side View 25.4 mm Flange uses pins Heat Slug of 80960RM/RN (over component) NOTES: The sides of the H-PBGA package are electrically conductive; traces run out to the edge of the package. Therefore, no materials are allowed to contact the sides of this package at any time, including during shock and vibration testing. Heatsink actual dimensions vary depending on vendor (see Table 21). Clips Board Pin Spring Board Heat Slug Thermal Interface Material Heat Slug Heat Sink Balls *

Thermal Solutions 56 Design Guide Figure 14-34. Board Level Keep Out Areas A5878-02 45 mm 55 mm Pin Keep-Out Area = 3.81 mm (Top and Bottom View) Clip Keep-Out Area = 9.2 mm (Bottom View) Trace Keep-Out Areas [Top View] Periphery Components Keep-Out Area Mounting hole diameter 3.175 ± 0.0508 mm Component Keep Out Area - except when component height is less than the height of the top of the package Package Trace and Component Keep Out Area = 3.81 mm Heat Sink Area *

Thermal Solutions 14.4 Clearances of PCI Board and Components Figure 14-35. Clearances of PCI Board and Components A5853-03 15.49 mm 6.35 mm 1.57 mm 2.67 mm 18.72 mm = total overall dimension 14.48 mm 312 mm Add-in Card Heat sink mounted on the processor Motherboard PCI Connector 106.68 mm height Add-in card #1 Add-in card #2 Maximum allowable component dimension on the backside (as per PCI Local Bus Specification Rev 2.1) Heat sink mounted on the package Side View Note: The two PCI add-in cards are assumed to be in two adjacent slots. *

Thermal Solutions 58 Design Guide 14.5 Heat Sink Information Table 14-21 provides a list of suggested sources for heat sinks. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. 14.5.1 Socket Information Table 14-22 and Table 14-23 provide vendor details for socket-headers and burn-in sockets for the RM/RN I/O processor. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. 14.5.2 Socket-Header Vendor 14.5.3 Burn-in Socket Vendor Table 14-21. Heat Sink Vendors and Contacts Company Factory Rep Phone # Fax # Heatsink Part # Passive AAVID THERMALLOY, LLC 2021 W. Valley View Lane Dallas Texas 75234-8993 Email:[email protected] Outside of USA, refer to web page for contact information: http://www.thermalloy.com Attn: Sales (972) 243-4321 (972) 241-4656 21933B w/o thermal grease (uses pins) 21935B with Easy Ply (thermal grease (uses pins) Table 14-22. Socket-Header Vendor Company Factory Represen- tative Phone/Fax # Part # BGA 540 Pin Header BGA 540 Pin Socket Carrier Adapter Technologies, Inc. 214-218 South 4th St. Perkasie, PA 18944 John Miller 215-258-5750/ 215-258-5760 BGAH-540-0-01-320 1-0277-1 BGA-540-0-02-3201 -0275P-130 Table 14-23. Burn-in Socket Vendor Company Factory Representative Phone # Burn-in Socket Part # Texas Instruments 111 Forbes Blvd. Mansfield, MA 02048 W. Ray Johnson 508-236-5375 ULGA540-005 *

Thermal Solutions 14.5.4 Shipping Tray Vendor 14.5.5 Logic Analyzer Interposer Vendor 14.5.6 JTAG Emulator Vendor Table 14-24. Shipping Tray Vendor Company Factory Rep Phone # Shipping Tray Part # 3M Ron Goth 602-465-5381 7-0000-21001-184-167 Table 14-25. Logic Analyzer Interposer Vendor Company Factory Rep Phone/Fax # Part # Packard-Hughes Interconnect 17150 Von Karman Ave Irvine, CA 92614-0968 Sue Wood 714-660-5766 714-660-5825 1126898 Table 14-26. JTAG Emulator Vendor Company Factory Rep Phone/Fax # Part # Corelis Mike Winters 562-926-6727 562-484-6196 TBD *

References 60 Design Guide 15.0 References 15.1 Related Documents Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. To obtain Intel literature: call 1-800-548-4725 or visit Intel’s website at http://www.intel.com 15.2 Electronic Information Table 15-27. Related Documentation Document Title Intel Order # Intel Packaging Databook 240800 PCI Local Bus Specification Revision 2.2 PCI Special Interest Group 1-800-433-5177 PC SDRAM Unbuffered DIMM Specification v1.0 http://developer.intel.com/ technology/memory/unb_001.pdf PCI-to-PCI Bridge Architecture Specification Revision 1.1 PCI Special Interest Group 1-800-433-5177 Table 15-28. Electronic Information Intel’s World-Wide Web (WWW) Location: http://www.intel.com Customer Support (US and Canada): 800-628-8686 *

Intel® i960® RM I/O Processor Schematics Intel® i960® RM I/O Processor Schematics A Schematics in this document supersede schematics in Document #AZ1-00886. *

Intel® i960® RM I/O Processor Schematics 62 Design Guide Figure 15-36. Decoupling and 3.3 V Power Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 TP1 1 R46 0.012 1W 1% 1 2 3 4 5 6 7 L2 3.3uH COIL-SMT2 1 2 CR6 MBRS340T3 1 2 Q2 RFD16N05L 2 1 3 Q3 RFD16N05L 2 1 3 C60 220uF CAPT7343 2 1 C75 220uF CAPT7343 2 1 C78 220uF CAPT7343 2 1 C93 47uF CAPT7343 2 1 C90 47uF CAPT7343 2 1 C91 47uF CAPT7343 2 1 C67 0.1uF CAP0805 2 1 C79 0.1uF CAP0805 2 1 C85 0.1uF CAP0805 2 1 C40 0.1uF CAP0805 2 1 C39 0.1uF CAP0805 2 1 C38 0.1uF CAP0805 2 1 C37 0.1uF CAP0805 2 1 C36 0.1uF CAP0805 2 1 C35 0.1uF CAP0805 2 1 C34 0.1uF CAP0805 2 1 C33 0.1uF CAP0805 2 1 C6 0.1uF CAP0805 2 1 C5 0.1uF CAP0805 2 1 C4 0.1uF CAP0805 2 1 C14 0.1uF CAP0805 2 1 C13 0.1uF CAP0805 2 1 C12 0.1uF CAP0805 2 1 C22 0.1uF CAP0805 2 1 C21 0.1uF CAP0805 2 1 C1 0.1uF CAP0805 2 1 C7 0.1uF CAP0805 2 1 C8 0.1uF CAP0805 2 1 C9 0.1uF CAP0805 2 1 C15 0.1uF CAP0805 2 1 C16 0.1uF CAP0805 2 1 C17 0.1uF CAP0805 2 1 C23 0.1uF CAP0805 2 1 C24 0.1uF CAP0805 2 1 C25 0.1uF CAP0805 2 1 C31 0.1uF CAP0805 2 1 C32 0.1uF CAP0805 2 1 C20 0.1uF CAP0805 2 1 C30 0.1uF CAP0805 2 1 C29 0.1uF CAP0805 2 1 C28 0.1uF CAP0805 2 1 C116 0.1uF CAP0805 2 1 C117 0.1uF CAP0805 2 1 C111 0.1uF CAP0805 2 1 C113 0.1uF CAP0805 2 1 C105 0.1uF CAP0805 2 1 C109 0.1uF CAP0805 2 1 C106 0.1uF CAP0805 2 1 C108 0.1uF CAP0805 2 1 C114 0.1uF CAP0805 2 1 C115 0.1uF CAP0805 2 1 C112 0.1uF CAP0805 2 1 C107 0.1uF CAP0805 2 1 C45 0.1uF CAP0805 2 1 C59 0.1uF CAP0805 2 1 C46 0.1uF CAP0805 2 1 C70 0.1uF CAP0805 2 1 C99 0.1uF CAP0805 2 1 C103 0.1uF CAP0805 2 1 C81 0.1uF CAP0805 2 1 C72 0.1uF CAP0805 2 1 C80 0.1uF CAP0805 2 1 C69 0.1uF CAP0805 2 1 C87 0.1uF CAP0805 2 1 C73 0.1uF CAP0805 2 1 C49 0.1uF CAP0805 2 1 C62 0.1uF CAP0805 2 1 C66 0.1uF CAP0805 2 1 C42 0.1uF CAP0805 2 1 C41 0.1uF CAP0805 2 1 C71 0.1uF CAP0805 2 1 C43 0.1uF CAP0805 2 1 C48 0.1uF CAP0805 2 1 C44 0.1uF CAP0805 2 1 C50 0.1uF CAP0805 2 1 C86 0.1uF CAP0805 2 1 C84 0.22uF CAP1206 2 1 R54 10 1/8W 5% 1 2 C83 0.01uF CAP0805 2 1 C88 4.7uF CAPT7343 2 1 CR9 CMPSH3 2 3 U17 MAX767CAP 17 BST 1 CS 19 DH 16 DL 20 FB 4GND1 5GND2 6GND3 7GND4 11GND5 18 LX 3ON/OFF# 13 PGND 8REF 2SS 9SYNC 10VCC1 14VCC2 15VCC3 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 1 10 +5V +5V +5V +3V +3V +3V +5V P33V {2,4,8,9} RAM3V {4,6,10} NOTE: PINS 3-7 ARE VIAS SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING DECOUPLING & 3.3V POWER *

Intel® i960® RM I/O Processor Schematics Figure 15-37. Primary PCI Interface Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 U16 74ALS08 1 2 3 U16 74ALS08 4 5 6 U16 74ALS08 9 10 8 U16 74ALS08 12 13 11 PRIMARY PCI SIGNALS U15 i960RM C20 P_CLK H3 P_IDSEL N3 P_PAR R2 P_C/BE0 N5 P_C/BE1 K1 P_C/BE2 H4 P_C/BE3 L1P_DEVSEL L5P_FRAME A7 P_GNT E8 P_INTA D8 P_INTB E7 P_INTC C7 P_INTD L3P_IRDY M4 P_LOCK M3 P_PERR E6 P_REQ B7 P_RST M1 P_SERR M5 P_STOP L2P_TRDY U1 P_AD0 U2 P_AD1 P1 P_AD10 P3 P_AD11 P4 P_AD12 P5 P_AD13 N1 P_AD14 N2 P_AD15 K3 P_AD16 K4 P_AD17 K5 P_AD18 J1 P_AD19 U3 P_AD2 J2 P_AD20 J3 P_AD21 J5 P_AD22 H1 P_AD23 H5 P_AD24 G1 P_AD25 G2 P_AD26 G3 P_AD27 E5 P_AD28 A6 P_AD29 T1 P_AD3 C6 P_AD30 D6 P_AD31 T3 P_AD4 T4 P_AD5 T5 P_AD6 R1 P_AD7 R3 P_AD8 R5 P_AD9 J14 CONNPCI_B 36+3V1 41+3V2 43+3V3 54+3V4 59+5V1 61+5V2 62+5V3 60ACK64# 58AD1 48AD10 47AD12 45AD14 32AD17 56AD3 55AD5 53AD7 52AD8 44C/BE1# 33C/BE2# 37DEVSEL# 34GND1 38GND2 46GND3 49GND4 57GND5 35IRDY# 39LOCK# 40PERR# 42SERR# J14 CONNPCI_B 25+3V1 31+3V2 5+5V1 6+5V2 19+5V3 1-12V 30AD19 29AD21 27AD23 24AD25 23AD27 21AD29 20AD31 26C/BE3# 16CLK 3GND1 12GND2 13GND3 15GND4 17GND5 22GND6 28GND7 7INTB# 8INTD# 9PRSNT1# 11PRSNT2# 18REQ# 10 14 2TCK 4TDO J15 CONNPCI_A 33+3V1 39+3V2 45+3V3 53+3V4 59+5V1 61+5V2 62+5V3 58AD0 47AD11 46AD13 44AD15 32AD16 57AD2 55AD4 54AD6 49AD9 52C/BE0# 34FRAME# 35GND1 37GND2 42GND3 48GND4 56GND5 43PAR 60REQ64# 41SBO# 40SDONE 38STOP# 36TRDY# J15 CONNPCI_A 2+12V 21+3V1 27+3V2 5+5V1 8+5V2 10+5V3 16+5V4 31AD18 29AD20 28AD22 25AD24 23AD26 22AD28 20AD30 12GND1 13GND2 18GND3 24GND4 30GND5 17GNT# 26IDSEL 6INTA# 7INTC# 9 11 14 19 15RST# 4TDI 3TMS 1TRST# R58 10K 1/10W 5% 1 2 R39 10K 1/10W 5% 1 2 Z3 JUMP1X2 1 2 R55 22 RNC4R8P 8 7 6 5 4 3 2 1 R40 22 RNC4R8P 8 7 6 5 4 3 2 1 U18 CY7B9910-7 13 FB 3FS 1REF 23TEST 7 Q0 8 Q1 10 Q2 11 Q3 15 Q4 16 Q5 18 Q6 19 Q7 C89 47uF CAPT7343 2 1 C97 0.1uF CAP0805 2 1 C98 0.1uF CAP0805 2 1 C100 0.1uF CAP0805 2 1 C101 0.1uF CAP0805 2 1 C102 0.1uF CAP0805 2 1 C104 0.1uF CAP0805 2 1 C94 0.1uF CAP0805 2 1 C95 0.1uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 2 10 PPCI P33V +12V +5V N12V +5V TD TD PPCI PINTA# PINTB# PINTC# PINTD# PRST# +5V PC/BE0# PINTA# PGNT# PC/BE1# PINTB# PREQ# PC/BE2# PINTC# PC/BE3# PINTD# PAD31 PAD30 PAD29 P33V PFRAME# PPERR# PAD28 PRST# PDEVSEL# PSERR# RST# {10} PAD27 PAD26 PIRDY# PAD25 PTRDY# P33V PAD24 PSTOP# PC/BE3# PIDSEL PIDSEL PAD23 P33V PPAR PAD22 PREQ# PAD21 PAD20 PGNT# PAD19 RST# P33V PAD18 PLOCK# PAD17 PAD16 PC/BE2# P33V PFRAME# PIRDY# P33V PTRDY# PDEVSEL# PAD31 PAD30 PAD29 PAD28 PAD27 PAD26 PAD25 PAD24 PAD23 PAD22 PAD21 PAD20 PAD19 PAD18 PAD17 PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PSTOP# PLOCK# P33V PPERR# PSERR# P33V PPAR PC/BE1# PAD15 PAD14 P33V PAD13 PAD12 PAD11 PAD10 CLK_960 PAD9 LOGIC_CLK {5} PAD8 PC/BE0# CLK PAD7 P33V P33V PAD6 PAD5 PAD4 PAD3 PAD2 CLKA {8} PAD1 PAD0 CLKB {8} CLKC {9} CLKD {9} SPARES PRIMARY PCI INTERFACE *

Intel® i960® RM I/O Processor Schematics 64 Design Guide Figure 15-38. Memory Controller Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R57 2.7K 1/10W 5% 1 2 TP2 1 MEMORY CONTROLLER U15 i960RM E21 DCLKIN T31 SBA0 T30 SBA1 C21 ONCE D22 DQ0 A23 DQ1 E27 DQ10 C28 DQ11 H32 DQ12 H30 DQ13 J32 DQ14 J29 DQ15 W29 DQ16 Y32 DQ17 Y30 DQ18 AA32 DQ19 C23 DQ2 AA29 DQ20 AB32 DQ21 AB30 DQ22 AC32 DQ23 AC29 DQ24 AD32 DQ25 AD30 DQ26 AE32 DQ27 AE29 DQ28 AF32 DQ29 A24 DQ3 AF30 DQ30 AG32 DQ31 E22 DQ32 B23 DQ33 E23 DQ34 C24 DQ35 E24 DQ36 B25 DQ37 E25 DQ38 C26 DQ39 D24 DQ4 A27 DQ40 C27 DQ41 A28 DQ42 G32 DQ43 H31 DQ44 H28 DQ45 J30 DQ46 J28 DQ47 W28 DQ48 Y31 DQ49 A25 DQ5 Y28 DQ50 AA30 DQ51 AA28 DQ52 AB31 DQ53 AB28 DQ54 AC30 DQ55 AC28 DQ56 AD31 DQ57 AD28 DQ58 AE30 DQ59 C25 DQ6 AE28 DQ60 AF31 DQ61 AF28 DQ62 AH32 DQ63 A26 DQ7 E26 DQ8 B27 DQ9 B13 RAD1 E15 RAD10 E17 RAD11 A18 RAD12 C18 RAD13 D18 RAD14 E18 RAD15 A19 RAD16 C13 RAD2/32BITMEM_EN# E13 RAD3/RETRY A14 RAD4/STEST C14 RAD5 D14 RAD6/RST_MODE# C15 RAD9 K32 SCB0 K30 SCB1 V31 SCB2 W32 SCB3 K31 SCB4 K28 SCB5 V30 SCB6 W30 SCB7 A22 DCLKOUT A13 RAD0 E14 RAD7 A15 RAD8 B19 RALE N30 SA0 N29 SA1 R28 SA10 T32 SA11 N28 SA2 P32 SA3 P31 SA4 P30 SA5 P28 SA6 R32 SA7 R30 SA8 R29 SA9 T28 SCKE0 U32 SCKE1 L29 SDQM0 M32 SDQM1 U30 SDQM2 U28 SDQM3 L28 SDQM4 M31 SDQM5 U29 SDQM6 V32 SDQM7 C19 RCE0 E19 RCE1 D20 ROE A20 RWE L30 SCAS M30 SCE0 M28 SCE1 N32 SRAS L32 SWE U13 74ALS32 12 13 11 U13 74ALS32 9 10 8 U13 74ALS32 4 5 6 U13 74ALS32 1 2 3 C110 18pF CAP0805 2 1 R22 30 RNC4R8P 8 7 6 5 4 3 2 1 R23 30 RNC4R8P 8 7 6 5 4 3 2 1 R37 24 1/10W 5% 1 2 R29 36 1/10W 5% 1 2 R13 1.5K RNC4R8P 8 7 6 5 4 3 2 1 R41 1.5K 1/10W 5% 1 2 R42 1.5K 1/10W 5% 1 2 Z1 JUMP1X2 1 2 Z2 JUMP1X2 1 2 U9 MPC9140/CDC318 11CLKIN 38OE 4 OUT0 5 OUT1 35 OUT10 36 OUT11 40 OUT12 41 OUT13 44 OUT14 45 OUT15 21 OUT16 28 OUT17 8 OUT2 9 OUT3 13 OUT4 14 OUT5 17 OUT6 18 OUT7 31 OUT8 32 OUT9 25SCLK 24SDA S1 SWDIP4 1 2 3 4 8 7 6 5 R51 22 1/10W 5% 1 2 R50 22 1/10W 5% 1 2 U6 74ALS04 11 10 U6 74ALS04 13 12 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 3 10 +3V SDRAM {5,6} DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DCLKIN DCLKOUT DRAMCLK_LA {5} DCLKOUT DCLK0 {6} DCLK1 {6} SCB7 DCLKIN SCB6 SCB5 SA11 SCB4 SA10 SCB3 DCLK2 {6} SA9 SCB2 DCLK3 {6} SA8 SCB1 SA7 SCB0 RAD {4,5} SA6 SA5 ROE# SA4 RWE# SA3 RCE0# SDA {6,7} SA2 RCE1# SCL {6,7} SA1 RALE SA0 ONCE# SBA0 RAD16 SBA1 RAD15 SRAS# RAD14 SCAS# RAD13 SWE# RAD12 ROMA {4} SCE0# RAD11 ROMA18 SCE1# RAD10 SELUART# {4} SCKE0 {6,10} RAD9 RCE1# RAD8 RAD7 SM7 RAD6/RST_MODE# SCKE1 {6,10} SM6 RAD5 IOW# {4} RWE# SM5 RAD4/STEST SM4 RAD3/RETRY SM3 RAD2/32BITMEM_EN# SEL_LED# {4} SM2 RAD1 SM1 RAD0 SM0 IOR# {4} DQ24 DQ19 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ23 DQ22 DQ21 DQ20 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 RAD6/RST_MODE# RAD3/RETRY RAD2/32BITMEM_EN# RAD4/STEST RAD0 MEMORY CONTROLLER *

Intel® i960® RM I/O Processor Schematics Figure 15-39. Flash ROM, UART and LEDs Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R18 1.6K 1/10W 5% 1 2 CR4 LED GREEN LP 2 1 R59 10K 1/10W 5% 1 2 U11 E28F016S5 24A0 23A1 14A10 13A11 8A12 7A13 6A14 5A15 4A16 3A17 2A18 1A19 22A2 40A20 21A3 20A4 19A5 18A6 17A7 16A8 15A9 36 RY/BY 11 VPP 9CE 37OE 12 RP 38WE 25 D0 26 D1 27 D2 28 D3 32 D4 33 D5 34 D6 35 D7 Z4 JUMP1X2 1 2 R19 330 1/10W 5% 1 2 R17 470 1/10W 5% 1 2 CR3 LED RED 2 1 CR5 LED GREEN 2 1 U6 74ALS04 5 6 U6 74ALS04 3 4 U6 74ALS04 9 8 U6 74ALS04 1 2 CR1 LED4SM 8 7 CR1 LED4SM 2 1 CR1 LED4SM 4 3 CR1 LED4SM 6 5 CR2 LED4SM 2 1 CR2 LED4SM 4 3 CR2 LED4SM 8 7 CR2 LED4SM 6 5 R15 470 RNC4R8P 8 7 6 5 4 3 2 1 R16 470 RNC4R8P 8 7 6 5 4 3 2 1 U3 74ABT273 31D 42D 73D 84D 135D 146D 177D 188D 11CLK 1CLR 2 1Q 5 2Q 6 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q U2 74ABT573 21D 32D 43D 54D 65D 76D 87D 98D 11LE 1OC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q U1 74ABT573 21D 32D 43D 54D 65D 76D 87D 98D 11LE 1OC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q J7 CONNJ6-6P 1 2 3 5 4 6 U4 OSC1.8432MHz 1E/D 5 O U5 1488 2IN1A 4IN1B 5IN2B 9IN3A 10IN3B 12IN4A 13IN4B 3 OUTA 6 OUTB 8 OUTC 11 OUTD U7 1489A 13 12 11 U7 1489A 10 9 8 U7 1489A 1 2 3 U7 1489A 4 5 6 U12 16C550 31A0 30A1 29A2 14CS0 15CS1 25IOR 21IOW 39RST 10 RXCLK 11 RXD 18 XTAL1 28AS 42 CD 16CS2 40 CTS 41 DSR 24IOR 20IOW 43 RI 2D0 3D1 4D2 5D3 6D4 7D5 8D6 9D7 33 INT 32 RXRDY 13 TXD 27 TXRDY 19 XTAL2 17 BAUDOUT 26 DDIS 37 DTR 38 OP1 35 OP2 36 RTS C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 4 10 +5V RAD16 ROMA {3} RAD15 RAD14 RAD {3,5} RAD13 RAD12 +5V RAD11 RAD10 RAD16 ROMA16 RAD9 RAD15 ROMA15 RAD2/32BITMEM_EN# RAD14 ROMA14 RAD1 RAD13 ROMA13 RAD0 RAD12 ROMA12 +5V RAD11 ROMA11 SELUART# {3} RAD10 ROMA10 RAD9 ROMA9 RALE IOR# {3} IOW# {3} I_RST# {5,7} IRQUART# {7} RAD6/RST_MODE# ROMA20 RAD5 ROMA19 RAD4/STEST ROMA18 +12V RAD3/RETRY ROMA17 +5V ROMA20 ROMA19 ROMA18 ROMA17 RALE ROMA16 I_RST# {5,7} ROMA15 RAD9 LED0 ROMA14 RAD10 LED1 ROMA13 RAD11 LED2 ROMA12 RAD12 LED3 ROMA11 RAD13 LED4 ROMA10 RAD14 LED5 ROMA9 RAD15 LED6 RAD8 RAD16 LED7 RAD7 SEL_LED# {3} LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 RAD6/RST_MODE# RAD5 RAD4/STEST +5V RAD3/RETRY RAD16 RAD2/32BITMEM_EN# RAD15 RAD1 RAD14 RAD0 RAD13 RAD12 +5V RWE# RAD11 FAIL# {7} RCE0# RAD10 ROE# RAD9 RAM3V {1,6,10} P33V {1,2,8,9} SPARES FLASH ROM, UART, & LEDS *

Intel® i960® RM I/O Processor Schematics 66 Design Guide Figure 15-40. Logic Analyzer I/F Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 J12 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J11 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J10 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J8 MICTOR 4 25 24 23 22 21 20 5 6 3 CLK0 36 CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J9 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 5 10 SDRAM {3,6} RAD {3,4} DRAMCLK_LA {3} DQ15 SM7 DQ31 RAD15 DQ14 SM6 DQ30 RAD14 DQ13 SM5 DQ29 RAD13 DQ12 SM4 DQ28 RAD12 DQ11 SM3 DQ27 RAD11 DQ10 SM2 DQ26 RAD10 DQ9 SM1 DQ25 RAD9 DQ8 SM0 DQ24 RAD8 DQ7 SCB7 DQ23 RAD7 DQ6 SCB6 DQ22 RAD6/RST_MODE# DQ5 SCB5 DQ21 RAD5 DQ4 SCB4 DQ20 RAD4/STEST SCE0# DQ3 SCB3 DQ19 RAD3/RETRY SCE1# DQ2 SCB2 DQ18 RAD2/32BITMEM_EN# SBA1 DQ1 SCB1 DQ17 RAD1 SBA0 DQ0 SCB0 DQ16 RAD0 LOGIC_CLK {2} RALE DQ47 SWE# DQ63 DQ46 SCAS# DQ62 DQ45 SRAS# DQ61 DQ44 DQ60 SPCI {7,8,9} SGNT5# DQ43 SA11 DQ59 SGNT4# DQ42 SA10 DQ58 SGNT3# DQ41 SA9 DQ57 I_RST# {4,7} SGNT2# DQ40 SA8 DQ56 SGNT1# DQ39 SA7 DQ55 RWE# SGNT0# DQ38 SA6 DQ54 ROE# SREQ5# DQ37 SA5 DQ53 RCE1# SREQ4# DQ36 SA4 DQ52 RCE0# SREQ3# DQ35 SA3 DQ51 RALE SREQ2# DQ34 SA2 DQ50 SREQ1# DQ33 SA1 DQ49 SREQ0# DQ32 SA0 DQ48 RAD16 LOGIC ANALYZER I/F *

Intel® i960® RM I/O Processor Schematics Figure 15-41. SDRAM 168-Pin DIMM Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 U21 TL7702BCD 2 RESIN 3 CT 1 REF 7 SENSE 5 RESET 6 RESET U20 TL7702BCD 2 RESIN 3 CT 1 REF 7 SENSE 5 RESET 6 RESET C119 0.047uF CAP0805 2 1 C118 0.047uF CAP0805 2 1 J5 SDRAM-DIMM168P 117 A1 123 A11 118 A3 119 A5 120 A7 121 A9 122 BA0 111 CAS 105 CB4 106 CB5 136 CB6 137 CB7 128 CKE0 125 CLK1 163 CLK3 114 CS1 129 CS3 85GND1 96GND2 107 GND3 116 GND4 127 GND5 138 GND6 148 GND7 152 GND8 162 GND9 112 M4 113 M5 130 M6 131 M7 108 NC1 147 NC10 164 NC11 109 NC2 126 NC4 132 NC5 134 NC6 135 NC7 145 NC8 146 NC9 115 RAS 165 SA0 166 SA1 167 SA2 90VCC1 102 VCC2 110 VCC3 124 VCC4 133 VCC5 143 VCC6 157 VCC7 168 VCC8 86DQ32 87DQ33 88DQ34 89DQ35 91DQ36 92DQ37 93DQ38 94DQ39 95DQ40 97DQ41 98DQ42 99DQ43 100 DQ44 101 DQ45 103 DQ46 104 DQ47 139 DQ48 140 DQ49 141 DQ50 142 DQ51 144 DQ52 149 DQ53 150 DQ54 151 DQ55 153 DQ56 154 DQ57 155 DQ58 156 DQ59 158 DQ60 159 DQ61 160 DQ62 161 DQ63 J5 SDRAM-DIMM168P 33A0 38A10 34A2 35A4 36A6 37A8 39BA1 21CB0 22CB1 52 CB2 53 CB3 63 CKE1 42CLK0 79 CLK2 30CS0 45 CS2 9DQ6 1GND1 12GND2 23GND3 32GND4 43 GND5 54 GND6 64 GND7 68 GND8 78 GND9 28M0 29M1 46 M2 47 M3 24NC1 80 NC10 81 NC11 25NC2 31NC3 44 NC4 48 NC5 50 NC6 51 NC7 61 NC8 62 NC9 83 SCL 82 SDA 6VCC1 18VCC2 26VCC3 40VCC4 41VCC5 49 VCC6 59 VCC7 73 VCC8 84 VCC9 27WE 2DQ0 3DQ1 14DQ10 15DQ11 16DQ12 17DQ13 19DQ14 20DQ15 55 DQ16 56 DQ17 57 DQ18 58 DQ19 4DQ2 60 DQ20 65 DQ21 66 DQ22 67 DQ23 69 DQ24 70 DQ25 71 DQ26 72 DQ27 74 DQ28 75 DQ29 5DQ3 76 DQ30 77 DQ31 7DQ4 8DQ5 10DQ7 11DQ8 13DQ9 R62 1K 1/10W 5% 1 2 R61 1K 1/10W 5% 1 2 C121 0.1uF CAP0805 2 1 C120 0.1uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 6 10 RAM3V {1,4,10} SDRAM {3,5} DQ0 DQ32 SCKE0 {3,10} DQ1 SCE0# DQ33 SCE1# DQ2 SM2 DQ34 SM6 DQ3 SM3 DQ35 SM7 DQ4 DQ36 DQ5 DQ37 +3V DQ6 DQ38 DQ7 SCB2 DQ39 SCB6 DQ8 SCB3 DQ40 SCB7 SCKE0 {3,10} DQ9 DQ16 DQ41 DQ48 DQ10 DQ17 DQ42 DQ49 DQ11 DQ18 DQ43 DQ50 DQ12 DQ19 DQ44 DQ51 DQ13 DQ45 DQ20 DQ52 DQ14 DQ46 DQ15 DQ47 SCB0 SCKE1 {3,10} SCB4 SCB1 SCB5 +3V DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 SCKE1 {3,10} SWE# DQ24 SCAS# DQ56 SM0 DQ25 SM4 DQ57 SM1 DQ26 SM5 DQ58 SCE0# DQ27 SCE1# DQ59 SRAS# DQ28 DQ60 SA0 DQ29 SA1 DQ61 SA2 DQ30 SA3 DQ62 SA4 DQ31 SA5 DQ63 SA6 SA7 SA8 DCLK2 {3} SA9 DCLK3 {3} SA10 SBA0 SBA1 SA11 SDA {3,7} SCL {3,7} DCLK1 {3} DCLK0 {3} SDRAM 168-PIN DIMM *

Intel® i960® RM I/O Processor Schematics 68 Design Guide Figure 15-42. Secondary PCI/80960 Core Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 JX CORE/I2C/JTAG U15 i960RM C12 TCK A12 TDI B11 TMS E20 VCC5REF C22 VCCPLL1 B15 VCCPLL2 D26 VCCPLL3 A21 LCDINIT A9 NMI B9 S_INTA/XINT0 C9 S_INTB/XINT1 E9 S_INTC/XINT2 A10 S_INTD/XINT3 C11 TRST C10 XINT4 D10 XINT5 C8 SDA A8 SCL E11 TDO E12 FAIL A11 I_RST SECONDARY PCI SIGNALS U15 i960RM AL26 S_REQ0 AH27 S_REQ1 AK27 S_REQ2 AH28 S_REQ3 AL28 S_REQ4 AJ29 S_REQ5 AH14 S_AD0 AK14 S_AD1 AM17 S_AD10 AH18 S_AD11 AK18 S_AD12 AL18 S_AD13 AM18 S_AD14 AH19 S_AD15 AH22 S_AD16 AK22 S_AD17 AL22 S_AD18 AM22 S_AD19 AL14 S_AD2 AH23 S_AD20 AJ23 S_AD21 AK23 S_AD22 AM23 S_AD23 AK24 S_AD24 AL24 S_AD25 AM24 S_AD26 AH25 S_AD27 AJ25 S_AD28 AK25 S_AD29 AM14 S_AD3 AM25 S_AD30 AH26 S_AD31 AH15 S_AD4 AJ15 S_AD5 AK15 S_AD6 AM15 S_AD7 AJ17 S_AD8 AK17 S_AD9 AK19 S_PAR AH17 S_C/BE0 AJ19 S_C/BE1 AM21 S_C/BE2 AH24 S_C/BE3 AM20 S_DEVSEL AK21 S_FRAME AJ21 S_IRDY AK20 S_LOCK AH20 S_PERR AM19 S_SERR AL20 S_STOP AH21 S_TRDY AM26 S_GNT0 AJ27 S_GNT1 AM27 S_GNT2 AK28 S_GNT3 AM28 S_GNT4 AK29 S_GNT5 AK26 S_RST R14 1.5K 1/10W 5% 1 2 R36 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R3 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R44 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R52 100 1/2W 5% 1 2 J6 HEAD16SH JTAG HEADER 1 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 R43 10 1/8W 5% 1 2 R30 10 1/8W 5% 1 2 R56 10 1/8W 5% 1 2 C61 0.01uF CAP0805 2 1 C96 0.01uF CAP0805 2 1 C77 0.01uF CAP0805 2 1 C57 4.7uF CAPT7343 2 1 C92 4.7uF CAPT7343 2 1 C76 4.7uF CAPT7343 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 7 10 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 7 10 SPCI {5,8,9} +5V SREQ0# SC/BE0# SREQ1# SC/BE1# SREQ2# SC/BE2# SREQ3# SC/BE3# SREQ4# SREQ5# SFRAME# SIRDY# SGNT0# STRDY# SGNT1# SSTOP# SDA {3,6} SCL {3,6} SGNT2# SDEVSEL# SGNT3# SSERR# +3V SGNT4# SRST# SGNT5# SPERR# SLOCK# SINTA# SPAR SINTB# SINTC# SINTD# IRQFAN# {10} IRQUART# {4} FAIL# {4} SAD31 SAD30 SAD29 SAD28 SAD27 SAD26 SAD25 SAD24 SAD23 SAD22 SAD21 SAD20 SAD19 SAD18 SAD17 SAD16 SAD15 SAD14 SAD13 SAD12 SAD11 SAD10 SAD9 SAD8 SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 I_RST# {4,5} +5V +3V SECONDARY PCI/960 CORE *

Intel® i960® RM I/O Processor Schematics Figure 15-43. Secondary PCI Bus 1/2 Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 J1 CONNPCI_32 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J2 CONNPCI_32 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J2 CONNPCI_32 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST J1 CONNPCI_32 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST R12 10K 1/10W 5% 1 2 R11 10K 1/10W 5% 1 2 R9 10K 1/10W 5% 1 2 R10 10K 1/10W 5% 1 2 R45 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R31 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R33 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R38 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R1 2.7K RNC4R8P 8 7 6 5 4 3 2 1 C19 0.01uF CAP0805 2 1 C18 0.01uF CAP0805 2 1 C27 0.01uF CAP0805 2 1 C26 0.01uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 8 10 SPCI {5,7,9} +12V N12V +5V +5V +5V +5V STRST# {9} SAD17 SAD16 STCK {9} SC/BE2# P33V {1,2,4,9} STMS {9} SFRAME# STDI {9} SIRDY# +5V P33V {1,2,4,9} STRDY# SINTA# SDEVSEL# SINTB# SINTC# SSTOP# STMS SINTD# SLOCK# SPERR# STDI STRST# SSERR# STCK SPAR SC/BE1# SAD15 SAD14 SRST# SAD13 CLKA {2} SAD12 SAD11 +5V SGNT0# SAD10 SFRAME# SREQ0# SAD9 STRDY# SAD31 SAD30 SIRDY# SAD29 P33V {1,2,4,9} SAD8 SC/BE0# SDEVSEL# SAD28 SAD7 SAD27 SAD26 SAD6 SAD25 SAD5 SAD4 P33V {1,2,4,9} SAD24 SAD3 SC/BE3# SAD16 SAD2 SAD23 +5V SAD1 SAD0 +5V SSTOP# SAD22 SAD21 SAD20 SSERR# SAD19 SPERR# SAD18 SLOCK# +12V N12V STRST# {9} SAD17 SAD16 STCK {9} SC/BE2# P33V {1,2,4,9} STMS {9} SFRAME# STDI {9} SIRDY# P33V {1,2,4,9} STRDY# SREQ0# SINTB# SDEVSEL# SREQ1# SINTC# SINTD# SSTOP# SINTA# SLOCK# SREQ2# SPERR# SREQ3# SSERR# SPAR SC/BE1# SAD15 SAD14 SRST# SAD13 SREQ4# CLKB {2} SAD12 SAD11 SREQ5# SGNT1# SAD10 SREQ1# SAD9 SAD31 SAD30 SAD29 SAD8 SC/BE0# SAD28 SAD7 SAD27 SAD26 SAD6 SAD25 SAD5 SAD4 SAD24 SAD3 SC/BE3# SAD17 SAD2 SAD23 +5V SAD1 SAD0 +5V SAD22 SAD21 SAD20 SAD19 SAD18 SPCI CONN 2 SPCI CONN 1 SECONDARY PCI BUS 1/2 *

Intel® i960® RM I/O Processor Schematics 70 Design Guide Figure 15-44. Secondary PCI Bus 3/4 Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 J3 CONNPCI_32 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J4 CONNPCI_32 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J4 CONNPCI_32 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST J3 CONNPCI_32 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST R6 10K 1/10W 5% 1 2 R5 10K 1/10W 5% 1 2 R8 10K 1/10W 5% 1 2 R7 10K 1/10W 5% 1 2 C3 0.01uF CAP0805 2 1 C2 0.01uF CAP0805 2 1 C11 0.01uF CAP0805 2 1 C10 0.01uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 9 10 SPCI {5,7,8} +12V N12V +5V +5V +5V +5V STRST# {8} SAD17 SAD16 STCK {8} SC/BE2# P33V {1,2,4,8} STMS {8} SFRAME# STDI {8} SIRDY# P33V {1,2,4,8} STRDY# SINTC# SDEVSEL# SINTD# SINTA# SSTOP# SINTB# SLOCK# SPERR# SSERR# SPAR SC/BE1# SAD15 SAD14 SRST# SAD13 CLKC {2} SAD12 SAD11 SGNT2# SAD10 SREQ2# SAD9 SAD31 SAD30 SAD29 P33V {1,2,4,8} SAD8 SC/BE0# SAD28 SAD7 SAD27 SAD26 SAD6 SAD25 SAD5 SAD4 P33V {1,2,4,8} SAD24 SAD3 SC/BE3# SAD18 SAD2 SAD23 +5V SAD1 SAD0 +5V SAD22 SAD21 SAD20 SAD19 SAD18 +12V N12V STRST# {8} SAD17 SAD16 STCK {8} SC/BE2# P33V {1,2,4,8} STMS {8} SFRAME# STDI {8} SIRDY# P33V {1,2,4,8} STRDY# SINTD# SDEVSEL# SINTA# SINTB# SSTOP# SINTC# SLOCK# SPERR# SSERR# SPAR SC/BE1# SAD15 SAD14 SRST# SAD13 CLKD {2} SAD12 SAD11 SGNT3# SAD10 SREQ3# SAD9 SAD31 SAD30 SAD29 SAD8 SC/BE0# SAD28 SAD7 SAD27 SAD26 SAD6 SAD25 SAD5 SAD4 SAD24 SAD3 SC/BE3# SAD19 SAD2 SAD23 +5V SAD1 SAD0 +5V SAD22 SAD21 SAD20 SAD19 SAD18 SPCI CONN 4 SPCI CONN 3 SECONDARY PCI BUS 3/4 *

Intel® i960® RM I/O Processor Schematics Figure 15-45. Battery Monitor Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R24 100K 1/10W 5% 1 2 R32 100K 1/10W 5% 1 2 R60 10 1/10W 5% 1 2 R27 1 1/10W 5% 1 2 R28 1 1/10W 5% 1 2 R53 47K 1/10W 5% 1 2 R49 4.7K 1/10W 5% 1 2 R48 4.7K 1/10W 5% 1 2 U19 PALLV16V8-10JC 1 I0 2 I1 3 I2 4 I3 5 I4 6 I5 7 I6 8 I7 9 I8 11 I9 20 VCC 12 F0 13 F1 14 F2 15 F3 16 F4 17 F5 18 F6 19 F7 U10 LM339 9 + 8 - 14 U10 LM339 11 + 10 - 13 U10 LM339 7 + 6 - 1 U10 LM339 5 + 4 - 2 R35 10K 1/10W 5% 1 2 C82 0.047uF CAP0805 2 1 R47 2.4K 1/10W 5% 1 2 C47 22uF CAPT7343 2 1 C65 0.47uF CAP1206 2 1 J13 FAN CONN 1 FAN 2GND 3PWR C63 33uF CAPT7343 2 1 Q4 2N6109 1 2 3 R21 0.05 1W 1% 1 2 R20 150 1/10W 5% 1 2 R26 68K 1/10W 5% 1 2 R34 22K 1/10W 5% 1 2 BT8 BATT_HLDR 2 1 BT6 BATT_HLDR 2 1 BT1 BATT_HLDR 2 1 BT3 BATT_HLDR 2 1 BT7 BATT_HLDR 2 1 BT5 BATT_HLDR 2 1 BT2 BATT_HLDR 2 1 BT4 BATT_HLDR 2 1 CR8 CMR1-02 1 2 C64 330uF CAPT7343H 2 1 C56 100uF CAPT7343H 2 1 U8 MAX1651 2FB 8GND 4REF 3SHDN 6 CS 7 EXT 1 OUT 5 V+ U14 MAX712 11CC 13GND 3 PGM0 4 PGM1 9 PGM2 10 PGM3 7TEMP 5THI 6TLO 1VLIMIT 2 BATT+ 12 BATT- 14 DRV 16REF 15V+ 8 FASTCHG L1 47uH 1 2 7 6 5 4 3 CR7 MBRS340T3 1 2 Q1 SI9430 5 6 7 8 4 1 2 3 R25 1K 1/10W 5% 1 2 C74 1uF CAPT3216 2 1 C54 10uF CAPT7343 2 1 C52 10uF CAPT7343 2 1 C51 0.1uF CAP0805 2 1 C53 0.1uF CAP0805 2 1 C58 0.01uF CAP0805 2 1 C55 0.01uF CAP0805 2 1 C68 0.01uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 10 10 SCKE0 {3,6} +12V SCKE1 {3,6} RST# {2} RAM3V {1,4,6} BATTERY RAM3V {1,4,6} +5V +5V IRQFAN# {7} PART # 101-1950-01 NOTE: VCC FOR LM339 IS +5V SPARES + + + + BATTERY/MONITOR *

Intel® IQ80960RM Board Bill of Material 72 Design Guide Intel® IQ80960RM Board Bill of MaterialB This appendix identifies all components on the IQ80960RM Evaluation Platform (Table B-1). Table B-1. Intel® IQ80960RM Bill of Materials (Sheet 1 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # 1 1 U13 IC/SM 74ALS32 SOIC-14 National Semiconductor DM74ALS32M 2 1 U6 IC/SM 74ALS04 SOIC National Semiconductor DM74ALS04BM 3 1 U3 IC/SM 74ABT273 SOIC Texas Instruments SN74ABT273DW 4 2 U1, U2 IC/SM 74ABT573 SOIC Texas Instruments SN74ABT573DW 5 1 U16 IC/SM 74ALS08 SOIC National Semiconductor DM74ALS08M 6 1 U5 IC / SM 1488A SOIC National Semiconductor DS1488M 7 1 U7 IC / SM 1489A SOIC National Semiconductor DS1489AM 8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY 9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 10 1 U10 IC/SM LM339 SOIC-14 National Semiconductor LM339M 11 1 U8 IC/SM MAX1651CSA SOIC-8 Maxim MAX1651CSA 12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE 13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 PROCESSOR (frm Intel) i960RM Intel 15 1 U12 VLSI I/O UART 16C550 PLCC Texas Instruments TL16C550AFN 16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0 17 15 C2, C3, C10, C11, C18, C19, C26, C27, C55, C58, C61, C68, C77, C83, C96 CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC *

Intel® IQ80960RM Board Bill of Material 18 79 C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C48, C49, C50, C51, C53, C59, C62, C66, C67, C69, C70, C71, C73, C79, C80, C81, C85, C86, C87, C94, C95, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C111, C112, C113, C114, C115, C116, C117 CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2 19 1 C110 CAP SM, 18 pF(0805) Kemet C0805C180J5GAC 20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT 21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT 22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT 23 12 R5, R6, R7 R8, R9, R10, R11, R12, R35, R39, R58, R59 R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT 24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT 25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT 26 3 R14, R41, R42 R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT 27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT 28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT 29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT Table B-1. Intel® IQ80960RM Bill of Materials (Sheet 2 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # *

Intel® IQ80960RM Board Bill of Material 74 Design Guide 30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT 31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT 32 1 R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT 33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT 34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT 35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT 36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT 37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT 38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT 39 4 R30, R43, R54, R56 R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT 40 5 J8, J9, J10, J11, J12 CONN SM/TH Mictor 43P Recptcl AMP 767054-1 41 4 J1, J2, J3, J4a CONN PCI Slot 5V/PCB ThruHole AMP 145154-4 42 1 J5 CONN DIMM 168P/RAng/Socket/TH Molex 73790-0059 43 1 J7 CONN TJ6 PCB 6/6 LP through hole KYCON GM-N-66 44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03 45 1 J6 CONN Hdr 16 pin/w shell, pcb AMP 103308-3 46 4 Z1, Z2, Z3, Z4 Jumper JUMP2X1 Molex 22-54-1402 47 1 L1 Inductor/SM 47 µH 20% Coilcraft D03340P-473 48 1 L2 Inductor/SM 3.3 µH 20% Coilcraft D03316P-332 49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S 50 1 U4 OSC 1.8432 MHz 1/2 - Through hole Kyocera KH0HC1CSE 1.843 51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC 52 1 CR5 LED Green Hewlett Packard HLMP-3507$010 53 1 CR3 LED-Red Hewlett Packard HLMP3301$010 54 1 CR4 LED Green LP Hewlett Packard HLMP4740#010 55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001 56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM 57 1 Q4 Transistor 2N6109 (Through Hole) Motorola 2N6109 58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269-1 60 1 U11 SOCKET / SM / TSOP / 40 pin Meritec 980020-40-02 61 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery Clips/PC/Snap-In/AA Keystone #92 62 1 U19 PALLV16V8Z-20JI AMD PALLV16V8Z-20JI 63 1 U11 MEM Flash E28F016S5-090 TSOP Intel E28F016S5-090 Table B-1. Intel® IQ80960RM Bill of Materials (Sheet 3 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # *

Intel® IQ80960RM Board Bill of Material 64 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery AA NiCd @ 600 mA/Hour SAFT NIC-AA-600-SAFT 65 1 U15 HeatSink/Fan Assy 80960RN/RM Panasonic UDQFNBEOIF 66 3 C84 CAP SM, 0.22 µF (1206) Philips 12062E224M9BB2 67 3 C60, C75, C78 CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010 68 4 C89, C90, C91, C93 CAP TANT SM 47 µF, 16 V (7343) AVX TPSD476K016R015 69 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T 70 4 C57, C76, C88, C92 CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T 71 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T 72 1 C74 CAP TANT SM 1 µF, 16 V (3216) Sprague 293D105X0016A2T 73 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprague 293D1060025D2T 74 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100 75 1 C64 CAP TANT SM 330 µF 6.3 V (7343) AVX TPSE337K063R0100 76 1 C82 CAP SM, 0.047 µF (0805) Kemet C0805C473K5RAC 77 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012 78 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050 79 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT 80 7 R1, R31, R33, R36, R38, R44, R45 Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR 81 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR 82 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR 83 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR 84 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR 85 1 CR9 Diode CMPSH3 Surface Mount Central Semiconductor CMPSH3 86 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3 87 1 CR8 Diode/SM 1N4001 (CMR1-02) Central Semiconductor CMR1-02 88 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG a. Connectors for IQ80960RM, CONN PCI 32-BIT 5 V/PCB ThruHole, AMP #145154-4. Table B-1. Intel® IQ80960RM Bill of Materials (Sheet 4 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # *

Intel® i960® RN I/O Processor Schematics 76 Design Guide Intel® i960® RN I/O Processor Schematics C Schematics in this document supersede schematics in Document #AZ1-00886. *

Intel® i960® RN I/O Processor Schematics Figure 15-46. Decoupling and 3.3 V Power Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 TP1 1 R46 0.012 1W 1% 1 2 3 4 5 6 7 L2 3.3uH COIL-SMT2 1 2 CR6 MBRS340T3 1 2 Q2 RFD16N05L 2 1 3 Q3 RFD16N05L 2 1 3 C60 220uF CAPT7343 2 1 C75 220uF CAPT7343 2 1 C78 220uF CAPT7343 2 1 C93 47uF CAPT7343 2 1 C90 47uF CAPT7343 2 1 C91 47uF CAPT7343 2 1 C67 0.1uF CAP0805 2 1 C79 0.1uF CAP0805 2 1 C85 0.1uF CAP0805 2 1 C40 0.1uF CAP0805 2 1 C39 0.1uF CAP0805 2 1 C38 0.1uF CAP0805 2 1 C37 0.1uF CAP0805 2 1 C36 0.1uF CAP0805 2 1 C35 0.1uF CAP0805 2 1 C34 0.1uF CAP0805 2 1 C33 0.1uF CAP0805 2 1 C6 0.1uF CAP0805 2 1 C5 0.1uF CAP0805 2 1 C4 0.1uF CAP0805 2 1 C14 0.1uF CAP0805 2 1 C13 0.1uF CAP0805 2 1 C12 0.1uF CAP0805 2 1 C22 0.1uF CAP0805 2 1 C21 0.1uF CAP0805 2 1 C1 0.1uF CAP0805 2 1 C7 0.1uF CAP0805 2 1 C8 0.1uF CAP0805 2 1 C9 0.1uF CAP0805 2 1 C15 0.1uF CAP0805 2 1 C16 0.1uF CAP0805 2 1 C17 0.1uF CAP0805 2 1 C23 0.1uF CAP0805 2 1 C24 0.1uF CAP0805 2 1 C25 0.1uF CAP0805 2 1 C31 0.1uF CAP0805 2 1 C32 0.1uF CAP0805 2 1 C20 0.1uF CAP0805 2 1 C30 0.1uF CAP0805 2 1 C29 0.1uF CAP0805 2 1 C28 0.1uF CAP0805 2 1 C116 0.1uF CAP0805 2 1 C117 0.1uF CAP0805 2 1 C111 0.1uF CAP0805 2 1 C113 0.1uF CAP0805 2 1 C105 0.1uF CAP0805 2 1 C109 0.1uF CAP0805 2 1 C106 0.1uF CAP0805 2 1 C108 0.1uF CAP0805 2 1 C114 0.1uF CAP0805 2 1 C115 0.1uF CAP0805 2 1 C112 0.1uF CAP0805 2 1 C107 0.1uF CAP0805 2 1 C45 0.1uF CAP0805 2 1 C59 0.1uF CAP0805 2 1 C46 0.1uF CAP0805 2 1 C70 0.1uF CAP0805 2 1 C99 0.1uF CAP0805 2 1 C103 0.1uF CAP0805 2 1 C81 0.1uF CAP0805 2 1 C72 0.1uF CAP0805 2 1 C80 0.1uF CAP0805 2 1 C69 0.1uF CAP0805 2 1 C87 0.1uF CAP0805 2 1 C73 0.1uF CAP0805 2 1 C49 0.1uF CAP0805 2 1 C62 0.1uF CAP0805 2 1 C66 0.1uF CAP0805 2 1 C42 0.1uF CAP0805 2 1 C41 0.1uF CAP0805 2 1 C71 0.1uF CAP0805 2 1 C43 0.1uF CAP0805 2 1 C48 0.1uF CAP0805 2 1 C44 0.1uF CAP0805 2 1 C50 0.1uF CAP0805 2 1 C86 0.1uF CAP0805 2 1 C84 0.22uF CAP1206 2 1 R54 10 1/8W 5% 1 2 C83 0.01uF CAP0805 2 1 C88 4.7uF CAPT7343 2 1 CR9 CMPSH3 2 3 U17 MAX767CAP 17 BST 1 CS 19 DH 16 DL 20 FB 4GND1 5GND2 6GND3 7GND4 11GND5 18 LX 3ON/OFF# 13 PGND 8REF 2SS 9SYNC 10VCC1 14VCC2 15VCC3 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 1 11 +5V +5V +5V +3V +3V +3V +5V P33V {2,4,8,9} RAM3V {4,6,11} NOTE: PINS 3-7 ARE VIAS SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING DECOUPLING & 3.3V POWER *

Intel® i960® RN I/O Processor Schematics 78 Design Guide Figure 15-47. Primary PCI Interface Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 U16 74ALS08 4 5 6 U16 74ALS08 9 10 8 U16 74ALS08 12 13 11 U16 74ALS08 1 2 3 R58 10K 1/10W 5% 1 2 R39 10K 1/10W 5% 1 2 Z3 JUMP1X2 1 2 PRIMARY PCI SIGNALS U15 i960RN C20 P_CLK H3 P_IDSEL N3 P_PAR W3 P_PAR64 R2 P_C/BE0 N5 P_C/BE1 K1 P_C/BE2 H4 P_C/BE3 W5 P_C/BE4 V1 P_C/BE5 V3 P_C/BE6 V4 P_C/BE7 L1P_DEVSEL L5P_FRAME A7 P_GNT E8 P_INTA D8 P_INTB E7 P_INTC C7 P_INTD L3P_IRDY M4 P_LOCK M3 P_PERR E6 P_REQ U5 P_REQ64 B7 P_RST M1 P_SERR M5 P_STOP L2P_TRDY U1 P_AD0 U2 P_AD1 P1 P_AD10 P3 P_AD11 P4 P_AD12 P5 P_AD13 N1 P_AD14 N2 P_AD15 K3 P_AD16 K4 P_AD17 K5 P_AD18 J1 P_AD19 U3 P_AD2 J2 P_AD20 J3 P_AD21 J5 P_AD22 H1 P_AD23 H5 P_AD24 G1 P_AD25 G2 P_AD26 G3 P_AD27 E5 P_AD28 A6 P_AD29 T1 P_AD3 C6 P_AD30 D6 P_AD31 AG2 P_AD32 AG3 P_AD33 AF1 P_AD34 AF3 P_AD35 AF4 P_AD36 AF5 P_AD37 AE1 P_AD38 AE2 P_AD39 T3 P_AD4 AE3 P_AD40 AE5 P_AD41 AD1 P_AD42 AD3 P_AD43 AD4 P_AD44 AD5 P_AD45 AC1 P_AD46 AC2 P_AD47 AC3 P_AD48 AC5 P_AD49 T4 P_AD5 AB1 P_AD50 AB3 P_AD51 AB4 P_AD52 AB5 P_AD53 AA1 P_AD54 AA2 P_AD55 AA3 P_AD56 AA5 P_AD57 Y1 P_AD58 Y3 P_AD59 T5 P_AD6 Y4 P_AD60 Y5 P_AD61 W1 P_AD62 W2 P_AD63 R1 P_AD7 R3 P_AD8 R5 P_AD9 V5 P_ACK64 R55 22 RNC4R8P 8 7 6 5 4 3 2 1 R40 22 RNC4R8P 8 7 6 5 4 3 2 1 U18 CY7B9910-7 13 FB 3FS 1REF 23TEST 7 Q0 8 Q1 10 Q2 11 Q3 15 Q4 16 Q5 18 Q6 19 Q7 J15 CONNPCI_A 66+5V1 75+5V2 84+5V3 91AD32 89AD34 88AD36 86AD38 85AD40 83AD42 82AD44 80AD46 79AD48 77AD50 76AD52 74AD54 73AD56 71AD58 70AD60 68AD62 65C/BE5# 64C/BE7# 63GND1 69GND2 72GND3 78GND4 81GND5 87GND6 90GND7 93GND8 67PAR64 92 94 J14 CONNPCI_B 70+5V1 79+5V2 88+5V3 90AD33 89AD35 87AD37 86AD39 84AD41 83AD43 81AD45 80AD47 78AD49 77AD51 75AD53 74AD55 72AD57 71AD59 69AD61 68AD63 66C/BE4# 65C/BE6# 64GND1 67GND2 73GND3 76GND4 82GND5 85GND6 91GND7 94GND8 63 92 93 J15 CONNPCI_A 33+3V1 39+3V2 45+3V3 53+3V4 59+5V1 61+5V2 62+5V3 58AD0 47AD11 46AD13 44AD15 32AD16 57AD2 55AD4 54AD6 49AD9 52C/BE0# 34FRAME# 35GND1 37GND2 42GND3 48GND4 56GND5 43PAR 60REQ64# 41SBO# 40SDONE 38STOP# 36TRDY# J15 CONNPCI_A 2+12V 21+3V1 27+3V2 5+5V1 8+5V2 10+5V3 16+5V4 31AD18 29AD20 28AD22 25AD24 23AD26 22AD28 20AD30 12GND1 13GND2 18GND3 24GND4 30GND5 17GNT# 26IDSEL 6INTA# 7INTC# 9 11 14 19 15RST# 4TDI 3TMS 1TRST# J14 CONNPCI_B 36+3V1 41+3V2 43+3V3 54+3V4 59+5V1 61+5V2 62+5V3 60ACK64# 58AD1 48AD10 47AD12 45AD14 32AD17 56AD3 55AD5 53AD7 52AD8 44C/BE1# 33C/BE2# 37DEVSEL# 34GND1 38GND2 46GND3 49GND4 57GND5 35IRDY# 39LOCK# 40PERR# 42SERR# J14 CONNPCI_B 25+3V1 31+3V2 5+5V1 6+5V2 19+5V3 1-12V 30AD19 29AD21 27AD23 24AD25 23AD27 21AD29 20AD31 26C/BE3# 16CLK 3GND1 12GND2 13GND3 15GND4 17GND5 22GND6 28GND7 7INTB# 8INTD# 9PRSNT1# 11PRSNT2# 18REQ# 10 14 2TCK 4TDO C89 47uF CAPT7343 2 1 C97 0.1uF CAP0805 2 1 C98 0.1uF CAP0805 2 1 C100 0.1uF CAP0805 2 1 C101 0.1uF CAP0805 2 1 C102 0.1uF CAP0805 2 1 C104 0.1uF CAP0805 2 1 C94 0.1uF CAP0805 2 1 C95 0.1uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 2 11 PPCI P33V +12V +5V N12V +5V TD TD PPCI PINTA# PINTB# PINTC# PINTD# PAD63 PAD62 PAD61 PAD60 PAD59 PAD58 PAD57 PAD56 PAD55 PAD54 PAD53 PAD52 PAD51 PAD50 PAD49 PAD48 PAD47 PAD46 PAD45 PAD44 PAD43 PAD42 PAD41 PAD40 PAD39 PAD38 PAD37 PAD36 PAD35 PAD34 PAD33 PAD32 +5V +5V PC/BE7# PC/BE6# PC/BE5# PC/BE4# PRST# PPAR64 PAD63 PAD62 PC/BE0# PINTA# PGNT# PAD61 PC/BE1# PINTB# PREQ# PAD60 PC/BE2# PINTC# PAD59 PAD58 PC/BE3# PINTD# PAD31 PAD30 PAD57 PC/BE4# PAD29 P33V PAD56 PC/BE5# PPAR64 PAD28 PAD55 PAD54 PC/BE6# PPERR# PAD27 PAD26 PAD53 PC/BE7# PSERR# PAD25 PAD52 PREQ64# P33V PAD24 PAD51 PAD50 PFRAME# PACK64# PC/BE3# PIDSEL PAD49 PDEVSEL# PAD23 P33V PAD48 PIRDY# PAD22 PAD47 PAD46 PTRDY# PAD21 PAD20 PAD45 PSTOP# PAD19 PAD44 PIDSEL P33V PAD18 PAD43 PAD42 PPAR PAD41 PREQ# PAD17 PAD16 PAD40 PGNT# PC/BE2# P33V PAD39 PAD38 RST# PFRAME# PAD37 PLOCK# PIRDY# PAD36 P33V PTRDY# PAD35 PAD34 PDEVSEL# PAD33 PSTOP# PAD32 PLOCK# P33V PPERR# +5V PAD31 PAD30 PAD29 PAD28 PAD27 PAD26 PAD25 PAD24 PAD23 PAD22 PAD21 PAD20 PAD19 PAD18 PAD17 PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PSERR# P33V PPAR PC/BE1# PAD15 PAD14 P33V PAD13 PAD12 PAD11 PRST# PAD10 RST# {11} CLK_960 PAD9 LOGIC_CLK {5} PAD8 PC/BE0# CLK PAD7 P33V P33V PAD6 PAD5 PAD4 PAD3 PAD2 CLKA {8} PAD1 PAD0 CLKB {8} PACK64# PREQ64# CLKC {9} CLKD {9} SPARES PRIMARY PCI INTERFACE *

Intel® i960® RN I/O Processor Schematics Figure 15-48. Memory Controller Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 TP2 1 U13 74ALS32 12 13 11 U13 74ALS32 9 10 8 U13 74ALS32 4 5 6 U13 74ALS32 1 2 3 C110 18pF CAP0805 2 1 R22 30 RNC4R8P 8 7 6 5 4 3 2 1 R23 30 RNC4R8P 8 7 6 5 4 3 2 1 R57 2.7K 1/10W 5% 1 2 R37 24 1/10W 5% 1 2 R29 36 1/10W 5% 1 2 R13 1.5K RNC4R8P 8 7 6 5 4 3 2 1 R41 1.5K 1/10W 5% 1 2 R42 1.5K 1/10W 5% 1 2 Z2 JUMP1X2 1 2 Z1 JUMP1X2 1 2 U9 MPC9140/CDC318 11CLKIN 38OE 4 OUT0 5 OUT1 35 OUT10 36 OUT11 40 OUT12 41 OUT13 44 OUT14 45 OUT15 21 OUT16 28 OUT17 8 OUT2 9 OUT3 13 OUT4 14 OUT5 17 OUT6 18 OUT7 31 OUT8 32 OUT9 25SCLK 24SDA MEMORY CONTROLLER U15 i960RN E21 DCLKIN T31 SBA0 T30 SBA1 C21 ONCE D22 DQ0 A23 DQ1 E27 DQ10 C28 DQ11 H32 DQ12 H30 DQ13 J32 DQ14 J29 DQ15 W29 DQ16 Y32 DQ17 Y30 DQ18 AA32 DQ19 C23 DQ2 AA29 DQ20 AB32 DQ21 AB30 DQ22 AC32 DQ23 AC29 DQ24 AD32 DQ25 AD30 DQ26 AE32 DQ27 AE29 DQ28 AF32 DQ29 A24 DQ3 AF30 DQ30 AG32 DQ31 E22 DQ32 B23 DQ33 E23 DQ34 C24 DQ35 E24 DQ36 B25 DQ37 E25 DQ38 C26 DQ39 D24 DQ4 A27 DQ40 C27 DQ41 A28 DQ42 G32 DQ43 H31 DQ44 H28 DQ45 J30 DQ46 J28 DQ47 W28 DQ48 Y31 DQ49 A25 DQ5 Y28 DQ50 AA30 DQ51 AA28 DQ52 AB31 DQ53 AB28 DQ54 AC30 DQ55 AC28 DQ56 AD31 DQ57 AD28 DQ58 AE30 DQ59 C25 DQ6 AE28 DQ60 AF31 DQ61 AF28 DQ62 AH32 DQ63 A26 DQ7 E26 DQ8 B27 DQ9 B13 RAD1/32BITPCI_EN# E15 RAD10 E17 RAD11 A18 RAD12 C18 RAD13 D18 RAD14 E18 RAD15 A19 RAD16 C13 RAD2/32BITMEM_EN# E13 RAD3/RETRY A14 RAD4/STEST C14 RAD5 D14 RAD6/RST_MODE# C15 RAD9 K32 SCB0 K30 SCB1 V31 SCB2 W32 SCB3 K31 SCB4 K28 SCB5 V30 SCB6 W30 SCB7 A22 DCLKOUT A13 RAD0 E14 RAD7 A15 RAD8 B19 RALE N30 SA0 N29 SA1 R28 SA10 T32 SA11 N28 SA2 P32 SA3 P31 SA4 P30 SA5 P28 SA6 R32 SA7 R30 SA8 R29 SA9 T28 SCKE0 U32 SCKE1 L29 SDQM0 M32 SDQM1 U30 SDQM2 U28 SDQM3 L28 SDQM4 M31 SDQM5 U29 SDQM6 V32 SDQM7 C19 RCE0 E19 RCE1 D20 ROE A20 RWE L30 SCAS M30 SCE0 M28 SCE1 N32 SRAS L32 SWE S1 SWDIP4 1 2 3 4 8 7 6 5 R51 22 1/10W 5% 1 2 R50 22 1/10W 5% 1 2 U6 74ALS04 11 10 U6 74ALS04 13 12 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 3 11 +3V SDRAM {5,6} DQ63 DQ62 DQ61 DQ60 DQ59 DQ58 DQ57 DQ56 DQ55 DQ54 DQ53 DQ52 DQ51 DQ50 DQ49 DQ48 DQ47 DQ46 DQ45 DQ44 DQ43 DQ42 DQ41 DQ40 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 DCLKIN DCLKOUT DRAMCLK_LA {5} DCLKOUT DCLK0 {6} DCLK1 {6} SCB7 DCLKIN SCB6 SCB5 SA11 SCB4 SA10 SCB3 DCLK2 {6} SA9 SCB2 DCLK3 {6} SA8 SCB1 SA7 SCB0 RAD {4,5} SA6 SA5 ROE# SA4 RWE# SA3 RCE0# SDA {6,7} SA2 RCE1# SCL {6,7} SA1 RALE SA0 ONCE# SBA0 RAD16 SBA1 RAD15 SRAS# RAD14 SCAS# RAD13 SWE# RAD12 ROMA {4} SCE0# RAD11 ROMA18 SCE1# RAD10 SELUART# {4} SCKE0 {6,11} RAD9 RCE1# RCE1# RAD8 RAD7 SM7 RAD6/RST_MODE# SCKE1 {6,11} SM6 RAD5 IOW# {4} RWE# SM5 RAD4/STEST SM4 RAD3/RETRY SM3 RAD2/32BITMEM_EN# SEL_LED# {4} SM2 RAD1/32BITPCI_EN# SM1 RAD0 SM0 IOR# {4} DQ24 DQ19 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ23 DQ22 DQ21 DQ20 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 RAD6/RST_MODE# RAD3/RETRY RAD2/32BITMEM_EN# RAD4/STEST RAD1/32BITPCI_EN# RAD0 MEMORY CONTROLLER *

Intel® i960® RN I/O Processor Schematics 80 Design Guide Figure 15-49. Flash ROM, UART and LEDs Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R18 1.6K 1/10W 5% 1 2 CR4 LED GREEN LP 2 1 R59 10K 1/10W 5% 1 2 U11 E28F016S5 24A0 23A1 14A10 13A11 8A12 7A13 6A14 5A15 4A16 3A17 2A18 1A19 22A2 40A20 21A3 20A4 19A5 18A6 17A7 16A8 15A9 36 RY/BY 11 VPP 9CE 37OE 12 RP 38WE 25 D0 26 D1 27 D2 28 D3 32 D4 33 D5 34 D6 35 D7 Z4 JUMP1X2 1 2 R19 330 1/10W 5% 1 2 R17 470 1/10W 5% 1 2 CR3 LED RED 2 1 CR5 LED GREEN 2 1 U6 74ALS04 5 6 U6 74ALS04 3 4 U6 74ALS04 9 8 U6 74ALS04 1 2 CR1 LED4SM 8 7 CR1 LED4SM 2 1 CR1 LED4SM 4 3 CR1 LED4SM 6 5 CR2 LED4SM 2 1 CR2 LED4SM 4 3 CR2 LED4SM 8 7 CR2 LED4SM 6 5 R15 470 RNC4R8P 8 7 6 5 4 3 2 1 R16 470 RNC4R8P 8 7 6 5 4 3 2 1 U3 74ABT273 31D 42D 73D 84D 135D 146D 177D 188D 11CLK 1CLR 2 1Q 5 2Q 6 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q U2 74ABT573 21D 32D 43D 54D 65D 76D 87D 98D 11LE 1OC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q U1 74ABT573 21D 32D 43D 54D 65D 76D 87D 98D 11LE 1OC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q J7 CONNJ6-6P 1 2 3 5 4 6 U4 OSC1.8432MHz 1 E/D 5 O U5 1488 2IN1A 4IN1B 5IN2B 9IN3A 10IN3B 12IN4A 13IN4B 3 OUTA 6 OUTB 8 OUTC 11 OUTD U7 1489A 13 12 11 U7 1489A 10 9 8 U7 1489A 1 2 3 U7 1489A 4 5 6 U12 16C550 31A0 30A1 29A2 14CS0 15CS1 25IOR 21IOW 39RST 10 RXCLK 11 RXD 18 XTAL1 28AS 42 CD 16CS2 40 CTS 41 DSR 24IOR 20IOW 43 RI 2D0 3D1 4D2 5D3 6D4 7D5 8D6 9D7 33 INT 32 RXRDY 13 TXD 27 TXRDY 19 XTAL2 17 BAUDOUT 26 DDIS 37 DTR 38 OP1 35 OP2 36 RTS C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 4 11 +5V RAD16 ROMA {3} RAD15 RAD14 RAD {3,5} RAD13 RAD12 +5V RAD11 RAD10 RAD16 ROMA16 RAD9 RAD15 ROMA15 RAD2/32BITMEM_EN# RAD14 ROMA14 RAD1/32BITPCI_EN# RAD13 ROMA13 RAD0 RAD12 ROMA12 +5V RAD11 ROMA11 SELUART# {3} RAD10 ROMA10 RAD9 ROMA9 RALE IOR# {3} IOW# {3} I_RST# {5,7} IRQUART# {7} RAD6/RST_MODE# ROMA20 RAD5 ROMA19 RAD4/STEST ROMA18 +12V RAD3/RETRY ROMA17 +5V ROMA20 ROMA19 ROMA18 ROMA17 RALE ROMA16 I_RST# {5,7} ROMA15 RAD9 LED0 ROMA14 RAD10 LED1 ROMA13 RAD11 LED2 ROMA12 RAD12 LED3 ROMA11 RAD13 LED4 ROMA10 RAD14 LED5 ROMA9 RAD15 LED6 RAD8 RAD16 LED7 RAD7 SEL_LED# {3} LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 RAD6/RST_MODE# RAD5 RAD4/STEST RAD3/RETRY RAD16 +5V RAD2/32BITMEM_EN# RAD15 RAD1/32BITPCI_EN# RAD14 RAD0 RAD13 RAD12 +5V RWE# RAD11 FAIL# {7} RCE0# RAD10 ROE# RAD9 RAM3V {1,6,11} P33V {1,2,8,9} SPARES FLASH ROM, UART, & LEDS *

Intel® i960® RN I/O Processor Schematics Figure 15-50. Logic Analyzer I/F Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 J12 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J11 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J10 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J8 MICTOR 4 25 24 23 22 21 20 5 6 3 CLK0 36 CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 J9 MICTOR 4 25 24 23 22 21 20 5 6 3CLK0 36CLK1 7 8 9 10 39 GND1 40 GND2 41 GND3 42 GND4 43 GND5 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 5 11 SDRAM {3,6} RAD {3,4} DRAMCLK_LA {3} DQ15 SM7 DQ31 RAD15 DQ14 SM6 DQ30 RAD14 DQ13 SM5 DQ29 RAD13 DQ12 SM4 DQ28 RAD12 DQ11 SM3 DQ27 RAD11 DQ10 SM2 DQ26 RAD10 DQ9 SM1 DQ25 RAD9 DQ8 SM0 DQ24 RAD8 DQ7 SCB7 DQ23 RAD7 DQ6 SCB6 DQ22 RAD6/RST_MODE# DQ5 SCB5 DQ21 RAD5 DQ4 SCB4 DQ20 RAD4/STEST SCE0# DQ3 SCB3 DQ19 RAD3/RETRY SCE1# DQ2 SCB2 DQ18 RAD2/32BITMEM_EN# SBA1 DQ1 SCB1 DQ17 RAD1/32BITPCI_EN# SBA0 DQ0 SCB0 DQ16 RAD0 LOGIC_CLK {2} RALE DQ47 SWE# DQ63 DQ46 SCAS# DQ62 DQ45 SRAS# DQ61 DQ44 DQ60 SPCI {7,8,9,10} SGNT5# DQ43 SA11 DQ59 SGNT4# DQ42 SA10 DQ58 SGNT3# DQ41 SA9 DQ57 I_RST# {4,7} SGNT2# DQ40 SA8 DQ56 SGNT1# DQ39 SA7 DQ55 RWE# SGNT0# DQ38 SA6 DQ54 ROE# SREQ5# DQ37 SA5 DQ53 RCE1# SREQ4# DQ36 SA4 DQ52 RCE0# SREQ3# DQ35 SA3 DQ51 RALE SREQ2# DQ34 SA2 DQ50 SREQ1# DQ33 SA1 DQ49 SREQ0# DQ32 SA0 DQ48 RAD16 LOGIC ANALYZER I/F *

Intel® i960® RN I/O Processor Schematics 82 Design Guide Figure 15-51. SDRAM 168-Pin DIMM Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 U21 TL7702BCD 5 RESET 2 RESIN 3 CT 1 REF 6 RESET 7 SENSE U20 TL7702BCD 5 RESET 2 RESIN 3 CT 1 REF 6 RESET 7 SENSE C119 0.047uF CAP0805 2 1 C118 0.047uF CAP0805 2 1 J5 SDRAM-DIMM168P 117 A1 123 A11 118 A3 119 A5 120 A7 121 A9 122 BA0 111 CAS 105 CB4 106 CB5 136 CB6 137 CB7 128 CKE0 125 CLK1 163 CLK3 114 CS1 129 CS3 85GND1 96GND2 107 GND3 116 GND4 127 GND5 138 GND6 148 GND7 152 GND8 162 GND9 112 M4 113 M5 130 M6 131 M7 108 NC1 147 NC10 164 NC11 109 NC2 126 NC4 132 NC5 134 NC6 135 NC7 145 NC8 146 NC9 115 RAS 165 SA0 166 SA1 167 SA2 90VCC1 102 VCC2 110 VCC3 124 VCC4 133 VCC5 143 VCC6 157 VCC7 168 VCC8 86DQ32 87DQ33 88DQ34 89DQ35 91DQ36 92DQ37 93DQ38 94DQ39 95DQ40 97DQ41 98DQ42 99DQ43 100 DQ44 101 DQ45 103 DQ46 104 DQ47 139 DQ48 140 DQ49 141 DQ50 142 DQ51 144 DQ52 149 DQ53 150 DQ54 151 DQ55 153 DQ56 154 DQ57 155 DQ58 156 DQ59 158 DQ60 159 DQ61 160 DQ62 161 DQ63 J5 SDRAM-DIMM168P 33A0 38A10 34A2 35A4 36A6 37A8 39BA1 21CB0 22CB1 52 CB2 53 CB3 63 CKE1 42CLK0 79 CLK2 30CS0 45 CS2 9DQ6 1GND1 12GND2 23GND3 32GND4 43 GND5 54 GND6 64 GND7 68 GND8 78 GND9 28M0 29M1 46 M2 47 M3 24NC1 80 NC10 81 NC11 25NC2 31NC3 44 NC4 48 NC5 50 NC6 51 NC7 61 NC8 62 NC9 83 SCL 82 SDA 6VCC1 18VCC2 26VCC3 40VCC4 41VCC5 49 VCC6 59 VCC7 73 VCC8 84 VCC9 27WE 2DQ0 3DQ1 14DQ10 15DQ11 16DQ12 17DQ13 19DQ14 20DQ15 55 DQ16 56 DQ17 57 DQ18 58 DQ19 4DQ2 60 DQ20 65 DQ21 66 DQ22 67 DQ23 69 DQ24 70 DQ25 71 DQ26 72 DQ27 74 DQ28 75 DQ29 5DQ3 76 DQ30 77 DQ31 7DQ4 8DQ5 10DQ7 11DQ8 13DQ9 R62 1K 1/10W 5% 1 2 R61 1K 1/10W 5% 1 2 C121 0.1uF CAP0805 2 1 C120 0.1uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 6 11 RAM3V {1,4,11} SDRAM {3,5} DQ0 DQ32 SCKE0 {3,11} DQ1 SCE0# DQ33 SCE1# DQ2 SM2 DQ34 SM6 DQ3 SM3 DQ35 SM7 +3V DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 SCKE0 {3,11} DQ7 SCB2 DQ39 SCB6 DQ8 SCB3 DQ40 SCB7 DQ9 DQ16 DQ41 DQ48 DQ10 DQ17 DQ42 DQ49 DQ11 DQ18 DQ43 DQ50 DQ12 DQ19 DQ44 DQ51 DQ13 DQ45 DQ20 DQ52 +3V DQ14 DQ46 DQ15 DQ47 SCB0 SCKE1 {3,11} SCB4 SCB1 SCB5 SCKE1 {3,11} DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 SWE# DQ24 SCAS# DQ56 SM0 DQ25 SM4 DQ57 SM1 DQ26 SM5 DQ58 SCE0# DQ27 SCE1# DQ59 SRAS# DQ28 DQ60 SA0 DQ29 SA1 DQ61 SA2 DQ30 SA3 DQ62 SA4 DQ31 SA5 DQ63 SA6 SA7 SA8 DCLK2 {3} SA9 DCLK3 {3} SA10 SBA0 SBA1 SA11 SDA {3,7} SCL {3,7} DCLK1 {3} DCLK0 {3} SDRAM 168-PIN DIMM *

Intel® i960® RN I/O Processor Schematics Figure 15-52. Secondary PCI/80960 Core Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R14 1.5K 1/10W 5% 1 2 JX CORE/I2C/JTAG U15 i960RN C12 TCK A12 TDI B11 TMS E20 VCC5REF C22 VCCPLL1 B15 VCCPLL2 D26 VCCPLL3 A21 LCDINIT A9 NMI B9 S_INTA/XINT0 C9 S_INTB/XINT1 E9 S_INTC/XINT2 A10 S_INTD/XINT3 C11 TRST C10 XINT4 D10 XINT5 C8 SDA A8 SCL E11 TDO E12 FAIL A11 I_RST SECONDARY PCI SIGNALS U15 i960RN AM13 S_ACK64 AL26 S_REQ0 AH27 S_REQ1 AK27 S_REQ2 AH28 S_REQ3 AL28 S_REQ4 AJ29 S_REQ5 AH14 S_AD0 AK14 S_AD1 AM17 S_AD10 AH18 S_AD11 AK18 S_AD12 AL18 S_AD13 AM18 S_AD14 AH19 S_AD15 AH22 S_AD16 AK22 S_AD17 AL22 S_AD18 AM22 S_AD19 AL14 S_AD2 AH23 S_AD20 AJ23 S_AD21 AK23 S_AD22 AM23 S_AD23 AK24 S_AD24 AL24 S_AD25 AM24 S_AD26 AH25 S_AD27 AJ25 S_AD28 AK25 S_AD29 AM14 S_AD3 AM25 S_AD30 AH26 S_AD31 AH1 S_AD32 AH3 S_AD33 AH4 S_AD34 AJ2 S_AD35 AJ5 S_AD36 AK5 S_AD37 AM5 S_AD38 AH6 S_AD39 AH15 S_AD4 AK6 S_AD40 AL6 S_AD41 AM6 S_AD42 AH7 S_AD43 AJ7 S_AD44 AK7 S_AD45 AM7 S_AD46 AH8 S_AD47 AK8 S_AD48 AL8 S_AD49 AJ15 S_AD5 AM8 S_AD50 AH9 S_AD51 AJ9 S_AD52 AK9 S_AD53 AM9 S_AD54 AH10 S_AD55 AK10 S_AD56 AL10 S_AD57 AM10 S_AD58 AH11 S_AD59 AK15 S_AD6 AJ11 S_AD60 AK11 S_AD61 AM11 S_AD62 AH12 S_AD63 AM15 S_AD7 AJ17 S_AD8 AK17 S_AD9 AK19 S_PAR AK12 S_PAR64 AH17 S_C/BE0 AJ19 S_C/BE1 AM21 S_C/BE2 AH24 S_C/BE3 AL12 S_C/BE4 AM12 S_C/BE5 AH13 S_C/BE6 AJ13 S_C/BE7 AM20 S_DEVSEL AK21 S_FRAME AJ21 S_IRDY AK20 S_LOCK AH20 S_PERR AK13 S_REQ64 AM19 S_SERR AL20 S_STOP AH21 S_TRDY AM26 S_GNT0 AJ27 S_GNT1 AM27 S_GNT2 AK28 S_GNT3 AM28 S_GNT4 AK29 S_GNT5 AK26 S_RST R36 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R3 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R44 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R52 100 1/2W 5% 1 2 J6 HEAD16SH JTAG HEADER 1 10 11 12 13 14 15 16 2 3 4 5 6 7 8 9 R30 10 1/8W 5% 1 2 R56 10 1/8W 5% 1 2 R43 10 1/8W 5% 1 2 C61 0.01uF CAP0805 2 1 C96 0.01uF CAP0805 2 1 C77 0.01uF CAP0805 2 1 C57 4.7uF CAPT7343 2 1 C92 4.7uF CAPT7343 2 1 C76 4.7uF CAPT7343 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 7 11 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 7 11 SPCI {5,8,9,10} SAD63 SAD62 SAD61 SAD60 SAD59 SAD58 SAD57 SAD56 SAD55 SAD54 SAD53 SAD52 SAD51 SAD50 SAD49 SAD48 SAD47 SAD46 SAD45 SAD44 SAD43 SAD42 SAD41 SAD40 SAD39 SAD38 SAD37 SAD36 SAD35 SAD34 SAD33 SAD32 +5V SC/BE0# SC/BE1# SREQ0# SC/BE2# SREQ1# SC/BE3# SREQ2# SC/BE4# SREQ3# SC/BE5# SREQ4# SC/BE6# SREQ5# SC/BE7# SGNT0# SREQ64# SGNT1# SACK64# SDA {3,6} SCL {3,6} SGNT2# SFRAME# SGNT3# SIRDY# +3V SGNT4# STRDY# SGNT5# SSTOP# SDEVSEL# SINTA# SPAR SSERR# SINTB# SPAR64 SRST# SINTC# SPERR# SINTD# SLOCK# IRQFAN# {11} IRQUART# {4} FAIL# {4} I_RST# {4,5} SAD31 SAD30 SAD29 SAD28 SAD27 SAD26 SAD25 SAD24 SAD23 SAD22 SAD21 SAD20 SAD19 SAD18 SAD17 SAD16 SAD15 SAD14 SAD13 SAD12 SAD11 SAD10 SAD9 SAD8 SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 +5V +3V SECONDARY PCI/960 CORE *

Intel® i960® RN I/O Processor Schematics 84 Design Guide Figure 15-53. Secondary PCI Bus 1/2 Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 J1 CONNPCI_64 A66 +5V1 A75 +5V2 A84 +5V3 B70 +5V4 B79 +5V5 B88 +5V6 A91 AD32 B90 AD33 A89 AD34 B89 AD35 A88 AD36 B87 AD37 A86 AD38 B86 AD39 A85 AD40 B84 AD41 A83 AD42 B83 AD43 A82 AD44 B81 AD45 A80 AD46 B80 AD47 A79 AD48 B78 AD49 A77 AD50 B77 AD51 A76 AD52 B75 AD53 A74 AD54 B74 AD55 A73 AD56 B72 AD57 A71 AD58 B71 AD59 A70 AD60 B69 AD61 A68 AD62 B68 AD63 A63 GND1 B67 GND10 B73 GND11 B76 GND12 B82 GND13 B85 GND14 B91 GND15 B94 GND16 A69 GND2 A72 GND3 A78 GND4 A81 GND5 A87 GND6 A90 GND7 A93 GND8 B64 GND9 A67 PAR64 A92 A94 B63 B92 B93 B66 C/BE4 A65 C/BE5 B65 C/BE6 A64 C/BE7 J2 CONNPCI_64 A66 +5V1 A75 +5V2 A84 +5V3 B70 +5V4 B79 +5V5 B88 +5V6 A91 AD32 B90 AD33 A89 AD34 B89 AD35 A88 AD36 B87 AD37 A86 AD38 B86 AD39 A85 AD40 B84 AD41 A83 AD42 B83 AD43 A82 AD44 B81 AD45 A80 AD46 B80 AD47 A79 AD48 B78 AD49 A77 AD50 B77 AD51 A76 AD52 B75 AD53 A74 AD54 B74 AD55 A73 AD56 B72 AD57 A71 AD58 B71 AD59 A70 AD60 B69 AD61 A68 AD62 B68 AD63 A63 GND1 B67 GND10 B73 GND11 B76 GND12 B82 GND13 B85 GND14 B91 GND15 B94 GND16 A69 GND2 A72 GND3 A78 GND4 A81 GND5 A87 GND6 A90 GND7 A93 GND8 B64 GND9 A67 PAR64 A92 A94 B63 B92 B93 B66 C/BE4 A65 C/BE5 B65 C/BE6 A64 C/BE7 J2 CONNPCI_64 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J1 CONNPCI_64 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J2 CONNPCI_64 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST J1 CONNPCI_64 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST C19 0.01uF CAP0805 2 1 C18 0.01uF CAP0805 2 1 C27 0.01uF CAP0805 2 1 C26 0.01uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 8 11 SPCI {5,7,9,10} +12V +5V +5V N12V +5V +5V +5V +5V SC/BE7# STRST# {9,10} SAD17 SAD16 SC/BE6# SC/BE5# STCK {9,10} SC/BE2# P33V {1,2,4,9} SC/BE4# STMS {9,10} SFRAME# SPAR64 STDI {9,10} SIRDY# SAD63 SAD62 P33V {1,2,4,9} STRDY# SAD61 SINTA# SDEVSEL# SAD60 SINTB# SINTC# SSTOP# SAD59 SAD58 SINTD# SLOCK# SAD57 SPERR# SAD56 SAD55 SAD54 SSERR# SAD53 SPAR SAD52 SC/BE1# SAD15 SAD51 SAD50 SAD14 SAD49 SRST# SAD13 SAD48 CLKA {2} SAD12 SAD11 SAD47 SAD46 SGNT0# SAD10 SAD45 SREQ0# SAD9 SAD44 SAD43 SAD42 SAD31 SAD30 SAD41 SAD29 P33V {1,2,4,9} SAD8 SC/BE0# SAD40 SAD28 SAD7 SAD39 SAD38 SAD27 SAD26 SAD6 SAD37 SAD25 SAD5 SAD4 SAD36 P33V {1,2,4,9} SAD24 SAD3 SAD35 SAD34 SC/BE3# SAD16 SAD2 SAD33 SAD23 SAD1 SAD0 SAD32 SAD22 SAD21 SAD20 SACK64# SREQ64# SAD19 SAD18 +12V N12V STRST# {9,10} SAD17 SAD16 SC/BE7# STCK {9,10} SC/BE2# P33V {1,2,4,9} SC/BE6# SC/BE5# STMS {9,10} SFRAME# SC/BE4# STDI {9,10} SIRDY# SPAR64 P33V {1,2,4,9} STRDY# SAD63 SAD62 SINTB# SDEVSEL# SAD61 SINTC# SINTD# SSTOP# SAD60 SINTA# SLOCK# SAD59 SAD58 SPERR# SAD57 SAD56 SSERR# SAD55 SAD54 SPAR SAD53 SC/BE1# SAD15 SAD52 SAD14 SAD51 SAD50 SRST# SAD13 SAD49 CLKB {2} SAD12 SAD11 SAD48 SGNT1# SAD10 SAD47 SAD46 SREQ1# SAD9 SAD45 SAD44 SAD31 SAD30 SAD43 SAD42 SAD29 SAD8 SC/BE0# SAD41 SAD28 SAD7 SAD40 SAD27 SAD26 SAD6 SAD39 SAD38 SAD25 SAD5 SAD4 SAD37 SAD24 SAD3 SAD36 SC/BE3# SAD17 SAD2 SAD35 SAD34 SAD23 SAD1 SAD0 SAD33 SAD22 SAD32 SAD21 SAD20 SACK64# SREQ64# SAD19 SAD18 SPCI CONN 2 SPCI CONN 1 SECONDARY PCI BUS 1/2 *

Intel® i960® RN I/O Processor Schematics Figure 15-54. Secondary PCI Bus 3/4 Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 J4 CONNPCI_64 A66 +5V1 A75 +5V2 A84 +5V3 B70 +5V4 B79 +5V5 B88 +5V6 A91 AD32 B90 AD33 A89 AD34 B89 AD35 A88 AD36 B87 AD37 A86 AD38 B86 AD39 A85 AD40 B84 AD41 A83 AD42 B83 AD43 A82 AD44 B81 AD45 A80 AD46 B80 AD47 A79 AD48 B78 AD49 A77 AD50 B77 AD51 A76 AD52 B75 AD53 A74 AD54 B74 AD55 A73 AD56 B72 AD57 A71 AD58 B71 AD59 A70 AD60 B69 AD61 A68 AD62 B68 AD63 A63 GND1 B67 GND10 B73 GND11 B76 GND12 B82 GND13 B85 GND14 B91 GND15 B94 GND16 A69 GND2 A72 GND3 A78 GND4 A81 GND5 A87 GND6 A90 GND7 A93 GND8 B64 GND9 A67 PAR64 A92 A94 B63 B92 B93 B66 C/BE4 A65 C/BE5 B65 C/BE6 A64 C/BE7 J3 CONNPCI_64 A66 +5V1 A75 +5V2 A84 +5V3 B70 +5V4 B79 +5V5 B88 +5V6 A91 AD32 B90 AD33 A89 AD34 B89 AD35 A88 AD36 B87 AD37 A86 AD38 B86 AD39 A85 AD40 B84 AD41 A83 AD42 B83 AD43 A82 AD44 B81 AD45 A80 AD46 B80 AD47 A79 AD48 B78 AD49 A77 AD50 B77 AD51 A76 AD52 B75 AD53 A74 AD54 B74 AD55 A73 AD56 B72 AD57 A71 AD58 B71 AD59 A70 AD60 B69 AD61 A68 AD62 B68 AD63 A63 GND1 B67 GND10 B73 GND11 B76 GND12 B82 GND13 B85 GND14 B91 GND15 B94 GND16 A69 GND2 A72 GND3 A78 GND4 A81 GND5 A87 GND6 A90 GND7 A93 GND8 B64 GND9 A67 PAR64 A92 A94 B63 B92 B93 B66 C/BE4 A65 C/BE5 B65 C/BE6 A64 C/BE7 J4 CONNPCI_64 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J3 CONNPCI_64 A33 +3V1 A39 +3V2 A45 +3V3 A53 +3V4 B36 +3V5 B41 +3V6 B43 +3V7 B54 +3V8 A59 +5V1 A61 +5V2 A62 +5V3 B59 +5V4 B61 +5V5 B62 +5V6 A58 AD00 B58 AD01 A57 AD02 B56 AD03 A55 AD04 B55 AD05 A54 AD06 B53 AD07 B52 AD08 A49 AD09 B48 AD10 A47 AD11 B47 AD12 A46 AD13 B45 AD14 A44 AD15 A32 AD16 B32 AD17 A35 GND1 B57 GND10 A37 GND2 A42 GND3 A48 GND4 A56 GND5 B34 GND6 B38 GND7 B46 GND8 B49 GND9 A43 PAR A40 SDONE B60 ACK64 A52 C/BE0 B44 C/BE1 B33 C/BE2 B37 DEVSEL A34 FRAME B35 IRDY B39 LOCK B40 PERR A60 REQ64 A41 SBO B42 SERR A38 STOP A36 TRDY J4 CONNPCI_64 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST J3 CONNPCI_64 A2 +12V A21 +3V1 A27 +3V2 B25 +3V3 B31 +3V4 A5 +5V1 A8 +5V2 A10 +5V3 A16 +5V4 B5 +5V5 B6 +5V6 B19 +5V7 B1 -12V A31 AD18 B30 AD19 A29 AD20 B29 AD21 A28 AD22 B27 AD23 A25 AD24 B24 AD25 A23 AD26 B23 AD27 A22 AD28 B21 AD29 A20 AD30 B20 AD31 B16 CLK A12 GND1 B17 GND10 B22 GND11 B28 GND12 A13 GND2 A18 GND3 A24 GND4 A30 GND5 B3 GND6 B12 GND7 B13 GND8 B15 GND9 A26 IDSEL A9 A11 A14 A19 B10 B14 B2 TCK A4 TDI B4 TDO A3 TMS B26 C/BE3 A17 GNT A6 INTA B7 INTB A7 INTC B8 INTD B9 PRSNT1 B11 PRSNT2 B18 REQ A15 RST A1 TRST C3 0.01uF CAP0805 2 1 C2 0.01uF CAP0805 2 1 C11 0.01uF CAP0805 2 1 C10 0.01uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 9 11 SPCI {5,7,8,10} +12V +5V +5V +5V N12V +5V +5V +5V SC/BE7# STRST# {8,10} SAD17 SAD16 SC/BE6# SC/BE5# STCK {8,10} SC/BE2# P33V {1,2,4,8} SC/BE4# STMS {8,10} SFRAME# SPAR64 STDI {8,10} SIRDY# SAD63 SAD62 P33V {1,2,4,8} STRDY# SAD61 SINTC# SDEVSEL# SAD60 SINTD# SINTA# SSTOP# SAD59 SAD58 SINTB# SLOCK# SAD57 SPERR# SAD56 SAD55 SAD54 SSERR# SAD53 SPAR SAD52 SC/BE1# SAD15 SAD51 SAD50 SAD14 SAD49 SRST# SAD13 SAD48 CLKC {2} SAD12 SAD11 SAD47 SAD46 SGNT2# SAD10 SAD45 SREQ2# SAD9 SAD44 SAD43 SAD42 SAD31 SAD30 SAD41 SAD29 P33V {1,2,4,8} SAD8 SC/BE0# SAD40 SAD28 SAD7 SAD39 SAD38 SAD27 SAD26 SAD6 SAD37 SAD25 SAD5 SAD4 SAD36 P33V {1,2,4,8} SAD24 SAD3 SAD35 SAD34 SC/BE3# SAD18 SAD2 SAD33 SAD23 SAD1 SAD0 SAD32 SAD22 SAD21 SAD20 SACK64# SREQ64# SAD19 SAD18 +12V N12V STRST# {8,10} SAD17 SAD16 SC/BE7# STCK {8,10} SC/BE2# P33V {1,2,4,8} SC/BE6# SC/BE5# STMS {8,10} SFRAME# SC/BE4# STDI {8,10} SIRDY# SPAR64 P33V {1,2,4,8} STRDY# SAD63 SAD62 SINTD# SDEVSEL# SAD61 SINTA# SINTB# SSTOP# SAD60 SINTC# SLOCK# SAD59 SAD58 SPERR# SAD57 SAD56 SSERR# SAD55 SAD54 SPAR SAD53 SC/BE1# SAD15 SAD52 SAD14 SAD51 SAD50 SRST# SAD13 SAD49 CLKD {2} SAD12 SAD11 SAD48 SGNT3# SAD10 SAD47 SAD46 SREQ3# SAD9 SAD45 SAD44 SAD31 SAD30 SAD43 SAD42 SAD29 SAD8 SC/BE0# SAD41 SAD28 SAD7 SAD40 SAD27 SAD26 SAD6 SAD39 SAD38 SAD25 SAD5 SAD4 SAD37 SAD24 SAD3 SAD36 SC/BE3# SAD19 SAD2 SAD35 SAD34 SAD23 SAD1 SAD0 SAD33 SAD22 SAD32 SAD21 SAD20 SACK64# SREQ64# SAD19 SAD18 SPCI CONN 4 SPCI CONN 3 SECONDARY PCI BUS 3/4 *

Intel® i960® RN I/O Processor Schematics 86 Design Guide Figure 15-55. SPCI Pull-Ups Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R2 2.7K 1/10W 5% 1 2 R4 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R5 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R6 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R7 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R8 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R9 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R10 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R11 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R12 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R45 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R31 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R33 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R38 2.7K RNC4R8P 8 7 6 5 4 3 2 1 R1 2.7K RNC4R8P 8 7 6 5 4 3 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RN 1999/02/04 10 11 SPCI {5,7,8,9} +5V +5V +5V SAD32 SAD52 STMS SAD33 SAD53 STDI SAD34 SAD54 STRST# SAD35 SAD55 STCK +5V SAD36 SAD56 SFRAME# SAD37 SAD57 STRDY# SAD38 SAD58 SIRDY# SAD39 SAD59 SDEVSEL# SAD40 SAD60 SSTOP# SAD41 SAD61 SSERR# SAD42 SAD62 SPERR# SAD43 SAD63 SLOCK# SAD44 SC/BE4# SREQ0# SAD45 SC/BE5# SREQ1# SAD46 SC/BE6# SREQ2# SAD47 SC/BE7# SREQ3# SAD48 SPAR64 SREQ4# SAD49 SREQ5# SAD50 SACK64# SAD51 SREQ64# SPCI PULL-UPS *

Intel® i960® RN I/O Processor Schematics Figure 15-56. Battery/Monitor Schematic A B C D E F G H A B C D E F G H 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R24 100K 1/10W 5% 1 2 R32 100K 1/10W 5% 1 2 R60 10 1/10W 5% 1 2 R27 1 1/10W 5% 1 2 R28 1 1/10W 5% 1 2 R53 47K 1/10W 5% 1 2 R49 4.7K 1/10W 5% 1 2 R48 4.7K 1/10W 5% 1 2 U19 PALLV16V8-10JC 1 I0 2 I1 3 I2 4 I3 5 I4 6 I5 7 I6 8 I7 9 I8 11 I9 20 VCC 12 F0 13 F1 14 F2 15 F3 16 F4 17 F5 18 F6 19 F7 U10 LM339 9 + 8 - 14 U10 LM339 11 + 10 - 13 U10 LM339 7 + 6 - 1 U10 LM339 5 + 4 - 2 R35 10K 1/10W 5% 1 2 C82 0.047uF CAP0805 2 1 R47 2.4K 1/10W 5% 1 2 C47 22uF CAPT7343 2 1 C65 0.47uF CAP1206 2 1 J13 FAN CONN 1 FAN 2GND 3PWR C63 33uF CAPT7343 2 1 Q4 2N6109 1 2 3 R21 0.05 1W 1% 1 2 R20 150 1/10W 5% 1 2 R26 68K 1/10W 5% 1 2 R34 22K 1/10W 5% 1 2 BT8 BATT_HLDR 2 1 BT6 BATT_HLDR 2 1 BT1 BATT_HLDR 2 1 BT3 BATT_HLDR 2 1 BT7 BATT_HLDR 2 1 BT5 BATT_HLDR 2 1 BT2 BATT_HLDR 2 1 BT4 BATT_HLDR 2 1 CR8 CMR1-02 1 2 C64 330uF CAPT7343H 2 1 C56 100uF CAPT7343H 2 1 U8 MAX1651 2FB 8GND 4REF 3SHDN 6 CS 7 EXT 1 OUT 5 V+ U14 MAX712 11CC 13GND 3 PGM0 4 PGM1 9 PGM2 10 PGM3 7TEMP 5THI 6TLO 1VLIMIT 2 BATT+ 12 BATT- 14 DRV 16REF 15V+ 8 FASTCHG L1 47uH 1 2 7 6 5 4 3 CR7 MBRS340T3 1 2 Q1 SI9430 5 6 7 8 4 1 2 3 R25 1K 1/10W 5% 1 2 C74 1uF CAPT3216 2 1 C54 10uF CAPT7343 2 1 C52 10uF CAPT7343 2 1 C51 0.1uF CAP0805 2 1 C53 0.1uF CAP0805 2 1 C58 0.01uF CAP0805 2 1 C55 0.01uF CAP0805 2 1 C68 0.01uF CAP0805 2 1 C REV Title: Name: Date: NEW HAVEN, CT 06511 25 SCIENCE PARK CYCLONE MICROSYSTEMS Sheet of 80960RM 2000/06/26 10 10 SCKE0 {3,6} +12V SCKE1 {3,6} RST# {2} RAM3V {1,4,6} BATTERY RAM3V {1,4,6} +5V +5V IRQFAN# {7} PART # 101-1950-01 NOTE: VCC FOR LM339 IS +5V SPARES + + + + BATTERY/MONITOR *

Intel® IQ80960RN Board Bill of Material 88 Design Guide Intel® IQ80960RN Board Bill of MaterialD This appendix identifies all components on the IQ80960RN Evaluation Platform (Table D-1). Table D-1. Intel® IQ80960RN Bill of Materials (Sheet 1 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # 1 1 U13 IC/SM 74ALS32 SOIC-14 National Semiconductor DM74ALS32M 2 1 U6 IC/SM 74ALS04 SOIC National Semiconductor DM74ALS04BM 3 1 U3 IC/SM 74ABT273 SOIC Texas Instruments SN74ABT273DW 4 2 U1,U2 IC/SM 74ABT573 SOIC Texas Instruments SN74ABT573DW 5 1 U16 IC/SM 74ALS08 SOIC National Semiconductor DM74ALS08M 6 1 U5 IC / SM 1488A SOIC National Semiconductor DS1488M 7 1 U7 IC / SM 1489A SOIC National Semiconductor DS1489AM 8 1 Q1 IC/SM Si9430DY SOIC-8 Siliconix Si9430DY 9 1 U9 IC/SM LVCMOS Fanout Buffr SSOP Motorola MPC9140 10 1 U10 IC/SM LM339 SOIC-14 National Semiconductor LM339M 11 1 U8 IC/SM MAX1651CSA SOIC-8 Maxim MAX1651CSA 12 1 U14 IC/SM MAX712CSE SOIC-16 Maxim MAX712CSE 13 1 U17 IC/SM MAX767CAP SOIC Maxim MAX767CAP 14 1 U15 80960RN PROCESSOR Intel 15 1 U12 VLSI I/O UART 16C550 PLCC Texas Instruments TL16C550AFN 16 1 C65 CAP SM, 0.47 µF (1206) Philips Philips 12062F474Z9BB0 17 15 C2, C3, C10, C11, C18, C19, C26, C27, C55, C58, C61, C68, C77, C83, C96 CAP SM, 0.01 µF (0805) Kemet C0805C103K5RAC *

Intel® IQ80960RN Board Bill of Material 18 79 C1, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C48, C49, C50, C51, C53, C59, C62, C66, C67, C69, C70, C71, C73, C79, C80, C81, C85, C86, C87, C94, C95, C97, C98, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C111, C112, C113, C115, C116, C114, C117 CAP SM, 0.1 µF (0805) Philips 08052R104K8BB2 19 1 C110 CAP SM, 18 pF (0805) Kemet C0805C180J5GAC 20 2 R27, R28 R/SM 1/10 W 5% 1 ohm (0805) Dale CRCW0805100JT 21 1 R60 R/SM 1/10 W 5% 10 ohm (0805) Dale CRCW08051000JT 22 1 R25 R/SM 1/10 W 5% 1 Kohm (0805) Dale CRCW08051001FRT 23 4 R35, R39, R58, R59 R/SM 1/10 W 5% 10 Kohm (0805) Dale CRCW08051002FRT 24 2 R24, R32 R/SM 1/10 W 5% 100 Kohm (0805) Dale CRCW08051003FRT 25 1 R20 R/SM 1/10 W 1% 150 ohm (0805) Dale CRCW08051500FRT 26 3 R14, R41, R42 R/SM 1/10 W 5% 1.5 Kohm (0805) Dale CRCW0805152JT 27 1 R18 R/SM 1/10 W 5% 1.6 Kohm (0805) Dale CRCW0805162JT 28 2 R50, R51 R/SM 1/10 W 5% 22 ohm (0805) Dale CRCW0805220JT 29 1 R34 R/SM 1/10 W 5% 22 Kohm (0805) Dale CRCW0805223JT 30 1 R37 R/SM 1/10 W 5% 24 ohm (0805) Dale CRCW0805240JT 31 1 R47 R/SM 1/10 W 5% 2.4 Kohm (0805) Dale CRCW0805242JT 32 2 R2, R57 R/SM 1/10 W 5% 2.7 Kohm (0805) Dale CRCW0805272JT Table D-1. Intel® IQ80960RN Bill of Materials (Sheet 2 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # *

Intel® IQ80960RN Board Bill of Material 90 Design Guide 33 1 R19 R/SM 1/10 W 5% 330 ohm (0805) Dale CRCW0805331JT 34 1 R29 R/SM 1/10 W 5% 36 ohm (0805) Dale CRCW0805360JT 35 1 R17 R/SM 1/10 W 5% 470 ohm (0805) Dale CRCW 0805 471JT 36 2 R48, R49 R/SM 1/10 W 1% 4.7 Kohm (0805) Dale CRCW08054701FRT 37 1 R53 R/SM 1/10 W 5% 47 Kohm (0805) Dale CRCW0805473JT 38 1 R26 R/SM 1/10 W 5% 68 Kohm (0805) Dale CRCW0805683JT 39 4 R30, R43, R54, R56 R/SM 1/8 W 5% 10 ohm chip 1206 Dale CRCW1206100FT 40 5 J8, J9, J10, J11, J12 CONN SM/TH Mictor 43P Recptcl AMP 767054-1 41 4 J1, J2, J3, J4a CONN PCI 64BIT 5 V/PCB ThruHole AMP 145166-4 42 1 J5 CONN DIMM 168P/RAng/Socket/TH Molex 73790-0059 43 1 J7 CONN TJ6 PCB 6/6 LP through hole KYCON GM-N-66 44 1 J13 CONN/FAN ASSY/Socket/ThruHole AMP 173981-03 45 1 J6 CONN Hdr 16 pin/w shell, pcb AMP 103308-3 46 4 Z1, Z2, Z3, Z4 Jumper JUMP2X1 Molex 22-54-1402 47 1 L1 Inductor/SM 47µH 20% Coilcraft D03340P-473 48 1 L2 Inductor/SM 3.3 µH 20% Coilcraft D03316P-332 49 1 S1 Switch/SM DIP4 Mors# DHS-4S Mors DHS-4S 50 1 U4 OSC 1.8432 MHz 1/2 - Through hole Kyocera KH0HC1CSE 1.843 51 1 U18 Clock Chip CY7B9910-7SC Cypress CY7B9910-7SC 52 1 CR5 LED Green Hewlett Packard HLMP-3507$010 53 1 CR3 LED-Red Hewlett Packard HLMP3301$010 54 1 CR4 LED Green LP Hewlett Packard HLMP4740#010 55 2 CR1, CR2 LED-Red-Small Group Dialight 555-4001 56 2 Q2, Q3 Transistor/SM N-Channel Harris RFD16N05LSM 57 1 Q4 Transistor 2N6109 (Through Hole) Motorola 2N6109 58 1 U19 SOCKET PLCC20 LP Surface Mount AMP 822269-1 60 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery Clips/PC/Snap-In/AA Keystone #92 61 1 U19 PALLV16V8Z-20JI AMD PALLV16V8Z-20JI 62 1 U11 MEM Flash E28F016S5-090 TSOP Intel E28F016S5-090 63 8 BT1, BT2, BT3, BT4, BT5, BT6, BT7, BT8 Battery AA NiCd @ 600 mA/Hour SAFT NIC-AA-600-SAFT 64 1 U15 HeatSink/Fan Assy 80960RM/RN Panasonic UDQFNBEOIF Table D-1. Intel® IQ80960RN Bill of Materials (Sheet 3 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # *

Intel® IQ80960RN Board Bill of Material 65 1 C84 CAP SM, 0.22 µF (1206) Philips 12062E224M9BB2 66 3 C60, C75, C78 CAP TANT SM 220 µF, 10 V (7343) AVX TPSE227K010R010 67 4 C89, C90, C91, C93 CAP TANT SM 47 µF, 16 V (7343) AVX TPSD476K016R015 68 1 C63 CAP TANT SM 33 µF, 10 V (7343) Sprague 293D336X9016D2T 69 4 C57, C76, C88, C92 CAP TANT SM 4.7 µF, 35 V (7343) Sprague 293D475X9035D2T 70 1 C47 CAP TANT SM 22 µF, 20 V (7343) Sprague 293D226X9020D2T 71 1 C74 CAP TANT SM 1 µF, 16 V (3216) Sprague 293D105X0016A2T 72 2 C52, C54 CAP TANT SM 10 µF, 25/35 V Sprague 293D1060025D2T 73 1 C56 CAP TANT SM 100 µF 10 V (7343) AVX TPSD107K010R0100 74 1 C64 CAP TANT SM 330 µF 6.3 V (7343 AVX TPSE337K063R0100 75 1 C82 CAP SM, 0.047 µF (0805) Kemet C0805C473K5RAC 76 1 R46 Res/SM 1 W 1% 0.012 ohm (2512) Dale WSL-2512-R012 77 1 R21 Res/SM 1 W 1% 0.05 ohm (2512) Dale WSL-2512-R050 78 1 R52 Resistor/SM 1/2 W 5% 100 ohm Beckmen BCR 1/2 101 JT 79 16 R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R33, R36, R38, R44, R45, Resistor Pk SM RNC4R8P 2.7 Kohm CTS 742083272JTR 80 2 R40, R55 Resistor Pk SM RNC4R8P 22 ohm CTS 742083220JTR 81 2 R15, R16 Resistor Pk SM RNC4R8P 470 ohm CTS 742083471JTR 82 1 R13 Resistor Pk SM RNC4R8P 1.5 Kohm CTS 742083152JTR 83 2 R22, R23 Resistor Pk SM RNC4R8P 30 ohm CTS 742083300JTR 84 1 CR9 Diode CMPSH3 Surface Mount Central Semiconductor CMPSH3 85 2 CR6, CR7 Diode SM / MBRS340T3 Motorola MBRS340T3 86 1 CR8 Diode/SM 1N4001 (CMR1-02) Central Semiconductor CMR1-02 87 1 J5 SDRAM, DIMM, ECC, 2Mx72, 16 MB Unigen UG52S7408GSG a. Connectors for IQ80960RN, CONN PCI 32-BIT 5 V/PCB ThruHole, AMP #145154-4. Table D-1. Intel® IQ80960RN Bill of Materials (Sheet 4 of 4) Item Qty Location Part Description Manufacturer Manufacturer Part # *

Intel® IQ80960RM/RN SDRAM Battery Backup PLD Equations 92 Design Guide Intel® IQ80960RM/RN SDRAM Battery Backup PLD Equations E MODULE BATT //TITLE SDRAM Battery Backup Enable //PATTERN101-1809-01 //REVISION //AUTHORJ. Neumann //COMPANYCyclone Microsystems Inc. //DATE 10/30/97 //CHIP PALLV16V8Z-20JI // 1/20/98 Modify target device to PALLV16V8Z-20JI //Initial release. PRSTn PIN 9;//Primary PCI reset SCKE0 PIN 13; //SDRAM bank 0 clock enable SCKE1 PIN 16; //SDRAM bank 1 clock enable OUT0 PIN 14; //SCKE0 output enable OUT1 PIN 17; //SCKE1 output enable EQUATIONS // If SDRAM clock enable goes low, SDRAM clock enable // must be held low to ensure that the SDRAM is held in auto refresh mode. // Reset going high will release the hold on SCKE. OUT0 = SCKE0.PIN & PRSTn//SCKE is the set term, PRSTn is the reset term # SCKE0.PIN & OUT0.PIN # !SCKE0.PIN & PRSTn; SCKE0 = 0; SCKE0.OE = !OUT0;//When OUT = 0, SCKE is grounded //When OUT = 1, SCKE is high impedance OUT1 = SCKE1.PIN & PRSTn # SCKE1.PIN & OUT1.PIN # !SCKE1.PIN & PRSTn; SCKE1 = 0; SCKE1.OE = !OUT1; *

Intel® 80960RM/RN Processor PBGA Signal Ball Map Intel® 80960RM/RN Processor PBGA Signal Ball Map F Table F-1 details the ballout for the 80960RM processor. Table F-1. 540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 1 of 5) Ball # Signal Ball # Signal Ball # Signal A1 VSS A32 VSS B31 VCC A2 VSS B1 VSS B32 VSS A3 VSS B2 VCC C1 VSS A4 VSS B3 VCC C2 VCC A5 VSS B4 VCC C3 VCC A6 P_AD29 B5 VCC C4 VSS A7 P_GNT# B6 VCC C5 VCC A8 SCL B7 P_RST# C6 P_AD30 A9 NMI# B8 VCC C7 P_INTD# A10 XINT3# B9 XINT0# C8 SDA A11 I_RST# B10 VCC C9 XINT1# A12 TDI B11 TMS C10 XINT4# A13 RAD00 B12 VCC C11 TRST# A14 RAD04 B13 RAD01 C12 TCK A15 RAD08 B14 VCC C13 RAD02 A16 N/C B15 VCCPLL2 C14 RAD05 A17 VCC B16 VCC C15 RAD09 A18 RAD12 B17 VCC C16 VCC A19 RAD16 B18 VCC C17 VSS A20 RWE# B19 RALE C18 RAD13 A21 LCDINIT# B20 VCC C19 RCE0# A22 DCLKOUT B21 VSS C20 P_CLK A23 DQ01 B22 VCC C21 ONCE# A24 DQ03 B23 DQ33 C22 VCCPLL1 A25 DQ05 B24 VCC C23 DQ02 A26 DQ07 B25 DQ37 C24 DQ35 A27 DQ40 B26 VCC C25 DQ06 A28 DQ42 B27 DQ09 C26 DQ39 A29 VCC B28 VCC C27 DQ41 A30 VSS B29 VCC C28 DQ11 A31 VSS B30 VCC C29 VCC *

Intel® 80960RM/RN Processor PBGA Signal Ball Map 94 Design Guide C30 VCC E5 P_AD28 G2 P_AD26 C31 VCC E6 P_REQ# G3 P_AD27 C32 VSS E7 P_INTC# G4 VSS D1 VSS E8 P_INTA# G5 N/C D2 VCC E9 XINT2# G28 VSS D3 VSS E10 VCC G29 VSS D4 VSS E11 TDO G30 VCC D5 VSS E12 FAIL# G31 VCC D6 P_AD31 E13 RAD03 G32 DQ43 D7 VSS E14 RAD07 H1 P_AD23 D8 P_INTB# E15 RAD10 H2 VCC D9 VSS E16 VSS H3 P_IDSEL D10 XINT5# E17 RAD11 H4 P_C/BE3# D11 VSS E18 RAD15 H5 P_AD24 D12 VCC E19 RCE1# H28 DQ45 D13 VSS E20 VCC5REF H29 VSS D14 RAD06 E21 DCLKIN H30 DQ13 D15 VSS E22 DQ32 H31 DQ44 D16 VSS E23 DQ34 H32 DQ12 D17 VSS E24 DQ36 J1 P_AD19 D18 RAD14 E25 DQ38 J2 P_AD20 D19 VSS E26 DQ08 J3 P_AD21 D20 ROE# E27 DQ10 J4 VSS D21 VSS E28 VSS J5 P_AD22 D22 DQ00 E29 VSS J28 DQ47 D23 VSS E30 VSS J29 DQ15 D24 DQ04 E31 VCC J30 DQ46 D25 VSS E32 VSS J31 VCC D26 VCCPLL3 F1 VSS J32 DQ14 D27 VSS F2 VCC K1 P_C/BE2# D28 VSS F3 VCC K2 VCC D29 VSS F4 VCC K3 P_AD16 D30 VCC F5 VSS K4 P_AD17 D31 VCC F28 VSS K5 P_AD18 D32 VCC F29 VSS K28 SCB5 E1 VSS F30 VSS K29 VSS E2 VCC F31 VSS K30 SCB1 E3 VCC F32 VSS K31 SCB4 E4 VSS G1 P_AD25 K32 SCB0 Table F-1. 540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 2 of 5) Ball # Signal Ball # Signal Ball # Signal *

Intel® 80960RM/RN Processor PBGA Signal Ball Map L1 P_DEVSEL# P32 SA03 V31 SCB2 L2 P_TRDY# R1 P_AD07 V32 SDQM7 L3 P_IRDY# R2 P_C/BE0# W1 P_AD62/ N/C L4 VSS R3 P_AD08 W2 P_AD63/ N/C L5 P_FRAME# R4 VSS W3 P_PAR64/ N/C L28 SDQM4 R5 P_AD09 W4 VSS L29 SDQM0 R28 SA10 W5 P_C/BE4#|| N/C L30 SCAS# R29 SA09 W28 DQ48 L31 VCC R30 SA08 W29 DQ16 L32 SWE# R31 VCC W30 SCB7 M1 P_SERR# R32 SA07 W31 VCC M2 VCC T1 P_AD03 W32 SCB3 M3 P_PERR# T2 VCC Y1 P_AD58/ N/C M4 P_LOCK# T3 P_AD04 Y2 VCC M5 P_STOP# T4 P_AD05 Y3 P_AD59/ N/C M28 SCE1# T5 P_AD06 Y4 P_AD60/ N/C M29 VSS T28 SCKE0 Y5 P_AD61/ N/C M30 SCE0# T29 VSS Y28 DQ50 M31 SDQM5 T30 SBA1 Y29 VSS M32 SDQM1 T31 SBA0 Y30 DQ18 N1 P_AD14 T32 SA11 Y31 DQ49 N2 P_AD15 U1 P_AD00 Y32 DQ17 N3 P_PAR U2 P_AD01 AA1 P_AD54/ N/C N4 VSS U3 P_AD02 AA2 P_AD55/ N/C N5 P_C/BE1# U4 VSS AA3 P_AD56/ N/C N28 SA02 U5 P_REQ64#/ N/C AA4 VSS N29 SA01 U28 SDQM3 AA5 P_AD57/ N/C N30 SA00 U29 SDQM6 AA28 DQ52 N31 VCC U30 SDQM2 AA29 DQ20 N32 SRAS# U31 VCC AA30 DQ51 P1 P_AD10 U32 SCKE1 AA31 VCC P2 VCC V1 N/C AA32 DQ19 P3 P_AD11 V2 VCC AB1 P_AD50/ N/C P4 P_AD12 V3 N/C AB2 VCC P5 P_AD13 V4 N/C AB3 N/C P28 SA06 V5 N/C AB4 N/C P29 VSS V28 N/C AB5 N/C P30 SA05 V29 VSS AB28 DQ54 P31 SA04 V30 SCB6 AB29 VSS Table F-1. 540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 3 of 5) Ball # Signal Ball # Signal Ball # Signal *

Intel® 80960RM/RN Processor PBGA Signal Ball Map 96 Design Guide AB30 DQ22 AF29 VSS AH26 S_AD31 AB31 DQ53 AF30 DQ30 AH27 S_REQ1# AB32 DQ21 AF31 DQ61 AH28 S_REQ3# AC1 P_AD46/ N/C AF32 DQ29 AH29 VSS AC2 P_AD47/ N/C AG1 NC1/ N/C AH30 VCC AC3 P_AD48/ N/C AG2 P_AD32/ N/C AH31 VCC AC4 VSS AG3 P_AD33/ N/C AH32 DQ63 AC5 P_AD49/ N/C AG4 VSS AJ1 VCC AC28 DQ56 AG5 VSS AJ2 S_AD35/ N/C AC29 DQ24 AG28 VSS AJ3 VSS AC30 DQ55 AG29 VSS AJ4 VSS AC31 VCC AG30 VCC AJ5 S_AD36/ N/C AC32 DQ23 AG31 VCC AJ6 VSS AD1 P_AD42/ N/C AG32 DQ31 AJ7 S_AD44/ N/C AD2 VCC AH1 S_AD32/ N/C AJ8 VSS AD3 P_AD43/ N/C AH2 VCC AJ9 S_AD52/ N/C AD4 P_AD44/ N/C AH3 S_AD33/ N/C AJ10 VSS AD5 P_AD45/ N/C AH4 S_AD34/ N/C AJ11 S_AD60/ N/C AD28 DQ58 AH5 VSS AJ12 VSS AD29 VSS AH6 S_AD39/ N/C AJ13 S_C/BE7#|| N/C AD30 DQ26 AH7 S_AD43/ N/C AJ14 VSS AD31 DQ57 AH8 S_AD47/ N/C AJ15 S_AD05 AD32 DQ25 AH9 S_AD51/ N/C AJ16 VSS AE1 P_AD38/ N/C AH10 S_AD55/ N/C AJ17 S_AD08 AE2 P_AD39/ N/C AH11 S_AD59/ N/C AJ18 VSS AE3 P_AD40/ N/C AH12 S_AD63/ N/C AJ19 S_C/BE1# AE4 VSS AH13 S_C/BE6#|| N/C AJ20 VSS AE5 P_AD41/ N/C AH14 S_AD00 AJ21 S_IRDY# AE28 DQ60 AH15 S_AD04 AJ22 VSS AE29 DQ28 AH16 VSS AJ23 S_AD21 AE30 DQ59 AH17 S_C/BE0# AJ24 VSS AE31 VCC AH18 S_AD11 AJ25 S_AD28 AE32 DQ27 AH19 S_AD15 AJ26 VSS AF1 N/C AH20 S_PERR# AJ27 S_GNT1# AF2 VCC AH21 S_TRDY# AJ28 VSS AF3 N/C AH22 S_AD16 AJ29 S_REQ5# AF4 N/C AH23 S_AD20 AJ30 VCC AF5 N/C AH24 S_C/BE3# AJ31 VCC AF28 DQ62 AH25 S_AD27 AJ32 VSS Table F-1. 540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 4 of 5) Ball # Signal Ball # Signal Ball # Signal *

Intel® 80960RM/RN Processor PBGA Signal Ball Map AK1 VSS AL1 VSS AM1 VSS AK2 VCC AL2 VCC AM2 VSS AK3 VCC AL3 VCC AM3 VSS AK4 VSS AL4 VCC AM4 VCC AK5 S_AD37/ N/C AL5 VCC AM5 N/C AK6 S_AD40/ N/C AL6 N/C AM6 N/C AK7 S_AD45/ N/C AL7 VCC AM7 N/C AK8 S_AD48/ N/C AL8 N/C AM8 N/C AK9 S_AD53/ N/C AL9 VCC AM9 N/C AK10 S_AD56/ N/C AL10 N/C AM10 N/C AK11 S_AD61/ N/C AL11 VCC AM11 N/C AK12 S_PAR64/ N/C AL12 N/C AM12 N/C AK13 S_REQ64#/ N/C AL13 VCC AM13 N/C AK14 S_AD01 AL14 S_AD02 AM14 S_AD03 AK15 S_AD06 AL15 VCC AM15 S_AD07 AK16 VSS AL16 N/C AM16 VCC AK17 S_AD09 AL17 VCC AM17 S_AD10 AK18 S_AD12 AL18 S_AD13 AM18 S_AD14 AK19 S_PAR AL19 VCC AM19 S_SERR# AK20 S_LOCK# AL20 S_STOP# AM20 S_DEVSEL# AK21 S_FRAME# AL21 VCC AM21 S_C/BE2# AK22 S_AD17 AL22 S_AD18 AM22 S_AD19 AK23 S_AD22 AL23 VCC AM23 S_AD23 AK24 S_AD24 AL24 S_AD25 AM24 S_AD26 AK25 S_AD29 AL25 VCC AM25 S_AD30 AK26 S_RST# AL26 S_REQ0# AM26 S_GNT0# AK27 S_REQ2# AL27 VCC AM27 S_GNT2# AK28 S_GNT3# AL28 S_REQ4# AM28 S_GNT4# AK29 S_GNT5# AL29 VCC AM29 VSS AK30 VCC AL30 VCC AM30 VSS AK31 VCC AL31 VCC AM31 VSS AK32 VSS AL32 VSS AM32 VSS Table F-1. 540-Lead H-PBGA Pinout — Intel® i960® RM I/O Processor Processor (Sheet 5 of 5) Ball # Signal Ball # Signal Ball # Signal *

Intel® 80960RM/RN Processor PBGA Signal Ball Map 98 Design Guide Table F-2 details the ballout for the 80960RN processor. Table F-2. 540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 1 of 5) Ball # Signal Ball # Signal Ball # Signal A1 VSS B6 VCC C11 TRST# A2 VSS B7 P_RST# C12 TCK A3 VSS B8 VCC C13 RAD02 A4 VSS B9 XINT0# C14 RAD05 A5 VSS B10 VCC C15 RAD09 A6 P_AD29 B11 TMS C16 VCC A7 P_GNT# B12 VCC C17 VSS A8 SCL B13 RAD01 C18 RAD13 A9 NMI# B14 VCC C19 RCE0# A10 XINT3# B15 VCCPLL2 C20 P_CLK A11 I_RST# B16 VCC C21 ONCE# A12 TDI B17 VCC C22 VCCPLL1 A13 RAD00 B18 VCC C23 DQ02 A14 RAD04 B19 RALE C24 DQ35 A15 RAD08 B20 VCC C25 DQ06 A16 N/C B21 VSS C26 DQ39 A17 VCC B22 VCC C27 DQ41 A18 RAD12 B23 DQ33 C28 DQ11 A19 RAD16 B24 VCC C29 VCC A20 RWE# B25 DQ37 C30 VCC A21 LCDINIT# B26 VCC C31 VCC A22 DCLKOUT B27 DQ09 C32 VSS A23 DQ01 B28 VCC D1 VSS A24 DQ03 B29 VCC D2 VCC A25 DQ05 B30 VCC D3 VSS A26 DQ07 B31 VCC D4 VSS A27 DQ40 B32 VSS D5 VSS A28 DQ42 C1 VSS D6 P_AD31 A29 VCC C2 VCC D7 VSS A30 VSS C3 VCC D8 P_INTB# A31 VSS C4 VSS D9 VSS A32 VSS C5 VCC D10 XINT5# B1 VSS C6 P_AD30 D11 VSS B2 VCC C7 P_INTD# D12 VCC B3 VCC C8 SDA D13 VSS B4 VCC C9 XINT1# D14 RAD06 B5 VCC C10 XINT4# D15 VSS *

Intel® 80960RM/RN Processor PBGA Signal Ball Map D16 VSS E23 DQ34 H32 DQ12 D17 VSS E24 DQ36 J1 P_AD19 D18 RAD14 E25 DQ38 J2 P_AD20 D19 VSS E26 DQ08 J3 P_AD21 D20 ROE# E27 DQ10 J4 VSS D21 VSS E28 VSS J5 P_AD22 D22 DQ00 E29 VSS J28 DQ47 D23 VSS E30 VSS J29 DQ15 D24 DQ04 E31 VCC J30 DQ46 D25 VSS E32 VSS J31 VCC D26 VCCPLL3 F01 VSS J32 DQ14 D27 VSS F02 VCC K1 P_C/BE2# D28 VSS F03 VCC K2 VCC D29 VSS F04 VCC K3 P_AD16 D30 VCC F05 VSS K4 P_AD17 D31 VCC F28 VSS K5 P_AD18 D32 VCC F29 VSS K28 SCB5 E1 VSS F30 VSS K29 VSS E2 VCC F31 VSS K30 SCB1 E3 VCC F32 VSS K31 SCB4 E4 VSS G1 P_AD25 K32 SCB0 E5 P_AD28 G2 P_AD26 L1 P_DEVSEL# E6 P_REQ# G3 P_AD27 L2 P_TRDY# E7 P_INTC# G4 VSS L3 P_IRDY# E8 P_INTA# G5 N/C L4 VSS E9 XINT2# G28 VSS L5 P_FRAME# E10 VCC G29 VSS L28 SDQM4 E11 TDO G30 VCC L29 SDQM0 E12 FAIL# G31 VCC L30 SCAS# E13 RAD03 G32 DQ43 L31 VCC E14 RAD07 H1 P_AD23 L32 SWE# E15 RAD10 H2 VCC M1 P_SERR# E16 VSS H3 P_IDSEL M2 VCC E17 RAD11 H4 P_C/BE3# M3 P_PERR# E18 RAD15 H5 P_AD24 M4 P_LOCK# E19 RCE1# H28 DQ45 M5 P_STOP# E20 VCC5REF H29 VSS M28 SCE1# E21 DCLKIN H30 DQ13 M29 VSS E22 DQ32 H31 DQ44 M30 SCE0# Table F-2. 540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 2 of 5) Ball # Signal Ball # Signal Ball # Signal *

Intel® 80960RM/RN Processor PBGA Signal Ball Map 100 Design Guide M31 SDQM5 T30 SBA1 Y29 VSS M32 SDQM1 T31 SBA0 Y30 DQ18 N1 P_AD14 T32 SA11 Y31 DQ49 N2 P_AD15 U1 P_AD00 Y32 DQ17 N3 P_PAR U2 P_AD01 AA1 P_AD54 N4 VSS U3 P_AD02 AA2 P_AD55 N5 P_C/BE1# U4 VSS AA3 P_AD56 N28 SA02 U5 P_REQ64# AA4 VSS N29 SA01 U28 SDQM3 AA5 P_AD57 N30 SA00 U29 SDQM6 AA28 DQ52 N31 VCC U30 SDQM2 AA29 DQ20 N32 SRAS# U31 VCC AA30 DQ51 P1 P_AD10 U32 SCKE1 AA31 VCC P2 VCC V1 P_C/BE5# AA32 DQ19 P3 P_AD11 V2 VCC AB1 P_AD50 P4 P_AD12 V3 P_C/BE6# AB2 VCC P5 P_AD13 V4 P_C/BE7# AB3 P_AD51 P28 SA06 V5 P_ACK64# AB4 P_AD52 P29 VSS V28 N/C AB5 P_AD53 P30 SA05 V29 VSS AB28 DQ54 P31 SA04 V30 SCB6 AB29 VSS P32 SA03 V31 SCB2 AB30 DQ22 R1 P_AD07 V32 SDQM7 AB31 DQ53 R2 P_C/BE0# W1 P_AD62 AB32 DQ21 R3 P_AD08 W2 P_AD63 AC1 P_AD46 R4 VSS W3 P_PAR64 AC2 P_AD47 R5 P_AD09 W4 VSS AC3 P_AD48 R28 SA10 W5 P_C/BE4# AC4 VSS R29 SA09 W28 DQ48 AC5 P_AD49 R30 SA08 W29 DQ16 AC28 DQ56 R31 VCC W30 SCB7 AC29 DQ24 R32 SA07 W31 VCC AC30 DQ55 T1 P_AD03 W32 SCB3 AC31 VCC T2 VCC Y1 P_AD58 AC32 DQ23 T3 P_AD04 Y2 VCC AD1 P_AD42 T4 P_AD05 Y3 P_AD59 AD2 VCC T5 P_AD06 Y4 P_AD60 AD3 P_AD43 T28 SCKE0 Y5 P_AD61 AD4 P_AD44 T29 VSS Y28 DQ50 AD5 P_AD45 Table F-2. 540-Lead H-PBGA Pinout — Intel® i960® RN I/O Processor Processor (Sheet 3 of 5) Ball # Signal Ball # Signal Ball # Signal *