Mostek z80 Technical Manual

TABLE OF CONTENTS 1 .0 Introduction 2.0 Architecture 3.0 Pin Description 5 4.0 Programming the PIO 9 4.1 Reset 9 4.2 Loading the Interrupt Vector 9 4.3 Selecting an Operating Mode 10 4.4 Setting the Interrupt Control Word 11 5.0 Timing 13 5.1 Output Mode Timing 13 5.2 Input Mode Timing 13 5.3 Bidirectional Mode Timing 14 5.4 Control Mode 14 6.0 Interrupt Control 15 7.0 Applications 17 7.1 Interrupt Daisy Chain 17 7.2 I/O Device Interface 18 7.3 Control Interface 19 8.0 Programming Summary 21 8.1 Load Interrupt Vector 21 8.2 Set Mode 21 8.3 Set Interrupt Control 21 9.0 Electrical Specifications 23 9.1 Absolute Maximum Ratings 23 9.2 D.C. Characteristics 23 9.3 Clock Driver 23 9.4 A.C. Characteristics 24 9.5 Capacitance 24 10.0 Timing Chart 25

compatible interface between peripheral devices and the Z80-CPU. "rtie CPU can configure the Z80-PIO to interface with a wide range of peripheral devices with no other external logic required. Typical peripheral devices that are fully compatible with the Z80-PIO include most keyboards, paper tape readers and punches, printers, PROM programmers, etc. The Z80-PIO utilizes N channel silicon gate depletion load technology and is packaged in a 40 pin DIP. Major features of the Z80-PIO include: • Two independent 8 bit bidirectional peripheral interface ports with 'handshake' data transfer control • Interrupt driven 'handshake' for fast response • Any one of four distinct modes of operation may be selected for a port including: Byte output Byte input Byte bidirectional bus (Available on Port A only) Bit control mode All with interrupt controlled handshake • Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external logic • Eight outputs are capable of driving Darlington transistors. • All inputs and outputs fully TTL compatible • Single 5 volt supply and single phase clock are required. One of the unique freatures of the Z80-PIO that separates it from other interface controllers is that all data transfer between the peripheral device and the CPU is accomplished under total interrupt control. The interrupt logic of the PIO permits full usage of the efficient interrupt capabilities of the Z80-CPU during I/O transfers. All logic necessary to implement a fully nested interrupt structure is included in the PIO so that additional circuits are not required. Another unique feature of the PIO is that it can be programmed to interrupt the CPU on the occurrence of specified status conditions in the peripheral device. For example, the PIO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This interrupt capability reduces the amount of time that the processor must spend in polling peripheral status. 1

consists of a Z80-CPU bus interface, internal control logic, Port A I/O logic. Port B I/O logic, and interrupt control logic. The CPU bus interface logic allows the PIO to interface directly to the Z80-CPU with no other external logic. However, address decoders and/or line buffers may be required for large systems. The internal control logic synchronizes the CPU data bus to the peripheral device interfaces (Port A and Port B). The two I/O ports (A and B) are virtually identical and are used to interface directly to peripheral devices. +S' GNO * iii INTERNAL CONTROL LOGIC CPU INTERFACE^ < 7 H DATA BUS 4- PIO CONTROL LINES CPU BUS I/O c INTERNAL BUS INTERRUPT CONTROL PORT A I/O a '/ E a c HANDSHAKE PORT B I/O (] y >DATA OR CONTROL HANDSHAKE PERIPHERAL INTERFACE INTERRUPT CONTROL LINES FIGURE ZO-1 PIO BLOCK DIAGRAM The Port I/O logic is composed of 6 registers with "handshake" control logic as shown in figure 2.0-2. The registers include: an 8 bit data input register, an 8 bit data output register, a 2 bit mode control register, an 8 bit mask register, an 8 bit input/output select register, and a 2 bit mask control register. MODE CONTROL REG (2 BITS) INTERNAL BUS INPUT/OUTPUT SELECT REG (8 BITS) 1 OUTPUT ENABLE MASK CONTROL REG (2 BITS) MASK REG (8 BITS) c INPUT DATA DATA INPUT REG (8 BITS) PERIPHERAL DATA OR CONTROL BUS INTERRUPT , REQUESTS HANDSHAKE READY^ 1 CONTROL ^STROBE a LOGIC , HANDSHAKE LINES FIGURE ZO-2 PORT I/O BLOCK DIAGRAM 3

output, byte input, byte bidirectional bus, or bit control mode). All data transfer between the peripheral device and the CPU is achieved through the data input and data output registers. Data may be written into the output register by the CPU or read back to the CPU from the input register at any time. The handshake lines associated with each port are used to control the data transfer between the PIO and the peripheral device. The 8-bit mask register and the 8-bit input/output select register are used only in the bit control mode. In this mode any of the 8 peripheral data or control bus pins can be programmed to be an input or an output as specified by the select register. The mask register is used in this mode in conjunction with a special interrupt feature. This feature allows an interrupt to be generated when any or all of the unmasked pins reach a specified state (either high or low). The 2-bit mask control register specifies the active state desired (high or low) and if the interrupt should be generated when all unmasked pins are active (AND condition) or whenan>' unmasked pin is active (OR condition). This feature reduces the requirement for CPU status checking of the peripheral by allowing an interrupt to be automatically generated on specific peripheral status conditions. For example, in a system with 3 alarm conditions, an interrupt may be generated if any one occurs or if all three occur. The interrupt control logic section handles all CPU interrupt protocol for nested priority interrupt structures. The priority of any device is determined by its physical location in a daisy chain configuration. Two lines are provided in each PIO to form this daisy chain. The device closest to the CPU has the highest priority. Within a PIO, Port A interrupts have higher priority than those of Port B. In the byte input, byte output or bidirectional modes, an interrupt can be generated whenever a new byte transfer is requested by the peripheral. In the bit control mode an interrupt can be generated when the peripheral status matches a programmed value. The PIO provides for complete control of nested interrupts. That is, lower priority devices may not interrupt higher priority devices that have not had their interrupt service routine com- pleted by the CPU. Higher priority devices may interrupt the servicing of lower priority devices. When an interrupt is accepted by the CPU in mode 2, the interrupting device must provide an 8-bit interrupt vector for the CPU. This vector is used to form a pointer to a location in the computer memory where the address of the interrupt service routine is located. The 8-bit vector from the interrupting device forms the least significant 8 bits of the indirect pointer while the I Register in the CPU provides the most significant 8 bits of the pointer. Each port (A and B) has an independent interrupt vector. The least significant bit of the vector is automatically set to a within the PIO since the pointer must point to two adjacent memory locations for a complete 16-bit address. The PIO decodes the RETI (Return from interrupt) instruction directly from the CPU data bus so that each PIO in the system knows at all times whether it is being serviced by the CPU interrupt service routine without any other communication with the CPU. 4

function of each pin. D^-Dq Z80-CPU Data Bus (bidirectional, tristate) This bus is used to transfer all data and commands between the Z80-CPU and the Z80-PIO. Dq is the least significant bit of the bus. B/A Sel Port B or A Select (input, active high) This pin defines which port will be accessed during a data transfer between the Z80-CPU and the Z80-PIO. A low level on this pin selects Port A while a high level selects Port B. Often Address bit Aq from the CPU will be used for this selection function. C/D Sel Control or Data Select (input, active high) This pin defines the type of data transfer to be performed between the CPU and the PIO. A high level on this pin during a CPU write to the PIO causes the Z-80 data bus to be inter- preted as a command for the port selected by the B/A Select Hne. A low level on this pin means that he Z-80 data bus is being used to transfer data between the CPU and the PIO. Often Address bit Aj from the CPU will be used for this function. CE Chip Enable (input, active low) A low level on this pin enables the PIO to accept command or data inputs from the CPU during a write cycle or to transmit data to the CPU during a read cycle. This signal is generally a decode of four I/O port numbers that encompass port A and B, data and control. $ System Clock (input) The Z80-PIO uses the standard Z-80 system clock to synchronize certain signals intemally. This is a single phase clock. Ml Machine Cycle One Signal from CPU (input, active low) This signal from the CPU is used as a sync pulse to control several internal PIO operations. When Ml is active and the RD signal is active, the Z80-CPU is fetching an instruction from memory. Conversely, when M l is active and lORQ is active, the CPU is acknowledging an interrupt. In addition, the Ml Signal has two other functions within the Z80-PIO. 1 . Ml synchronizes the PIO interrupt logic. 2. When Ml occurs without an active RD or lORQ signal the PIO logic enters a reset state. lORQ Input/Output Request from Z80-CPU (input, active low) The lORQ signal is used in conjunction with the B/A Select, C/D Select, CE, and RD signals to transfer commands and data between the Z80-CPU and the Z80-PIO. When CE, RD and lORQ are active, the port addressed by B/A will transfer data to the CPU (a read operation). Conversely, when CE and lORQ are active but RD is not active, then the port addressed by B/A will be written into from the CPU with either data or control information as specified by the C/D Select signal. Also, if lORQ and Ml are active simultaneously, the CPU is acknowledging an interrupt and the interrupting port will automatically place its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt. RD Read Cycle Status from the Z80-CPU (input, active low) If RD is active a MEMORY READ or I/O READ operation is in progress. The RD signal is used with B/A Select, C/D Select, CE, and lORQ signals to transfer data from the Z80-PIO to the Z80-CPU. 5

This signal is used to form a priority interrupt daisy chain when more than one interrupt driven device is being used. A high level on this pin indicates that no other devices of higher priority are being serviced by a CPU interrupt service routine. lEO Interrupt Enable Out (output, active high) The lEO signal is the other signal required to form a daisy chain priority scheme. It is high only if lEI is high and the CPU is not servicing an interrupt from this PIO. Thus this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its CPU interrupt service routine. INT Interrupt Request (output, open drain, active low) When INT is active the Z80-PIO is requesting an interrupt from the Z80-CPU. Aq - Ay Port A Bus (bidirectional, tristate) This 8 bit bus is used to transfer data and/or status or control information between Port A of the Z80-PIO and a peripheral device. Aq is the least significant bit of the Port A data bus. A STB Port A Strobe Pulse from Peripheral Device (input, active low) The meaning of this signal depends on the mode of operation selected for Port A as follows: 1) Output mode: The positive edge of this strobe is issued by the peripheral to acknowledge the receipt of data made available by the PIO. 2) Input mode: The strobe is issued by the peripheral to load data from the peripheral into the Port A input register. Data is loaded into the PIO when this signal is active. 3) Bidirectional mode: When this signal is active, data from the Port A output register is gated onto Port A bidirectional data bus. The positive edge of the strobe acknowledges the receipt of the data. 4) Control mode: The strobe is inhibited internally. A RDY Register A Ready (output, active high) The meaning of this signal depends on the mode of operation selected for Port A as follows: 1) Output mode: This signal goes active to indicate that the Port A output register has been loaded and the peripheral data bus is stable and ready for transfer to the peripheral device. 2) Input mode: This signal is active when the Port A input register is empty and is ready to accept data from the peripheral device. 3) Bidirectional mode: This signal is active when data is available in the Port A output register for transfer to the peripheral device. In this mode data is not placed on the Port A data bus unless A STB is active. 4) Control mode: This signal is disabled and forced to a low state. Bq - Bj Port B Bus (bidirectional, tristate) This 8 bit bus is used to transfer data and/or status or control information between Port B of the PIO and a peripheral device. The Port B data bus is capable of supplying 1 .5ma @ 1.5V to drive Darlington transistors. Bq is the least significant bit of the bus. B STB Port B Strobe Pulse from Peripheral Device (input, active low) The meaning of this signal is similar to that of A STB with the following exception: In the Port A bidirectional mode this signal strobes data from the peripheral device into the Port A input register. B RDY Register B Ready (output, active high) The meaning of this signal is similar to that of A Ready with the following exception: In the Port A bidirectional mode this signal is high when the Port A input register is empty and ready to accept data from the peripheral device. 6

CONTROL/DATA SEL- PIO . CONTROL S CHIP ENABLE- MT- lORQ RD -H5V - GND- <1>- INTERRUPT CONTROL ' INT INT ENABLE IN INT ENABLE OUT 39 38 37 36 JTT? 35 26 11 25 23 24 22 Z80-PIO MK 3881 15 14 13 12 10 18 16 27 28 29 30 31 32 33 34 21 17 -B RDY -BSTB PORTA I/O • A RDY •A STB PORT B I/O FIGURE 3.0-1 PIO PIN CONFIGURATION 7

4.1 RESET The Z80-PIO automatically enters a reset state when power is applied. The reset state performs the following functions: 1) Both port mask registers are reset. 2) Port data bus lines are set to a high impedance state and the Ready "handshake" signals are inactive (low). 3) The vector address registers are not reset. 4) Both port interrupt enable flip flops are reset. 5) Both port output registers are reset. In addition to the automatic power on reset , the PIO can be reset by applying an Ml signal without the presence of a RD or lORQ signal. If no RD or lORQ is detected during Ml the PIO will enter the reset state immediately after the Ml signal goes inactive. The purpose of this reset is to allow a single external gate to generate a reset without a power down sequence. This approach was required due to the 40 pin packaging Umitation. Once the PIO has entered the internal reset state it is held there until the PIO receives a control word from the CPU. 4.2 LOADING THE INTERRUPT VECTOR The PIO has been designed to operate with the Z80-CPU using the mode 2 interrupt response. This mode requires that an interrupt vector be suppHed by the interrupting device. This vector is used by the CPU to form the address for the interrupt service routine of that port. This vector is placed on the Z-80 data bus during an interrupt acknowledge cycle by the highest priority device requesting service at that time. (Refer to the Z80-CPU Technical Manual for details on how an interrupt is serviced by the CPU). The desired interrupt vector is loaded into the PIO by writing a control word to the desired port of the PIO with the following format: D7 D6 D5 D4 D3 D2 Dl DO V7 V6 V5 V4 V3 V2 VI ^ signifies this control word is an interrupt vector DO is used in this case as a flag bit which when low causes V7 thru VI to be loaded into the vector register. At interrupt acknowledge time, the vector of the interrupting port will appear on the Z-80 data bus exactly as shown in the format above. 9

Port A of the PIG may be operated in any of four distinct modes: Mode (output mode), Mode 1 (input mode), Mode 2 (bidirectional mode), and Mode 3 (control mode). Note that the mode numbers have been selected for mnemonic significance; i.e. O=0ut, l=In, 2=Bidirectional. Port B can operate in any of these modes except Mode 2. The mode of operation must be established by writing a control word to the PIG in the following format: D7 D6 D5 D4 D3 D2 Dl DO Ml MO X X 1 1 1 1 X=unused bit s/ mode word —\/ signifies mode word to be set Bits Ml and MO from the binary code for the desired mode according to the following table: Mode Ml 1 1 Mq 1 1 (output) 1 (input) 2 (bidirectional) 3 (control) Bits D5 and D4 are ignored. Bits D3-D0 must be set to 1111 to indicate "Set Mode". Selecting Mode enables any data written to the port output register by the CPU to be enabled onto the port data bus. The contents of the output register may be changed at any time by the CPU simply by writing a new data word to the port. Also the current contents of the output register may be read back to the Z80-CPU at any time through the execution of an input instruction. With Mode active, a data write from the CPU causes the Ready handshake line of that port to go high to notify the peripheral that data is available. This signal remains high until a strobe is received from the peripheral. The rising edge of the strobe generates an interrupt (if it has been enabled) and causes the Ready line to go inactive. This very simple handshake is similar to that used in many peripheral devices. Selecting Mode 1 puts the port into the input mode. To start handshake operation, the CPU merely performs an input read operation from the port. This activates the Ready line to the peripheral to signify that data should be loaded into the empty input register. The peripheral device then strobes data into the port input register using the strobe line. Again, the rising edge of the strobe causes an interrupt request (if it has been enabled) and deactivates the Ready signal. Mode 2 is a bidirectional data transfer mode which uses all four handshake lines. Therefore only Port A may be used for Mode 2 operation. Mode 2 operation uses the Port A handshake signals for output control and the Port B handshake signals for input control. Thus, both A RDY and B RDY may be active simultaneously. The only operational difference between Mode and the output portion of Mode 2 is that data from the Port A output register is allowed on to the port data bus orJy when A STB is active in order to achieve a bidirectional capability. Mode 3 operation is intended for status and control applications and does not utilize the handshake signals. When Mode 3 is selected, the next control word sent to that port defines which of the port data bus lines are to be inputs and which are outputs. The format of the control word is shown below: D7 D6 D5 D4 D3 D2 Dl DO I/G7 V06 I/G5 I/G4 I/G3 I/O2 I/O I 10

is reset, the line will be used as an output. During Mode 3 operation the strobe signal is ignored and the Ready line is held low. Data may be written to a port or read from a port by the Z80-CPU at any time during Mode 3 operation. When reading a port, the data returned to the CPU will be composed of input data from port data bus lines assigned as inputs plus port output register data from those lines assigned as outputs. 4.4 SETTING THE INTERRUPT CONTROL WORD The interrupt control word for each port has the following format: D7 D6 D5 D4 D3 D2 Dl DO Enable Interrupt AND/ OR High/ Low Masks follows 1 1 1 used in Mode 3 only signifies interrupt control word If bit D7=l the interrupt enable flip flop of the port is set and the port may generate an interrupt. If bit D7=0 the enable flag is reset and interrupts may not be generated. If an interrupt is pending when the enable flag is set, it will then be enabled onto the CPU interrupt request line. Bits D6, D5, and D4 are used only with Mode 3 operation. They are disregarded for all other modes. These three bits are used to allow for interrupt operation in Mode 3 when any group of the I/O lines go to certain defined states. Bit D6 (AND/ OR) defines the logical operation to be performed in port monitoring. If bit D6=l an AND function is specified and if D6=0, an OR function is specified. For example, if the AND function is specified, all bits must go to a specified state before an interrupt will be generated while the OR function will generate an interrupt if any specified bit goes to the active state. Bit D5 defines the active polarity of the port data bus line to be monitored. If bit D5=l the port data lines are monitored for a high state while if D5=0 they will be monitored for a low state. If bit D4=l the next control word sent to the port will be interpreted as a mask as follows: D7 D6 D5 D4 D3 D2 Dl DO MB-j MBg MB5 MB4 MB3 MB2 MBj MBq Only those port lines whose mask bit is zero will be monitored for generating an interrupt. 11

Figure 5.0-1 illustrates the timing associated with Mode operation. An output cycle is always started by the execution of an output instruction by the CPU. The low level of the WR signal is used to latch the data from the CPU data bus into the addressed port's (A or B) output register. The rising edge of the write pulse then raises the Ready flag after the next falling edge of $ to indicate that data is available for the peri- pheral device. In most systems the rising edge of the Ready signal can be used as a latching signal in the peripheral device if desired. The Ready signal will remain active until a positive edge is received from the strobe line indicating that the peripheral has taken the data. However, the Ready signal will not go inactive until a falling edge occurs on the clock ($) line. The purpose of delaying the negative transition of the Ready signal until after a negative clock transition is that it allows for a very simple generation scheme for the strobe pulse. By merely connecting the Ready line to the Strobe line, a strobe with a duration of one clock period will be generated with no other logic required. The positive edge of the strobe pulse auto- matically generates an INT request if the interrupt enable flip flop has been set and this device is the highest priority device requesting an interrupt. 5.2 INPUT MODE (MODE 1) Figure 5.0-2 illustrates the timing of an input cycle. The peripheral initiates this cycle using the strobe line after the CPU has performed a data read. A low level on this line loads data into the port input register and the rising edge of the strobe line activates the interrupt request line (INT) if the interrupt enable is set and this is the highest priority requesting device. The next falling edge of the clock line ($) will then reset the Ready Une to an inactive state signifying that the input register is full and further loading must be inhibited until the CPU reads the data. The CPU will in the course of its interrupt service routine, read the data from the interrupting port. When this occurs, the positive edge from the CPU read signal will raise the Ready line with the next low going transition of indicating that new data can be loaded into the PIG. MODE lOUTPUTI TIMING WR* >: RD CE - £75- lORQ FIGURE 5.0-1 MODE (OUTPUT) TIMING RD* = RD • CE • C/D • lORO FIGURE &0-2 MODE 1 (INPUT) TIMING 13

This mode is merely a combination of Mode and Mode 1 using all four handshake lines. Since it requires all four lines, it is available only on Port A. When this mode is used on Port A, Port B must be set to the Bit Control Mode. Figure 5.0-3 illustrates the timing for this mode. It is almost identical to that pre- viously described for Mode and Mode 1 with the Port A handshake lines used for output control and the Port B lines used for input control. The difference between the two modes is that, in Mode 2, data is allowed out onto the bus only when the A strobe is low. The rising edge of this strobe can be used to latch the data into the peripheral since the data will remain stable until after this edge. The input portion of Mode 2 operates identically to Mode 1 . B RDY \_ WR» = RD CE • C/D • lORQ FIGURE 5.0-3 PORT A, MODE 2 (BIDIRECTIONAL) TIMING The peripheral must no t gate data onto a port data bus while A STB is active. Bus contention is avoided if the peripheral uses B STB to gate input data onto the bus. The PIG uses the B STB low level to latch this data. The PIG has been designed with a zero hold time requirement for the data when latching in this mode so that this simple gating structure can be used by the peripheral. That is, the data can be disabled from the bus immediately after the strobe rising edge. 5.4 CONTROL MODE (MODE 3) The control mode does not utilize the handshake signals and a normal port write or port read can be executed at any time. When writing, the data will be latched into output registers with the same timing as Mode 0. When reading the PIG, the data returned to the CPU will be composed of output register data from those port data lines assigned as outputs and input register data from those port data lines assigned as inputs. The input register will contain data which was present immediately prior to the falling edge of RD. An interrupt will be generated if interrupts from the port are enabled and the data on the port data lines satisfies the logical equation defined by the 8-bit mask and 2-bit mask control registers. PORT DATA BUS INT lORO ~) [ DATA WORD 1 X DATA WORD 2 ](~ CH \_ DATA MATCH \ Ll( OCCURS HERE ' " RD (DATA IN 1 • Inserted by 280-CPU "ata word i placed on bus FIGURE 5.0-4 14

edge (Ml and lORQ). During this time the interrupt logic of the PIO will determine the highest priority port which is requesting an interrupt. (This is simply the device with its Interrupt Enable Input high and its Interrupt Enable Output low). To insure that the daisy chain enable lines stabilize, devices are inhibited from changing their interrupt request status when Ml is active. The highest priority device places the con- tents of its interrupt vector register onto the Z80 data bus during interrupt acknowledge. Figure 6.0-1 illustrates the timing associated with interrupt requests. During Ml time, no new interrupt requests can be generated. This gives time for the Int Enable signals to ripple through up to four PIO circuits. The PIO with lEI high and lEO low during INTA will place the 8-bit interrupt vector of the appropriate port on the data bus at this time. IE! •Inserted by Z80-CPU FIGURE 6.0-1 INTERRUPT ACKNOWLEDGE TIMING lEO is held low until a return from interrupt (RETI) Instruction is executed while lEI is high. The PIO chip decodes the 2 byte RETI instruction internally. Figure 6.0-2 illustrates a typical nested interrupt sequence that could occur with four ports connected in the daisy chain. In this sequence Port 2A requests and is granted an interrupt. While this port is being serviced, a higher priority port (IB) requests and is granted an interrupt. The service routine for the higher priority port is completed and a RETI instruction is executed to indicate to the port that its routine is complete. At this time the service routine of the lower priority port is completed. 15

4 PORT 1A PORT IB PORT 2A PORT 2B |H, lEI lEO HI IE! lEO HI lEI lEO HI lEI lEO HI 1. PRIORITY INTERRUPT DAISY CHAIN BEFORE ANY INTERRUPT OCCURS. UNDER SERVICE 1 lEI lEO HI lEI lEO HI lEI lEO LO lEI lEO LO 2. PORT 2A REOUESTS AN INTERRUPT AND IS ACKNOWLEDGED. UNDER SERVICE SERVICE SUSPENDED 1"' lEI lEO HI lEI lEO LO lEI lEO LO lEI lEO LO 3. PORT IB INTERRUPTS, SUSPENDS SERVICING OF PORT 2A. SERVICE COMPLETE SERVICE RESUMED 1 lEI lEO HI lEI lEO HI lEI lEO LO lEI lEO LO 4. PORT IB SERVICE ROUTINE COMPLETE, "RETI" ISSUED, PORT 2A SERVICE RESUMED. SERVICE COMPLETE lEI lEO HI lEI lEO HI lEI lEO HI lEI lEO HI 5. SECOND "RETI" INSTRUCTION ISSUED ON COMPLETfON OF PORT 2A SERVICE ROUTINE. FIGURE &0-2 DAISY CHAIN INTERRUPT SERVICING 16

Without any external logic, a maximum of four Z80-PIO devices may be daisy chained into a priority interrupt structure. This limitation is required so that the interrupt enable status (lEO) ripples through the entire chain between the beginning of Ml, and the beginning of lORQ during an interrupt acknowledge cycle. Since the interrupt enable status cannot change during Ml, the vector address returned to the CPU is assured to be from the highest priority device which requested an interrupt. If more than four PIO devices must be accommodated, a "look-ahead" structure may be used as shown in figure 7.0-1 . With this technique more than thirty PIO's may be chained together using standard TTL logic. no El lEO no lEI lEO no lEI lEO no lEI lEOl— ZID-CPU no lEO no El IE( no HIEO lEI no HEO lEI > DATA BUS > FIGURE 7.0-1 A METHOD OF EXTENDING THE INTERRUPT PRIORITY DAISY CHAIN 7.2 I/O DEVICE INTERFACE In this example, the Z80-PIO is connected to an I/O terminal device which communicates over an 8 bit parallel bidirectional data bus as illustrated in figure 7.0-2. Mode 2 operation (bidirectional) is selected by sending the following control word to Port A: D7 D6 D5 04 D3 D2 Dl DO 1 X X 1 1 1 1 Mode Control 17

lORQ Ml INT Z80-PIO MK 3881 B/A c/D CE ADDRESS BUC> ADDRESS BUS DECODER C POBT DATA BUS > D D D D S R R A T Q C V B V D I/O TERMINAL FIGURE 7.0-2 EXAMPLE I/O INTERFACE Next, the proper interrupt vector is loaded (refer to CPU Manual for details on the operation of the interrupt). V7 V6 V5 V4 V3 V2 VI Interrupts are then enabled by the rising edge of the first after the interrupt mode word is set unless that Ml defines an interrupt acknowledge cycle. If a mask follows the interrupt mode word, interrupts are enabled by the rising edge of the first Ml following the setting of the mask. Data can now be transferred between the peripheral and the CPU. The timing for this transfer is as described in Section 5.0. 18

monitored. The occurrence of any abnormal operating condition is to be reported to a Z80-CPU based control system. The process control and status word has the following format: D7 D6 D5 D4 D3 D2 Dl DO Special Test Turn On Power Power Failure Alarm Halt Process- ing Temp. Alarm Turn Heaters On Pressur- ize System Pressure Alarm Z80-CPU MK 3880 c A0-A15 D7-D0 > ADDRESS DECODER Z80 - PIG MK 3881 B/A C/D CE PORTA BUS SPEC. TEST TURN ON PWR._ PWR. FAIL ALM. HALT TEMP. ALM. I> HTRS. ON PRESS. SYS. PRESS. ALM. INDUSTRIAL PROCESSING SYSTEM FIGURE 7.0-3 CONTROL MODE APPLICATION The FIG may be used as follows. First Port A is set for Mode 3 operation by writing the following control word to Port A. D7 D6 D5 D4 D3 D2 Dl DO 1 1 X X 1 1 1 1 Whenever Mode 3 is selected, the next control word sent to the port must be an I/O select word. In this example we wish to select port data lines A5, A3 and AO as inputs and so the following control word is written: D7 06 D5 D4 D3 D2 Dl DO 1 1 1 Next the desired interrupt vector must be loaded (refer to the CPU manual for details); D7 D6 D5 D4 D3 D2 Dl DO V7 V6 V5 V4 V3 V2 VI 19

D7 D6 D5 D4 D3 D2 Dl DO 1 1 1 1 1 1 Enable OR Active Mask ^ v Interrupts Logic High Follows Interrupt control The mask word following the interrupt mode word is: D7 D6 D5 D4 D3 D2 Dl DO 1 1 I 1 1 Selects A5, A3 and AO to be monitored Now, if a sensor puts a high level on line A5, A3, or AO, an interrupt request will be generated. The mask word may select any combination of inputs or outputs to cause an interrupt. For example, if the mask word above had been: D7 D6 D5 D4 D3 D2 Dl DO 1 1 1 1 then an interrupt request would also occur if bit A7 (Special Test) of the output register was set. Assume that the following port assignments are to be used: EOjj= Port A Data Eljj= Port B Data E2jj= Port A Control E3jj= Port B Control All port numbers are in hexadecimal notation. This particular assigrunent of port numbers is convenient since Aq of the address bus can be used as the Port B/A Select and A] of the address bus can be used as the Control/Data Select. The Chip Enable would be the decode of CPU address bits Ay thru A2 (1 110 00). Note that if only a few peripheral devices are being used, a Chip Enable decode may not be required since a higher order address bit could be used directly. 20

V7 V6 V5 V4 V3 V2 VI SET MODE Ml MO X X 1 1 1 1 Mode Number Mj_ Mo Mode Output 1 1 Input 2 1 Bidirectional 3 1 1 Bit Control When selecting Mode 3, the next word must set the I/O Register: I/07 1/06 I/O5 I/O4 I/O3 I/O2 I/Oj I/Oq I/O = 1 Sets bit to Input I/O = Sets bit to Output SET INTERRUPT CONTROL Int AND/ ffigh/ Mask 1 1 1 Enable OR Low Follows Used in Mode 3 only If the "maslc follows" bit is high, the next control word written to the port must be the mask: MB7 MBg MB5 MB4 MB3 MB2 MB J MBq MB = 0, Monitor bit MB = 1, Mask bit from being monitored Also, the interrupt enable flip flop of a port may be set or reset without modifying the rest of the interrupt control word by using the following command: Int Enable X X X 1 1 21

9.1 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias Storage Temperature Voltage On Any Pin With Respect To Ground Power Dissipation 0° C to 70° C -65° C to +150° C -0.3 V to +7 V LOW Comment Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specifica- tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9.2 D.C. CHARACTERISTICS TA = 0° C to 70° C, Vcc = 5 V + 5% unless otherwise specified Symbol Parameter Min. Max. Unit Test Condition ViLC Clock Input Low Voltage -0.3 0.6 V Clock Input High Voltage Vcc Vcc V ViL Input Low Voltage -0.3 0.8 V Input High Voltage 2.0 Vcc V Vol Output Low Voltage 0.4 V IOL=l-8niA VOH Output High Voltage 2.4 V IqH-100)uA ^cc Power Supply Current 100 mA Tq = 400 n sec 'li Input Leakage Current 10 MA Vjf^ = to Vcc ^LOH Tri-State Output Leakage Current in Float 10 ma Vqux = 2.4 to Vcc ^lol Tri-State Output Leakage Current in Float -10 M VouT = 0.4V ''ld Data Bus Leakage Current in Input Mode ±10 mA 0 TTL Vcc 7400 TTL An external pull-up resistor of 330 S2 will meet all A.C. and D.C. clock requirements. 23

Signal Symbol Parameter Min. Max. Unit Comments 'W (*H) 'W (*L) V'f Clock Period Clock Pulse Width, Clock High Clock Pulse Width, Clock Low Clock Rise and Fall Times .4 180 180 2 30 Msec nsec nsec nsec .'hw (D) 'hR (D) 'dr (D) 'DI (D) 'F(D) 'S(D) 'S*(D) 'F(V) Data Hold Time During Write Cycle Data Hold Time From Rising Edge of RD During M I Cycle Data Output Delay During Read Cycle Data Output Delay During INTA Delay to Floating Bus During Read Cycle Data Setup Time to Rising Edge of lORQ During Write Cycle Data Setup Time to Rising Edge of Clock During M 1 Cycle Delay to Floating Bus From Falling Edge of lEI 50 600 100 350 [11 160 200 nsec nsec nsec nsec nsec nsec nsec During INTA Cycle BqBj 'H(PD) •S(PD) ^DS (PD) 'f (PD^ 'DI (PD) Port Data Hold Time From Rising Edge of STROBE run Uaia dciup 1 line lo tvising cage oi klidc. Port Data Output Delay From Falling Edge of STROBE Delay to Floating Port Data Bus From Rising Edge of STROBE Port Data Stable From Rising Edge of lORQ During Write Cycle inn 120 360 200 nsec nsec nsec nsec nsec Mode 1 Mooe i Mode 2 Mode 2 Mode B/A,C/D, CE 'h (CS) 'S (CS) Control Signal Hold Time From Rising Edge of iORQ Control Signal Setup Time to Falling Edge of IORQ 30 nsec nsec A STB, 'W (ST) Pulse Width, STROBE 500 250 nsec nsec Input Mode Output Mode BSTB iNT 'D (IT) 'D (IT3) INT Delay Time From Rising Edge of STROBE INT Delay Time From Data Match During Mode 3 Operation 480 400 nsec nsec Mode 0, 1 or 2 Mode 3 lEO 'DL (10) 'DH (10) lEO Delay Time From Falling Edge of lEl lEO Delay Time From Rising Edge of'RD During RETl 170 l.5t -t 400'' nsec nsec ARDY or BRDY 'DH (RY) 'dl(ry) READY Delay Time From Rising Edge of IORQ READY Delay Time From Rising Edge of STROBE 'c + 200 «c^ 200 nsec nsec [ 1 ] Delay = N • tp^ (jq) + ts*(D) + 'f (V) * * '^'^^ '*^'^>'' ^"^ '^^ 'c where N = number of PlO's in daisy chain Output load circuit. 9.5 CAPACITANCE TA = 25°C,f= 1 MHz Symbol Parameter Max. Unit Test Condition Clock Capacitance 10 pF Unmeasured Pins Returned to Ground Input Capacitance 5 pF ^OUT Output Capacitance 10 pF 24

"1" "0" CLOCK 4.2 V .8 V OUTPUT 2.0 V .8 V INPUT 2.0 V .8 V FLOAT AV = i0.5V

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