Altera Cyclone V Operation & User’s Manual

5–5 Avalon-ST RX Interface November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide To facilitate the interface to 64-bit memories, the Cyclone V Hard IP for PCI Express aligns data to the qword or 64 bits by default; consequently, if the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the correct alignment. Figure 5–2 shows how an address that is not qword aligned, 0x4, is stored in memory. The byte enables only qualify data that is being written. This means that the byte ...

A. Transaction Layer Packet (TLP) Header Formats TLP Packet Format without Data Payload Table A–1 through A–2 show the header format for TLPs without a data payload. \ Table A–1. Memory Read Request, 32-Bit Addressing +0 +1 +2 +3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Byte 0 0 0 0 0 0 0 0 0 0 TC 0 0 0 0 TD EP Attr 0 0 Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address[31:2] 0 0 Byte 12 Reserved Table A–2. Memory Read Request, Locked 32-Bit Addressing +0 +1 +2 +3 7 6 5 4 3 2 1 0 7 6 5 ...

Additional Information This chapter provides additional information about the document and Altera. Revision History The table below displays the revision history for the chapters in this User Guide. How to Contact Altera To locate the most up-to-date information about Altera products, refer to the following table. Typographic Conventions The following table shows the typographic conventions this document uses. Date Version Changes Made SPR November 2011 11.1 First release. Contact (1) Contact Method Address Technical support We ...

A. Transaction Layer Packet (TLP) Header Formats TLP Packet Format without Data Payload Table A–1 through A–2 show the header format for TLPs without a data payload. \ Table A–1. Memory Read Request, 32-Bit Addressing +0 +1 +2 +3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Byte 0 0 0 0 0 0 0 0 0 0 TC 0 0 0 0 TD EP Attr 0 0 Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address[31:2] 0 0 Byte 12 Reserved Table A–2. Memory Read Request, Locked 32-Bit Addressing +0 +1 +2 +3 7 6 5 4 3 2 1 0 7 6 5 ...

Hardware Bring-Up Issues Cyclone V Hard IP for PCI Express November 2011 Altera Corporation ...

4. IP Core Architecture This chapter describes the architecture of the Cyclone V Hard IP for PCI Express. The Cyclone V Hard IP for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification 2.1. The protocol stack includes the following layers: ■ Transaction Layer—The Transaction Layer contains the Configuration Space, the RX and TX channels, the RX buffer, and flow control credits. ■ Data Link Layer—The Data Link Layer, located between the Physical Layer and the Tra ...

5–5 Avalon-ST RX Interface November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide To facilitate the interface to 64-bit memories, the Cyclone V Hard IP for PCI Express aligns data to the qword or 64 bits by default; consequently, if the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the correct alignment. Figure 5–2 shows how an address that is not qword aligned, 0x4, is stored in memory. The byte enables only qualify data that is being written. This means that the byte ...