Microchip Technology PIC18LF67K40 Manual
Text of the manual
2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 1
PIC18(L)F67K40
Description
PIC18(L)F67K40 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
These 64-pin devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider
(CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold
comparisons. They also offer a set of Core Independent Peripherals such as Complementary Waveform Generator
(CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross Detect
(ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system cost.
Core Features
• C Compiler Optimized RISC Architecture
• Only 83 Instructions
• Operating Speed:
- DC – 64 MHz clock input
- 62.5 ns minimum instruction cycle
• Programmable 2-Level Interrupt Priority
• 31-Level Deep Hardware Stack
• Four 8-Bit Timers (TMR2/4/6/8) with Hardware
Limit Timer (HLT)
• Five 16-Bit Timers (TMR0/1/3/5/7)
• Low-Current Power-on Reset (POR)
• Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Programmable Code Protection
• Windowed Watchdog Timer (WWDT):
- Timer monitoring of overflow and underflow
events
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
Memory
• 128K bytes Program Flash Memory
• 3568 Bytes Data SRAM Memory
• 1024 Bytes Data EEPROM
• Direct, Indirect and Relative Addressing modes
Operating Characteristics
• Operating Voltage Ranges:
- 1.8V to 3.6V (PIC18LF6xK40)
- 2.3V to 5.5V (PIC18F6xK40)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Operation Modes
• Doze: CPU and Peripherals Running at Different
Cycle Rates (typically CPU is lower)
• Idle: CPU Halted While Peripherals Operate
• Sleep: Lowest Power Consumption
• Peripheral Module Disable (PMD):
- Ability to selectively disable hardware module
to minimize active power consumption of
unused peripherals
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Windowed Watchdog Timer: 500 nA @ 1.8V,
typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
- 8 uA @ 32 kHz, 1.8V, typical
- 32 uA/MHz @ 1.8V, typical
Digital Peripherals
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Capture/Compare/PWM (CCP) modules:
- Five CCPs
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• 10-Bit Pulse-Width Modulators (PWM):
- Two 10-bit PWMs
• Serial Communications:
- Five Enhanced USART (EUSART) with
Auto-Baud Detect, Auto-wake-up on Start.
RS-232, RS-485, LIN compatible
- SPI
- I2C, SMBus and PMBus™ compatible
• 59 I/O Pins and One Input Pin:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change
- Input level selection control
64-Pin, Low-Power, High-Performance Microcontrollers
with XLP Technology
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 2
PIC18(L)F67K40
Digital Peripherals (Continued)
• Programmable CRC with Memory Scan:
- Reliable data/program memory monitoring for
Fail-Safe operation (e.g., Class B)
- Calculate CRC over any portion of Flash or
EEPROM
- High-speed or background operation
• Hardware Limit Timer (TMR2/4/6/8+HLT):
- Hardware monitoring and Fault detection
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• Data Signal Modulator (DSM)
• Two Signal Measurement Timer (SMT1/2):
- 24-bit timer/counter with prescaler
- Multiple gate and clock inputs
Analog Peripherals
• 10-Bit Analog-to-Digital Converter with Computa-
tion (ADC2):
- 47 external channels
- Conversion available during Sleep
- Four internal analog channels
- Internal and external trigger options
- Automated math functions on input signals:
- averaging, filter calculations, oversam-
pling and threshold comparison
• Hardware Capacitive Voltage Divider (CVD)
Support:
- 8-bit precharge timer
- Adjustable sample and hold capacitor array
- Guard ring digital output drive
• Zero-Cross Detect (ZCD):
- Detect when AC signal on pin crosses
ground
• 5-Bit Digital-to-Analog Converter (DAC):
- Output available externally
- Programmable 5-bit voltage (% of VDD)
- Internal connections to comparators, Fixed
Voltage Reference and ADC
• Three Comparators (CMP):
- Five external inputs
- External output via PPS
• Fixed Voltage Reference (FVR) module:
- 1.024V, 2.048V and 4.096V output levels
Clocking Structure
• High-Precision Internal Oscillator Block (HFINTOSC):
- Selectable frequency range up to 64 MHz
- ±1% at calibration
• 32 kHz Low-Power Internal Oscillator (LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
• External Oscillator Block:
- Three crystal/resonator modes
- 4x PLL with external sources
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
• Oscillator Start-up Timer (OST)
Programming/Debug Features
• In-Circuit Debug Integrated On-Chip
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• In-Circuit Debug (ICD) with Three Breakpoints via
Two Pins
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 3
PIC18(L)F67K40
PIC18(L)F6xK40 Family Types
Device
Data Sheet Index
Program Memory Flash
(words)
Data SRAM
(bytes)
Data EEPROM
(bytes)
I/O Pins
16-bit Timers
Comparators
10-bit ADC2 with
Computation (ch)
5-bit DAC
Zero-Cross Detect
CCP/10-bit PWM
CWG
Signal Measurement
Timer (SMT)
8-bit TMR with HLT
Windowed Watchdog
Timer
CRC with Memory Scan
EUSART
I2C/SPI
PPS
Peripheral Module Disable
Temperature Indicator
Debug(1)
PIC18(L)F65K40
(1)
32k
2048
1024
60
5
3
47
1
1
5/2
1
2
4
Y
Y
5
2
Y
Y
Y
I
PIC18(L)F66K40
(1)
64k
3568
1024
60
5
3
47
1
1
5/2
1
2
4
Y
Y
5
2
Y
Y
Y
I
PIC18(L)F67K40
(2)
128k
3568
1024
60
5
3
47
1
1
5/2
1
2
4
Y
Y
5
2
Y
Y
Y
I
Note
1:
Debugging Methods: (I) – Integrated on Chip.
Data Sheet Index: (Unshaded devices are described in this document.)
1.
DS40001842
PIC18(L)F65/66K40 Data Sheet, 64-Pin, 8-bit Flash Microcontrollers
2.
DS40001841
PIC18(L)F67K40 Data Sheet, 64-Pin, 8-bit Flash Microcontrollers
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 4
PIC18(L)F67K40
Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2
RE3
RE4
RE5
RE6
RE7
RD0
RH2
RH3
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
VSS
RA6
RA7
VDD
RB7
RC4
RC3
RC2
RF0
RF1
RG7
RG6
RA3
RA2
RA1
RA0
RH1
RH0
RA4
RA5
RC1
RC0
RC7
RC6
RC5
15
16
31
40
39
27 28 29 30
32
48
47
46
45
44
43
42
41
54 53 52 51
58 57 56 55
60 59
64 63 62 61
64-Pin TQFP (10x10x1)
PIC18(L)F67K40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2
RE3
RE4
RE5
RE6
RE7
RD0
RH2
RH3
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
VSS
RA6
RA7
VDD
RB7
RC4
RC3
RC2
RF0
RF1
RG7
RG6
RA3
RA2
RA1
RA0
RH1
RH0
RA4
RA5
RC1
RC0
RC7
RC6
RC5
15
16
31
40
39
27 28 29 30
32
48
47
46
45
44
43
42
41
54 53 52 51
58 57 56 55
60 59
64 63 62 61
PIC18(L)F67K40
64-Pin QFN (9x9x1)
Note:
It is recommended that the exposed bottom pad be connected to VSS. However, it must
not be the only VSS connection to the device.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 5
PIC18(L)F67K40
Pin Allocation Tables
TABLE 1:
64-PIN ALLOCATION TABLE (PIC18(L)F6XK40)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
RA0
24
ANA0
—
C1IN4-
C2IN4-
C3IN4-
T8IN(1)
—
—
—
—
—
—
—
—
—
RA1
23
ANA1
—
—
T2IN(1)
—
—
—
—
—
—
—
—
—
—
RA2
22
ANA2
VREF-
VREF-
C1IN1+
C2IN1+
C3IN1+
—
—
—
—
—
—
—
—
—
—
—
RA3
21
ANA3
VREF+
VREF+
—
—
—
—
—
—
—
—
—
—
—
—
RA4
28
ANA4
—
—
T0CKI(1)
—
—
—
—
—
—
—
—
—
—
RA5
27
ANA5
—
—
T3G(1)
—
—
—
—
—
—
—
—
—
—
RA6
40
ANA6
—
—
—
—
—
—
—
—
—
—
—
—
CLKOUT
OSC2
RA7
39
ANA7
—
—
—
—
—
—
—
—
—
—
—
OSC1
CLKIN
RB0
48
ANB0
—
—
—
—
—
ZCDIN
—
—
IOCB0
INT0(1)
—
—
—
RB1
47
ANB1
—
—
—
—
—
—
—
—
IOCB1
INT1(1)
—
—
—(4)
—
RB2
46
ANB2
—
—
—
—
—
—
—
—
IOCB2
INT2(1)
—
—
—(4)
—
RB3
45
ANB3
—
—
—
—
—
—
—
—
IOCB3
INT3(1)
—
—
—
—
RB4
44
ANB4
—
—
—
—
—
—
—
—
IOCB4
—
—
—
—
RB5
43
ANB5
—
—
T1G(1)
T3CKI(1)
—
—
—
—
—
IOCB5
—
—
—
—
RB6
42
ANB6
—
—
—
—
—
—
—
—
IOCB6
—
—
—
ICSPCLK
RB7
37
ANB7
DAC1OUT2
—
—
—
—
—
—
—
IOCB7
—
—
—
ICSPDAT
RC0
30
—
—
—
T1CKI(1)
—
—
—
—
—
IOCC0
CK4(3)
—
—
SOSCO
Note
1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2:
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4:
These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 6
PIC18(L)F67K40
RC1
29
—
—
—
T6IN(1)
—
—
—
IOCC1
RX4(1)
DT4(1)
—
—
SOSCI
RC2
33
—
—
—
—
—
CWG1IN(1)
—
—
—
IOCC2
—
—
—
—
RC3
34
—
—
—
—
—
—
—
—
—
IOCC3
—
—
SCL1(3,4)
SCK1(1)
—
RC4
35
—
—
—
—
—
—
—
—
—
IOCC4
—
—
SDA1(3,4)
SDI1(1)
—
RC5
36
—
—
—
—
—
—
—
—
—
IOCC5
—
—
—
—
RC6
31
—
—
—
—
—
—
—
—
—
IOCC6
CK1(3)
—
—
—
RC7
32
—
—
—
—
—
—
—
—
—
IOCC7
RX1(1)
DT1(3)
—
—
—
RD0
58
AND0
—
—
—
—
—
—
—
—
—
—
—
—
—
RD1
55
AND1
—
—
T5CKI(1)
T7G(1)
—
—
—
—
—
—
—
—
—
—
RD2
54
AND2
—
—
—
—
—
—
—
—
—
—
—
—
—
RD3
53
AND3
—
—
—
—
—
—
—
—
—
—
MDCARL(1)
—
—
RD4
52
AND4
—
—
—
—
—
—
—
—
—
—
MDCARH(1)
—
RD5
51
AND5
—
—
—
—
—
—
—
—
—
—
MDSRC(1)
SDA2(3,4)
SDI2(1)
—
RD6
50
AND6
—
—
—
—
—
—
—
—
—
—
—
SCL2(3,4)
SCK2(1)
RD7
49
AND7
—
—
—
—
—
—
—
—
—
—
—
SS2(1)
—
RE0
2
ANE0
—
—
—
—
—
—
—
—
IOCE0
CK3(3)
—
—
—
RE1
1
ANE1
—
—
—
—
—
—
—
—
IOCE1
RX3(1)
DT3(3)
—
—
—
RE2
64
ANE2
—
—
—
—
—
—
—
—
IOCE2
CK5(3)
—
—
—
RE3
63
ANE3
—
—
—
—
—
—
—
—
IOCE3
RX5(1)
DT5(3)
—
—
—
RE4
62
ANE4
—
—
T4IN(1)
CCP2(1)
—
—
—
—
IOCE4
—
—
—
—
TABLE 1:
64-PIN ALLOCATION TABLE (PIC18(L)F6XK40) (CONTINUED)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
Note
1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2:
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4:
These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 7
PIC18(L)F67K40
RE5
61
ANE5
—
—
—
CCP1(1)
—
—
—
—
IOCE5
—
—
—
—
RE6
60
ANE6
—
—
—
CCP3(1)
—
—
SMT1WIN1(1)
—
IOCE6
—
—
—
—
RE7
59
ANE7
—
—
—
—
—
—
SMT1SIG1(1)
—
IOCE7
—
—
—
—
RF0
18
ANF0—
—
C1IN0-
C2IN0-
—
—
—
—
—
—
—
—
—
—
—
RF1
17
ANF1
—
—
—
—
—
—
—
—
—
—
—
—
—
RF2
16
ANF2
—
—
—
—
—
—
—
—
—
—
—
—
—
RF3
15
ANF3—
—
C1IN2-
C2IN2-
C3IN2-
—
—
—
—
—
—
—
—
—
—
—
RF4
14
ANF4
—
C2IN0+
—
—
—
—
—
—
—
—
—
—
—
RF5
13
ANF5
DAC1OUT1
C1IN1-
C2IN1-
—
—
—
—
—
—
—
—
—
—
—
RF6
12
ANF6
—
C1IN0+
—
—
—
—
—
—
—
—
—
—
—
RF7
11
ANF7—
—
C1IN3-
C2IN3-
C3IN3-
—
—
—
—
—
—
—
—
—
SS1(1)
—
RG0
3
ANG0
—
—
—
—
—
—
—
—
—
—
—
—
—
RG1
4
ANG1
—
—
—
—
—
—
—
—
—
CK2(1)
—
—
—
RG2
5
ANG2
—
C3IN0+
—
—
—
—
—
—
—
RX2(1)
DT2(3)
—
—
—
RG3
6
ANG3
—
C3IN0-
—
CCP4(1)
—
—
—
—
—
—
—
—
—
RG4
8
ANG4
—
C3IN1-
T5G(1)
T7CKI(1)
CCP5(1)
—
—
—
—
—
—
—
—
—
RG5
7
—
—
—
—
—
—
—
—
—
—
IOCG5
—
—
MCLR, VPP
RG6
20
ANG6
—
—
—
—
—
—
SMT2WIN1(1)
—
—
—
—
—
—
RG7
19
ANG7
—
—
—
—
—
—
SMT2SIG1(1)
—
—
—
—
—
—
RH0
26
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RH1
25
ADCACT(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
TABLE 1:
64-PIN ALLOCATION TABLE (PIC18(L)F6XK40) (CONTINUED)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
Note
1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2:
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4:
These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 8
PIC18(L)F67K40
RH2
57
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RH3
56
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
10, 38
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
9, 41
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
OUT(2)
—
ADGRDA
ADGRDB
—
C1OUT
C2OUT
C3OUT
TMR0
CCP1
CCP2
CCP3
CCP4
CCP5
PWM6OUT
PWM7OUT
CWG1A
CWG1B
CWG1C
CWG1D
—
—
CLKR
—
TX1/CK1(3)
DT1(3)
TX2/CK2(3)
DT2(3)
TX3/CK3(3)
DT3(3)
TX4/CK4(3)
DT4(3)
TX5/CK5(3)
DT5(3)
DSM
SDO1
SCK1
SDO2
SCK2
—
TABLE 1:
64-PIN ALLOCATION TABLE (PIC18(L)F6XK40) (CONTINUED)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
Note
1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2:
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4:
These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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Preliminary
DS40001841B-page 9
PIC18(L)F67K40
Table of Contents
1.0
Device Overview ........................................................................................................................................................................ 11
2.0
Guidelines for Getting Started with PIC18(L)F6xK40 Microcontrollers ...................................................................................... 16
3.0
Device Configuration.................................................................................................................................................................. 19
4.0
Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 32
5.0
Reference Clock Output Module ................................................................................................................................................ 51
6.0
Power-Saving Operation Modes ................................................................................................................................................ 56
7.0
Peripheral Module Disable (PMD).............................................................................................................................................. 64
8.0
Resets ........................................................................................................................................................................................ 71
9.0
Windowed Watchdog Timer (WWDT) ........................................................................................................................................ 80
10.0 Memory Organization................................................................................................................................................................. 89
11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 126
12.0 8x8 Hardware Multiplier............................................................................................................................................................ 150
13.0 Cyclic Redundancy Check (CRC) Module with Memory Scanner............................................................................................ 152
14.0 Interrupts .................................................................................................................................................................................. 169
15.0 I/O Ports ................................................................................................................................................................................... 206
16.0 Interrupt-on-Change................................................................................................................................................................. 217
17.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 221
18.0 Timer0 Module ......................................................................................................................................................................... 231
19.0 Timer1/3/5/7 Module with Gate Control.................................................................................................................................... 237
20.0 Timer2/4/6/8 Module ................................................................................................................................................................ 253
21.0 Capture/Compare/PWM Module .............................................................................................................................................. 274
22.0 Pulse-Width Modulation (PWM 6/7) ......................................................................................................................................... 289
23.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 297
24.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 303
25.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 330
26.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 374
27.0 Master Synchronous Serial Port (MSSP1) Module ................................................................................................................. 385
28.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 442
29.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 473
30.0 Temperature Indicator Module ................................................................................................................................................. 475
31.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 477
32.0 Analog-to-Digital Converter with Computation (ADC2) Module ............................................................................................... 481
33.0 Comparator Module (C1/2/3) ................................................................................................................................................... 517
34.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 527
35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 534
36.0 Instruction Set Summary.......................................................................................................................................................... 536
37.0 Development Support............................................................................................................................................................... 586
38.0 Electrical Specifications............................................................................................................................................................ 590
39.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 620
40.0 Packaging Information.............................................................................................................................................................. 621
Appendix A: Revision History............................................................................................................................................................. 628
Appendix B: Device Differences ........................................................................................................................................................ 629
The Microchip Website ...................................................................................................................................................................... 630
Customer Change Notification Service .............................................................................................................................................. 630
Customer Support.............................................................................................................................................................................. 630
Product Identification System ............................................................................................................................................................ 631
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Preliminary
DS40001841B-page 10
PIC18(L)F67K40
TO OUR VALUED CUSTOMERS
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Preliminary
DS40001841B-page 11
PIC18(L)F67K40
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
This family offers the advantages of all PIC18
microcontrollers – namely, high computational perfor-
mance at an economical price – with the addition of
high-endurance, Program Flash Memory. In addition to
these features, the PIC18(L)F6xK40 family introduces
design enhancements that make these microcontrol-
lers a logical choice for many high-performance, power
sensitive applications.
1.1
New Core Features
1.1.1
XLP TECHNOLOGY
All of the devices in the PIC18(L)F6xK40 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
• Alternate Run Modes: By clocking the controller
from the secondary oscillator or the internal
oscillator block, power consumption during code
execution can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The power-
managed modes are invoked by user code during
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
• Peripheral Module Disable: Modules that are
not being used in the code can be selectively
disabled using the PMD module. This further
reduces the power consumption.
1.1.2
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18(L)F6xK40 family offer
several
different
oscillator
options.
The
PIC18(L)F6xK40 family can be clocked from several
different sources:
• HFINTOSC
- 1-16 MHz precision digitally controlled inter-
nal oscillator
• LFINTOSC
- 31 kHz internal oscillator
• EXTOSC
- External clock (EC)
- Low-power oscillator (LP)
- Medium power oscillator (XT)
- High-power oscillator (HS)
• SOSC
- Secondary oscillator circuit operating at
31 kHz
• A Phase Lock Loop (PLL) frequency multiplier
(4x) is available to both the External and Internal
Oscillator modes enabling clock speeds of up to
64 MHz
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the LFINTOSC. If a
clock failure occurs, the controller is switched to
the internal oscillator block, allowing for continued
operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F67K40
• PIC18LF67K40
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Preliminary
DS40001841B-page 12
PIC18(L)F67K40
1.2
Other Special Features
• Memory Endurance: The Flash cells for both
program memory and data EEPROM are rated to
last for many thousands of erase/write cycles – up
to 10K for program memory and 100K for
EEPROM. Data retention without refresh is
conservatively estimated to be greater than 40
years.
• Self-programmability: These devices can write
to their own program memory spaces under
internal software control. By using a boot loader
routine located in the protected Boot Block at the
top of program memory, it becomes possible to
create an application that can update itself in the
field.
• Extended Instruction Set: The PIC18(L)F6xK40
family introduces an optional extension to the
PIC18 instruction set, which adds eight new
instructions and an Indexed Addressing mode.
This extension, enabled as a device configuration
option, has been specifically designed to optimize
re-entrant application code originally developed in
high-level languages, such as C.
• Enhanced Peripheral Pin Select: The
Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O
pins. Only digital signals are included in the
selections. All analog inputs and outputs remain
fixed to their assigned pins.
• Enhanced Addressable EUSART: This serial
communication module is capable of standard
RS-232 operation and provides support for the
LIN bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
• 10-bit A/D Converter with Computation: This
module incorporates programmable acquisition
time, allowing for a channel to be selected and a
conversion to be initiated without waiting for a
sampling period and thus, reduce code overhead.
It has a new module called ADC2 with
computation features, which provides a digital
filter and threshold interrupt functions.
• Windowed Watchdog Timer (WWDT):
- Timer monitoring of overflow and underflow
events
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
1.3
Details on Individual Family
Members
Devices in the PIC18(L)F6xK40 family are available in
64-pin packages. The block diagram for this device is
shown in Figure 1-1.
The devices have the following differences:
1.
Program Flash Memory
2.
Data Memory SRAM
3.
Input Voltage Range/Power Consumption
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in the pin summary
tables (Table 1).
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 13
PIC18(L)F67K40
TABLE 1-1:
DEVICE FEATURES
Features
PIC18(L)F65K40
PIC18(L)F66K40
PIC18(L)F67K40
Program Memory (Bytes)
32768
65536
131072
Program Memory (Instructions)
16384
32768
65536
Data Memory (Bytes)
2048
3562
3562
Data EEPROM Memory (Bytes)
1024
1024
1024
I/O Ports
A,B,C,D,E,F,G,H
A,B,C,D,E,F,G,H
A,B, C,D,E,F,G,H
Capture/Compare/PWM Modules (CCP)
5
10-Bit Pulse-Width Modulator (PWM)
2
10-Bit Analog-to-Digital Module (ADC2)
with Computation Accelerator
4 internal
47 external
Packages
64-pin TQFP
64-pin QFN
Interrupt Sources
56
Timers (16-/8-bit)
5/4
Serial Communications
2 MSSP,
5 EUSART
Enhanced Complementary Waveform
Generator (ECWG)
1
Signal Measurement Timer (SMT)
2
Comparators
3
Zero-Cross Detect (ZCD)
1
Data Signal Modulator (DSM)
1
Peripheral Pin Select (PPS)
Yes
Peripheral Module Disable (PMD)
Yes
16-bit CRC with NVMSCAN
Yes
Programmable High/Low-Voltage Detect
(HLVD)
Yes
Programmable Brown-out Reset (BOR)
Yes
Resets (and Delays)
POR, BOR,
RESET Instruction,
Stack Overflow,
Stack Underflow
(PWRT, OST),
MCLR, WDT
Instruction Set
75 Instructions;
83 with Extended Instruction Set enabled
Operating Frequency
DC – 64 MHz
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 14
PIC18(L)F67K40
FIGURE 1-1:
PIC18(L)F6XK40 FAMILY BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODL
PRODH
8x8 Multiply
8
BITOP
8
8
ALU<8>
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
Note
1:
OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 4.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional information.
10-bit
ADC
W
Instruction Bus <16>
STKPTR
Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(1)
OSC2(1)
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
MCLR
Block
LFINTOSC
Oscillator
64 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
SOSCO
SOSCI
FVR
FVR
FVR
DAC
Address Latch
Program Memory
(8/16/32/64 Kbytes)
Data Latch
PORTA
RA<7:0>
PORTB
RB<7:0>
PORTC
RC<7:0>
PORTD
RD<7:0>
BOR
DAC
PORTE
RE<7:0>
PORTF
RF<7:0>
PORTG
RG<7:0>
PORTH
RH<3:0>
HLVD
Timer2
Timer4
Timer6
Timer8
Data
EEPROM
Timer1
Timer3
Timer5
Timer7
SMT1
Timer0
EUSART1
EUSART2
EUSART3
EUSART4
EUSART5
ZCD
CRC-Scan
Comparators
C1/C2/C3
PWM6
PWM7
MSSP1
MSSP2
CCP1
CCP2
CCP3
CCP4
CCP5
ECWG
DSM
PMD
SMT2
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 15
PIC18(L)F67K40
1.4
Register and Bit naming
conventions
1.4.1
REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance, and control identifier.
The control registers section will show just one
instance of all the register names with an ‘x’ in the place
of the peripheral instance number. This naming
convention may also be applied to peripherals when
there is only one instance of that peripheral in the
device to maintain compatibility with other devices in
the family that contain more than one.
1.4.2
BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.4.2.1
Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis-
ter can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.4.2.2
Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly pro-
grams. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
1.4.2.3
Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW ~(1<
2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 16
PIC18(L)F67K40
2.0
GUIDELINES FOR GETTING
STARTED WITH
PIC18(L)F6XK40
MICROCONTROLLERS
2.1
Basic Connection Requirements
Getting started with the PIC18(L)F6xK40 family of 8-bit
microcontrollers requires attention to a minimal set of
device pin connections before proceeding with
development.
The following pins must always be connected:
• All VDD and VSS pins (see Section 2.2 “Power
Supply Pins”)
• MCLR pin (see Section 2.3 “Master Clear (MCLR)
Pin”)
These pins must also be connected if they are being
used in the end application:
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.4 “ICSP™ Pins”)
• OSCI and OSCO pins when an external oscillator
source is used (see Section 2.5 “External
Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins are used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
2.2
Power Supply Pins
2.2.1
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins (VDD and VSS) is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
C1
R1
Rev. 10-000249A
9/1/2015
VDD
PIC18(L)Fxxxxx
R2
MCLR
C2
VDD
Vss
Vss
Key (all values are recommendations):
C1 and C2 : 0.1 F, 20V ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 17
PIC18(L)F67K40
2.3
Master Clear (MCLR) Pin
The
MCLR
pin
provides
two
specific
device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage
sags,
may
be
beneficial.
A
typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The
jumper
is
replaced
for
normal
run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
2.4
ICSP™ Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins), programmed
into the device, matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For
more
information
on
available
Microchip
development tools connection requirements, refer to
Section 37.0 “Development Support”.
Note 1:
R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R2 470 will limit any current flowing into
MCLR from the external capacitor, C1, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C1
R2
R1
VDD
MCLR
JP
PIC18(L)F6xK40
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 18
PIC18(L)F67K40
2.5
External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to Section
4.0 “Oscillator
Module
(with
Fail-Safe
Clock
Monitor)” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-3. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate website
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
2.6
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
FIGURE 2-3:
SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
GND
`
`
`
OSC1
OSC2
SOSCO
SOSCI
Copper Pour
Primary Oscillator
Crystal
Secondary Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
SOSC: C1
SOSC: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
(SOSC)
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 19
PIC18(L)F67K40
3.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection, Device ID and Rev ID.
3.1
Configuration Words
There are six Configuration Word bits that allow the
user to setup the device with several choices of
oscillators, Resets and memory protection options.
These are implemented as Configuration Word 1
through Configuration Word 6 at 300000h through
30000Bh.
Note:
The DEBUG bit in Configuration Words is
managed
automatically
by
device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
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Preliminary
DS40001841B-page 20
PIC18(L)F67K40
3.2
Register Definitions: Configuration Words
REGISTER 3-1:
Configuration Word 1L (30 0000h): Oscillators
U-1
R/W-1
R/W-1
R/W-1
U-1
R/W-1
R/W-1
R/W-1
—
RSTOSC<2:0>
—
FEXTOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘1’
bit 6-4
RSTOSC<2:0>: Power-up Default Value for COSC bits
This value is the Reset default value for COSC and selects the oscillator first used by user software.
Refer to COSC operation.
111 = EXTOSC operating per FEXTOSC bits (device manufacturing default)
110 = HFINTOSC with HFFRQ = 4 MHz (Register 4-5) and CDIV = 4:1 (Register 4-2)
101 = LFINTOSC
100 = SOSC
011 = Reserved
010 = EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
001 = Reserved
000 = HFINTOSC with HFFRQ = 64 MHz (Register 4-5) and CDIV = 1:1 (Register 4-2). Resets
COSC/NOSC to 3’b110.
bit 3
Unimplemented: Read as ‘1’
bit 2-0
FEXTOSC<2:0>: FEXTOSC External Oscillator Mode Selection bits
111 = EC (external clock) above 8 MHz; PFM set to high power (device manufacturing default)
110 = EC (external clock) for 500 kHz to 8 MHz; PFM set to medium power
101 = EC (external clock) below 500 kHz; PFM set to low power
100 = Oscillator not enabled
011 = Reserved (do not use)
010 = HS (crystal oscillator) above 8 MHz; PFM set to high power
001 = XT (crystal oscillator) above 500 kHz, below 8 MHz; PFM set to medium power
000 = LP (crystal oscillator) optimized for 32.768 kHz; PFM set to low power
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Preliminary
DS40001841B-page 21
PIC18(L)F67K40
REGISTER 3-2:
Configuration Word 1H (30 0001h): Oscillators
U-1
U-1
R/W-1
U-1
R/W-1
U-1
U-1
R/W-1
—
—
FCMEN
—
CSWEN
—
—
CLKOUTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘1’
bit 5
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = FSCM timer enabled
0 = FSCM timer disabled
bit 4
Unimplemented: Read as ‘1’
bit 3
CSWEN: Clock Switch Enable bit
1 = Writing to NOSC and NDIV is allowed
0 = The NOSC and NDIV bits cannot be changed by user software
bit 2-1
Unimplemented: Read as ‘1’
bit 0
CLKOUTEN: Clock Out Enable bit
If FEXTOSC = HS, XT, LP, then this bit is ignored
Otherwise:
1 = CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = CLKOUT function is enabled; FOSC/4 clock appears at OSC2
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Preliminary
DS40001841B-page 22
PIC18(L)F67K40
REGISTER 3-3:
Configuration Word 2L (30 0002h): Supervisor
R/W-1
R/W-1
R/W-1
U-1
U-1
U-1
R/W-1
R/W-1
BOREN<1:0>
LPBOREN
—
—
—
PWRTE
MCLRE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
BOREN<1:0>: Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by BORV bit
11 = Brown-out Reset enabled, SBOREN bit is ignored
10 = Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored
01 = Brown-out Reset enabled according to SBOREN
00 = Brown-out Reset disabled
bit 5
LPBOREN: Low-Power BOR Enable bit
1
= Low-Power Brown-out Reset is disabled
0
= Low-Power Brown-out Reset is enabled
bit 4-2
Unimplemented: Read as ‘1’
bit 1
PWRTE: Power-up Timer Enable bit
1
= PWRT disabled
0
= PWRT enabled
bit 0
MCLRE: Master Clear (MCLR) Enable bit
If LVP = 1
RE3 pin function is MCLR
If LVP = 0
1 = MCLR pin is MCLR
0 = MCLR pin function is port defined function
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 23
PIC18(L)F67K40
REGISTER 3-4:
Configuration Word 2H (30 0003h): Supervisor
R/W-1
U-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
XINST
—
DEBUG
STVREN
PPS1WAY
ZCD
BORV<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
XINST: Extended Instruction Set Enable bit
1
= Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)
0
= Extended Instruction Set and Indexed Addressing mode enabled
bit 6
Unimplemented: Read as ‘1’
bit 5
DEBUG: Debugger Enable bit
1
= Background debugger disabled
0
= Background debugger enabled
bit 4
STVREN: Stack Overflow/Underflow Reset Enable bit
1
= Stack Overflow or Underflow will cause a Reset
0
= Stack Overflow or Underflow will not cause a Reset
bit 3
PPS1WAY: PPSLOCKED bit One-Way Set Enable bit
1
= The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once
PPSLOCK is set, all future changes to PPS registers are prevented
0
= The PPSLOCKED bit can be set and cleared as needed (provided an unlocking sequence is
executed)
bit 2
ZCD: ZCD Disable bit
1
= ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0
= ZCD always enabled, ZCDMD bit is ignored
bit 1-0
BORV<1:0>: Brown-out Reset Voltage Selection bit(1)
PIC18F6xK40 device:
11
= Brown-out Reset Voltage (VBOR) set to 2.45V
10
= Brown-out Reset Voltage (VBOR) set to 2.45V
01
= Brown-out Reset Voltage (VBOR) set to 2.7V
00
= Brown-out Reset Voltage (VBOR) set to 2.85V
PIC18LF6xK40 device:
11
= Brown-out Reset Voltage (VBOR) set to 1.90V
10
= Brown-out Reset Voltage (VBOR) set to 2.45V
01
= Brown-out Reset Voltage (VBOR) set to 2.7V
00
= Brown-out Reset Voltage (VBOR) set to 2.85V
Note 1: The higher voltage setting is recommended for operation at or above 16 MHz.
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Preliminary
DS40001841B-page 24
PIC18(L)F67K40
REGISTER 3-5:
CONFIGURATION WORD 3L (30 0004h): WINDOWED WATCHDOG TIMER
U-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
WDTE<1:0>
WDTCPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘1’
bit 6-5
WDTE<1:0>: WDT Operating Mode bits
11 = WDT enabled regardless of Sleep; SEN bit in WDTCON0 is ignored
10 = WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit in WDTCON0 is ignored
01 = WDT enabled/disabled by SEN bit in WDTCON0
00 = WDT disabled, SEN bit in WDTCON0 is ignored
bit 4-0
WDTCPS<4:0>: WDT Period Select bits
WDTCPS
WDTPS at POR
Software Control
of WDTPS?
Value
Divider Ratio
Typical Time Out
(FIN = 31 kHz)
11111
01011
1:65536
216
2s
Yes
10011
...
11110
10011
...
11110
1:32
25
1 ms
No
10010
10010
1:8388608
223
256s
No
10001
10001
1:4194304
222
128s
10000
10000
1:2097152
221
64s
01111
01111
1:1048576
220
32s
01110
01110
1:524299
219
16s
01101
01101
1:262144
218
8s
01100
01100
1:131072
217
4s
01011
01011
1:65536
216
2s
01010
01010
1:32768
215
1s
01001
01001
1:16384
214
512 ms
01000
01000
1:8192
213
256 ms
00111
00111
1:4096
212
128 ms
00110
00110
1:2048
211
64 ms
00101
00101
1:1024
210
32 ms
00100
00100
1:512
29
16 ms
00011
00011
1:256
28
8 ms
00010
00010
1:128
27
4 ms
00001
00001
1:64
26
2 ms
00000
00000
1:32
25
1 ms
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Preliminary
DS40001841B-page 25
PIC18(L)F67K40
REGISTER 3-6:
CONFIGURATION WORD 3H (30 0005h): WINDOWED WATCHDOG TIMER
U-1
U-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
WDTCCS<2:0>
WDTCWS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘1’
bit 5-3
WDTCCS<2:0>: WDT Input Clock Selector bits
If WDTE<1:0> fuses = 2’b00
This bit is ignored.
Otherwise:
111 = Software Control
110 = Reserved (Default to LFINTOSC)
.
.
.
010 = Reserved (Default to LFINTOSC)
001 = WDT reference clock is the 31.25 kHz HFINTOSC (MFINTOSC)
000 = WDT reference clock is the 31.0 kHz LFINTOSC (default value)
bit 2-0
WDTCWS<2:0>: WDT Window Select bits
WDTCWS
WINDOW at POR
Software
control of
WINDOW
Keyed
access
required?
Value
Window delay
Percent of time
Window opening
Percent of time
111
111
n/a
100
Yes
No
110
111
n/a
100
No
Yes
101
101
25
75
100
100
37.5
62.5
011
011
50
50
010
010
62.5
37.5
001
001
75
25
000
000
87.5
12.5
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Preliminary
DS40001841B-page 26
PIC18(L)F67K40
Register 3-7:
Configuration Word 4L (30 0006h): Memory Write Protection
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WRT7
WRT6
WRT5
WRT4
WRT3
WRT2
WRT1
WRT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
WRT<7:0>: User NVM Self-Write Protection bits(1)
1
= Corresponding Memory Block NOT write-protected
0
= Corresponding Memory Block write-protected
Note 1: Refer to Table 10-2 for details on implementation of the individual WRT bits.
Register 3-8:
Configuration Word 4H (30 0007h): Memory Write Protection
U-1
U-1
R/W-1
R/W-1
U-1
R/W-1
R/W-1
R/W-1
—
—
LVP
SCANE
—
WRTD
WRTB
WRTC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘1’
bit 5
LVP: Low-Voltage Programming Enable bit
1
= Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit
is ignored.
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The
purpose of this rule is to prevent the user from dropping out of LVP mode while programming
from LVP mode, or accidentally eliminating LVP mode from the Configuration state.
0
= HV on MCLR/VPP must be used for programming
bit 4
SCANE: Scanner Enable bit
1
= Scanner module is available for use, SCANMD bit enables the module
0
= Scanner module is NOT available for use, SCANMD bit is ignored
bit 3
Unimplemented: Read as ‘1’
bit 2
WRTD: Data EEPROM Write Protection bit
1
= Data EEPROM NOT write-protected
0
= Data EEPROM write-protected
bit 1
WRTB: Boot Block Write Protection bit
1
= Boot Block NOT write-protected
0
= Boot Block write-protected
bit 0
WRTC: Configuration Register Write Protection bit
1
= Configuration Register NOT write-protected
0
= Configuration Register write-protected
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Preliminary
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PIC18(L)F67K40
REGISTER 3-9:
Configuration Word 5L (30 0008h): Code Protection
U-1
U-1
U-1
U-1
U-1
U-1
R/W-1
R/W-1
—
—
—
—
—
—
CPD
CP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
Unimplemented: Read as ‘1’
bit 1
CPD: Data NVM Memory Code Protection bit
1
= Data NVM code protection disabled
0
= Data NVM code protection enabled
bit 0
CP: User NVM Program Memory Code Protection bit
1
= User NVM code protection disabled
0
= User NVM code protection enabled
REGISTER 3-10:
Configuration Word 6L (30 000Ah): Memory Read Protection
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
EBTR7
EBTR6
EBTR5
EBTR4
EBTR3
EBTR2
EBTR1
EBTR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
EBTR<7:0>: Table Read Protection bits(1)
1
= Corresponding Memory Block NOT protected from table reads executed in other blocks
0
= Corresponding Memory Block protected from table reads executed in other blocks
Note 1: Refer to Table 10-2 for details on implementation of the individual EBTR bits.
REGISTER 3-11:
Configuration Word 6H (30 000Bh): Memory Read Protection
U-1
U-1
U-1
U-1
U-1
U-1
R/W-1
U-1
—
—
—
—
—
—
EBTRB
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
-n = Value for blank device
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
Unimplemented: Read as ‘1’
bit 1
EBTRB: Table Read Protection bit
1
= Memory Boot Block NOT protected from table reads executed in other blocks
0
= Memory Boot Block protected from table reads executed in other blocks
bit 0
Unimplemented: Read as ‘1’
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Preliminary
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PIC18(L)F67K40
TABLE 3-1:
SUMMARY OF CONFIGURATION WORDS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
30 0000h
CONFIG1L
—
RSTOSC2
RSTOSC1
RSTOSC0
—
FEXTOSC2
FEXTOSC1
FEXTOSC0
1111 1111
30 0001h
CONFIG1H
—
—
FCMEN
—
CSWEN
—
—
CLKOUTEN
1111 1111
30 0002h
CONFIG2L
BOREN1
BOREN0
LPBOREN
—
—
—
PWRTE
MCLRE
1111 1111
30 0003h
CONFIG2H
XINST
—
DEBUG
STVREN
PPS1WAY
ZCD
BORV1
BORV0
1111 1111
30 0004h
CONFIG3L
—
WDTE<1:0>
WDTCPS<4:0>
1111 1111
30 0005h
CONFIG3H
—
—
WDTCCS<2:0>
WDTCWS<2:0>
1111 1111
30 0006h
CONFIG4L
WRT7
WRT6
WRT5
WRT4
WRT3
WRT2
WRT1
WRT0
1111 1111
30 0007h
CONFIG4H
—
—
LVP
SCANE
—
WRTD
WRTB
WRTC
1111 1111
30 0008h
CONFIG5L
—
—
—
—
—
—
CPD
CP
1111 1111
30 000Ah
CONFIG6L
EBTR7
EBTR6
EBTR5
EBTR4
EBTR3
EBTR2
EBTR1
EBTR0
1111 1111
30 000Bh
CONFIG6H
—
—
—
—
—
—
EBTRB
—
1111 1111
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Preliminary
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PIC18(L)F67K40
3.3
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory are controlled independently. Internal
access to the program memory is unaffected by any
code protection setting.
3.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Self-writing the
program memory is dependent upon the write
protection
setting.
See
Section
3.4 “Write
Protection” for more information.
3.3.2
DATA MEMORY PROTECTION
The entire Data EEPROM Memory space is protected
from external reads and writes by the CPD bit in the
Configuration Words. When CPD = 0, external reads
and writes of Data EEPROM Memory are inhibited and
a read will return all ‘0’s. The CPU can continue to read
Data EEPROM Memory regardless of the protection bit
settings.
3.4
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
3.5
User ID
Eight words in the memory space (200000h-200000Fh)
are designated as ID locations where the user can
store checksum or other code identification numbers.
These locations are readable and writable during
normal execution. See Section 11.2 “User ID, Device
ID and Configuration Word Access” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC18(L)F6XK40
Memory
Programming
Specification” (DS40001822).
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PIC18(L)F67K40
3.6
Device ID and Revision ID
The 16-bit device ID word is located at 3F FFFEh and
the 16-bit revision ID is located at 3F FFFCh. These
locations are read-only and cannot be erased or
modified.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID,
Revision ID and Configuration Words. Refer to 11.0
“Nonvolatile Memory (NVM) Control” for more
information on accessing these locations.
3.7
Register Definitions: Device and Revision
REGISTER 3-12:
DEVICE ID: DEVICE ID REGISTER
R
R
R
R
R
R
R
R
DEV15
DEV14
DEV13
DEV12
DEV11
DEV10
DEV9
DEV8
bit 15
bit 8
R
R
R
R
R
R
R
R
DEV7
DEV6
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 7
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
0’ = Bit is cleared
x = Bit is unknown
bit 15-0
DEV<15:0>: Device ID bits
Device
Device ID
PIC18F67K40
6AC0h
PIC18LF67K40
6B20h
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PIC18(L)F67K40
REGISTER 3-13:
REVISION ID: REVISION ID REGISTER
R
R
R
R
R
R
R
R
1
0
1
0
MJRREV<5:2>
bit 15
bit 8
R
R
R
R
R
R
R
R
MJRREV<1:0>
MNRREV<5:0>
bit 7
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Read as ‘1010’
These bits are fixed with value ‘1010’ for all devices in this family.
bit 11-6
MJRREV<5:0>: Major Revision ID bits
These bits are used to identify a major revision. A major revision is indicated by an all-layer revision
(A0, B0, C0, etc.).
Revision A = 6’b00_0000
bit 5-0
MNRREV<5:0>: Minor Revision ID bits
These bits are used to identify a minor revision.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 32
PIC18(L)F67K40
4.0
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
4.1
Overview
The oscillator module has multiple clock sources and
selection features that allow it to be used in a wide
range of applications while maximizing performance
and
minimizing
power
consumption.
Figure 4-1
illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external oscillators,
quartz-crystal resonators and ceramic resonators. In
addition, the system clock source can be supplied from
one of two internal oscillators and PLL circuits, with a
choice of speeds selectable via software. Additional
clock features include:
• Selectable system clock source between external
or internal sources via software.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, ECH, ECM, ECL) and switch
automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources.
The
RSTOSC
bits
of
Configuration
Word
1
(Register 3-1) determine the type of oscillator that will
be used when the device runs after Reset, including
when it is first powered up.
If an external clock source is selected, the FEXTOSC
bits of Configuration Word 1 must be used in
conjunction with the RSTOSC bits to select the
External Clock mode.
The external oscillator module can be configured in one
of the following clock modes, by setting the
FEXTOSC<2:0> bits of Configuration Word 1:
1.
ECL – External Clock Low-Power mode
(below 100 kHz)
2.
ECM – External Clock Medium Power mode
(100 kHz to 8 MHz)
3.
ECH – External Clock High-Power mode
(above 8 MHz)
4.
LP – 32 kHz Low-Power Crystal mode.
5.
XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (between 100 kHz and 8 MHz)
6.
HS – High Gain Crystal or Ceramic Resonator
mode (above 4 MHz)
The ECH, ECM, and ECL Clock modes rely on an
external logic level signal as the device clock source.
The LP, XT, and HS Clock modes require an external
crystal or resonator to be connected to the device.
Each mode is optimized for a different frequency range.
The internal oscillator block produces low and
high-frequency clock sources, designated LFINTOSC
and HFINTOSC. (see Internal Oscillator Block,
Figure 4-1). Multiple device clock frequencies may be
derived from these clock sources.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 33
PIC18(L)F67K40
FIGURE 4-1:
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Rev. 10-000208D
5/10/2016
FRQ<3:0>
HFINTOSC
Secondary
Oscillator
(SOSC)
External
Oscillator
(EXTOSC)
CLKIN/OSC1
CLKOUT/OSC2
SOSCIN/SOSCI
SOSCO
31 kHz
Oscillator
4x PLL
000
110
011
001
101
100
010
111
COSC<2:0>
LFINTOSC
1,2,4,8,12,16,32,48,64
MHz
Oscillator
Post Divider
1000
1001
0000
0011
0010
0001
0100
0101
0110
0111
512
256
128
64
32
16
8
4
2
1
CDIV<4:0>
Sleep
Idle
Sleep
SYSCMD
System Clock
Peripheral Clock
FSCM
To Peripherals
To Peripherals
To Peripherals
MFINTOSC
31.25 kHz and 500 kHz
Oscillator
To Peripherals
Reserved
Reserved
Reserved
LFINTOSC is used to
monitor system clock
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 34
PIC18(L)F67K40
4.2
Register Definitions: Oscillator Control
TABLE 4-1:
DEFAULT OSCILLATOR SETTINGS
REGISTER 4-1:
OSCCON1: OSCILLATOR CONTROL REGISTER1
U-0
R/W-f/f
R/W-f/f
R/W-f/f
R/W-q/q
R/W-q/q
R/W-q/q
R/W-q/q
—
NOSC<2:0>
NDIV<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
f = determined by fuse setting
q = Reset value is determined by hardware
bit 7
Unimplemented: Read as ‘0’
bit 6-4
NOSC<2:0>: New Oscillator Source Request bits(1,2,3)
The setting requests a source oscillator and PLL combination per Table 4-2.
POR value = RSTOSC (Register 3-1).
bit 3-0
NDIV<3:0>: New Divider Selection Request bits(2,3)
The setting determines the new postscaler division ratio per Table 4-2.
Note1: The default value (f/f) is determined by the RSTOSC Configuration bits. See Table 4-1below.
2: If NOSC is written with a reserved value (Table 4-2), the operation is ignored and neither NOSC nor NDIV is
written.
3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.
RSTOSC
SFR Reset Values
Initial FOSC Frequency
NOSC/COSC
CDIV
OSCFRQ
111
111
1:1
4 MHz
EXTOSC per FEXTOSC
110
110
4:1
FOSC = 1 MHz (4 MHz/4)
101
101
1:1
LFINTOSC
100
100
1:1
SOSC
011
Reserved
010
010
1:1
4 MHz
EXTOSC + 4xPLL (1)
001
Reserved
000
110
1:1
64 MHz
FOSC = 64 MHZ
Note 1:
EXTOSC must meet the PLL specifications (Table 37-9).
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Preliminary
DS40001841B-page 35
PIC18(L)F67K40
REGISTER 4-2:
OSCCON2: OSCILLATOR CONTROL REGISTER 2
U-0
R-q/q
R-q/q
R-q/q
R-q/q
R-q/q
R-q/q
R-q/q
—
COSC<2:0>
CDIV<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Reset value is determined by hardware
bit 7
Unimplemented: Read as ‘0’
bit 6-4
COSC<2:0>: Current Oscillator Source Select bits (read-only)(1,2)
Indicates the current source oscillator and PLL combination per Table 4-2.
bit 3-0
CDIV<3:0>: Current Divider Select bits (read-only)(1,2)
Indicates the current postscaler division ratio per Table 4-2.
Note 1: The POR value is the value present when user code execution begins.
2: The Reset value (q/q) is the same as the NOSC/NDIV bits.
TABLE 4-2:
NOSC/COSC AND NDIV/CDIV BIT SETTINGS
NOSC<2:0>
COSC<2:0>
Clock Source
NDIV<3:0>
CDIV<3:0>
Clock Divider
111
EXTOSC(1)
1111-1010
Reserved
110
HFINTOSC(2)
1001
512
101
LFINTOSC
1000
256
100
SOSC
0111
128
011
Reserved
0110
64
010
EXTOSC + 4x PLL(3)
0101
32
001
Reserved
0100
16
000
Reserved
0011
8
0010
4
0001
2
0000
1
Note 1:
EXTOSC configured by the FEXTOSC bits of Configuration Word 1 (Register 3-1).
2:
HFINTOSC frequency is set with the HFFRQ bits of the OSCFRQ register (Register 4-5).
3:
EXTOSC must meet the PLL specifications (Table 37-9).
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Preliminary
DS40001841B-page 36
PIC18(L)F67K40
REGISTER 4-3:
OSCCON3: OSCILLATOR CONTROL REGISTER 3
R/W/HC-0/0
R/W-0/0
U-0
R-0/0
R-0/0
U-0
U-0
U-0
CSWHOLD
SOSCPWR
—
ORDY
NOSCR
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
CSWHOLD: Clock Switch Hold bit
1 =
Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready
0 =
Clock switch may proceed when the oscillator selected by NOSC is ready; NOSCR
becomes ‘1’, the switch will occur
bit 6
SOSCPWR: Secondary Oscillator Power Mode Select bit
1 =
Secondary oscillator operating in High-Power mode
0 =
Secondary oscillator operating in Low-Power mode
bit 5
Unimplemented: Read as ‘0’
bit 4
ORDY: Oscillator Ready bit (read-only)
1 =
OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0 =
A clock switch is in progress
bit 3
NOSCR: New Oscillator is Ready bit (read-only)(1)
1 =
A clock switch is in progress and the oscillator selected by NOSC indicates a “ready” condition
0 =
A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
If CSWHOLD = 0, the user may not see this bit set because, when the oscillator becomes ready there
may be a delay of one instruction clock before this bit is set. The clock switch occurs in the next instruction
cycle and this bit is cleared.
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Preliminary
DS40001841B-page 37
PIC18(L)F67K40
REGISTER 4-4:
OSCSTAT: OSCILLATOR STATUS REGISTER 1
R-q/q
R-q/q
R-q/q
R-q/q
R-q/q
R-q/q
U-0
R-q/q
EXTOR
HFOR
MFOR
LFOR
SOR
ADOR
—
PLLR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Reset value is determined by hardware
bit 7
EXTOR: EXTOSC (external) Oscillator Ready bit
1 =
The oscillator is ready to be used
0 =
The oscillator is not enabled, or is not yet ready to be used
bit 6
HFOR: HFINTOSC Oscillator Ready bit
1 =
The oscillator is ready to be used
0 =
The oscillator is not enabled, or is not yet ready to be used
bit 5
MFOR: MFINTOSC Oscillator Ready
1 = The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used
bit 4
LFOR: LFINTOSC Oscillator Ready bit
1 =
The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used
bit 3
SOR: Secondary (Timer1) Oscillator Ready bit
1 =
The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used
bit 2
ADOR: ADC Oscillator Ready bit
1 =
The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used
bit 1
Unimplemented: Read as ‘0’
bit 0
PLLR: PLL is Ready bit
1 =
The PLL is ready to be used
0 =
The PLL is not enabled, the required input source is not ready, or the PLL is not locked.
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Preliminary
DS40001841B-page 38
PIC18(L)F67K40
REGISTER 4-5:
OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER
U-0
U-0
U-0
U-0
R/W-q/q
R/W-q/q
R/W-q/q
R/W-q/q
—
—
—
—
HFFRQ<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Reset value is determined by hardware
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
HFFRQ<3:0>: HFINTOSC Frequency Selection bits
Note 1:
Refer to Table 4-1 for more information.
HFFRQ<3:0>
Nominal Freq (MHz)
1001
Reserved
1010
1111
1110
1101
1100
1011
1000(3)
64
0111
48
0110
32
0101(4)
16
0100
12
0011
8
0010(1,2)
4
0001
2
0000
1
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Preliminary
DS40001841B-page 39
PIC18(L)F67K40
REGISTER 4-6:
OSCTUNE: HFINTOSC TUNING REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
HFTUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
HFTUN<5:0>: HFINTOSC Frequency Tuning bits
01 1111 = Maximum frequency
•
•
•
00 0000 = Center frequency. Oscillator module is running at the calibrated frequency
(default value).
•
•
•
10 0000 = Minimum frequency
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Preliminary
DS40001841B-page 40
PIC18(L)F67K40
REGISTER 4-7:
OSCEN: OSCILLATOR MANUAL ENABLE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
EXTOEN
HFOEN
MFOEN
LFOEN
SOSCEN
ADOEN
—
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
EXTOEN: External Oscillator Manual Request Enable bit
1 =
EXTOSC is explicitly enabled, operating as specified by FEXTOSC
0 =
EXTOSC could be enabled by requesting peripheral
bit 6
HFOEN: HFINTOSC Oscillator Manual Request Enable bit
1 =
HFINTOSC is explicitly enabled, operating as specified by OSCFRQ (Register 4-5)
0 =
HFINTOSC could be enabled by requesting peripheral
bit 5
MFOEN: MFINTOSC (500 kHz/31.25 kHz) Oscillator Manual Request Enable bit (Derived from
HFINTOSC)
1 =
MFINTOSC is explicitly enabled
0 =
MFINTOSC could be enabled by requesting peripheral
bit 4
LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit
1 =
LFINTOSC is explicitly enabled
0 =
LFINTOSC could be enabled by requesting peripheral
bit 3
SOSCEN: Secondary Oscillator Manual Request Enable bit
1 =
Secondary Oscillator is explicitly enabled, operating as specified by SOSCPWR
0 =
Secondary Oscillator could be enabled by requesting peripheral
bit 2
ADOEN: ADC Oscillator Manual Request Enable bit
1 =
ADC oscillator is explicitly enabled
0 =
ADC oscillator could be enabled by requesting peripheral
bit 1-0
Unimplemented: Read as ‘0’
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PIC18(L)F67K40
4.3
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator
modules (ECH, ECM, ECL mode), quartz crystal
resonators or ceramic resonators (LP, XT and HS
modes).
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two
internal oscillators that are used to generate internal
system clock sources. The High-Frequency Internal
Oscillator (HFINTOSC) can produce 1, 2, 4, 8, 12, 16,
32, 48 and 64 MHz clock. The frequency can be
controlled
through
the
OSCFRQ
register
(Register 4-5). The Low-Frequency Internal Oscillator
(LFINTOSC) generates a fixed 31 kHz frequency.
A 4x PLL is provided that can be used in conjunction
with the external clock. See Section 4.3.1.4 “4x PLL”
for more details.
The system clock can be selected between external or
internal clock sources via the NOSC bits in the
OSCCON1
register.
See
Section
4.4 “Clock
Switching” for additional information. The system
clock can be made available on the OSC2/CLKOUT pin
for any of the modes that do not use the OSC2 pin. The
clock out functionality is governed by the CLKOUTEN
bit in the CONFIG1H register (Register 3-2). If enabled,
the clock out signal is always at a frequency of FOSC/4.
4.3.1
EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
• Program the RSTOSC<2:0> and FEXTOSC<2:0>
bits in the Configuration Words to select an
external clock source that will be used as the
default system clock upon a device Reset.
• Write the NOSC<2:0> and NDIV<3:0> bits in the
OSCCON1 register to switch the system clock
source.
See Section 4.4 “Clock Switching” for more
information.
4.3.1.1
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source
is
connected
to
the
OSC1
input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 4-2 shows the pin connections for EC
mode.
EC mode has three power modes to select from through
Configuration Words:
• ECH – High power, above 8 MHz
• ECM – Medium power, 100 kHz-8 MHz
• ECL – Low power, below 100 MHz
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 4-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
4.3.1.2
LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 4-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium
drive
level
specification
(above
100 kHz - 8 MHz).
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting
(above 8 MHz).
Figure 4-3 and Figure 4-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
OSC1/CLKIN
OSC2/CLKOUT
Clock from
Ext. System
PIC® MCU
FOSC/4 or I/O(1)
Note
1:
Output depends upon CLKOUTEN bit of the
Configuration Words (CONFIG1H).
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Preliminary
DS40001841B-page 42
PIC18(L)F67K40
FIGURE 4-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 4-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
4.3.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR), or a wake-up from Sleep. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.
4.3.1.4
4x PLL
The oscillator module contains a 4x PLL that can be
used with the external clock sources to provide a
system clock source. The input frequency for the PLL
must fall within specifications. See the PLL Clock
Timing Specifications in Table 37-9.
The PLL can be enabled for use by one of two
methods:
1.
Program the RSTOSC bits in the Configuration
Word 1 to 010 (enable EXTOSC with 4x PLL).
2.
Write the NOSC bits in the OSCCON1 register
to 010 (enable EXTOSC with 4x PLL).
Note 1:
A series resistor (RS) may be required for
quartz crystals with low drive level.
2:
The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2)
Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
Note 1:
A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2
Ceramic
RS(1)
OSC1/CLKIN
RF(2)
Sleep
To Internal
Logic
PIC® MCU
RP(3)
Resonator
OSC2/CLKOUT
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Preliminary
DS40001841B-page 43
PIC18(L)F67K40
4.3.1.5
Secondary Oscillator
The secondary oscillator is a separate oscillator block
that can be used as an alternate system clock source.
The secondary oscillator is optimized for 32.768 kHz,
and can be used with an external crystal oscillator con-
nected to the SOSCI and SOSCO device pins, or an
external clock source connected to the SOSCIN pin.
The secondary oscillator can be selected during
run-time using clock switching. Refer to Section
4.4 “Clock Switching” for more information.
FIGURE 4-5:
QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
4.3.2
INTERNAL CLOCK SOURCES
The device may be configured to use the internal
oscillator block as the system clock by performing one
of the following actions:
• Program the RSTOSC<2:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the NOSC<2:0> bits in the OSCCON1
register to switch the system clock source to the
internal oscillator during run-time. See Section
4.4 “Clock Switching” for more information.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in Configuration Words.
The internal oscillator block has two independent
oscillators that can produce two internal system clock
sources.
1.
The
HFINTOSC
(High-Frequency
Internal
Oscillator) is factory-calibrated and operates
from 1 to 64 MHz. The frequency of HFINTOSC
can
be
selected
through
the
OSCFRQ
Frequency Selection register, and fine-tuning
can be done via the OSCTUNE register.
2.
The
LFINTOSC
(Low-Frequency
Internal
Oscillator) is factory-calibrated and operates at
31 kHz.
Note 1:
Quartz
crystal
characteristics
vary
according
to
type,
package
and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2:
Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3:
For oscillator design assistance, reference
the following Microchip Application Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for PIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)
C1
C2
32.768 kHz
SOSCI
To Internal
Logic
PIC® MCU
Crystal
SOSCO
Quartz
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Preliminary
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PIC18(L)F67K40
4.3.2.1
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a precision digitally-controlled internal clock source
that produces a stable clock up to 64 MHz. The
HFINTOSC can be enabled through one of the
following methods:
• Programming the RSTOSC<2:0> bits in
Configuration Word 1 to ‘110’ (FOSC = 1 MHz) or
‘000’ (FOSC = 64 MHz) to set the oscillator upon
device Power-up or Reset.
• Write to the NOSC<2:0> bits of the OSCCON1
register during run-time. See Section 4.4 “Clock
Switching” for more information.
The HFINTOSC frequency can be selected by setting
the HFFRQ<3:0> bits of the OSCFRQ register.
The NDIV<3:0> bits of the OSCCON1 register allow for
division of the HFINTOSC output from a range between
1:1 and 1:512.
4.3.2.2
MFINTOSC
The module provides two (500 kHz and 31.25 kHz)
constant clock outputs. These clocks are digital
divisors of the HFINTOSC clock. Dynamic divider logic
is used to provide constant MFINTOSC clock rates for
all settings of HFINTOSC.
The MFINTOSC cannot be used to drive the system
but it is used to clock certain modules such as the
Timers and WWDT.
4.3.2.3
Internal Oscillator Frequency
Adjustment
The internal oscillator is factory-calibrated. This
internal oscillator can be adjusted in software by writing
to the OSCTUNE register (Register 4-3).
The default value of the OSCTUNE register is 00h. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), WWDT, Fail-Safe Clock Monitor (FSCM) and
peripherals, are not affected by the change in frequency.
4.3.2.4
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a factory-calibrated 31 kHz internal clock source.
The LFINTOSC is the frequency for the Power-up Timer
(PWRT), Windowed Watchdog Timer (WWDT) and
Fail-Safe Clock Monitor (FSCM).
The LFINTOSC is enabled through one of the following
methods:
• Programming the RSTOSC<2:0> bits of
Configuration Word 1 to enable LFINTOSC.
• Write to the NOSC<2:0> bits of the OSCCON1
register during run-time. See Section 4.4, Clock
Switching for more information.
4.3.2.5
ADCRC
The ADCRC is an oscillator dedicated to the ADC2
module. The ADCRC oscillator can be manually
enabled using the ADOEN bit of the OSCEN register.
The ADCRC runs at a fixed frequency of 600 kHz.
ADCRC is automatically enabled if it is selected as the
clock source for the ADC2 module.
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DS40001841B-page 45
PIC18(L)F67K40
4.3.2.6
Oscillator Status and Manual Enable
The Ready status of each oscillator (including the
ADCRC
oscillator)
is
displayed
in
OSCSTAT
(Register 4-4). The oscillators (but not the PLL) may be
explicitly enabled through OSCEN (Register 4-7).
4.3.2.7
HFOR and MFOR Bits
The HFOR and MFOR bits indicate that the HFINTOSC
and MFINTOSC is ready. These clocks are always
valid for use at all times, but only accurate after they are
ready.
When a new value is loaded into the OSCFRQ register,
the HFOR and MFOR bits will clear, and set again
when the oscillator is ready. During pending OSCFRQ
changes the MFINTOSC clock will stall at a high or a
low state, until the HFINTOSC resumes operation.
4.4
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the New Oscillator Source (NOSC) bits of the
OSCCON1 register. The following clock sources can be
selected using the following:
• External oscillator
• Internal Oscillator Block (INTOSC)
4.4.1
NEW OSCILLATOR SOURCE
(NOSC) AND NEW DIVIDER
SELECTION REQUEST (NDIV) BITS
The New Oscillator Source (NOSC) and New Divider
Selection Request (NDIV) bits of the OSCCON1
register select the system clock source and frequency
that are used for the CPU and peripherals.
When new values of NOSC and NDIV are written to
OSCCON1, the current oscillator selection will
continue to operate while waiting for the new clock
source to indicate that it is stable and ready. In some
cases, the newly requested source may already be in
use, and is ready immediately. In the case of a
divider-only change, the new and old sources are the
same, so the old source will be ready immediately. The
device may enter Sleep while waiting for the switch as
described in Section 4.4.3 “Clock Switch and
Sleep”.
When the new oscillator is ready, the New Oscillator
Ready (NOSCR) bit of OSCCON3 is set and also the
Clock Switch Interrupt Flag (CSWIF) bit of PIR1 sets. If
Clock Switch Interrupts are enabled (CSWIE = 1), an
interrupt will be generated at that time. The Oscillator
Ready (ORDY) bit of OSCCON3 can also be polled to
determine when the oscillator is ready in lieu of an
interrupt.
If the Clock Switch Hold (CSWHOLD) bit of OSCCON3
is clear, the oscillator switch will occur when the New
Oscillator is Ready bit (NOSCR) is set, and the
interrupt (if enabled) will be serviced at the new
oscillator setting.
If CSWHOLD is set, the oscillator switch is suspended,
while execution continues using the current (old) clock
source. When the NOSCR bit is set, software should:
• Set CSWHOLD = 0 so the switch can complete,
or
• Copy COSC into NOSC to abandon the switch.
If DOZE is in effect, the switch occurs on the next clock
cycle, whether or not the CPU is operating during that
cycle.
Changing the clock post-divider without changing the
clock source (i.e., changing FOSC from 1 MHz to
2 MHz) is handled in the same manner as a clock
source change, as described previously. The clock
source will already be active, so the switch is relatively
quick. CSWHOLD must be clear (CSWHOLD = 0) for
the switch to complete.
The current COSC and CDIV are indicated in the
OSCCON2 register up to the moment when the switch
actually occurs, at which time OSCCON2 is updated
and ORDY is set. NOSCR is cleared by hardware to
indicate that the switch is complete.
4.4.2
PLL INPUT SWITCH
Switching between the PLL and any non-PLL source is
managed as described above. The input to the PLL is
established when NOSC selects the PLL, and
maintained by the COSC setting.
When NOSC and COSC select the PLL with different
input sources, the system continues to run using the
COSC setting, and the new source is enabled per
NOSC. When the new oscillator is ready (and
CSWHOLD = 0), system operation is suspended while
the PLL input is switched and the PLL acquires lock.
This provides a truly glitch-free clock switch operation.
Note:
The
Clock
Switch
Enable
bit
in
Configuration Word 1 can be used to
enable or disable the clock switching
capability. When cleared, the NOSC and
NDIV bits cannot be changed by user
software. When set, writing to NOSC and
NDIV is allowed and would switch the
clock frequency.
Note:
The CSWIF interrupt will not wake the
system from Sleep.
Note:
If the PLL fails to lock, the FSCM will
trigger.
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Preliminary
DS40001841B-page 46
PIC18(L)F67K40
4.4.3
CLOCK SWITCH AND SLEEP
If OSCCON1 is written with a new value and the device
is put to Sleep before the switch completes, the switch
will not take place and the device will enter Sleep
mode.
When the device wakes from Sleep and the
CSWHOLD bit is clear, the device will wake with the
‘new’ clock active, and the clock switch interrupt flag bit
(CSWIF) will be set.
When the device wakes from Sleep and the
CSWHOLD bit is set, the device will wake with the ‘old’
clock active and the new clock will be requested again.
FIGURE 4-6:
CLOCK SWITCH (CSWHOLD = 0)
FIGURE 4-7:
CLOCK SWITCH (CSWHOLD = 1)
Note 1:
CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2:
The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.
CSWHOLD
NOSCR
OSC #2
CSWIF
OSCCON1
WRITTEN
NOTE 1
USER
CLEAR
OSC #1
NOTE 2
ORDY
Note 1:
CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.
CSWHOLD
NOSCR
OSC #1
OSC #2
CSWIF
OSCCON1
WRITTEN
NOTE 1
ORDY
USER
CLEAR
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Preliminary
DS40001841B-page 47
PIC18(L)F67K40
FIGURE 4-8:
CLOCK SWITCH ABANDONED
Note 1:
CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.
2:
ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.
CSWHOLD
NOSCR
OSC #1
CSWIF
OSCCON1
WRITTEN
NOTE 1
OSCCON1
WRITTEN
NOTE 2
ORDY
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Preliminary
DS40001841B-page 48
PIC18(L)F67K40
4.5
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, ECL/M/H and
Secondary Oscillator).
FIGURE 4-9:
FSCM BLOCK DIAGRAM
4.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 4-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
4.5.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM overwrites the
COSC bits to select HFINTOSC (3'b110). The
frequency of HFINTOSC would be determined by the
previous state of the HFFRQ bits and the NDIV/CDIV
bits. The bit flag OSCFIF of the PIR1 register is set.
Setting this flag will generate an interrupt if the OSCFIE
bit of the PIE1 register is also set. The device firmware
can then take steps to mitigate the problems that may
arise from a failed clock. The system clock will continue
to be sourced from the internal clock source until the
device firmware successfully restarts the external
oscillator and switches back to external operation, by
writing to the NOSC and NDIV bits of the OSCCON1
register.
4.5.3
FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the NOSC
and NDIV bits of the OSCCON1 register. When
switching to the external oscillator or PLL, the OST is
restarted. While the OST is running, the device
continues to operate from the INTOSC selected in
OSCCON1. When the OST times out, the Fail-Safe
condition is cleared after successfully switching to the
external clock source. The OSCFIF bit should be
cleared prior to switching to the external clock source.
If the Fail-Safe condition still exists, the OSCFIF flag
will again become set by hardware.
External
LFINTOSC
÷ 64
S
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
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Preliminary
DS40001841B-page 49
PIC18(L)F67K40
4.5.4
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC
Clock modes so that the FSCM will be active as soon
as the Reset or wake-up has completed.
FIGURE 4-10:
FSCM TIMING DIAGRAM
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Test
Test
Test
Clock Monitor Output
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DS40001841B-page 50
PIC18(L)F67K40
TABLE 4-3:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
OSCCON1
—
NOSC<2:0>
NDIV<3:0>
34
OSCCON2
—
COSC<2:0>
CDIV<3:0>
35
OSCCON3
CSWHOLD SOSCPWR
—
ORDY
NOSCR
—
—
—
36
OSCSTAT
EXTOR
HFOR
MFOR
LFOR
SOR
ADOR
—
PLLR
37
OSCTUNE
—
—
HFTUN<5:0>
39
OSCFRQ
—
—
—
—
HFFRQ<3:0>
38
OSCEN
EXTOEN
HFOEN
MFOEN
LFOEN
SOSCEN
ADOEN
—
—
40
PIE1
OSCFIE
CSWIE
—
—
—
—
ADTIE
ADIE
185
PIR1
OSCFIF
CSWIF
—
—
—
—
ADTIF
ADIF
174
IPR1
OSCFIP
CSWIP
—
—
—
—
ADTIP
ADIP
195
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 4-4:
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
Register
on Page
CONFIG1
13:8
—
—
FCMEN
—
CSWEN
—
—
CLKOUTEN
21
7:0
—
RSTOSC<2:0>
—
FEXTOSC<2:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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Preliminary
DS40001841B-page 51
PIC18(L)F67K40
5.0
REFERENCE CLOCK OUTPUT
MODULE
The reference clock output module provides the ability
to send a clock signal to the clock reference output pin
(CLKR). The reference clock output can also be used
as a signal for other peripherals, such as the Data
Signal Modulator (DSM), Memory Scanner and Timer
module.
The reference clock output module has the following
features:
• Selectable clock source using the CLKRCLK
register
• Programmable clock divider
• Selectable duty cycle
FIGURE 5-1:
CLOCK REFERENCE BLOCK DIAGRAM
Rev. 10-000261B
5/11/2016
000
011
010
001
100
101
110
111
CLKRDIV<2:0>
128
64
32
16
8
4
2
CLKREN
Counter Reset
Duty Cycle
PPS
To Peripherals
CLKR
CLKRCLK<3:0>
See
CLKRCLK
Register
CLKREN
Reference Clock Divider
CLKRDC<1:0>
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Preliminary
DS40001841B-page 52
PIC18(L)F67K40
FIGURE 5-2:
CLOCK REFERENCE TIMING
Rev. 10-000264B
5/25/2016
CLKRCLK
CLKREN
CLKRDIV<2:0> = 001
CLKRDC<1:0> = 10
CLKR Output
Duty Cycle
(50%)
CLKRDIV<2:0> = 001
CLKRDC<1:0> = 01
CLKR Output
Duty Cycle
(25%)
CLKRCLK/2
P1
P2
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Preliminary
DS40001841B-page 53
PIC18(L)F67K40
5.1
Clock Source
The input to the reference clock output can be selected
using the CLKRCLK register.
5.1.1
CLOCK SYNCHRONIZATION
Once the reference clock enable (EN) is set, the mod-
ule is ensured to be glitch-free at start-up.
When the reference clock output is disabled, the output
signal will be disabled immediately.
Clock dividers and clock duty cycles can be changed
while the module is enabled, but glitches may occur on
the output. To avoid possible glitches, clock dividers
and clock duty cycles should be changed only when the
CLKREN is clear.
5.2
Programmable Clock Divider
The module takes the clock input and divides it based
on the value of the DIV<2:0> bits of the CLKRCON reg-
ister (Register 5-1).
The following configurations can be made based on the
DIV<2:0> bits:
• Base FOSC value
• FOSC divided by 2
• FOSC divided by 4
• FOSC divided by 8
• FOSC divided by 16
• FOSC divided by 32
• FOSC divided by 64
• FOSC divided by 128
The clock divider values can be changed while the
module is enabled; however, in order to prevent
glitches on the output, the DIV<2:0> bits should only be
changed when the module is disabled (EN = 0).
5.3
Selectable Duty Cycle
The DC<1:0> bits of the CLKRCON register can be
used to modify the duty cycle of the output clock. A duty
cycle of 25%, 50%, or 75% can be selected for all clock
rates, with the exception of the undivided base FOSC
value.
The duty cycle can be changed while the module is
enabled; however, in order to prevent glitches on the
output, the DC<1:0> bits should only be changed when
the module is disabled (EN = 0).
5.4
Operation in Sleep Mode
The reference clock output module clock is based on
the system clock. When the device goes to Sleep, the
module outputs will remain in their current state. This
will have a direct effect on peripherals using the
reference clock output as an input signal. No change
should occur in the module from entering or exiting
from Sleep.
Note:
The DC1 bit is reset to ‘1’. This makes the
default duty cycle 50% and not 0%.
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Preliminary
DS40001841B-page 54
PIC18(L)F67K40
5.5
Register Definitions: Reference Clock
Long bit name prefixes for the Reference Clock periph-
erals are shown in Table 5-1. Refer to Section
1.4.2.2 “Long Bit Names” for more information.
TABLE 5-1:
Peripheral
Bit Name Prefix
CLKR
CLKR
REGISTER 5-1:
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
U-0
U-0
R/W-1/1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EN
—
—
DC<1:0>
DIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
EN: Reference Clock Module Enable bit
1 =
Reference clock module enabled
0 =
Reference clock module is disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 4-3
DC<1:0>: Reference Clock Duty Cycle bits(1)
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
bit 2-0
DIV<2:0>: Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value
Note 1:
Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.
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Preliminary
DS40001841B-page 55
PIC18(L)F67K40
REGISTER 5-2:
CLKRCLK: CLOCK REFERENCE CLOCK SELECTION MUX
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
—
CLK<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
CLK<2:0>: CLKR Clock Selection bits
111 = Unimplemented
110 = Unimplemented
101 = Unimplemented
100 = SOSC
011 = MFINTOSC (500 kHz)
010 = LFINTOSC (31 kHz)
001 = HFINTOSC
000 = FOSC
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CLKRCON
EN
—
—
DC<1:0>
DIV<2:0>
54
CLKRCLK
—
—
—
—
—
CLK<2:0>
55
PMD0
SYSCMD
FVRMD
HLVDMD
CRCMD
SCANMD
NVMMD
CLKRMD
IOCMD
65
RxyPPS
—
—
RxyPPS<5:0>
227
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.
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Preliminary
DS40001841B-page 56
PIC18(L)F67K40
6.0
POWER-SAVING OPERATION
MODES
The purpose of the Power-Down modes is to reduce
power consumption. There are three Power-Down
modes:
• Doze mode
• Sleep mode
• Idle mode
6.1
Doze Mode
Doze mode allows for power saving by reducing CPU
operation and program memory (PFM) access, without
affecting peripheral operation. Doze mode differs from
Sleep mode because the bandgap and system
oscillators continue to operate, while only the CPU and
PFM are affected. The reduced execution saves power
by eliminating unnecessary operations within the CPU
and memory.
When the Doze Enable (DOZEN) bit is set
(DOZEN = 1), the CPU executes only one instruction
cycle out of every N cycles as defined by the
DOZE<2:0> bits of the CPUDOZE register. For
example, if DOZE<2:0> = 001, the instruction cycle
ratio is 1:4. The CPU and memory execute for one
instruction cycle and then lay idle for three instruction
cycles. During the unused cycles, the peripherals
continue to operate at the system clock speed.
6.1.1
DOZE OPERATION
The Doze operation is illustrated in Figure 6-1. For this
example:
• Doze enable (DOZEN) bit set (DOZEN = 1)
• DOZE<2:0> = 001 (1:4) ratio
• Recover-on-Interrupt (ROI) bit set (ROI = 1)
As with normal operation, the PFM fetches for the next
instruction cycle. The Q-clocks to the peripherals
continue throughout.
FIGURE 6-1:
DOZE MODE OPERATION EXAMPLE (DOZE<2:0> = 001, 1:4)
System
Clock
/ŶƐƚƌƵĐƚŝŽŶ
WĞƌŝŽĚ
CPU Clock
PFM Op’s
CPU Op’s
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
3
3
3
3
3
3
4
4
4
4
4
4
2
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
Fetch
Fetch
Fetch
Fetch
Exec
Exec
Exec(1,2)
Exec
Exec
Exec
Push
NOP
0004h
Interrupt
Here
(ROI = 1)
Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.
2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.
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Preliminary
DS40001841B-page 57
PIC18(L)F67K40
6.1.2
INTERRUPTS DURING DOZE
If an interrupt occurs and the Recover-On-Interrupt bit
is clear (ROI = 0) at the time of the interrupt, the
Interrupt Service Routine (ISR) continues to execute at
the rate selected by DOZE<2:0>. Interrupt latency is
extended by the DOZE<2:0> ratio.
If an interrupt occurs and the ROI bit is set (ROI = 1) at
the time of the interrupt, the DOZEN bit is cleared and
the CPU executes at full speed. The prefetched instruc-
tion is executed and then the interrupt vector sequence
is executed. In Figure 6-1, the interrupt occurs during
the 2nd instruction cycle of the Doze period, and imme-
diately brings the CPU out of Doze. If the Doze-On-Exit
(DOE) bit is set (DOE = 1) when the RETFIE operation
is executed, DOZEN is set, and the CPU executes at
the reduced rate based on the DOZE<2:0> ratio.
EXAMPLE 6-1:
DOZE SOFTWARE
EXAMPLE
6.2
Sleep Mode
Sleep mode is entered by executing the SLEEP
instruction, while the Idle Enable (IDLEN) bit of the
CPUDOZE register is clear (IDLEN = 0).
Upon entering Sleep mode, the following conditions
exist:
1.
WDT will be cleared but keeps running if
enabled for operation during Sleep
2.
The PD bit of the STATUS register is cleared
(Register 10-2)
3.
The TO bit of the STATUS register is set
(Register 10-2)
4.
The CPU clock is disabled
5.
LFINTOSC, SOSC, HFINTOSC and ADCRC
are unaffected and peripherals using them may
continue operation in Sleep.
6.
I/O ports maintain the status they had before
Sleep was executed (driving high, low, or
high-impedance)
7.
Resets other than WDT are not affected by
Sleep mode
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
- I/O pins should not be floating
- External circuitry sinking current from I/O pins
- Internal circuitry sourcing current from I/O
pins
- Current draw from pins with internal weak
pull-ups
- Modules using any oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 31.0 “5-Bit Digital-to-Analog
Converter (DAC) Module” and Section 29.0 “Fixed
Voltage Reference (FVR)” for more information on
these modules.
//Mainline operation
bool somethingToDo = FALSE:
void main()
{
initializeSystem();
// DOZE = 64:1 (for example)
// ROI = 1;
GIE = 1; // enable interrupts
while (1)
{
// If ADC completed, process data
if (somethingToDo)
{
doSomething();
DOZEN = 1; // resume low-power
}
}
}
// Data interrupt handler
void interrupt()
{
// DOZEN = 0 because ROI = 1
if (ADIF)
{
somethingToDo = TRUE;
DOE = 0; // make main() go fast
ADIF = 0;
}
// else check other interrupts...
if (TMR0IF)
{
timerTick++;
DOE = 1; // make main() go slow
TMR0IF = 0;
}
}
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Preliminary
DS40001841B-page 58
PIC18(L)F67K40
6.2.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
External Reset input on MCLR pin, if enabled
2.
BOR Reset, if enabled
3.
Low-Power Brown-Out Reset (LPBOR), if
enabled
4.
POR Reset
5.
Windowed Watchdog Timer, if enabled
6.
All interrupt sources except clock switch
interrupt can wake-up the part.
The first five events will cause a device Reset. The last
one event is considered a continuation of program
execution. To determine whether a device Reset or
wake-up
event
occurred,
refer
to
Section
8.13 “Determining the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
Interrupt Enable bit must be enabled, as well as the
Peripheral Interrupt Enable bit (PEIE = 1), for every
interrupt not in PIR0. Wake-up will occur regardless of
the state of the GIE bit. If the GIE bit is disabled, the
device continues execution at the instruction after the
SLEEP instruction. If the GIE bit is enabled, the device
executes the instruction after the SLEEP instruction, the
device will then call the Interrupt Service Routine. In
cases where the execution of the instruction following
SLEEP is not desirable, the user should have a NOP
after the SLEEP instruction.
The WDT is cleared when the device wakes-up from
Sleep, regardless of the source of wake-up.
Upon a wake from a Sleep event, the core will wait for
a combination of three conditions before beginning
execution. The conditions are:
• PFM Ready
• COSC-Selected Oscillator Ready
• BOR Ready (unless BOR is disabled)
6.2.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source, with the exception of the clock
switch interrupt, has both its interrupt enable bit and
interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared
• If the interrupt occurs during or after the
execution of a SLEEP instruction
- SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
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Preliminary
DS40001841B-page 59
PIC18(L)F67K40
FIGURE 6-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
6.2.3
LOW-POWER SLEEP MODE
The PIC18F6xK40 device family contains an internal
Low Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode.
The PIC18F6xK40 devices allows the user to optimize
the operating current in Sleep, depending on the
application requirements.
Low-Power Sleep mode can be selected by setting the
VREGPM bit of the VREGCON register.
6.2.3.1
Sleep Current vs. Wake-up Time
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking-up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
The Low-Power Sleep mode is beneficial for
applications that stay in Sleep mode for long periods of
time. The Normal mode is beneficial for applications
that need to wake from Sleep quickly and frequently.
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC
PC + 1
PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(4)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Forced NOP
PC + 2
0004h
0005h
Forced NOP
TOST(3)
PC + 2
Note
1:
External clock. High, Medium, Low mode assumed.
2:
CLKOUT is shown here for timing reference.
3:
TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.
4:
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
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Preliminary
DS40001841B-page 60
PIC18(L)F67K40
6.2.3.2
Peripheral Usage in Sleep
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The Low-Power Sleep mode is intended for
use with these peripherals:
• Brown-out Reset (BOR)
• Windowed Watchdog Timer (WWDT)
• External interrupt pin/Interrupt-On-Change pins
• Peripherals that run off external secondary clock
source
It is the responsibility of the end user to determine what
is acceptable for their application when setting the
VREGPM settings in order to ensure operation in
Sleep.
6.2.4
IDLE MODE
When IDLEN is set (IDLEN = 1), the SLEEP instruction
will put the device into Idle mode. In Idle mode, the
CPU and memory operations are halted, but the
peripheral clocks continue to run. This mode is similar
to Doze mode, except that in IDLE both the CPU and
PFM are shut off.
6.2.4.1
Idle and Interrupts
IDLE mode ends when an interrupt occurs (even if GIE
= 0), but IDLEN is not changed. The device can
re-enter IDLE by executing the SLEEP instruction.
If Recover-On-Interrupt is enabled (ROI = 1), the
interrupt that brings the device out of Idle also restores
full-speed CPU execution when doze is also enabled.
6.2.4.2
Idle and WWDT
When in Idle, the WWDT Reset is blocked and will
instead wake the device. The WWDT wake-up is not an
interrupt, therefore ROI does not apply.
6.3
Peripheral Operation in Power
Saving Modes
All selected clock sources and the peripherals running
off them are active in both IDLE and DOZE mode. Only
in Sleep mode, both the FOSC and FOSC/4 clocks are
unavailable. All the other clock sources are active, if
enabled manually or through peripheral clock selection
before the part enters Sleep.
Note:
The PIC18LF6xK40 devices do not have a
configurable Low-Power Sleep mode.
PIC18LF6xK40 devices are unregulated
and are always in the lowest power state
when in Sleep, with no wake-up time
penalty. These devices have a lower max-
imum VDD and I/O voltage than the
PIC18F6xK40 devices. See Section
37.0 “Electrical
Specifications”
for
more information.
Note:
If CLKOUTEN is enabled (CLKOUTEN = 0,
Configuration Word 1H), the output will con-
tinue operating while in Idle.
Note:
The WDT can bring the device out of Idle,
in the same way it brings the device out of
Sleep. The DOZEN bit is not affected.
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Preliminary
DS40001841B-page 61
PIC18(L)F67K40
6.4
Register Definitions: Voltage Regulator Control
REGISTER 6-1:
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
—
—
—
—
—
—
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1:
PIC18F6xK40 only.
2:
See Section 37.0 “Electrical Specifications”.
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Preliminary
DS40001841B-page 62
PIC18(L)F67K40
REGISTER 6-2:
CPUDOZE: DOZE AND IDLE REGISTER
R/W-0/u
R/W/HC/HS-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
IDLEN
DOZEN
ROI
DOE
—
DOZE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other
Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
IDLEN: Idle Enable bit
1 = A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)
0 = A SLEEP instruction places the device into full Sleep mode
bit 6
DOZEN: Doze Enable bit(1,2)
1 = The CPU executes instruction cycles according to DOZE setting
0 = The CPU executes all instruction cycles (fastest, highest power operation)
bit 5
ROI: Recover-On-Interrupt bit
1 = Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed
operation
0 = Interrupt entry does not change DOZEN
bit 4
DOE: Doze-On-Exit bit
1 = Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation
0 = RETFIE does not change DOZEN
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles
111 =1:256
110 =1:128
101 =1:64
100 =1:32
011 =1:16
010 =1:8
001 =1:4
000 =1:2
Note 1:
When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
2:
Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.
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Preliminary
DS40001841B-page 63
PIC18(L)F67K40
TABLE 6-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
—
—
—
—
—
INTEDG
172
PIE0
—
—
TMR0IE
IOCIE
INT3IE
INT2IE
INT1IE
INT0IE
184
PIE1
OSCFIE
CSWIE
—
—
—
—
ADTIE
ADIE
185
PIE2
HLVDIE
ZCDIE
—
—
—
—
C2IE
C1IE
186
PIE3
RC2IE
TX2IE
RC1IE
TX1IE
BCL2IE
SSP2IE
BCL1IE
SSP1IE
187
PIE4
—
—
RC5IE
TX5IE
RC4IE
TX4IE
RC3IE
TX3IE
188
PIE5
—
—
—
—
—
TMR3IE
TMR2IE
TMR1IE
189
PIE6
—
—
—
—
TMR7GIE
TMR5GIE
TMR3GIE
TMR1GIE
190
PIE7
—
—
—
CCP5IE
CCP4IE
CCP3IE
CCP2IE
CCP1IE
191
PIE8
SCANIE
CRCIE
NVMIE
—
—
—
—
CWG1IE
192
PIE9
—
—
SMT2PWAIE
SMT2PRAIE
SMT2IE
SMT1PWAIE
SMT1PRAIE
SMT1IE
192
STATUS
—
—
—
TO
PD
Z
DC
C
120
VREGCON
—
—
—
—
—
—
VREGPM
Reserved
61
CPUDOZE
IDLEN
DOZEN
ROI
DOE
—
DOZE<2:0>
62
WDTCON0
—
—
WDTPS<4:0>
SEN
82
WDTCON1
—
WDTPS<2:0>
—
WINDOW<2:0>
83
Note
1:
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
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Preliminary
DS40001841B-page 64
PIC18(L)F67K40
7.0
PERIPHERAL MODULE
DISABLE (PMD)
Sleep, Idle and Doze modes allow users to
substantially reduce power consumption by slowing or
stopping the CPU clock. Even so, peripheral modules
still remain clocked, and thus, consume some amount
of power. There may be cases where the application
needs what these modes do not provide: the ability to
allocate limited power resources to the CPU while
eliminating power consumption from the peripherals.
The
PIC18(L)F6xK40
family
addresses
this
requirement by allowing peripheral modules to be
selectively enabled or disabled, placing them into the
lowest possible power mode.
For legacy reasons, all modules are ON by default
following any Reset.
7.1
Disabling a Module
Disabling a module has the following effects:
• All clock and control inputs to the module are
suspended; there are no logic transitions, and the
module will not function.
• The module is held in Reset.
• Any SFR becomes “unimplemented”
- Writing is disabled
- Reading returns 00h
• I/O functionality is prioritized as per Section 15.1,
I/O Priorities
• All associated Input Selection registers are also
disabled
7.2
Enabling a Module
When the PMD register bit is cleared, the module is
re-enabled and will be in its Reset state (Power-on
Reset). SFR data will reflect the POR Reset values.
Depending on the module, it may take up to one full
instruction cycle for the module to become active.
There should be no interaction with the module
(e.g., writing to registers) for at least one instruction
after it has been re-enabled.
7.3
Effects of a Reset
Following any Reset, each control bit is set to ‘0’,
enabling all modules.
7.4
System Clock Disable
Setting SYSCMD (PMD0, Register 7-1) disables the
system clock (FOSC) distribution network to the
peripherals. Not all peripherals make use of SYSCLK,
so not all peripherals are affected. Refer to the specific
peripheral description to see if it will be affected by this
bit.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 65
PIC18(L)F67K40
7.5
Register Definitions: Peripheral Module Disable
REGISTER 7-1:
PMD0: PMD CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SYSCMD
FVRMD
HLVDMD
CRCMD
SCANMD
NVMMD
CLKRMD
IOCMD
7
0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SYSCMD: Disable Peripheral System Clock Network bit(1)
See description in Section 7.4 “System Clock Disable”.
1 = System clock network disabled (FOSC)
0 = System clock network enabled
bit 6
FVRMD: Disable Fixed Voltage Reference bit
1 = FVR module disabled
0 = FVR module enabled
bit 5
HLVDMD: Disable Low-Voltage Detect bit
1 = HLVD module disabled
0 = HLVD module enabled
bit 4
CRCMD: Disable CRC Engine bit
1 = CRC module disabled
0 = CRC module enabled
bit 3
SCANMD: Disable NVM Memory Scanner bit(2)
1 = NVM Memory Scan module disabled
0 = NVM Memory Scan module enabled
bit 2
NVMMD: NVM Module Disable bit(3)
1 = All Memory reading and writing is disabled; NVMCON registers cannot be written
0 = NVM module enabled
bit 1
CLKRMD: Disable Clock Reference bit
1 = CLKR module disabled
0 = CLKR module enabled
bit 0
IOCMD: Disable Interrupt-on-Change bit, All Ports
1 = IOC module(s) disabled
0 = IOC module(s) enabled
Note 1:
Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked
by FOSC/4 are not affected.
2:
Subject to SCANE bit in CONFIG4H.
3:
When enabling NVM, a delay of up to 1 µs may be required before accessing data.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 66
PIC18(L)F67K40
REGISTER 7-2:
PMD1: PMD CONTROL REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR7MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
TMR7MD: Disable Timer TMR7 bit
1 = TMR7 module disabled
0 = TMR7 module enabled
bit 6
TMR6MD: Disable Timer TMR6 bit
1 = TMR6 module disabled
0 = TMR6 module enabled
bit 5
TMR5MD: Disable Timer TMR5 bit
1 = TMR5 module disabled
0 = TMR5 module enabled
bit 4
TMR4MD: Disable Timer TMR4 bit
1 = TMR4 module disabled
0 = TMR4 module enabled
bit 3
TMR3MD: Disable Timer TMR3 bit
1 = TMR3 module disabled
0 = TMR3 module enabled
bit 2
TMR2MD: Disable Timer TMR2 bit
1 = TMR2 module disabled
0 = TMR2 module enabled
bit 1
TMR1MD: Disable Timer TMR1 bit
1 = TMR1 module disabled
0 = TMR1 module enabled
bit 0
TMR0MD: Disable Timer TMR0 bit
1 = TMR0 module disabled
0 = TMR0 module enabled
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 67
PIC18(L)F67K40
REGISTER 7-3:
PMD2: PMD CONTROL REGISTER 2
U-0
U-0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
CWGMD
—
DSMMD
SMT2MD
SMT1MD
TMR8MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5
CWGMD: Disable CWG bit
1 = CWG module disabled
0 = CWG module enabled
bit 4
Unimplemented: Read as ‘0’
bit 3
DSMMD: Disable Comparator DSM bit
1 = DSM module disabled
0 = DSM module enabled
bit 2
SMT2MD: Disable Comparator SMT2 bit
1 = SMT2 module disabled
0 = SMT2 module enabled
bit 1
SMT1MD: Disable Comparator SMT1 bit
1 = SMT1 module disabled
0 = SMT1 module enabled
bit 0
TMR8MD: Disable Comparator TMR8 bit
1 = TMR8 module disabled
0 = TMR8 module enabled
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 68
PIC18(L)F67K40
REGISTER 7-4:
PMD3: PMD CONTROL REGISTER 3
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
DACMD
ADCMD
—
CMP3MD
CMP2MD
CMP1MD
ZCDMD(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6
DACMD: Disable DAC bit
1 = DAC module disabled
0 = DAC module enabled
bit 5
ADCMD: Disable ADC bit
1 = ADC module disabled
0 = ADC module enabled
bit 4
Unimplemented: Read as ‘0’
bit 3
CMP3MD: Disable Comparator C3 bit
1 = C3 module disabled
0 = C3 module enabled
bit 2
CMP2MD: Disable Comparator C2 bit
1 = C2 module disabled
0 = C2 module enabled
bit 1
CMP1MD: Disable Comparator C1 bit
1 = C1 module disabled
0 = C1 module enabled
bit 0
ZCDMD: Disable ZCD bit(1)
1 = ZCD module disabled
0 = ZCD module enabled
Note 1:
Subject to ZCD bit in CONFIG2H.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 69
PIC18(L)F67K40
REGISTER 7-5:
PMD4: PMD CONTROL REGISTER 4
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
PWM7MD
PWM6MD
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6
PWM7MD: Disable PWM7 Module bit
1 = PWM7 module disabled
0 = PWM7 module enabled
bit 5
PWM6MD: Disable PWM6 Module bit
1 = PWM6 module disabled
0 = PWM6 module enabled
bit 4
CCP5MD: Disable CCP5 Module bit
1 = CCP5 module disabled
0 = CCP5 module enabled
bit 3
CCP4MD: Disable CCP4 Module bit
1 = CCP4 module disabled
0 = CCP4 module enabled
bit 2
CCP3MD: Disable CCP3 Module bit
1 = CCP3 module disabled
0 = CCP3 module enabled
bit 1
CCP2MD: Disable CCP2 Module bit
1 = CCP2 module disabled
0 = CCP2 module enabled
bit 0
CCP1MD: Disable CCP1 Module bit
1 = CCP1 module disabled
0 = CCP1 module enabled
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 70
PIC18(L)F67K40
REGISTER 7-6:
PMD5: PMD CONTROL REGISTER 5
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
USART5MD
USART4MD
USART3MD
USART2MD
USART1MD
MSSP2MD
MSSP1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6
USART5MD: Disable USART5 Module bit
1 = USART5 module disabled
0 = USART5 module enabled
bit 5
USART4MD: Disable USART4 Module bit
1 = USART4 module disabled
0 = USART4 module enabled
bit 4
USART3MD: Disable USART3 Module bit
1 = USART3 module disabled
0 = USART3 module enabled
bit 3
USART2MD: Disable USART2 Module bit
1 = USART2 module disabled
0 = USART2 module enabled
bit 2
USART1MD: Disable USART4 Module bit
1 = USART1 module disabled
0 = USART1 module enabled
bit 1
MSSP2MD: Disable MSSP2 Module bit
1 = MSSP2 module disabled
0 = MSSP2 module enabled
bit 0
MSSP1MD: Disable MSSP1 Module bit
1 = MSSP1 module disabled
0 = MSSP1 module enabled
TABLE 7-1:
SUMMARY OF REGISTERS ASSOCIATED WITH PMD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
PMD0
SYSCMD
FVRMD
HLVDMD
CRCMD
SCANMD
NVMMD
CLKRMD
IOCMD
65
PMD1
TMR7MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
66
PMD2
—
—
CWGMD
—
DSMMD
SMT2MD
SMT1MD
TMR8MD
67
PMD3
—
DACMD
ADCMD
—
CMP3MD
CMP2MD
CMP1MD
ZCDMD
68
PMD4
—
PWM7MD
PWM6MD
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
69
PMD5
—
USART5MD
USART4MD USART3MD USART2MD USART1MD
MSSP2MD
MSSP1MD
70
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used by the PMD.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 71
PIC18(L)F67K40
8.0
RESETS
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 8-1.
FIGURE 8-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Device
Reset
Power-on
Reset
WWDT Time-out/
Window voilation
Brown-out
Reset(1)
LPBOR
Reset
RESET Instruction
MCLRE
PWRTE
LFINTOSC
VDD
ICSP™ Programming Mode Exit
Stack Underflow
Stack Overflow
R
Power-up
Timer
Rev. 10-000006E
5/11/2016
VPP/MCLR
Note
1:
See Table 8-1 for BOR active conditions.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 72
PIC18(L)F67K40
FIGURE 8-2:
LPBOR, BOR, POR RELATIONSHIP
8.1
Register Definitions: BOR Control
REGISTER 8-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
U-0
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
—
—
—
—
—
—
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SBOREN: Software Brown-out Reset Enable bit
If BOREN 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN = 01:
1 =
BOR Enabled
0 =
BOR Disabled
bit 6-1
Unimplemented: Read as ‘0’
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset Circuit is active and armed
0 = The Brown-out Reset Circuit is disabled or is warming up
Reset
POR
logic
LPBOR
To PCON
indicator bit
BOR
BOR Event
REARM POR
Event
POR Event
LPBOR Event
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 73
PIC18(L)F67K40
8.2
Register Definitions: Power Control
REGISTER 8-2:
PCON0: POWER CONTROL REGISTER 0
R/W/HS-0/q
R/W/HS-0/q
R/W/HC-1/q
R/W/HC-1/q R/W/HC-1/q
R/W/HC-1/q
R/W/HC-0/u
R/W/HC-q/u
STKOVF
STKUNF
WDTWV
RWDT
RMCLR
RI
POR
BOR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
STKOVF: Stack Overflow Flag bit
1 =
A Stack Overflow occurred (more CALLs than fit on the stack)
0 =
A Stack Overflow has not occurred or set to ‘0’ by firmware
bit 6
STKUNF: Stack Underflow Flag bit
1 =
A Stack Underflow occurred (more RETURNs than CALLs)
0 =
A Stack Underflow has not occurred or set to ‘0’ by firmware
bit 5
WDTWV: Watchdog Window Violation bit
1 =
A WDT window violation has not occurred or set to ‘1’ by firmware
0 =
A CLRWDT instruction was issued when the WDT Reset window was closed (set to ‘0’ in hardware
when a WDT window violation Reset occurs)
bit 4
RWDT: WDT Reset Flag bit
1 =
A WDT overflow/time-out Reset has not occurred or set to ‘1’ by firmware
0 =
A WDT overflow/time-out Reset has occurred (set to ‘0’ in hardware when a WDT Reset occurs)
bit 3
RMCLR: MCLR Reset Flag bit
1 =
A MCLR Reset has not occurred or set to ‘1’ by firmware
0 =
A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
bit 2
RI: RESET Instruction Flag bit
1 =
A RESET instruction has not been executed or set to ‘1’ by firmware
0 =
A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET
instruction)
bit 1
POR: Power-on Reset Status bit
1 =
No Power-on Reset occurred or set to ‘1’ by firmware
0 =
A Power-on Reset occurred (set to ‘0’ in hardware when a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 =
No Brown-out Reset occurred or set to ‘1’ by firmware
0 =
A Brown-out Reset occurred (set to ‘0’ in hardware when a Brown-out Reset occurs)
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Preliminary
DS40001841B-page 74
PIC18(L)F67K40
8.3
Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
8.4
Brown-out Reset (BOR)
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in
Configuration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to Table 8-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV<1:0> bits in Configuration
Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter TBORDC, the device
will reset. See Table 37-11 for more information.
8.4.1
BOR IS ALWAYS ON
When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
8.4.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
8.4.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or
the VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
8.4.4
BOR AND BULK ERASE
BOR is forced ON during PFM Bulk Erase operations
to make sure that the system code protection cannot be
compromised by reducing VDD.
During Bulk Erase, the BOR is enabled at 2.45V for F
and LF devices, even if it is configured to some other
value. If VDD falls, the erase cycle will be aborted, but
the device will not be reset.
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Preliminary
DS40001841B-page 75
PIC18(L)F67K40
FIGURE 8-3:
BROWN-OUT SITUATIONS
TABLE 8-1:
BOR OPERATING MODES
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
Instruction Execution upon:
Release of POR
Wake-up from Sleep
11
X
X
Active
Wait for release of BOR
(BORRDY = 1)
Begins immediately
10
X
Awake
Active
Wait for release of BOR
(BORRDY = 1)
N/A
Sleep
Hibernate
N/A
Wait for release of BOR
(BORRDY = 1)
01
1
X
Active
Wait for release of BOR
(BORRDY = 1)
Begins immediately
0
X
Hibernate
00
X
X
Disabled
Begins immediately
TPWRT(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset
TPWRT(1)
< TPWRT
TPWRT(1)
VBOR
VDD
Internal
Reset
Note 1:
TPWRT delay only if PWRTE bit is programmed to ‘0’.
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Preliminary
DS40001841B-page 76
PIC18(L)F67K40
8.5
Low-Power Brown-out Reset
(LPBOR)
The Low-Power Brown-out Reset (LPBOR) provides
an additional BOR circuit for low power operation.
Refer to Figure 8-2 to see how the BOR interacts with
other modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset.
8.5.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOREN bit of
Configuration Word 2L. When the device is erased, the
LPBOR module defaults to disabled.
8.5.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal, which goes
to the PCON0 register and to the power control block.
8.6
MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 8-2). The RMCLR bit in the
PCON0 register will be set to ‘0’ if a MCLR has
occurred.
8.6.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
8.6.2
MCLR DISABLED
When MCLR is disabled, the MCLR becomes
input-only and pin functions such as internal weak
pull-ups are under software control. See Section 15.1
“I/O Priorities” for more information.
8.7
Windowed Watchdog Timer
(WWDT) Reset
The Windowed Watchdog Timer generates a Reset if
the firmware does not issue a CLRWDT instruction
within the time-out period or window set. The TO and
PD bits in the STATUS register and the RWDT bit in the
PCON0 register are changed to indicate a WDT Reset.
The WDTWV bit in the PCON0 register indicates if the
WDT Reset has occurred due to a time out or a window
violation. See Section 9.0 “Windowed Watchdog
Timer (WWDT)” for more information.
8.8
RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON0 register will be set to ‘0’. See Table 8-3
for default conditions after a RESET instruction has
occurred.
8.9
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the
PCON0 register indicate the Reset condition. These
Resets are enabled by setting the STVREN bit in
Configuration Words. See Section 10.2.1 “Stack
Overflow and Underflow Resets” for more information.
8.10
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
8.11
Power-up Timer (PWRT)
The Power-up Timer provides a nominal 66 ms (2048
cycles of LFINTOSC) time out on POR or Brown-out
Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00000607).
TABLE 8-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
x
1
Enabled
1
0
Enabled
0
0
Disabled
Note:
An internal Reset event (RESET, instr,
BOR, WWDT, POR STK), does not drive
the MCLR pin low.
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Preliminary
DS40001841B-page 77
PIC18(L)F67K40
8.12
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
Power-up Timer runs to completion (if enabled).
2.
Oscillator start-up timer runs to completion (if
required for selected oscillator source).
3.
MCLR must be released (if enabled).
The total time out will vary based on oscillator
configuration and Power-up Timer configuration. See
Section 4.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
Start-up Timer will expire. Upon bringing MCLR high,
the device will begin execution after 10 FOSC cycles
(see Figure 8-4). This is useful for testing purposes or
to synchronize more than one device operating in
parallel.
FIGURE 8-4:
RESET START-UP SEQUENCE
TOST
TMCLR
TPWRT
VDD
Internal POR
Power-up Timer
MCLR
Internal RESET
Oscillator Modes
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
External Crystal
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Preliminary
DS40001841B-page 78
PIC18(L)F67K40
8.13
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON0 registers are updated to indicate the cause of
the Reset. Table 8-3 shows the Reset conditions of
these registers.
TABLE 8-3:
RESET CONDITION FOR SPECIAL REGISTERS
Condition
Program
Counter
STATUS
Register(2,3)
PCON0
Register
Power-on Reset
0
-110 0000
0011 110x
Brown-out Reset
0
-110 0000
0011 11u0
MCLR Reset during normal operation
0
-uuu uuuu
uuuu 0uuu
MCLR Reset during Sleep
0
-10u uuuu
uuuu 0uuu
WDT Time-out Reset
0
-0uu uuuu
uuu0 uuuu
WDT Wake-up from Sleep
PC + 2
-00u uuuu
uuuu uuuu
WWDT Window Violation Reset
0
-uuu uuuu
uu0u uuuu
Interrupt Wake-up from Sleep
PC + 2(1)
-10u 0uuu
uuuu uuuu
RESET Instruction Executed
0
-uuu uuuu
uuuu u0uu
Stack Overflow Reset (STVREN = 1)
0
-uuu uuuu
1uuu uuuu
Stack Underflow Reset (STVREN = 1)
0
-uuu uuuu
u1uu uuuu
Legend:
u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.
Note 1:
When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set the return address is
pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high
or low priority) after execution of PC + 2.
2:
If a Status bit is not implemented, that bit will be read as ‘0’.
3:
Status bits Z, C, DC are reset by POR/BOR (Register 10-2).
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 79
PIC18(L)F67K40
8.14
Power Control (PCON0) Register
The Power Control (PCON0) register contains flag bits
to differentiate between a:
• Brown-out Reset (BOR)
• Power-on Reset (POR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Watchdog Window Violation (WDTWV)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON0 register bits are shown in Register 8-2.
Hardware will change the corresponding register bit
during the Reset process; if the Reset was not caused
by the condition, the bit remains unchanged
(Table 8-3).
Software should reset the bit to the inactive state after
restart (hardware will not reset the bit).
Software may also set any PCON0 bit to the active
state, so that user code may be tested, but no Reset
action will be generated.
TABLE 8-4:
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
—
—
—
—
—
—
BORRDY
72
PCON0
STKOVF
STKUNF
WDTWV
RWDT
RMCLR
RI
POR
BOR
73
STATUS
—
TO
PD
N
OV
Z
DC
C
120
WDTCON0
—
—
WDTPS<4:0>
SEN
82
WDTCON1
—
WDTCS<2:0>
—
WINDOW<2:0>
83
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 80
PIC18(L)F67K40
9.0
WINDOWED WATCHDOG
TIMER (WWDT)
The Watchdog Timer (WDT) is a system timer that
generates a Reset if the firmware does not issue a
CLRWDT instruction within the time-out period. The
Watchdog Timer is typically used to recover the system
from unexpected events. The Windowed Watchdog
Timer (WWDT) differs in that CLRWDT instructions are
only accepted when they are performed within a
specific window during the time-out period.
The WWDT has the following features:
• Selectable clock source
• Multiple operating modes
- WWDT is always on
- WWDT is off when in Sleep
- WWDT is controlled by software
- WWDT is always off
• Configurable time-out period is from 1 ms to 256s
(nominal)
• Configurable window size from 12.5% to 100% of
the time-out period
• Multiple Reset conditions
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2016 Microchip Technology Inc.
Preliminary
DS40001841B-page 81
PIC18(L)F67K40
FIGURE 9-1:
WINDOWED WATCHDOG TIMER BLOCK DIAGRAM
Rev. 10-000 162A
1/2/201 4
WINDOW
CLRWDT
RESET
WDT Time-out
WDT
Window
Violation
PS
5-bit
WDT Counter
Overflow
Latch
18-bit Prescale
Counter
000
011
010
001
100
101
110
111
Reserved
Reserved
Reserved
Reserved
Reserved
626&
MFINTOSC/16
LFINTOSC
R
R
CS
WWDT
Armed
Window
Sizes
Comparator
Window Closed
E
WDTE<1:0> = 01
WDTE<1:0> = 11
WDTE<1:0> = 10
SEN
Sleep
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Preliminary
DS40001841B-page 82
PIC18(L)F67K40
9.1
Register Definitions: Windowed Watchdog Timer Control
REGISTER 9-1:
WDTCON0: WATCHDOG TIMER CONTROL REGISTER 0
U-0
U-0
R/W(3)-q/q(2)
R/W(3)-q/q(2)
R/W(3)-q/q(2)
R/W(3)-q/q(2)
R/W(3)-q/q(2)
R/W-0/0
—
—
WDTPS<4:0>
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
WDTPS<4:0>: Watchdog Timer Prescale Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0
SEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.
Note 1:
Times are approximate. WDT time is based on 31 kHz LFINTOSC.
2:
When WDTCPS <4:0> in CONFIG3L = 11111, the Reset value of WDTPS<4:0> is 01011. Otherwise, the
Reset value of WDTPS<4:0> is equal to WDTCPS<4:0> in CONFIG3L.
3:
When WDTCPS <4:0> in CONFIG3L ≠ 11111, these bits are read-only.
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Preliminary
DS40001841B-page 83
PIC18(L)F67K40
REGISTER 9-2:
WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1
U-0
R/W(3)-q/q(1) R/W(3)-q/q(1) R/W(3)-q/q(1)
U-0
R/W(4)-q/q(2)
R/W(4)-q/q(2)
R/W(4)-q/q(2)
—
WDTCS<2:0>
—
WINDOW<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6-4
WDTCS<2:0>: Watchdog Timer Clock Select bits
111 = Reserved
•
•
•
010 = Reserved
001 = MFINTOSC 31.25 kHz
000 = LFINTOSC 31 kHz
bit 3
Unimplemented: Read as ‘0’
bit 2-0
WINDOW<2:0>: Watchdog Timer Window Select bits
Note 1:
If WDTCCS <2:0> in CONFIG3H = 111, the Reset value of WDTCS<2:0> is 000.
2:
The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3H
register.
3:
If WDTCCS<2:0> in CONFIG3H ≠ 111, these bits are read-only.
4:
If WDTCWS<2:0> in CONFIG3H ≠ 111, these bits are read-only.
WINDOW<2:0>
Window delay
Percent of time
Window opening
Percent of time
111
N/A
100
110
12.5
87.5
101
25
75
100
37.5
62.5
011
50
50
010
62.5
37.5
001
75
25
000
87.5
12.5
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Preliminary
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PIC18(L)F67K40
REGISTER 9-3:
WDTPSL: WWDT PRESCALE SELECT LOW BYTE REGISTER (READ-ONLY)
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
PSCNT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PSCNT<7:0>: Prescale Select Low Byte bits(1)
Note 1:
The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal
operation.
REGISTER 9-4:
WDTPSH: WWDT PRESCALE SELECT HIGH BYTE REGISTER (READ-ONLY)
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
PSCNT<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PSCNT<15:8>: Prescale Select High Byte bits(1)
Note 1:
The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal
operation.
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Preliminary
DS40001841B-page 85
PIC18(L)F67K40
REGISTER 9-5:
WDTTMR: WDT TIMER REGISTER (READ-ONLY)
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
WDTTMR<4:0>
STATE
PSCNT<17:16>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
WDTTMR<4:0>: Watchdog Window Value bits
bit 2
STATE: WDT Armed Status bit
1 = WDT is armed
0 = WDT is not armed
bit 1-0
PSCNT<17:16>: Prescale Select Upper Byte bits(1)
Note 1:
The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal
operation.
WINDOW
WDT Window State
Open Percent
Closed
Open
111
N/A
00000-11111
100
110
00000-00011
00100-11111
87.5
101
00000-00111
01000-11111
75
100
00000-01011
01100-11111
62.5
011
00000-01111
10000-11111
50
010
00000-10011
10100-11111
37.5
001
00000-10111
11000-11111
25
000
00000-11011
11100-11111
12.5
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Preliminary
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9.2
Independent Clock Source
The WWDT can derive its time base from either the
31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal
oscillators, depending on the value of WDTE<1:0>
Configuration bits.
If WDTE = 2'b1x, then the clock source will be
enabled
depending
on
the
WDTCCS<2:0>
Configuration bits.
If WDTE = 2'b01, the SEN bit should be set by
software to enable WWDT, and the clock source is
enabled by the WDTCS bits in the WDTCON1 register.
Time intervals in this chapter are based on a minimum
nominal interval of 1 ms. See Section 37.0 “Electrical
Specifications” for LFINTOSC and MFINTOSC
tolerances.
9.3
WWDT Operating Modes
The Windowed Watchdog Timer module has four
operating modes controlled by the WDTE<1:0> bits in
Configuration Words. See Table 9-1.
9.3.1
WWDT IS ALWAYS ON
When the WDTE bits of Configuration Words are set to
‘11’, the WWDT is always on.
WWDT protection is active during Sleep.
9.3.2
WWDT IS OFF IN SLEEP
When the WDTE bits of Configuration Words are set to
‘10’, the WWDT is on, except in Sleep.
WWDT protection is not active during Sleep.
9.3.3
WWDT CONTROLLED BY
SOFTWARE
When the WDTE bits of Configuration Words are set to
‘01’, the WWDT is controlled by the SEN bit of the
WDTCON0 register.
WWDT protection is unchanged by Sleep. See
Table 9-1 for more details.
9.4
Time-out Period
If the WDTCPS<4:0> Configuration bits default to
5'b11111, then the WDTPS bits of the WDTCON0
register set the time-out period from 1 ms to
256 seconds (nominal). If any value other than the
default
value
is
assigned
to
WDTCPS<4:0>
Configuration bits, then the timer period will be based
on the WDTCPS<4:0> bits in the CONFIG3L register.
After a Reset, the default time-out period is 2s.
9.5
Watchdog Window
The Windowed Watchdog Timer has an optional
Windowed
mode
that
is
controlled
by
the
WDTCWS<2:0> Configuration bits and WINDOW<2:0>
bits of the WDTCON1 register. In the Windowed mode,
the CLRWDT instruction must occur within the allowed
window of the WDT period. Any CLRWDT instruction that
occurs outside of this window will trigger a window
violation and will cause a WWDT Reset, similar to a
WWDT time out. See Figure 9-2 for an example.
The window size is controlled by the WINDOW<2:0>
Configuration bits, or the WINDOW<2:0> bits of
WDTCON1, if WDTCWS<2:0> = 111.
The five Most Significant bits of the WDTTMR register
are used to determine whether the window is open, as
defined by the WINDOW<2:0> bits of the WDTCON1
register.
In the event of a window violation, a Reset will be
generated and the WDTWV bit of the PCON0 register
will be cleared. This bit is set by a POR or can be set in
firmware.
9.6
Clearing the WWDT
The WWDT is cleared when any of the following
conditions occur:
• Any Reset
• Valid CLRWDT instruction is executed
• Device enters Sleep
• Exit Sleep by Interrupt
• WWDT is disabled
• Oscillator Start-up Timer (OST) is running
• Any write to the WDTCON0 or WDTCON1
registers
9.6.1
CLRWDT CONSIDERATIONS
(WINDOWED MODE)
When in Windowed mode, the WWDT must be armed
before a CLRWDT instruction will clear the timer. This is
performed by reading the WDTCON0 register.
Executing a CLRWDT instruction without performing
such an arming action will trigger a window violation
regardless of whether the window is open or not.
See Table 9-2 for more information.
TABLE 9-1:
WWDT OPERATING MODES
WDTE<1:0>
SEN
Device
Mode
WWDT
Mode
11
X
X
Active
10
X
Awake
Active
Sleep
Disabled
01
1
X
Active
0
X
Disabled
00
X
X
Disabled
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Preliminary
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PIC18(L)F67K40
9.7
Operation During Sleep
When the device enters Sleep, the WWDT is cleared.
If the WWDT is enabled during Sleep, the WWDT
resumes counting. When the device exits Sleep, the
WWDT is cleared again.
The WWDT remains clear until the Oscillator Start-up
Timer (OST) completes, if enabled. See Section
4.3.1.3 “Oscillator Start-up Timer (OST)” for more
information on the OST.
When a WWDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON0 register can also be
used. See Section 10.0 “Memory Organization” for
more information.
FIGURE 9-2:
WINDOW PERIOD AND DELAY
TABLE 9-2:
WWDT CLEARING CONDITIONS
Conditions
WWDT
WDTE<1:0> = 00
Cleared
WDTE<1:0> = 01 and SEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
Change INTOSC divider (IRCF bits)
Unaffected
Rev. 10-000 163A
11/8/201 3
Window Period
CLRWDT Instruction
(or other WDT reset)
Window Delay
(window violation can occur)
Window Closed
Window Open
Time-out Event
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TABLE 9-3:
SUMMARY OF REGISTERS ASSOCIATED WITH WINDOWED WATCHDOG TIMER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PCON0
STKOVF
STKUNF
WDTWV
RWDT
RMCLR
RI
POR
BOR
73
STATUS
—
—
—
TO
PD
Z
DC
C
120
WDTCON0
—
—
WDTPS<4:0>
SEN
82
WDTCON1
—
WDTCS<2:0>
—
WINDOW<2:0>
83
WDTPSL
PSCNT<7:0>
84
WDTPSH
PSCNT<15:8>
84
WDTTMR
WDTTMR<4:0>
STATE
PSCNT<17:16>
85
Legend:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Windowed Watchdog Timer.
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Preliminary
DS40001841B-page 89
PIC18(L)F67K40
10.0
MEMORY ORGANIZATION
There are three types of memory in PIC18 enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate buses; this allows for
concurrent access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Program Flash Memory and Data EEPROM Memory is
provided in Section 11.0 “Nonvolatile Memory
(NVM) Control”.
10.1
Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2 Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2 Mbyte address will return all ‘0’s (a
NOP instruction).
These devices contains the following:
• PIC18(L)F67K40: 128 Kbytes of Flash memory, up
to 65,536 single-word instructions
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
Note:
For memory information on this family of
devices, see Table 10-1 and Table 10-2.
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Preliminary
DS40001841B-page 90
PIC18(L)F67K40
TABLE 10-1:
PROGRAM AND DATA EEPROM MEMORY MAP
PIC18(L)F65K40
PIC18(L)F66K40
PIC18(L)F67K40
PC<21:0>
PC<21:0>
PC<21:0>
Note 1
Stack (31 levels)
Stack (31 levels)
Stack (31 levels)
Note 1
00 0000h
Reset Vector
Reset Vector
Reset Vector
00 0000h
• • •
• • •
• • •
• • •
• • •
00 0008h
Interrupt Vector High
Interrupt Vector High
Interrupt Vector High
00 0008h
• • •
• • •
• • •
• • •
• • •
00 0018h
Interrupt Vector Low
Interrupt Vector Low
Interrupt Vector Low
00 0018h
00 001Ah
•
00 3FFFh
Program Flash Memory
(16 KW)
Program Flash Memory
(32 KW)
Program Flash Memory
(64 KW)
00 001Ah
•
00 3FFFh
00 4000h
•
00 7FFFh
00 4000h
•
00 7FFFh
00 8000h
•
00 FFFFh
Not present(2)
00 8000h
•
00 FFFFh
01 0000h
•
01 FFFFh
Not present(2)
01 0000h
•
01 FFFFh
02 0000h
•
1F FFFFh
Not present(2)
02 0000h
•
1F FFFFh
20 0000h
• • •
20 000Fh
User IDs (8 Words)(3)
20 0000h
• • •
20 000Fh
20 0010h
• • •
2F FFFFh
Reserved
20 0010h
• • •
2F FFFFh
30 0000h
• • •
30 000Bh
Configuration Words (6 Words)(3)
30 0000h
• • •
30 000Bh
30 000Ch
• • •
30 FFFFh
Reserved
30 000Ch
• • •
30 FFFFh
31 0000h
DataEEByte0
• • •
DataEEByte1023
31 0000h
• • •
31 00FFh
• • •
• • •
31 03FFh
• • •
31 03FFh
31 0400h
• • •
3F FFFBh
Reserved
31 0400h
• • •
3F FFFBh
3F FFFCh
• • •
3F FFFDh
Revision ID (1 Word)(4)
3F FFFCh
• • •
3F FFFDh
3F FFFEh
• • •
3F FFFFh
Device ID (1 Word)(4)
3F FFFEh
• • •
3F FFFFh
Note
1:
The stack is a separate SRAM panel, apart from all user memory panels.
2:
The addresses do not roll over. The region is read as ‘0’.
3:
Not code-protected.
4:
Device/Revision IDs are hard-coded in silicon.
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Preliminary
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PIC18(L)F67K40
TABLE 10-2:
MEMORY MAP AND CODE PROTECTION CONTROL
Reg.
Address
(from/to)
Device
PIC18(L)F65K40
PIC18(L)F66K40
PIC18(L)F67K40
PFM
00 0000h
Boot Block 1 KW
CP, WRTB, EBTRB
Boot Block 1 KW
CP WRTB, EBTRB
Boot Block 1 KW
CP WRTB, EBTRB
00 07FFh
00 0800h
Block 0
3 KW
CP, WRT0, EBTR0
Block 0
7 KW
CP, WRT0, EBTR0
Block 0
7 KW
CP, WRT0, EBTR0
00 1FFFh
00 2000h
Block 1
4 KW
CP, WRT1, EBTR1
00 3FFFh
00 4000h
Block 2
4 KW
CP, WRT2, EBTR2
Block 1
8 KW
CP, WRT1, EBTR1
Block 1
8 KW
CP, WRT1, EBTR1
00 5FFFh
00 6000h
Block 3
4 KW
CP, WRT3, EBTR3
00 7FFFh
00 8000h
Not present
Block 2
8 KW
CP, WRT2, EBTR2
Block 2
8 KW
CP, WRT2, EBTR2
00 BFFFh
00 C000h
Block 3
8 KW
CP, WRT3, EBTR3
Block 3
8 KW
CP, WRT3, EBTR3
00 FFFFh
01 0000h
Not present
Block 4
8 KW
CP, WRT4, EBTR4
01 3FFFh
01 4000h
Block 5
8 KW
CP, WRT5, EBTR5
01 7FFFh
01 8000h
Block 6
8 KW
CP, WRT6, EBTR6
01 BFFFh
01 C000h
Block 7
8 KW
CP, WRT7, EBTR7
01 FFFFh
CONFIG
30 0000h
6 Words
WRTC
30 000Bh
Data EEPROM
31 0000h
1 KW
CPD, WRTD
31 00FFh
31 0100h
31 03FFh
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PIC18(L)F67K40
10.1.1
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 10.2.3.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by two to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
10.1.2
RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is Acknowledged.
The PC value is pulled off the stack on a RETURN,
RETLW or a RETFIE instruction. PCLATU and PCLATH
are not affected by any of the RETURN or CALL
instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, or as a 35-word by 21-bit RAM with
a 6-bit Stack Pointer in ICD mode. The stack space is
not part of either program or data space. The Stack
Pointer is readable and writable and the address on the
top of the stack is readable and writable through the
Top-of-Stack (TOS) Special File registers. Data can
also be pushed to, or popped from the stack, using
these registers.
A CALL type instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits in the PCON0 register
indicate if the stack is full or has overflowed or has
underflowed.
10.1.2.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is readable
and writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the
STKPTR register (Figure 10-1). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU:TOSH:TOSL registers. These
values can be placed on a user defined software stack. At
return time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the Global Interrupt Enable (GIE)
bits while accessing the stack to prevent inadvertent
stack corruption.
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Preliminary
DS40001841B-page 93
PIC18(L)F67K40
FIGURE 10-1:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
10.1.2.2
Return Stack Pointer (STKPTR)
The STKPTR register (Register 10-1) contains the
Stack Pointer value. The STKOVF (Stack Overflow)
Status bit and the STKUNF (Stack Underflow) Status bit
can be accessed using the PCON0 register. The value
of the Stack Pointer can be 0 through 31. On Reset, the
Stack Pointer value will be zero. The user may read and
write the Stack Pointer value. This feature can be used
by a Real-Time Operating System (RTOS) for stack
maintenance. After the PC is pushed onto the stack 32
times (without popping any values off the stack), the
STKOVF bit is set. The STKOVF bit is cleared by soft-
ware or by a POR. The action that takes place when the
stack becomes full depends on the state of the
STVREN (Stack Overflow Reset Enable) Configuration
bit. (Refer to Section 3.1 “Configuration Words” for
a description of the device Configuration bits.)
If STVREN is set (default), a Reset will be generated
and a Stack Overflow will be indicated by the STKOVF
bit when the 32nd push is initiated. This includes CALL
and CALLW instructions, as well as stacking the return
address during an interrupt response. The STKOVF bit
will remain set and the Stack Pointer will be set to zero.
If STVREN is cleared, the STKOVF bit will be set on the
32nd push and the Stack Pointer will remain at 31 but
no Reset will occur. Any additional pushes will
overwrite the 31st push but the STKPTR will remain at
31.
Setting STKOVF = 1 in software will change the bit, but
will not generate a Reset.
The STKUNF bit is set when a stack pop returns a
value of zero. The STKUNF bit is cleared by software
or by POR. The action that takes place when the stack
becomes full depends on the state of the STVREN
(Stack Overflow Reset Enable) Configuration bit.
(Refer to Section 3.1 “Configuration Words” for a
description of the device Configuration bits.)
If STVREN is set (default) and the stack has been
popped enough times to unload the stack, the next pop
will return a value of zero to the PC, it will set the
STKUNF bit and a Reset will be generated. This
condition can be generated by the RETURN, RETLW and
RETFIE instructions.
If STVREN is cleared, the STKUNF bit will be set, but
no Reset will occur.
When STVREN = 0, STKUNF will be set but no Reset
will occur.
10.1.2.3
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-of-Stack
000D58h
TOSL
TOSH
TOSU
34h
1Ah
00h
STKPTR<4:0>
Top-of-Stack Registers
Stack Pointer
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
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Preliminary
DS40001841B-page 94
PIC18(L)F67K40
10.2
Register Definitions: Stack Pointer
10.2.1
STACK OVERFLOW AND
UNDERFLOW RESETS
Device Resets on Stack Overflow and Stack Underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a Full
or Underflow condition will set the appropriate STKOVF
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a Full or Underflow condition will
set the appropriate STKOVF or STKUNF bit but not
cause a device Reset. The STKOVF or STKUNF bits
are cleared by the user software or a Power-on Reset.
10.2.2
FAST REGISTER STACK
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All inter-
rupt sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers by software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be used
to restore the STATUS, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the fast register stack. A
RETURN, FAST instruction is then executed to restore
these registers from the fast register stack.
Example 10-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 10-1:
FAST REGISTER STACK
CODE EXAMPLE
REGISTER 10-1:
STKPTR: STACK POINTER REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
STKPTR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented
C = Clearable only bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
STKPTR<4:0>: Stack Pointer Location bits
Note:
The TO and PD bits of the STATUS regis-
ter are not copied over in this operation.
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN, FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
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Preliminary
DS40001841B-page 95
PIC18(L)F67K40
10.2.3
LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
10.2.3.1
Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 10-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of two (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 10-2:
COMPUTED GOTO USING
AN OFFSET VALUE
10.2.3.2
Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the data that is read from or written to program
memory. Data is transferred to or from program
memory one byte at a time.
Table read and table write operations are discussed
further in Section 11.1.1 “Table Reads and Table
Writes”.
MOVF
OFFSET, W
CALL
TABLE
ORG
nn00h
TABLE
ADDWF
PCL
RETLW
nnh
RETLW
nnh
RETLW
nnh
.
.
.
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Preliminary
DS40001841B-page 96
PIC18(L)F67K40
10.3
PIC18 Instruction Cycle
10.3.1
CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
instruction register during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 10-2.
10.3.2
INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 10-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 10-2:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 10-3:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC
PC + 2
PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. BRA SUB_1
Fetch 3
Execute 3
4. BSF PORTA, BIT3 (Forced NOP)
Fetch 4
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
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Preliminary
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PIC18(L)F67K40
10.3.3
INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instructions are stored as either two bytes or four bytes
in program memory. The Least Significant Byte of an
instruction word is always stored in a program memory
location with an even address (LSb = 0). To maintain
alignment
with instruction boundaries, the PC
increments in steps of two and the LSb will always read
‘0’ (see Section 10.1.1 “Program Counter”).
Figure 10-3 shows an example of how instruction
words are stored in the program memory.
The CALL and GOTO instructions have the absolute
program
memory
address
embedded
into
the
instruction. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 10-3 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 36.0 “Instruction Set Summary”
provides further details of the instruction set.
10.3.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LFSR. In all
cases, the second word of the instruction always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 10-4 shows how this works.
FIGURE 10-3:
INSTRUCTIONS IN PROGRAM MEMORY
EXAMPLE 10-4:
TWO-WORD INSTRUCTIONS
Note:
See Section 10.8 “PIC18 Instruction
Execution and the Extended Instruc-
tion Set” for information on two-word
instructions in the extended instruction set.
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, skip this word
1111 0100 0101 0110
; Execute this word as a NOP
0010 0100 0000 0000
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes, execute this word
1111 0100 0101 0110
; 2nd word of instruction
0010 0100 0000 0000
ADDWF
REG3
; continue code
Word Address
LSB = 1
LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
Instruction 1:
MOVLW
055h
0Fh
55h
000008h
Instruction 2:
GOTO
0006h
EFh
03h
00000Ah
F0h
00h
00000Ch
Instruction 3:
MOVFF
123h, 456h
C1h
23h
00000Eh
F4h
56h
000010h
000012h
000014h
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Preliminary
DS40001841B-page 98
PIC18(L)F67K40
10.4
Data Memory Organization
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. Figure 10-4
shows the data memory organization for the
PIC18(L)F6xK40 devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the Bank
Select Register (BSR). Section 10.4.2 “Access
Bank” provides a detailed description of the Access
RAM.
10.4.1
BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the four Most Significant bits of
a location’s address; the instruction itself includes the
eight Least Significant bits. Only the four lower bits of
the BSR are implemented (BSR<3:0>). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory; the eight bits in the instruction show the
location in the bank and can be thought of as an offset
from the bank’s lower boundary. The relationship
between the BSR’s value and the bank division in data
memory is shown in Figure 10-4.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh will end up resetting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory maps in
Figure 10-4 indicate which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
Note:
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 10.7 “Data Memory and the
Extended Instruction Set” for more
information.
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Preliminary
DS40001841B-page 99
PIC18(L)F67K40
FIGURE 10-4:
DATA MEMORY MAP FOR PIC18(L)F6XK40 DEVICES
Bank
BSR<3:0>
addr<7:0>
PIC18(L)F65K40 PIC18(L)F66K40
PIC18(L)F67K40
Address
addr<11:0>
Bank 0
0000
00h
Access RAM
Access RAM
000h
05Fh
GPR
GPR
060h
FFh
0FFh
Bank 1
0001
00h
GPR
GPR
100h
FFh
•
•
•
Bank 2
0010
00h
FFh
Bank 3
0011
00h
FFh
3FFh
Banks
4 to 7
0100
—
0111
00h
GPR
GPR
400h
•
•
•
FFh
7FFh
Banks
8 to 13
1000
—
1101
00h
Unimplemented
GPR
800h
•
•
•
DE9h
•
DFFh
SFR
SFR
FFh
Bank 14
1110
00h
SFR(1)
SFR
E00h
FFh
EFFh
Bank 15
1111
00h
SFR
SFR
F00h
F5Fh
F60h
FFh
FFFh
Virtual Bank
Access RAM
00h
5Fh
SFR
60h
FFh
Note 1:
It depends on the number of SFRs. Refer to Table 10-3 and Table 10-4.
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Preliminary
DS40001841B-page 100
PIC18(L)F67K40
FIGURE 10-5:
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Note
1:
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2:
The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
7
0
From Opcode(2)
0
0
0
0
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0
0
1
0
1
1
1
1
1
1
1
1
7
0
BSR(1)
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