Tektronix 7D01 Instruction Manual

PLEASE CHECK FOR CHANGE INFORMATION A""I""O"H REAR OF THIS MANUAL. C ANALYZER (Serial No. 802rdOQQ and up) WITH OPTIONS INSTRUCTION MANUAL Tektronix, Inc. P.O. Box 500 Beaverton, Oregon 9'7077 070-2206-02 Product Group 57 Serial Number - _.---__---______. . First Printing OCT 1976 Revised OCT 1982

Rochester, MN 55902 "High resolution scans of obsolete technical manuals" If your looking for a quality scanned technical manual in PDF format please visit our WEB site at www.artekmedia.com or drop us an email at [email protected] and we will be happy to email you a current list of the manuals we have available. If you don't see the manual you need on the tist drop us a tine anyway we may still be able to point you to other sources. If you have an existing manual you would like scanned please write for details, This can often be done very reasonably in consideration for adding your manual to our library. Typically the scans in our manuals are done as follows; I) Typed text pages are typically scanned in black and white at 300 dpi. 2) Photo pages are typically scanned in gray scale mode at 600 dpi 3) Schematic diagram pages are typiwlly scanned in b tack and white at 600 dpi unless the original manual had colored high lighting (as is the case for some 70's vintage TeMronix manuals). If you purchased this manual from us (typically through our Ebay name of ArtekMedia) thank you very much. If you received this from a well-meaning "friend" for free we would appreciate your treating this much like you would "share ware". By that we mean a donation of at least $5-10 per manual is appreciated in recognition of the time (a manual can take as much as 40 hours to reproduce, book, link etc.), energy and qualrty of effort that went into preserving this manual. Donations via PayPal go to: -. - - r n a n u a l s ~ ~ i ~ l ~ c o r n 7 - - or can be mailed to us the address above. T anks Dave 8 Lynn Henderson Artek Media

reserved. Contents of this publication may not be reproduced in any form without the written permission of Tektronix, Inc. Products of Tektronix, Inc. and its subsidiaries are covered by U.S. and foreign patents and/or pending patents. TEKTRONIX, T EK, SCOPL-MOBILE, and are registered tradernarks of "l ektronix, Inc. TELEQUI P- MENT' is a registered trademark of l'ektronix U.K. Limited. Printed in U.S.A. Specification and price change privileges are reserved.

TABLE OF CONTENTS LIST' OF ILLUS^I'RATIONS . . . . . . . . . . . . . . . . . . . LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . SAFETY SUMMARY . . . . . . . . . . . . . . . . . . . . . . SECTION 1 GENERAL INFORMATION INTRODUCTION . . . . . . . . . . . . . . . . . . . . . GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INSTALLATION . . . . . . . . . . . . . PACKAGING FOR SHIPMENT SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . S I ANDARD ACCESSORIES . . . . . . . . . . . . . . . . . SECTION 2 OPERATING INSTRUCTIONS PAGE PAGE FRONT PANEL CONTROLS. CONNECTORS AND INDICATORS . . . . . . . . . . . . 2-1 DETAILED OPERATING INFORMATION . . . . . . . . . . 2-1 . . . . . . . . . . . . . . . . . AUXILIARY FUNCTIONS 2-1 IN TkHNAL STRAP SELECTIONS . . . . . . . . . . . . 2-4 SlGNALCONNtCTlONS . . . . . . . . . . . . . . . . . . 2-6 DISPLAYING DATA . . . . . . . . . . . . . . . . . . . . . 2-7 TRIGGERING . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 CLOCK QUALIFIER OPERATION . . . . . . . . . . . . 2-8 ASYNCHRONOUS AND SYNCHRONOUS DATA SAMPLING . . . . . . . . . . . . . . . . . . . . . . 2-9 OPERATIONAL ANALYSIS . . . . . . . . . . . . . . . . 2.10 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 2.13 INTHODUCTION . . . . . . . . . . . . . . . . . . . . . . 2.13 FAULT IDENTIFICAI'ION . . . . . . . . . . . . . . . . 2.13 DELAY BY WORDS . . . . . . . . . . . . . . . . . . . . . 2.13 DELAY BY EVEN I'S . . . . . . . . . . . . . . . . . . . . . 2.14 STATE rABLE AND MAPPING DISPLAYS . . . . . . 2.14 MICROPHOCESSOR ANALYSIS . . . . . . . . . . . . . . 2.16 STORAGE BUFFER ANALYSIS . . . . . . . . . . . . . . 2.17 FUNCTIONAL CHECK . . . . . . . . . . . . . . . . . 2.17 W A R N I N G . . . II SECTION 3 THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . 1 1 BLOCK DIAGRAM DESCRIPTION 3.1 . . . . . . . . . . . . . . 111 DE I AILED CIRCUIT DESCRIPTION 3.3 . . . FRONT PANEL WIRING . . . . . . . . . . . . . . . . . . . 3.3 . . . . . . . . . . . . . . . . . . . . . WORD RECOGNIZER 3.3 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMORY 3-4 . . . 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRIGGER 3-7 . . . 1.1 TIME BASE 3.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 . . . . . . . . . . . . . . . . . . . . . VER rlCAL OUTPUT 3.9 . . . 1.3 HORIZONI-AL OUTPU r . . . . . . . . . . . . . . . . . . 3.10 . . . 1.9 CURSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 . . . POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . 3.12 SECTION 4 MAINTENANCE PREVENTIVE MAINTENANCE . . . . . . . . . . . . . . . . . 4.1 CLEANING . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 VISUAL INSPECTION . . . . . . . . . . . . . . . . . . . . . 4.1 LUBRICATION . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 SEMICONDUC OR CHECKS . . . . . . . . . . . . . . . . . 4.2 TROUBLESHOO'TING . . . . . . . . . . . . . . . . . . . . . . . 4.3 . . . . . . . . . . . . lHOUBLESHOOTlNG EQUIPMEhT 4.3 THOUBLESHOOTING TECHNIQUES . . . . . . . . . . . 4.3 CORRECTIVE MAINTENANCE . . . . . . . . . . . . . . . . . 4.7 . . . . . . . . . . . OBTAINING REPLACEMENT PARTS 4.7 . . . . . . . . . . . . . . . . . SOLDERING TECHNIQUES 4.7 COMPONENT REMOVAL AND REPLACEMENT . . . . . 4.8 ADJUSTMENT AFTER REPAIR . . . . . . . . . . . . . . 4.14 SECTION 5 PERFORMANCE CHECK AND ADJUSTMENT PRELIMINARY INFORMATION . . . . . . . . . . . . . . 5.1 . . . . . . . . . . . . . . . TEST EQUIPMEN'T REQUIRED 5.1 . . . . . . . . . . . . . . . . PRELIMINARY PROCEDURE 5.3 PERFORMANCE CHECK AND ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . PROCEDURE 5-5 SECTION 6 REPLACEABLE ELECTRICAL PARTS SECTION 7 INSTRUMENT OPTIONS THE REMAINING PORTION OF "THIS I ABLE OF CON- SECTION 8 DIAGRAMS AND ClpCUlT BOARD TENTS LISTS THE SERVICING INSTRUCTIONS . THESE ILLUSTRATIONS SERVICING INSIRUCTIONS ARE FOR USE BY QUALI- ON REPLACEABLE MECHANICAL PARTS FlED PERSONNEL ONLY . TO AVOID ELECTRICAL SHOCK. DO NOT PERFORM ANY SERVICING OTHER THAN THAT CALLED OUT IN THE OPERATING IN- ST RUCTIONS UNLESS BIJALIFIED TO DO SO . CHANGE INFORMATION REV C JUN 1980

LIST OF ILLUSTRATIONS FIGURE NO. Frontis. piece 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-1 0 2-1 1 2-1 2 3- 1 3-2 3-3 TABLE NO. FIGURE PAGE NO. ' PAGE 7001 Logic Analyzer. . . . . . . . . . . . . . . . . . . .iv 7D01 Dimensional Drawing . . . . . . . . . . . . . . .I-8 Front-panel controls, connectors, and indicators . . . . . . . . . . . . . . . . . . . . . . . . .2-2 Internal Display Clock Source and Full DisplayIFirst Trigger Selectors. . . . . . . . . . .2-4 l nternal Signal Selector. . . . . . . . . . . . . . . . . .2-5 Pin assignments for Data Out connector J120 . . . . . . . . . . . . . . . . . . . . . .2-6 Suggested methods for terminating data outputs from Data Out connector J120 . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7 Suggested method for assembling a remote Manual Reset button . . . . . . . . . . . . . .2-7 Typical channel 0 to 15 pretrigger data display . . . . . . . . . . . . . . . . . . . . . . . .2-8 Equipment setup and displays for finding a data fault and examining it on an analog display . . . . . . . . . . . . . . . . . .2-14 Equipment setup and data display window that has been positioned after a preselected word has occurred 25 times . . . . . .2-15 Equipment setup and display window that has been positioned after 10,500 clock pulses have occurred. . . . . . . . . . . . . . .2-15 Typical setup for troubleshooting a microprocessor system . . . . . . . . . . . . . . . . . 2-1 6 Typical setup and display for trouble- shooting a storage buffer. . . . . . . . . . . . . . . . 2-1 7 7D01 Block Diagram . . . . . . . . . . . . . . . . . . .3-2 Equivalent circuit for one channel of P6451 Data Acquisition Probe . . . . . . . . . . . . .3-3 Truth Table for StoreIDisplay Clock Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5 Latch Clock timing for 4-channel . . . . . . . . . . . . . . . . . . . . . . . . operation. .3-5 Latch Clock timing for 8-channel operation. . . . . . . . . . . . . . . . . . . . . . . . . .3-6 Memory Selector timing for 4-channel . . . . . . . . . . . . . operation (display time only) .3-6 Memory Selector timing for 8-channel operation (display time only) .3-6 -. . . . . . . . . . . . . . Binary output of U628 versus channel displayed. . . . . . . . . . . . . . . . . . . . . . . . . .3-9 Lubrication procedure for a typical cam . . . . . . . . . . . . . . . . . . . . . . . . . . switch .4-2 - . . . . . . . . . . . . . . . . Circuit board locations. .4-5 Power supply +5 volt test point location. . . . . . . .4-6 Location of securing screws on the Memory circuit board . . . . . . . . . . . . . . . . . .4-8 Multi-pin connector and P number orientation for the Memory circuit board . . . . . . .4-9 Location of securing screws on the . . . . . . . . . . . . . . . . . Interface circuit board 4-10 Locations of securing screws on the . . . . . . . . . . . . . . . . . . Output circuit board 4-10 Locations of securing screws and shield . . . . . . . . . . . . . . on the Power Supply board 4-1 1 Locations of securing screws on the Cursor circuit board . . . . . . . . . . . . . . . . . . 4-1 1 - Locations of hex nuts and screws on front sub panel which secure the Word Recog- . . . . . . . . . . . . . . . . . . . nizer circuit board 4-1 2 Exploded view of circuit-board pin -. and ferrule. . . . . . . . . . . . . . . . . . . . . . . .4-14 The illustrations in Section 8 are located near their associated Diagrams on the foldout pages. LIST OF TABLES TABLE PAGE NO. PAGE 1-1 Electrical Characteristics. . . . . . . . . . . . . . . . . .I-3 2-3 Operational Analysis . . . . . . . . . . . . . . . . . . . 2-10 1-2 Environmental Characteristics. . . . . . . . . . . . . . .l-8 4-1 Power Supply Tolerances . . . . . . . . . . . . . . . . .4-6 1-3 Physical Characteristics. . . . . . . . . . . . . . . . . . . l - 8 5-1 Test Equipment. . . . . . . . . . . . . . . . . . . . . . .5-1 2-1 Format Output Levels . . . . . . . . . . . . . . . . . . .2-1 7-1 Option Information Locator. . . . . . . . . . . . . . . .7-1 2-2 Minimum Clock Pulses Required to Display - Data (After the MANUAL RESET Button is Pressed) . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9 REV. A, MAR 1977

SAFETY SUMMARY The following safety information is provided to ensure safe operation of this instrument. WARNING information is intended to protect the operator; CAUTION information is intended to protect the instrument. i he following are general safety pre- cautions that must be observed during all phases of operation and maintenance. Ground the Instrument To reduce electrical-shock hazard, the mainframe (oscilloscope) chassis must be properly grounded. Refer to the mainframe manual for grounding information. Do Not Operate in Explosive Atmosphere Do not operate this instrument in an area where flammable gases or fumes are present. Such operation could cause an explosion. Avoid Live Circuits Electrical-shock hazards are present in this instrument. The protective instrument covers must not be removed by operating personnel. Component replacement and internal adjustments must be referred to qualified service personnel. Do Not Service or Adjust Alone Do not service or make internal adjustments to this instrument unless another person, capable of giving first aid and resusci- ta tion, is present.

7D01 FEATURES The 7D01 Logic Analyzer will store and display up to 16 channels of digital data when installed in a 7000-series mainframe. - The cursor function provides an intensified zone on the data display, and a corresponding numerical readout display shows the logic state (1 or 0) for each displayed channel of data. The positlon of the cursor, relative to the trlgger, is also displayed on the crt readout. Cursor readout is displayed in either 3-bit or 4-bit bytes. - Digital data can be stored in 3 formats: 4 channels a t 1016 bitslchannel, 8 channels at 508 bitslchannel, or 16 channels at 254 bitslchannel. The sample rate is selectable from 10 nanoseconds to 5 milliseconds/sample (in a 5-2-1 sequence) when - using the internal time base, or can be used with an external clock signal (up to 50 megahertz). The 7D01 can be triggered from 4 sources: channel 0 data, an external signal, a bullt-in 16-channel word recognlzer, or man- ually. Phe triggered data can be produced following the trigger (POST TRIG), centered around the trlgger (CENTER), or pre- - ceedlng the trigger (PRE TRIG). The input threshold can be varied from minus 12 volts to plus 12 volts, or set to plus 1.4 volts for TI-L logic levels. - The Word Recognizer produces an output when the logic states of the 16 input data channels match the states of the corres- ponding Word Recognizer switches. "Two qualifier inputs are also provided to enable the Word Recognizer output. The Word Recognizer operates in either the synchronous or asynchronous mode. A variable filter (to at least 300 nanoseconds) allows .- rejection of brief false-trigger signals.

7D01 FEATURES The 7D01 Logic Analyzer will store and display up to 16 channels of digital data when installed in a 7000-series mainframe. The cursor function provides an intensified zone on the data display, and a corresponding numerical readout display shows the logic state (1 or 0) for each displayed channel of data. The position of the cursor, relative to the trigger, i s also displayed on the crt readout. Cursor readout is displayed in either 3-bit or 4-bit bytes. Digital data can be stored in 3 formats: 4 channels at 1016 bitdchannel, 8 channels at 508 bitslchannel, or 16 channels at 254 bitslchannel. I^he sample rate is selectable from 10 nanoseconds to 5 millisecondslsample (in a 5-2-1 sequence) when using the internal time base, or can be used with an external clock signal (up to 50 megahertz). The 7001 can be triggered from 4 sources: channel 0 data, an external signal, a built-in 16-channel word recognizer, or man- ually. The triggered data can be produced following the trigger (POST- I"HIG), centered around the trigger (CENTER), or pre- ceeding the trigger (PRE TRIG). The input threshold can be varied from minus 12 volts to plus 12 volts, or set to plus 1.4 volts for TTL logic levels. The Word Recognizer produces an output when the logic states of the 16 input data channels match the states of the corres- ponding Word Recognizer switches. Two qualifier inputs are also provided to enable the Word Recognizer output. The Word Recognizer operates in either the synchronous or asynchronous mode. A variable filter (to at least 300 nanoseconds) allows rejection of brief false-trigger signals. REV B, JAN 1979

GENERAL INFORMATION I N T R O D U C T I O N 7DOl Operator's Manual Parity Bits--"Bits added to the data stream which enable the receiver to verify whether the data is correctly or incor- rectl y received. - I'he Operator's manual contains the information necessary to operate the 7D01 Logic Analyzer. The manual is divided PROM-Programmable Read Only Memory. into three sections, each covering a specific topic of the instrument. Section 1 provides a basic description of the RAM-Random Access Memory. 7D01, a glossary of logic terms, installation instructions, Serial Data -Data transferred on a single line. Serial data and specifications. Sectiorl 2 contains operating information logic is derived in a sequential mode. for the instrument. Information concerning available op- tions for the 7D01 is on a tabbed page in Section 3. Store Clock-'l'he clock used to store information into the 7D01 memory. 71901 Instruction Manual Synchronous-Digital information transferred with the The Instruction manual provides operating and servicing same clock reference. information for the 7D01 Logic Analyzer. I'he manual is . ~ divided into ten sections. Operating information is covered in the first two sections; servicing information is contained in the remaining eight sections of the manual. Schematics - are located a t the rear of the manual and can be unfolded and used for reference while reading other parts of the manual. The reference designators and symbols used on the schematics are defined on the first page of the Diagrams section. Abbreviations used in the manuals, except in the parts list and schematics, comply with the American National Standards Institute Y1.l-1972 publication. 'The parts lists are computer printouts and use computer- supplied abbreviations. Threshold Voltage-.-The comparator input voltage on the inverting input, which is used as a reference. Thus, if the signal on the non-inverting input is above the threshold voltage, the output is HI; if the signal is below the threshold voltage, the output is LO. TTL-.-Transistor-Transistor Logic. "Wired-OR"-ECL gate outputs that are connected together to yield the equivalent output of an OR gate. ! INSTALLATION \i GLOSSARY /' [-he terms l~sted in this glossary are used throughout this manual. Asynchronous-- Multiple digital information transferred at non-common clock rates. - Bit-The smallest increment of digital information. CPU.-Central Processing Unit. - ECL Emitter-Coupled Logic. Jit.ter - A form of d~stort~on In asynchronous systems that IS due to tlm~ng varlatlons of the rece~ved data. Multiplexing--The combining of multiple inputs into a - single output. Parallel-to-Serial Conversion-The technique of storing a - digital pattern from a parallel bus, then transferring that pattern out to a serial bus. REV OCT 1982 The 7D01 is calibrated and ready to use when received. It is designed to occupy a vertical and horizontal plug-in corn- ',. partment in all 7000-series mainframes with readout except \ the 7104, which may suffer crt damage that will not be cov- 1 ered by the instrument warranty, and the Digital Processing Oscilloscope (DPO), which will not digitize the 7D01 out- puts. There are some operating modes, however, that will not provide proper operation. l'hese modes are discussed under Displaying Data in Section 2. Install the 7D01 in the two conipartments on the right side of a three-compartment mainframe, or in the right vertical and A horizontal compart- nt mainframe. NOTE Some rackmounted mainframes have vertically ' \ mounted rods in front of the plug-in compart- ments that interfere with the installation of the 700 1. Detach these rods by removing the mount- ing screws at each end before installing the 7001.

To install the 7D01 in the mainframe, align the 7D01 tracks with the rails of a vertical and horizontal plug-in compart- ment. Gently slide the 7D01 into the mainframe and push firmly to lock the 7D01 front panel flush with the mainframe. To remove the 7DO1, grasp the release latch in the lower left corner and pull the 7D01 out of the mainframe. PACKAGING FOR SHIPMENT If this instrument is to be shipped for long distances by commercial transportation, it is recommended that the instrument be packaged in the original manner for maxi- mum protection. 'The carton and packing material in which your inslrument was shipped should be saved and used for this purpose. If the original packaging is unfit for use or not available, package the instrument as follows: 1. Obtain a carton of corrugated cardboard with at least a 200 pound test strength and inside dimensions of no less than six inches more than the instrument dimensions; this will allow for cushioning. 2. Surround the instrument with polyethylene sheeting to protect the finish of the instrument. 3. Cushion the instrument on all sides by tightly packing dunnage or urethane foam between the carton and the instrument, allowing three inches on all sides. 4. Seal the carton with shipping tape or an industrial stapler. Also, if this instrument is to be shipped to a rektronix - Service Center for service or repair, attach a tag to the instrument showing the following: Owner of the instru- ment (with address), the name of an individual at your firm - that can be contacted, complete instrument type and serial number, and a description of the service required. Mark the address of the 1 ektronix Service Center, and your return address, on the carton in one or more prominent locations. - REV. A, MAR 1977 -

The electrical specifications listed in "Table 1-1 apply when the following conditions are met: (1) The instrument must have been adjusted at an ambient temperatyre betwezn +20° and +30° C (+68' and t86' F), (2) the instrument must be operating in an ambient temperature between 0 and +40 C (+32' and +104" F), and (3) the instrument must have been operating for at least 20 minutes. TABLE 1-1 Electrical Characteristics aractertstic - - - - 1. - - -- - -- CLOCKANDDATA I N P U ~ S Probe Inputs (Clock, Oual~f~er, and Data) lnput R and C - -- - - - - - - -- . -- - 1 ~ a w ~ t h ~ n 5%, paralleled by approx 5 pF. - - - - -- I hreshold Voltage VAR (at Mon~tor Jack) -- - 12 V or less, to at least +I2 V - - 1 1 L - - - - - - -" - -- Mtn~mum Logic Sw~ng 500 mV plus 2% of threshold voltage p p or less, centered on threshold voltage - Ma threshold Maximum Non-Destructive Input Voltage 1 60 V or less, to at least +60 V. External Clock Minimum Clock Period t 20 ns or less. - - - - -- -- - . --- . - - - 20 ns or less. CH 0 15 40 ns or less. -- - - - - M ~ n ~ m u m Clock Pulse W~dth HI Level LO Level 1- - . _ - CH 0-3 I 10 ns or less I 10 ns or less CH 0-7 I 10 ns or less I 10 ns or less CH 0-15 1 20 ns or less 1 20 ns or less Minimum Data Setup rime CH 0-3 20 ns or less. CH 0-7 ( 20 ns or less. CH Minim - Clock Oualrfier 1 P6451 Probe Setup Time t Hold f ime -- -- - - - -- -- - -- - -- 20 ns 0 ns External Input (measured at external 1 1 input connector) I I 1 ns REV OCT 1982

TABLE 1-1 (CONT.) Electrical Characteristics --- 1 Characteristic Performance Requirement ." "" .- -" -- -- - CLOCK AND DATA INPUTS (CONT.) Internal Clock Minimum Sample Interval CH 0-3 CH 0-7 "- - - CH 0-15 50 ns or less. Minimum Data Pulse Width (to Ensure Recording) 1 1 sample interval plus 5 ns or less. INTERNAL CLOCK TRIGGER CH 0 I Triggers on rising edge of CH 0 data. Trigger Sources External TrigIOualifier lnput I - Threshold 11.4 V within 0.2 V ( l L L Level). --- Minimum Pulse Width 15 ns or less. - Max Safe Input Voltage 5 V or less, to at least +I0 V. - Word Recognizer 16 Data inputs, Probe Qualifier, and External Qualifier. Output is true when input conditions match switch settings - (H I, X, LO). -..----.-~.,--.-..w-.-----w Minimum lnput Pulse Width (Asynchronous Mode) I Any Single Channel 1 10 ns or less. Channels 0-3 15 ns or less. -. " " " " .... .""... Any Other Combination 20 ns or less. Filter 1 Contin~ously variable to at least 300 ns. Synchronous Mode Coincidence of matching combination and an external clock - edge must occur for recognition. Minimum Setup Time -----I- 12.5 ns or less. .- - --- Minimum Hold Time 8.5 ns or less. "" -. h -. " -. . " . .. REV OCT 1982

TABLE 1-1 (CONT.) Electrical Characteristics - - -- -- ,--- - ---me--- I -- Characteristic -.p.--e'.---- Performance Requirement .- --,--.----.-* p-. C."" ".*"A , . . . a . w. P ---....----,-- "--- ---"" --**--,-- "- ..--*.."--""."",---- --em.-" TRIGGER (CONT.) - Word Recognizer Output Voltage HI least +I .9 V (0.95 V into 50-a load). .". L 0 .1 V or less (50 mV into 5042 load). Outl~ut Impedance (Rising Edge) I 50 a, within 10%. Full DisplayIFirst Trigger Mode Selection electable by internal jumper, P617. - " ",."-", Full Display Mode II horizontal display. ,--.- -. First 7 rigger Mode 1 Accepts the first trigger after reset. ---- -. --- -- --" - - .-- - ----- -- -- -- ----- ---- ------.--" -.... -- DISPLAY ",--*."*-- _ Vertical Magnify I X I to at least X5. Position Positions magnified display within graticule area. -- "~ """ ~ -------.. Horizontal Magnify I X I to at least X9. Position ons magnified display within graticule area. Display Length in X I Mag (With Full Data) .. -- ""------ Raster Shift With Format Change 1 div or less at X I mag. " .". *"." "-" Manual Reset Resets to store mode when button is pushed. -- Display Format Selectable by DATA CHANNELS switch: """ ." "--"- Ch 0-3 x 1016 BitsICh 1 group of 4 traces. - --- Display Time Range Ch 0-7 x 508 BitsICh 1 2 groups of 4 traces each. Approximately 1 sec to 10 sec, followed by reset; or infinite hold. Ch 0-15 x 254 BitsICh s of 4 traces each. - ""---- """ Blanking Time -"".--*" ---- ". .. .- -- Ch 0-3 8 bits. --.-- "- -" I "" ~--'----- Ch 0-7 4 bits. "."--- .. "- --- -em". .- ------ Ch 0-15 2 bits. REV. A, MAR 1977 1-5

TABLE 1-1 (CONT.) Electrical Characteristics -. "-- ' -.-. .." -. -- Characteristic Performance Requirement -- -" -" - - . -- -- ----- - - --- - DISPLAY (CONT.) -- - - '-*- -- - - -1- ----r-- Cursor Cursor Position Control ntensified zone to any displayed bit, in incre- bit or 16 bits. ---- Readout Cursor Position Data Byte Switch Trigger Intensified Zone Position (Relative to Displayed Trigger Event) Top right-hand readout shows cursor position (in sample relative to trigger (e.g., TRIG + xxx). "-- "- -*---- -I Bottom readout shows the logic state of each displayed channel at the cursor (Hi = 1; Lo = 0). ""--- ---- Breaks data readout into 3-bit or 4-bit bytes. In 16 channels and 3-bit bytes, the left hand group remains 4 bits. lected by data position switch. "-"---, 10 nslsample I "l.ypically within 4 bits. 20 ns/Sarnple I-ypically within 3 bits. "-- - - - - - -- 50 ns to 5 msISample I_ Within 1 bit. ~ - -- DATA OUT .rm"- Data Out Connector J120" I Parallel Data Out Serial Data Out Pin 4 Serial data from memory, non-inverted. p p p - - ~ w m p ~ ~ .- ----" Channel Sequence: CH 0-3 1 2-3-0-1 -2, etc. . . ... .. ... . . . . . . . CH 0-7 CH 0-15 -1 3- 14- 15-8-9-1 0- 1 1-4-5-6-7-0-1 -2, etc. "" ", 'All logic levels are ECL levels unless otherwise specified. REV C, JAN 1979

TABLE 1-1 (CONT.) Electrical Characteristics ." Characteristic Performance Requirement ...... ... . . - " ~ ~ L = i - - . - - -" ..... - - - - - DATA OUT (CONT.) " - . ..-.. T-------- Data Out Connector J120x (Cont.) Frame Output Pin 16. Falling edge indicates end of Ch 2; rising edge indicates end of Ch 3. Frame occurs every 16th sweep 'ndependent of format). -.. Flag Output in-1 4 Falling edge indicates end of channel; rising edge ~ndicates beginning of channel. "-" - Record Enable Pin 15 HI lnput forces reset. HI output occurs when RESET 1s pressed. - - - - - -- - - - - -- -- - - - - - "- External Display Clock Input .. " -- Frequency Range . " .. " ... Ground "- -.- Signal Select Jumper P300 Pin 3, terminated with 100 fi to 2 V. - . " .,.. -...--- Less than 1 Hz to at least 2 MHz. -- t- 1 Pin 17. Pins 1, 2, and 5 of J120 are connected to pins 7, 8, and 6, respectively of the Signal Select Jumper. There are 5 signals available to the Signal Select Jumper. Format Output Pins 1 and 2 of Signal Select Jumper: " ----.-.--.-...-,u.~....-- . .- Pin 1 I Pin 2 " " - . -" "" - Ch 0-3 . . . Hi Hi Ch 0-7 Hi Lo """ Ch 0-15 LO L o ... .- DisplayIStore Output Pin 3 of the Signal Select Jumper: "." " ."".. " . Store Hi ".. " . - ". .. - Display L o Trigger Intensify Output Pin 4 of Signal Select Jumper, LO = intensified trigger point on display. Master Reset Output Pin 5 of Signal Select Jumper, HI during reset. - POWER SUPPLY "-.- - Line Voltage Ranges -- - -- - - - " Internal Power Suppl~es 4.8 Volt Accuracy ( 4 20" to +30° C) measured at 1 P 112 on memory board. -- - - - - - -2.0 Volt Refer to 7000-series oscilloscope performance requirements. Within 4.80 V to -4.975 V. Accuracy (+20° to +30° C) "" ~ Within 0.2 V. *All logic levels are ECL levels unless otherwise specified. REV OCT 1982

TABLE 1-2 Environmental Characteristics . . "" -. Characteristic Performance Requirement - --- - "-" - - -- - -*-- -"----- - -- -- --*- "- -- -a - - ---" - Temperature I Operating Storage .. - Altitude Operating To 15,000 feet. ---" " -- -- - Storage To 50,000 feet. Quallfled under National Safe 7rans1t Comm~ttee 1 est - Transportatron Procedure I A , Category 11. - -- - " I- - - - -- TABLE 1-3 Physical Characteristics Characteristic Description - -w,--.--.-.--... "" "m"-~""..."~~""-.-.~---.""~""~.."~-.""-.--"--.-.""* - - - I - Welght (Wlthout Accessories) Approx~mately 4.4 Ibs (2.0 kg). -- -- - -- ---- - - *"." Dimensions ~..- "- "" .,,, " " ~e "". NOTE I - DIMENSIONS ARE GIVEN WITH TOP FIGURE I N INCHES AND BOTTOM FIGURE I N CENTIMETERS. -.-" Figure 1-1. 7D01 Dimensional Drawing. - REV. A, MAR 1977 -

STANDARD ACCESSORIES . . . . . . . . . . . . . . . . . . . . . . . . 1 ea Instruction Manual . . . . . . . . . . . . . . . . . . . . . . . . 1 ea Operator's Manual . . . . . . . . . . . . . . . . . . . . . . 2 ea P6451 Probe Package For more information, refer to the tabbed Accessories page in the back of this manual.

OPERATING INSTRUCTIONS This section includes a description of the 7D01 front-panel controls, connectors, and indicators. Also included is detailed operating information, some basic application procedures and a functional check procedure. Refer to Section 1, General Information, for a glossary of terms and installation instructions. FRONT-PANEL CONTROLS, CONNECTORS, AND INDICATORS Refer to Detailed Operating Information for a discussion of the auxiliary functions available with the internal selectors, ^]-he location and function of the front-panel controls, and the input and output signals available through the Data connectors, and indicators are illustrated in Figure 2-1. Out connector. DETAILED OPERATING INFOWMAVON AUXl LlARY FUNC'TIONS Several auxiliary functions can be selected by connectors and jumpers located inside the 7D01. A 25-pin Data Out connector is also located inside the 7D01 to provide various input and output signals for use with external equipment. The following information describes the auxiliary functions with procedures for making the appropriate internal connections. Display Clock Source Selector (P835) Two-pin jumper which determines whettler the 7D01 is to be used for display only, or for display and data output (serial and parallel data at the Data Out connector). When the 7D01 is used for data displays, P835 must be set to Internal Display Clock (see Fig. 2-2). When the 7D01 is to be used for display and data output (serial and parallel), P835 must be set to External Display Clock (see Fig. 2-2) and an external display clock signal must be applied to pin 3 of Data Out connector J120 to synchronize the data out- put. "The rate per bit of the serial and parallel output data is determined by the rate of the external display clock signal applied to pin 3 of Data Out connector J120. If a display is desired, as well as serial and parallel data, the external dis- play clock signal repetition rate must be approximately 2 microseconds. The internal display clock signal is not available as an output. Full DisplayIFirst Trigger Selector (P617) Two-pin jumper which determines whether data is displayed at the first acceptable trigger after the memory has addres- sed one full block of data, or whether data is displayed after the first acceptable trigger. REV. A, MAR 1977 - When P617 IS set to Full Display (see Fig. 2-2), the memory stores one complete block of data and then accepts the next trigger. The Full Display position is recommended for most repetitive signal applications. If a trigger is expected soon after a reset pulse, or if the wait between displays at slow sample rates is objectionable, P617 can be set to the First Trigger position (see Fig. 2-2). Refer to Synchronous and Asyr~chronous Data Sampling for more information. Signal Selector (P300) Internal multi-pin connector P300 provides 5 signals for connection to 3 outputs on Data Out connector J120. Any 3 of the 5 signals can be used for external use. Figure 2-3 shows the location of P300, and identifies the pin assign- ments as they are connected when shipped from thefactory. To change signal outputs at J120, move the jumper connec- tions at P300 (refer to Fig's. 2-3 and 2-4). FORMAT OUTPUT. Two outputs (P300 pins 1 and 2) provide ECL-level outputs which indicate the channel selected by the front-panel DATA CHANNELS switch. Table 2-1 shows the ECL levels at pins 1 and 2 of P300 for each position of the DATA CHANNELS switch. TABLE 2-1 Format Output Levels DATA CHANNELS - - -- ....

DATA OUT LOGIC ANALYZER TEKTRONIXO 1 E X T CLOCK POLARITY Switch-Selects the active edge o f the external clock signal applied t o the C (clock) input o f thechannel 0-7 Data input connector. 2 SAMPLE I N T E R V A L Switch-Selects thedata input sample rate. Sample ratesfrom 5 milliseconds t o 1 0 nanoseconds are provided 0 in a 5-2-1 sequence. A lamp behind the knob skirt blinks when the sample rate is t o o fast for 8-channel operation (10 nanosecond) or 16-channel (10 o r 2 0 nanosecond) sample intervals. When set t o the EXT position, the C (clock) input is selected. TheSAMPLE I N T E R V A L lamp does not blink when operating i n the E X T position. L.-"-. ------"--"----- - ---- ----- ---.------ 2206-3A Figure 2-1. Front panel controls, connectors, and indicators. REV B, JAN 1979

1 EX7- CLOCK P O L A R I T Y Switch--Selects the active edge o f the external clock signal applied t o the C (clock) input o f thechannel 0-7 Data lnput connector. SAMPLE I N T E R V A L Switch-Selects thedata input sample rate.Sample ratesfrom 5 milliseconds t o 1 0 nanoseconds are provided i n a 5-2-1 sequence. A lamp behind the knob skirt blinks when the sample rate is t o o fast for 8-channel operation (10 nanosecond) or 16-channel (10 o r 2 0 nanosecond) sample intervals. When set t o the I N T E R V A L lamp does not blink when operating i n the f X"T position. 3 DISPLAY T I M E Control--Sets the time that the stored data is dispia ' tinuously variable f r o m approximately I t o 1 0 seconds, o r can be he - detertt position. 4 M A N U A L RESE'T Pushbutton (concentric w i t h DISPLAY T I M E control)-Overrides the DISPLAY TlME control and starts a new 0 ,ore cycle. r; 5 D A T A CHANNELS and BITSICH Switch-Selects data f r o m ctrannels 0 through 3 w i t h 1016 bits o f memory per channel (0-31 ' 1015). Selects data f r o m channels 0 through 7 w i t h 508 bits o f memory per channel 10-71508). Selects data f r o m channels 0 through 15 w i t h 254 bits o f memory per channel (0-151254). 6 F I N E POSICOARSE Controls-Positions the cursor intensified zone t o any bit o n the data display i n one-bit (FINE POS) or 16- ' b i t increments ICOARSEI. B Y T E Switch-Selects the display format o f the cursor readout (displayed o n the crt o f 7000-series oscilloscope mainframe) for @ either 3-bit Ie.g ., 0 100 101 010 001 1001 or .-bit (e.g., 0100 1010 1000 1100) bytes. H O R I Z POSIMAG Controls-Horizontally positions the display w i t h the graticule area (POS) and provides continuously variable O horizontal magnification ( X I t o X l O ) o f the display (MAG). - M A N U A L TRIGGER Switch-Activates the trigger circuit. TRIG'D Indicator-.Lights o n the first accepted trigger (after reset) and remains o n until the store cycle is reset. D A T A POSl TlON Switch--.Three-position switch selects data f o r storage i n the memory after the trigger (POST TRIG), before and after the trigger (CENTER), o r before the trigger (PRE TRIG). TRIGGER SOURCE Switch-Three-position switch derives the trigger signal f r o m the rising edge o f the channel 0 data (CH 0). f r o m an external signal applied t o the E X T TRIGIQUALIFIER INPUT Connector (EXT), o r f r o m the Word Recognizer (W.R.). E X T T R I G P O L A R I T Y Switch-Selects either the rising o r the falling slope as the active edge o f the external triggering signal. EX* r R I G 1 Q U A L I F I E R INPUT Connector-.Provides input for an external signal ( T T L level) t o be used as an external trigger sig- nal or as an external qualifier signal for the Word Recognizer. Channel Switches.--Sixteen three-position switches (chalrnels 0 through 15) select the active state f o r each channel o f data input. The active state for each channel can be selected t o be a high level (HI), a l o w level (LO), o r t o disregard the data level (XI. The amplitude of the H I and L O states is determined b y the THRESHOLD V O L T A G E controls. 16 E X T E R N A L Q U A L I F I E R Switch- Three-position switch selects active state o f the signal applied t o the E X T TRIGIQUALIFIER INPUT connector. The active state can be selected t o be a high level (HI), a l o w level (LO), o r t o disregard the data level (XI. 17 PROBE Q U A L I F I E R Switch-Three-position switch selects the active state o f the signal applied t o pin Q of the channel 0-15 Data Input connector. The active state can be selected t o be a high level (HI), a l o w level (LO), or t o disregard the data level (XI. The amplitude of the H I and L O states is determined b y the THRESHOLD V O L T A G E controls. 18 W.R. MODE Switch-Two-position switch determines the operating mode o f the Word Recogrtirer system. I n the SYNC position, the signal at the W.R. O U T connector goes H I o n the active edge o f the clock signal after all WORD RECOGNILER conditions are met (Channels 0 through 15, E X T E R N A L QUALIFIER, and PROBE QUALIFIER). The clock input is applied t o the C (clock) in- p u t o f the Digital Acquisition Probe connected t o the Channel 0-7 and External Clock Data lnput connector. I n the ASYNC posi- tion, the signal at the W.R. O U T connector goes H I after all WORD RECOGNIZER conditions are met (Channels 0 through 15, E X T E R N A L QIJALIFIER, and PROBE QUALIFIER). 19 FILTER Control-Inhibits the H I output at the W.R. O U T connector f o r about 300 nanoseconds. The F I L T E R control is func- tional only when operating i n the ASYNC W.R. M O D E and is used t o prevent triggering f r o m noise o r bits that have n o meaning a H I output level f o r external use when all WORD RECO_C;NIZEH conditions have been satisfied. u Q - Q / j k . ' ' 1 ; A_,<,+'i- . , STORE CLOCK O U T Conne xternal equ~pment. This output will drive an uirterminated 50-ohm cable. @ D A T A O U T Access-Provide @ Channel 8-15 and Probe Qualifier Data lnput Connector-Provides probe inputs t o Channels 8 through 15 and the Probe Qualifier. @ Channel 0-7 and External Clock Data lnput Connector--Provides probe inputs for Channels 0 through 7 and the External Clock. (25) THRESHOLD V O L T A G E M O N I T O R Pin Jack-Provides an output t o monitor the dc threshold voltage o f the data inputs. I 26 THRESHOLD V O L T A G E Selector Switch-Three-position switch selects a preset threshold voltage f o r Y'TL logic levels (I. I L), or a + t o - 12-volt variable threshold voltage W A R ) as determined b y the screwdriver adjustment. Also selects the preset threshold voltage f o r the Channel 0-7 and External Clock Data lnput connector and the variable threshold voltage (+ t o - 1 2 volts) for the h Channel 8-15 and Probe Qualifier Data lnput connector (TTL-VAR). variable threshold voltage (plus or minus 1 2 volts) when the THRESHOLD /-. VERY' POSIMAG-Vertically positions the display within the graticule area (POS). Provides continuously variable vertical magnifi- cation ( X I t o X 5 ) o f the display (MAG). Figure 2-1 (Continued). Front panel controls, connector , and indicators. 6 I I- .. . , I ? , \ L - I' I /\I ,, R t V . A, M A R 1977 i 2-3

- t - . SOURCE SELECTOR FIRST TRIGGER SELECTOR - CLOCK SQUARE PAD DENOTES PIN 1 22064 n Figure 2-2. Internal Display Clock Source and Full DisplayIFint Trigger Selectors. DISPLAY-STORE OUTPUT (P300, pin 3). This output indicates whether the 7D01 memory is in the display or store mode. An ECL LO level indicates the memory is in the display mode. An ECL HI level indicates that the mem- ory is in the store mode. TRIGGER INTENSIFY OUTPUT (P300, pin 4). During the bit when the trigger point on the data display is inten- sified, an ECL LO level is present at pin 4 of P300. MASTER RESET OUTPUT (P300, pin 5). This output indicates whether the 7D01 is in the store and display or reset mode. An ECL HI level indicates that the memory is in a reset mode. An ECL LO level indicates that the mem- ory is in either the store or display mode. - SIGNAL CONNECTIONS Data Acquisition - Data is acquired through two high input-impedance Tek- tronix P6451 Data Acquisition Probes supplied with the 7D01. One probe applies data inputs to channels 0 through - 7 and the external clock; the other applies data inputs to channels 8 through 15 and the probe qualifier. The probe microhook connectors provide a convenient means of attaching the probe to the data source. A preset threshold -. voltage (+1.4 volts) for TTL logic levels or a variable threshold voltage (+I2 to -1 2 volts) can be selected for either or both probes with the THRESHOLD VOLTAGE ,- selector switch. REV. A, MAR 1977 *-

k - - REV B, JAN 1979 J Figure 2-3. Internal Signal Selector. C EXTERNAL QUALIFIER SETTING PROBE QUALIFIER SETTING Input Select Jumper .------_ P300 JUMPER PLACEMENT SIGNAL SELECTOR PROCEDURE JUMPER LEAD CONNECTOR 1. Remove P300 from instrument. 2. Bend grooved portion of holder away from the jumper lead connector in direction of its hinged side. 3. Insert the jumper lead connector into the selected hole in the holder. Crimped side of jumper lead connector faces toward hinged portion of holder. 4. Bend the grooved part of holder back to its vertical position so connector is inserted into groove. 5. Observe the connector polarity and install P300 back into the instrument. 2206-51 -

- ' Refer to Figure 2-3 for m 51 2 0 D A T A O U T CONNECTOR P300 PIN 7 SIGNAL* OUTPUT P300 PIN 8 EXTERNAL DISPLAY CLOCK I N SERIAL DATA OUT SIGNAL'- - - - - - - - OUTPUT P300 PIN 6 f CHANNEL 8 PARALLEL DATA { OUT CHANNEL 6 I CHANNEL 2 FLAG OUT RECORD ENABLE FRAME OUT GROUND CHANNEL l5 1 CHANNEL 11 I CHANNEL 9 t PARALLEL CHANNEL 7 DATA OUT CHANNEL 3 CHANNEL I J ignal outputs available. - Figure 2 4 . Pin assignments for Data Out connector 5120. SIGNAL CONNECTIONS Data Output Data Acquisition Data is acquired through two high input-impedance Tek- tronix P6451 Data Acquisition Probes supplied with the 7D01. One probe applies data inputs to channels 0 through 7 and the external clock; the other applies data inputs to channels 8 through 15 and the probe qualifier. The probe microhook connectors provide a convenient means of attaching the probe to the data source. A preset threshold voltage (+1.4 volts) for TTL logic levels or a variable threshold voltage (+I2 to -1 2 volts) can be selected for either or both probes with the THRESHOLD VOLTAGE selector switch. The internal 25-pin Data Out connector (J120) provides A access for various input and output signals that can be used with external equipment. See Figure 2-4 for the location of the Data Out connector and the pin assignments. - The outputs from the Data Out connector are unbuffered ECL levels; therefore, it is necessary to assemble a cable h- terminated to meet the test requirements of the external equipment. One end of the cable should be terminated with a connector that mates with the Data Out connector (J120). T Use a type DB-25P, 25-pin male connector, such as Tek- tronix Part 131-0570-00. See Figure 2-5 for two suggested assembly methods. The external display clock and record - REV B, JAN 1979 - ArtekMedia Digitally signed by ArtekMedia DN: cn=ArtekMedia, o=ArtekMedia.com, ou, [email protected], c=US Date: 2008.11.17 14:26:10 -06'00'

FROM DATA OUT I CONNECTOR RECEIVING END (UNTERMINATED) I 100 A2 SENDING-END SERIES TERMINATION I FROM DATA OUT CONNECTOR ( ~ 1 2 0 ) loo n Figure 2-5. Suggested methods for terminating data outputs from Data Out connector J120. enable inputs are terminated in 100 ohms to 2 volts in the 7D01. For further information, contact your rektronix Field Office or representative. In addition to the channel 0 through 15 parallel data out- puts, the following input and output signals can be obtained through the Data Out connector (refer to Fig. 2-4 for the location of Data Out connector J120 and the pin assignments). EXTERNAL DISPLAY CLOCK IN. Provides input for an ECL-level clock pulse and must be used to synchronize serial and parallel data. I-he internal Display Clock Source Selector, P835, must be set to the External Display Clock position (see procedure under Auxiliary Functions). SERIAL DATA OUT. Provides serial data from channel 0 through 15. An external display clock must be applied to pin 3, and the Display Clock Source Selector, P835, must be set to the External Display Clock position for synchro- nized output (see procedure under Auxiliary Functions). TO RECORD ENABLE INPUT (PIN 15, 5120) Figure 2-6. Suggested method for assembling a remote Manual Reset button. PARALLEL DATA OUTPUT. Provides outputs from channels 0 through 15. An external display clock must be applied to pin 3, and the Display Clock Source Selector, P835, must be set to External Display Clock for synchro- nized output (see procedure under Auxiliary Functions). FLAG OUT. Provides an output pulse which indicates the beginning of each data channel. A positive-going edge indi- cates the beginning of a data channel (channels 0 through 15). Data is not valid during a LO ECL level. RECORD ENABLE. A HI ECL level input pulse forces reset of the memory. When the front-panel MANUAL RESk-I bution is pushed, a HI output level is produced. A remote Manual Reset bution can be assembled as shown in Figure 2-6. FRAME OUT. Provides pulse to synchronize serial data. An ECL LO level occurs at every sixteenth flag pulse for the duration of channel 3. The Frame Out pulse occurs at every sixteenth flag pulse regardless of the setting of the DATA CHANNELS switch. For the sequence in 4, 8, and 16 data channel operation, see Serial Data Out Channel Sequence in Table 1-1, Electrical Characteristics. DISPLAY l NG DATA The 7D01 provides some convenient and unique display capabilities. Figure 2-7 shows a typical channel 0 to 15 display with a 254-bit window. One row of intensified dots are trigger markers that indicate whether the logic analyzer is operating in the pre, center, or post trigger mode as selected by the DATA POSl i ION switch. A second row of intensified dots are cursor markers that can be moved across the timing diagram with the CURSOR COARSE and FINE POS controls. rhe cursor function provides a simultaneous timing and logic state display by reading out the selected timing diagram word in 3-bit or 4-bit byte binary at the bottom of the crt. In addition, the number of sample Inter- vals and direction (i.e., -- or +) from the intensified trigger markers to the cursor markers appears at the top right side of the crt. The X I 0 horizontal and X5 vertical POS and MAG controls expand any portion of the display for close examination. Further magnification can be obtained with a vertical amp- lifier and time-base plug-in unit, In addition to a 7D01, installed in a 4-compartment mainframe. Refer to Trigger- ing for more information. NOTE If the 7007 is used in a storage mainframe, i t is recommended that the mainframe be operated in the non-store mode. TRIGGERING The built-in Word Recognizer provides a versatile trigger source. Logic states of parallel words up to 18 bits wide can be preselected by the front-panel channel switches. The Word Recognizer then triggers the 7D01 when the incoming parallel word matches the one preselected by the channel switches (HI, LO, or X-don't care). The intensified trigger markers on the data display indicate the trigger point selected by the Word Recognizer. REV B, JAN 1979

DIRECTION AND SAMPLE INTERVALS FROM TRIGGER T"0 CURSOR MARKERS -CHANNEL 0 , INTENSIFIED MARKERS INTENSIFIED CURSOR MAR TRIGGER KERS / LOGIC STATE FOR CHANNEL 15 EACH CHANNEL OF \ CHANNEL 0 BINARY BINARY CODE DISPLAYED DATA AT CODE INTENSIFIED CURSOR MARKERS 2206-42 ---,- "" --m--,-.-..--pp--. --' Figure 2-7. Typical channel 0 to 15 pretrigger data display. The Word Recognizer also provides a +2-volt (approximately) CLOCK QUALIFIER OPERATION output pulse from a 50-ohm source at the front-panel W.R. OUT connector when the incoming parallel word matches the preselected word on the channel switches. This output The Clock Qualifier allows you to make optimum use of pulse can be used to trigger a time-base plug-in to provide the 4K memory present in the 7D01. In many test an analog display when the 7D01 is installed in a 4-compart- situations, continuous sampling fills the memory with data ment mainframe. By selecting the mainframe Alternate or that isn't relevant to the problem at hand. When a Right Vertical Mode operation, analog and digital informa- properly timed qualifier signal is available, then entire tion can be displayed either simultaneously or separately. memory space can be filled only with pertinent data. The 7D01 is not designed to operate in the mainframe Horizontal Alternate mode. However, dual-trace displays (i.e. between the 7D01 and a pair of plug-in units in- stalled in the Left Vertical and B Horizontal compartments) can be obtained by selecting the mainframe Vertical Alter- nate and Horizontal Chop modes. Refer to Fault Identifi- cation under Applications for an example of combined digital and analog display operation. In addition to triggering the 7D01 on a preselected word or pattern, a trigger can be obtained from channel 0 of the input data or from an external qualifier signal such as an error flag, sector pulse, enable signal, or any unique single- channel event. For example, in the synchronous mode, a microprocessor loop can be checked by inputting from the external qualifier with all other channels set to X (don't care). Thus, the Word Recognizer triggers on the qualifier without recognizing the other channels, and displays an isolated window rather than the entire data train. The Clock Qual~fier is used when the 7D01 is sampling in synchronous mode, using the clock of the system under test. Dur~ng normal synchronous operation, data is stored - in memory once during each clock cycle. When the Clock Qualifier i s activated, new data is stored only when the clock cycle is qualified by an external signal. - The qualifying signal can come from the Probe Qualifier of the data probe (CH 8-1 5) or can come from a source ex- ternal to the 7D01 through the unit's EXT TRIG/QUALI- FlER INPUT. An internal jumper is used to select either the Probe Qualifier or the External Qualifier. If the Probe - Qualifier is used, the PROBE QUALIFIER switch in the WORD RECOGNIZER section of the 7D01 should be set to the don't care (X) position. If an External Qualifier is used, the EXTERNAL QUALIFIER switch should be set to the don't care (X) position. If you use and External Qualifier signal, a word recognizer unit such as the WR 501 can be bsed to obtain multi-line qualifier capabilities. REV B, JAN 1979

The CLOCK QUALIFIER switch on the 7D01 i s used to enable the Clock Qualifier, and also to select whether a high or low input signal will be used as the qualifier. This is true for External Qualifier signals and Probe Qualifier signals alike. You can also use the EX I CLOCK POLARITY switch to select whether the positive (1) or negative (I ) edge of the clock pulse will start the data sampling process. Different combinations of the CLOCK QUALIFIER switch and the EXT CLOCK POLARI I"Y switch will cause vari- ations in the sampling process. CLOCK QUALIFIER SWITCH DESCRIPTION The CLOCK QUALIFIER is a three-position front-panel switch. I-he switch positions control Clock Qualifier oper- ations in the following ways: HI -- Data is clocked into memory in the active clock edge while the Qualifier input is high. OFF - Clock Qualifier is disabled. LO - - Data is clocked into memory on the active clock edge while the Qualifier input is low. I he EX"I CLOCK POLARI r Y switch selecis either the positive (I) or negative (I) clock edge as the active edge. ADDITIONAL OPERA I'ING INFORMATION CLOCK QUALIFIER RULE NO. 1. The WORD RECOG- NIZER is not automatically qualified by the clock qualifier. To qualify both the clock and WORD RECOGNIZER trig- ger, a WORD RECOGNIZER input and clock qualifier must be connected to the same signal. Therefore, whenever WORD RECOGNILEH triggering is employed with clock qualification, it is necessary to also qualify the WORD RECOGNIZER with the same signal which is qualifying the clock. Example: Use the probe qualifier as WORD RECOG- NlLER input, and use the external qualifier to qualify the clock. CLOCK QUALIFIER RULE NO. 2. When the clock qualifier is utilized, the qualifying signal is input through either the EX]' QUALIFIER connector or through the probe qualifier line on the CH 8-15 probe, by selecting the appropriate jumper position on the Clock Qualifier circuit board. Whichever qualifier input is used, the respective - WORD RECOGNIZER qualification switch must be left in the "X" (don't care) position. ASYNCHRONOUS AND SYNCHRONOUS DATA SAMPLING . ASYNCHRONOUS. When analyzing logic timing in a hard- ware system, it i s desirable to sample data asynchronously. The 7001 is then clocked internally (i.e., asynchronous to the system under test) to determine clock frequencies and make timing comparisons. Data is sampled asynchronously at a rate of up to 100 megahertz with a minimum data pulse width of 1 sample interval plus 5 nanoseconds. Asynchro- nous testing requires that data be sampled frequently for maximum timing resolution. SYNCHRONOUS. For applications where the data is valid at qualified clock transitions is of interest and not the changes in between (e.g., when checking software), the program flow of clocked systems should be sampled ex- ternally or synchronously. The 7D01 is then synchronized with the measured system clock at a sampling rate of up to 50 megahertz. When data is being recorded by the 7DO1, there i s a mini- mum number of external clock pulses necessary to produce a transition from record to display mode. The required number of clock pulses varies depending on the D A I A POSITION switch and Full DisplayIFirst Trigger Selector (P617) settings. Refer to Figure 2-2 for the location of the Full DisplayIFirst 1 rigger Selector (P617). When in Full Display mode after the MANUAL RESET button is pressed, the entire 4096 bits of memory must be filled with new data before the 7D01 will accept a trigger (4096 bits corresponds to 1024 clock pulses in 4 channel, 51 2 clock pulses in 8 channel, and 256 clock pulses in 16 channel). After the trigger is accepted, another block of data must be acquired before the 7D01 will switch from the record to the display mode. The size of this block of data depends on the DATA CHANNELS and DATA POSITION switch settings and contains all of the information stored from the trigger point to the end of the displayed trace. This block of data corresponds to the minimum number of clock pulses given in Table 2-2 for the First Trigger mode. TABLE 2-2 Minimum Clock Pulses Required to Display Data (After the MANUAL RESET Button is Pressed) First Trigger Mode Full Display ode' - - - - DATA I DATA POSI"TI0N DATA POSITION C H A N N E L S j ~ O S T ~ ] P R E I F S ~ - ~ - F TRlG CENTER TRlG TRlG CENTER TRlG ' In Full Display mode, the 7D01 must have 1024 clock pulses with 0-3 data channels, 512 clock pulses with 0-7 data channels, and 256 clock pulses with 0-15 data channels before a trigger is accepted. In First Trigger mode, however, it is not necessary to fill the entire 4096-bit memory before a trigger is accepted. In- stead, a trigger can be accepted at any time after the MAN- UAL RESET button is pressed and one clock pulse is accepted. Thus, the number of clock pulses needed to cause the 7D01 to switch from record to display mode (af- ter the MANUAL RESET button is pressed) is always less in REV OC1- 1 982

First Trigger mode than in Full Display mode (i.e., by 1024, 512, or 256 clock pulses). For the 7D01 to trigger, the trigger event must change from a FALSE condition to a TRUE condition after the 7001 is ready to accept a trigger as described above. The only ex- ception to this is when the trigger event comes from the Word Recognizer (in SYNC mode) with the 7D01 in First Trigger Mode and with the SAMPLE INTERVAL switch in available. The additional clock pulses necessary to switch the 7D01 from record to display mode can be obtained by changing the SAMPLE INTERVAL switch from the EX'T po- sition to the 5 ms position after the data is recorded. How- ever, the data recorded after the SAMPLE IN"TERVAL switch was changed to the 5 ms position is not valid since the system being measured is not functioning during that interval. E*. Under these conditions, the trigger event may be TRUE when the aquisition is started, in which case the BPERATlONdab ANALYSIS 7D01 will trigger on the first clock pulse after the aquisition begins. When measuring a circuit with gated clock pulses and data, there may not be enough clock pulses before the system is gated off to cause the 7DO-1 to trigger or display data in the Full Display mode. If this condition occurs, the First Trigger mode will enable the 7D01 to accept a trigger and store the data. However, the data will not be displayed unless the minimum number of clock pulses specified in Table 2-2 is The following table lists some irregular operating symptoms with their probable causes and corrective procedures. Table 2-3 is intended to assist the operator in determining whether an irregular operating symptom is the result of a measure- ment technique problem or a malfunction in the 7D01. The probable causes for the symptoms listed in Table 2-3 as- sume that the 7D01 and associated equipment is operating properly. The corrective procedures can be performed by the operator without additional test equipment. TABLE 2-3 - Operational Analysis -r - - - - ----- Symptom Probable Cause Corrective Procedure . - . .. 1. No data display. Display positioned off screen. Wrong threshold voltage. Check THRESHOLD VOLTAGE selector and/or adjustment setting. Check that clock signal is applied through Data Acquisition Probe. 2. No data display with SAMPLE IN I t R V A L in EXI- position. Wrong threshold voltage. No external clock signal. Check THRESHOLD VOLTAGE selector and/or adjustment for proper setting. 3. No data display with: a. W.R. MODE in SYNC position. b. TRIGGER SOURCE in W.R. position. c. TRIG'D indicator not lit. 4. No data display with: a. W.R. MODE in ASYNC position. b. TRIGGER SOURCE in W.R. No external clock signal. Word selected on WORD RECOG- NlZER channel switches does not exist exlst. - -- Word selected on WORD RECOG- NlZER channel sw~tches does not Check that clock signal is applied through Data Acquisition Probe. -- - - - - Check that WORD RECOGNIZER channel sw~tches are set for an exise~ng word. - - ---- - - . Check that WORD RECOGNIZER channel sw~tches are set for an exlstlng word. posltlon. - - I - -- - c. TRIG'D ~nd~cator not Ilt. Asynchronous f~lter IS rejecting valid Check that F I L-I kR 1s not set too far 5. When Testing Circuits with Gated Clocks a. No data display with: (1) SAMPLE INTERVAL in EXT position. (2) Full DisplayIFirst Trigger (P617) in First Trigger position. (3) TRIG'D indicator not lit. data. Trigger word existed only during first clock pulse and i s ignored by the 7D01. clockwise. See Asynchronous and Synchronous Data Sampling for rnlnlrnurn number of clock pulses requ~red to obtain a d~splay In F~rst 1 rlgger mode. -OR Set SAMPLE INTERVAL to 5 ms posl- tion for a t least 5 seconds. Then reset SAMPLE INTERVAL to EXT posltion and start data source. REV OCT 1982 -

TABLE 2-3 (CONT.) Operational Analysis Symptom - -- - - - - - -- 5. (Continued) b. No data display with: (1) SAMPLE INTERVAL in EXT position. (2) Full DisplayIFirst Trigger (P617) in First I rigger position. (3) 1 HIG'D ind~cator lit. Probable Cause - -- - - -- -- - - - - - - - - ---- Insufficient number of clock pulses after trigger word to fill memory (display) from trigger markers to end of sweep. Corrective Procedure See Asynchronous and Synchronous Data Sampling for minimum number of clock pulses required to obtain a display in First Trigger mode. Set SAMPLE INTERVAL to 5 ms posi- tion until display appears. Then reset SAMPLE IN TERVAL to EXT position. c. No data display with: (1) SAMPLE IN [ ERVAL in EXT position. (2) Full DisplayIFirst Trigger (P617) in Full Display position. (3) T RIG'D indicator lit. lnsufficient number of clock pulses after trigger word to fill 7D01 memory (display) from trigger markers to end of sweep. See Asynchronous and Synchronous Data Sampling for minimum number of clock pulses required to obtain a display in Full Display mode. Set SAMPLE INT EHVAL to 5 ms posi- tion until display appears. Then reset SAMPLE IN I ERVAL to EXT position. NOTE First Trigger mode may be pre- ferred since fewer clock pulses are required to switch from re- cord to display mode. d. No data display with: (1) SAMPLE INTERVAL in EXT position. (2) Full DisplayIFirst "Trigger (P617) in Full Display position. (3) 7' RIG'D indicator not lit. REV B, JAN 1979 - lnsufficient number of clock pulses to fill 7D01 memory. See Asynchronous and Synchronous Data Sampling for minimum number of clock pulses required to obtain a display in Full Display mode. Set SAMPLE INTERVAL to 5 rns posi- tion for at least 5 seconds. "Then reset SAMPLE IN I'ERVAL to EXT position. When data is present from Data Acquisi- tion Probe, TRIG'D indicator should light and display should appear. But: (1) If there is no display and TRIG'D indicator is lit, set SAMPLE INTER- VAL to 5 n ~ s position until display appears. Then reset SAMPLE INTER- VAL to EXT position. (2) If display does not appear and TRIG'D indicator is not lit, refer to Corrective Procedure for Symptom 3 and 4. NOTE First Trigger mode may be pre- ferred since fewer clock pulses are required to switch from re- cord to display mode.

TABLE 2-3 (CONT.) Operational Analysis - -- - - - - - I - 1 - - - - ---- Symptom I Probable Cause - I Corrective Procedure -- - -- -- - - - -- - - - - - -- - -- --- 6. Incorrect data display when installed in a storage mainframe. Mainframe set for store mode. - - - - --- - - -. - 7. Incorrect data display. Wrong mainframe Vertical and/or Horizontal Mode. i Set mainframe for non-store mode. N O'T E When the 700 1 is used in a storage mainframe, i t is recommended that the mainframe be operated in the non-store mode. --- Check that proper mainframe Vertical and/or Horizontal Mode is selected. Wrong threshold voltage. - - - -- - 8. Incorrect data display after MANUAL RESET was not pressed changing DATA CHANNEL or after changing DATA CHANNEL or POSITION setting. DATA POSITION setting. Check I HRESHOLD VOLTAGE selector and/or adjustment for proper setting. Press MANUAL RESET to store new data in memory in the correct format. 9. lncorrect or noisy data display on channels that are not connected to a Data Acquisition Probe. Data input lines are not biased proper- ly when a Data Acquisition Probe i s not connected. Connect a Data Acquisition Probe to un- used channels. Use only channel 0-7 and set DATA CHANNELS to 0-3 or 0-7 position. Set all unused WORD RECOGNIZER chan- nel switches (8-1 5) to X (don't care) position. 10. Random or incorrect triggering from WORD RECOGNIZER with only one Data Acquisition Probe connected. I I. Displayed data on left side of trigger marker is blanked out. - -- - - - - - - - - 12. Portions of data input do not appear on display (aliasing) with internal clock pulses. WORD RECOGNIZER channel switches on unused channels are set to HI or LO positions which can cause some channels to oscillate. -- - - - - - -- Full DisplayIFirst Trigger (P617) is in First Trigger position. - Data changes faster than the sampling rate. Set WORD RECOGNILER channel switches on unused channels to X (don't care) position. -- - -- - - - - - . - Set Full DisplayIFirsi Trigger (P617) to Full Display position. - - - Set SAMPLE INTERVAL for more than 1 sample interval for each data pulse (i.e., data pulse = shortest period of time that data remains in HI or LO state). REV B, JAN 1979

APPLICATIONS INTRODUCTION The 7D01 with its built-in Word Recognizer is a versatile measurement tool for detailed logic analysis. A choice of configurations are available to meet a variety of logic analy- sis and troubleshooting requirements. 'The following infor- mation includes some specific application procedures and examples of applications for the 7001. Contact your local Tektronix Field Office or representative for assistance on applications that are not included here. FAULT' IDENTI FlCATlON The following procedure describes a method for finding a fault, determining its location on a data train, and exarnin- ing it on a real-time analog display. This method assumes that the fault occurs at a unique word. For this application, the 7D01 is used with a companion vertical amplifier and time-base plug-in unit in a 4-compartment mainframe with readout. 1. Connect test equipment as shown in Figure 2-8A. 2. Set the 7D01 W.R. MODE switch to ASYNC and the TRIGGER SOURCE switch to W.R. 3. Set the mainframe to display the right vertical and A horizontal compartments. 4. Obtain the desired data display (see example in Fig. 2-8B). 5. Set the CURSOR controls to position the intensified cursor markers to the leading edge of the displayed fault. 6. Note the binary word readout (bottom right side of graticule). 7. Set the Word Recognizer for the binary word code noted in step 6. 8. Connect a 10X probe from the vertical amplifier plug-in unit to the data channel that contains the fault as deter- mined in step 5. REV B, JAN 1979 9. Set the mainframe to display the left vertical and B horizontal compartments. 10. Set the vertical amplifier deflection factor and time- base plug-in unit sweep rate and triggering for a stable analog display of the data channel selected in step 8 (see example in Fig. 2-8C). NOTE The 7001 FIL TEH control can be used to provide some horizontal positioning of the display. DELAY BY WORDS The following describes a method for preselecting a binary word and positioning the data display window anywhere from the first to .the 10 millionth time that the binary word occurs. For this application, the 7D01 is used with a com- panion digital events delay plug-in unit (e.g., Tektronix 7D10 Digital Events Delay) in a mainframe with readout. 1. Connect the test equipment as shown in Figure 2-9A. 2. Set Lhe digital events delay plug-in unit for independent B sweep delay mode and external ac-coupled t slope triggering. 3. Set the 7D01 W.R. MODE switch to ASYNC and the TRIGGER SOURCE switch to W.R. 4. Set the WORD RECOGNIZER channel switches for the desired binary word code. 5. Set the mainframe to display the right vertical compartment. 6. Set the digital events delay plug-in unit for a stable display triggered on the .+ slope of the events start trigger Input. 7. Set the digital events delay plug-in unit to indicate, on the events count readout, the desired number of times

-wp---m---p-p 7000-S ER I ES MAINFRAME WITH READOUT OX PROBE DATA L--.--.-..-.---l u INPUT DATA INPUT (CHANNEL CON'T'AINING FAULT) B CUHSOR MARKERS FAULT FAULT OCCURS IN CHAN 2 AFTtH WORD 0101 0100 - -- REAL TIME ANALOG DISPLAY OF FAULT -- (2148) 2206-43 -- _I Figure 2-8. Equipment setup and displays for finding a data fault and examining it on an analog display. that the preselected binary word is to occur before a data display is initiated. For example, if the digital events delay plug-in unit is set for an events count readout of 0000025, the word recognizer will initiate a display of the data be- fore, after, or on both sides of the 25th time that the preselected binary word occurs (see example in Fig. 2-98]. DELAY BY EVENTS The following procedure describes a method for positioning the data display window to virtually anywhere along a data train. For this application, the 7D01 is used with a compan- ion digital events delay plug-in unit (e.g., Tektronix 7D10 Digital Events Delay) in a mainframe with readout. 1. Connect the test equipment as shown in Figure 2-10A. 2. Set the digital events delay plug-in unit for external ac- coupled + slope triggering. 3. Set the 7D01 TRIGGER SOURCE switch to EXT and trigger from the external trigger input. 4. Set the mainframe to display the right vertical compartment. 5. Set the digital events delay plug-in unit for a stable dis- play triggered on the + slope of the events start trigger input. 6. Set the digital events delay plug-in unit to indicate the desired number of clock pulses, on the events count read- out, that the 7D01 bit-storage window is to be shifted down the data train. For example, if the digital events, delay plug-in unit is set for an events count readout of - 0010500, the 7D01 will initiate a display of the data before, after, or on both sides of the 10,500th clock pulse (see example in Fig. 2-10B). STATE TABLE AND MAPPING DISPLAYS The 7D01 in combination with a display formalter (e.g., Tektronix DFI Display Formatter) adds state table and mapping displays to the timing diagram display normally available with the 7D01 alone. The state table mode enables the data stored in the 7D01 memory to be displayed in a tabular format. The display formatter generates the cursor readout in the timing dia- gram mode, and the state table mode then generates a state display of 17 samples, starting at the cursor, in hexadecimal, octal, or binary code. REV B, JAN 1979

7000-SE R I ES M A I N F R A M E W l T H R E A D O U T E X T T R I G / Q U A L I F I E R E X T E V E N T S 0 T R I G S T A R T D A T A I N P U T I N TRIG I N D E L A Y E V E N T S S E T TO D I S P L A Y D A T A A F I t R THE 2 5 T H T I M E T H A T T H E P R E S E L E C T E D 8 - B I T B I N A R Y W O R D (0101 0 1 0 0 ) OCCURS I N T H E D A T A T R A I N . (2148) 2206-44 Figure 2-9. Equipment setup and data display window that has been positioned after a preselected word has occurred 25 times. By using the EXCLUSIVE OR mode (featured w ~ t h the rektronix DFI Display Formatter), the state table from the 7D01 and a reference state table can be displayed simul- taneously and faulty bits can be quickly identified. For example, data from the 7D01 memory can be transferred to the display formatter memory for a reference and then 7000-SE R I ES M A I N F R A M E W l T H R E A D O U T EXT CLOCK INPUT PULSE PULSES INPUl I H I G IN D E L A Y E V E N T S S E T T O D I S P L A Y D A T A A F T E R 10,500 C L O C K PULSES. Figure 2-10. Equipment setup and display window that has been positioned after 10,500 clock pulses have occurred. incoming data stored in the 7D01 memory can be com- pared to the reference data. Any difierences in the 7D01 data can be identified (each bit that does not agree with the reference data is intensified by the T-ektronix DFI Display Formatter) and the problem located by using the timing diagram display. REV B, JAN 1979

The map display is useful for fast overall checks of digital- system program flow. First, determine the pattern (map) for a particular set of digital inputs, then check for a change in the displayed pattern which might indicate abnormal operation. The ~iiapping and state table modes are particularly useful for checking faulty address lines. For example, evaluate program flow by examining a map display. If a problem word is located, switch to a hexadecimal state-table display in the EXCLUSIVE OR mode for more precise identifica- tion of the problem (refer to the preceding EXCLUSIVE OR discussion). Then switch to the binary state-table dis- play to locate the incorrect address line. Further examina- tion of the address line on a timing diagram display reveals a set up and hold problem between the clock and the address line. If desired, use the word recognizer output to trigger an analog display of the 7D01 data output for an even closer examination (refer to the previous Fault Identi- fication discussion for more information). MICROPROCESSOR ANALYSIS "The following is an example of a technique for trouble- shooting a malfunctioning microprocessor system. A malfunctioning microprocessor system i s shown in Figure 2-1 1. Software had previously worked properly, but was still not free of suspicion. Data was stored in the RAM (random-access readlwrite memory). The system program was resident in the PROM (programmable read only memory). Restart vectors pointed to the address of the first instruction in the restart routine. When the restart hardware was exercised, the CPU (central processing unit) should have performed certain initialization routines and then gone to the Wait for Interrupt mode. -/"he terminal would then call up other operating software in the PROM, or provide access to a binary loader. The failure consisted of very erratic operation after restart. 'The 7D01 was connected to the system as shown in Figure 2-1 1 to store and display a large data block from the 8 data lines. The display was obtained by triggering the 7D01 on the beginning of the restart cycle and using the system clock as an external data sampling slrobe. MAINFRAME WITH READOUT L- EXT CLOCK RESTART - 4 RESTART ,--Qp PUSHBUTION 2206-46 .-..A- ". "~ Figure 2-1 I. Typical setup for troubleshooting a microprocessor system. Analysis of the data display showed the problem to be a dropped bit in the portion of the PROM providing the restart routine. "The CPU fetched an invalid restart vector, causing data from the RAM to be executed as instructions. REV 0 , JAN 1979 -

7000-SERI ES MAINFRAME WITH READOUT The 7001 can store 8 input and 8 output lines simulta- neously and display all 16 data lines on a single display. By displaying an input line and the corresponding output line together, a quick comparison can be made. A typical setup and display is shown in Figure 2-1 2A and B. When the 7D01 is clocked asynchronously from the internal clock, a high-resolution timing diagram display will provide timing information as well as reveal malfunctions that would otherwise be difficult to detect with any other type of test equipment such as an oscilloscope or dvm. FUNCTIONAL CHECK The following procedure checks the basic operation of this instrument. Functions only are checked in this procedure, therefore a minimum amount of test equipment is required. Measure- ment quantities and tolerances are not checked. 'The Word Recognizer Filter and Output signal, and the Variable Threshold Voltage functions are not checked in this procedure because extra test equipment would be re- quired. These functions, and their associated specifications are checked in the Performance Check and Adjustment section of the 7D01 Instruction manual. Refer these checks to a qualified service technician. Preliminary Procedure 1. Install 7D01 in oscilloscope mainframe (see Installation instructions in General Information section). Figure 2-12. Typical setup and display for troublmhooting a storage buffer. 2. Connect a P6451 Data Acquisition Probe to top data- input connector (Channel 0-7 and External Clock). STORAGE BUFFER ANALYSIS The following procedure describes a method for checking the performance of a storage buffer by monitoring the inputs and outputs simultaneously. The non-synchronous buffer is a commonly used type, in which data flows continuously from input to output. A display of this data flow will show at a glance if all the memory cells are functioning properly. 3. Set 7D01 front-panel controls as follows: VERT POS . . . . . . . . . . . midrange M A G . . . . . . . . . . . . . X I RECORD DISPLAY TIME. . =(fully clockwise detent) CURSOR BYTE (SN B086084-- below). . 4 BIT CLOCK QUALIFIER (SN B086085-up) . . . . OFF REV D JUN 1980

HORlZ . . . . . . . . POS .midrange MAG. . . . . . . . .XI THRESHOLD VOLTAGE. . . . . . .TTL E X I CLOCK . . . . POLARITY.. J-^l SAMPLE . . . . INTERVAL. .I ps DATA CHANNELS. . . . . .O-3 DATA POSITION. . . . . . .CENTER rRIG SOURCE. . . .CH 0 EXT TRIG . . . . POLARITY. .A- WORD RECOGNIZER W.R. MODE. . . .ASYNC FILTER . . . . . .MIN CH 0 through 15 . . . . . . . . . .X (center) EXTERNAL QUALIFIER . . .X (center) PROBE QUALIFIER . . .X (center) 4. Apply power to oscilloscope mainframe. Functional Check Procedure 1. Press the RECORD MANUAL RESET and MANUAL TRIGGER pushbuttons (in that order) to obtain display. 2. Adjust Test Oscilloscope intensity and focus controls as desired. ' 3. Check that four traces are displayed on the crt. 4. Set DA"T A CHANNELS switch to 0-7 5. Check that eight traces are displayed in two groups of four traces each. 6. Set DATA CHANNELS switch to 0-15. 7. Check that sixteen traces are displayed in four groups of four traces each. 8. Check that the VERT POS and HORlZ POS controls will position any portion of the displayed traces on screen for any setting of the VERT MAG and HORlZ MAG controls. 9A. (SN B086085-up) Check that sixteen zeros are displayed by the Cursor Data readout (bottom of screen) in groups of four. This will be the case when the Byte Select jumper is set for 4-bit bytes. See step 10. - 9B. (SN B086084-below) Check that sixteen zeros are displayed by the Cursor Data readout (bottom of screen) in groups of four. 10A. (SN B086085-up) If the Byte Select jumper is set for 3-bit bytes check that sixteen zeros are displayed in four groups of three bits each and one group of four bits. The Byte Selection function is an internal adjustment which requires removing hte 7D01 from the mainframe - and removal of the side covers. Changes should be referred to qualified service personnel. 10B. (SN B086085-below) Set the CURSOR BYTE switch to 3 BIT- and check that sixteen zeros are displayed in four groups of three bits each and one group of four bits. - 11. Check that the Cursor lntensified Zone can be horizon- tally positioned on the display by the CURSOR COARSE and FINE POS controls. 12. Check that the Trigger lntensified Zone is approxi- mately centered (horizontally) on the display. 13. Set DATA POSITION switch to POST TRIG.. 14. Check that the Trigger lntensified Zone moves toward the left end of the displayed traces. 15. Set DATA POSITION switch to PRE TRIG. - 16. Check that Trigger Intensified Zone moves toward the right end of the displayed traces. 17. Set DATA POSITION switch back to CENTER. - 18. Set RECORD DISPLAY TIME control to 1 s position _ (fully counterclockwise). 20. Connect channel 0 probe lead to 4-volt, I-kilohertz output of oscilloscope calibrator. 19. Check that TRIG'D light goes out and that display disappears. 21. Check that display reappears and that rising edge of channel 0 waveform i s approximately centered (horizon- tally) on display. (Disregard any noise displayed on channels 7-15.) - REV C JUN 1980 -

22. Set TRIGGER SOURCE switch to W.R. 38. Check that falling edges of channel 8 through 15 wave- forins are approximately centered on the display. 23. Set WORD RECOGNIZER channel 0 switch to HI. 39. Set all WORD RECOGNIZER channel and qualifier 24. Check that rising edge of channel 0 waveform is switches to X. approximately centered on the display. 40. Remove Data Acquisition Probe from borton Data 25. Connect channel 0 through 7 probe leads to oscillo- Input Connector and connect to top Data Input Connector. scope calibrator output. 26. Set WORD RECOGNIZER channel 0 through 7 switches to HI. 4 1. Disconnect all probe leads from oscilloscope calibrator. 42. Connect oscilloscope calibrator to EXT TRIG/QUALI- FlER INPUT. 27. Check that rising edges of channel 0 through 7 wave- forms are approximately centered on the display. 28. Set WORD RECOGNIZER channel 0 through 7 switches to LO. 29. Check that falling edge of channel 0 through 7 wave- forms are approximately centered on the display. 43. Set WORD RECOGNIZER EXTERNAL QUALIFIER switch to HI. 44. Check that TRIG'D light is on and display is present. 45. Set WORD RECOGNIZER EXTERNAL QUALIFIER switch to LO. 30. Set W.R. MODE switch to SYNC. 46. Check that TRIG'D light is on and display is present. 31. Check that the I-RIG'D light goes out and that display disappears (with external clock probe lead disconnected). 32. Set W. R. MODE switch back to ASYNC. 33. Connect external clock probe lead to oscilloscope cali- brator output. 34. Remove Data Acquisition Probe from top Data lnput Connector (Channel 0-7 and External Clock) and connect to bottom Data lnput Connector (Channel 8-15 and Probe Qualifier). 35. Set WORD RECOGNIZER channel 0 through 7 switches to X and channel 8 through 15 and PROBE QUALIFIER switches to HI. 36. Check that rising edges of channel 8 through 15 wave- forms are approximately centered on the display. 37. Set WORD RECOGNIZER channel 8 through 15 and PROBE QUALIFIER switches t o LO. REV B, JAN 1979 47. Set WORD RECOGNIZER EXTERNAL QUALIFIER switch to X. 48. Set TRIG SOURCE switch to EXT. 49. Check that TRIG'D light is on and display is present. 50. Set EXT TRIG POLARITY switch to 1. 51. Check that TRIG'D light is on and display is present. 52. Disconnect oscilloscope calibrator from EXT TR IG/ QUALIFIER INPUT. 53. Set TRIGGER SOURCE switch to CH 0. 54. Connect channel 0 and external clock probe leads to 4-volt, 1-kilohertz signal from the oscilloscope calibrator.

55. Set DATA CHANNELS switch to 0-3. 58. Check that a display is present for both positions of the EXT CLOCK POLARITY switch. 56. Check that a display is present for each position of the SAMPLE INTERVAL switch. 59. Disconnect probe leads ffom oscilloscope calibrator output. 57. Set SAMPLE INTERVAL switch to EXT. This completes the Functional Check Procedure. @ JAN 1979

THEORY OF OPERATION This section of the manual contains a description of the The Memory circuit stores and displays input data at a circuitry used in the 7D01 Logic Analyzer. The description rate set by the 'Time Base circuit. The Memory circuit con- begins with a discussion of the instrument using the Block sists of sixteen 256-bit RAM (Random Access Memories) Diagram (Fig. 3-1) to show the major interconnections be- and the required Data SelectorILatches and control circuits. tween circuits. Each circuit is then described in detail in the Depending on the setting of the DATA CHANNELS switch, Detailed Circuit Description. the Memory circuit will store and display 101 6 bits of data from each of four channels (0-3), 508 bits from each of eight channels (0-7), or 254 bits from each of sixteen channels (O- BLOCK DIAGRAM DESCRIPTION The Word Recognizer circuit perforlns three major func- tions; it provides the threshold voltage and input buffering for the data signals from the Data Acquisition Probe(s), and allows triggering of the 7D01 (andlor external equipment) on - any preset, parallel-data "word" of up to 16 bits. The threshold Voltage stage sets the offset voltage used by the Data Acquisition Probe. The Input Buffer stage provides iso- _ lation between the Data Acquisition Probe and the Memory and Word Recognizer gates. The Word Recognizer stage provides a HI output when the logic states of the input data channels match the states set by the corresponding Word - Recognirer switches (CH 0-15). The output from the Word Recognirer can be used internally to trigger the 7D01, or externally by other equipment or plug-in units. 'Pwo Qualifier inputs can be used to enable Synchronous Mode, the Word Recognizer output signal goes HI on the first active edge of the External Clock signal after all Word Recognizer condi- , tions have been satisfied (including External Qualifier andior Probe Qualifier). In the Asynchronous Mode, the Word Rec- ognizer output signal goes HI as soon as all Word Recogniz- er conditions have been satisfied. A variable Filter inhibits - the Word Recognizer output for up to 300 nanoseconds to prevent false triggering on very brief signals when in the Asynchronous Mode. 'The Word Recognizer output signal is - connected to the ^('RIGGER SOURCE switch and to the front-panel W.R. OUT connector. I^he Clock Qual~f~er (SN 8086085 and up) c~rcuit provides control over data storage into the memory when the SAM- PLE IN I EHVAL switch is set to EXP. Storage will occur only when an external qualifying signal (from EXP TRIGIQUALIFIER or PROBE QUALIFIER) matches the CLOCK QUALIFIER switch setting. 15). The Memory StoreIDisplay mode is controlled by the Trigger circuit. rhe Trigger circuit controls the Store and Display modes of the Memory cirucit and the position of the displayed data realtive to the trigger. (The trigger point is shown on the display as an intensified zone.) The Time Base circuit provides the store clock (set by the SAMPLE INTERVAL switch) and the display clock signals used by the Memory circuit. An External Clock signal (from the Data Acquisition Probe) can also be selected by the SAMPLE INTERVAL switch. The Vertical Output circuit provides the parallel-to-serial conversion required to display the stored data on the crt. The vertical position and magnification of the display are adjusted by the VERT POS and MAG controls. The vertical offset between displayed channels is also generated by the Vertical Output circuit. The Horizontal Output circuit generates the horizontal- sweep and the crt-blanking waveforms for the display. The Cursor circuit provides an intensified zone on the display and a readout of the logic state (1 or 0) of each displayed channel. The position of the cursor on the display is set by the CURSOR COARSE and FINE POS controls. The cursor readout can be displayed in 3-bit or 4-bit bytes. The position of the cursor, relative to the trigger, is also shown on the crt readout. - REV OCT 1982 3- 1 -

DETAILED CIRCUIT DESCRIPTION Complete schematic diagrams are given in the Diagrams and Circuit Board Illustrations section in the rear of this manual. Re.fer to these diagrams throughout the following circuit description. FRONT PANEL WIRING @ The Front Panel Wiring diagram shows the front-panel controls, switches, indicators, and connectors and their connections to the circuit boards. Also shown are the inter- connecting cables and the connector numbers. The Word Recognizer performs three major functions; it provides the threshold voltage and input buffering for the data signals from the Data Acquisition Probe(s), and allows triggering of the 7D01 (andlor external equipment) on any preset, parallel-data "word" of up to 16 bits. The offset voltage is connected to the bottom of the probe input-signal attenuator (see Fig. 3-2) to change the effective comparison voltage of the probe comparator. Example: Using the offset voltage of -6.5 volts from the previous ex- ample, the effective comparison voltage (threshold voltage) can be calculated as follows: Threshold Voltage - (HI /R2) (Reference Voltage ----Offset Voltage) I (Reference Voltage) 1-hreshold Voltage 4 [-4.7- (-6.5)] r (4.7) - 4 (-4.7 t 6.5) -4.7 -- 1 2.5 volts Threshold Voltage Input Buffers The Threshold Voltage stage sets the dc offset voltage used by the Data Acquisition Probe. The THRESHOLD VOCI- AGE switch, S1275, selects either VAR or TTL threshold voltage for each probe. The wiper of R1270 is connected to R1274 and the MONITOR jack, J1274. The threshold volt- age is inverted, divided, and offset by U1276. The approxi- mate offset voltage at the output of U1276 can be calculated using the following formula: Offset Voltage - Reference Voltage- rhreshold Voltage . --- 4 The push-pull output signal from the probe comparator is connected through J110 or J115 to the lnput Buffer stage of the 7D01 Word Recognizer circuit. The lnput Buffer stage consists of U1215, U1218, U1224, U1234, U1236, and U1248. One output from each buffer is connected to the Memory circuit through P I 21 2, P I 21 3, P I 224, P I 225, P I 236, P I 237, P I 248, or P I 249. One output from the Channel 0 buffer is also connected to the Trigger Selector stage of the Word Recognizer circuit. Both outputs from each buffer are connected to the Word Selector stage. Example: Word Selector According to thls formula, the offset voltage for a i-2.5-volt threshold level (MOS) wlll be approxlrnately: The push-pull data slgnal from each Input Buffer IS connect- ed to the corresponding Word Recogn~zer channel swltch. (-4'7 -2i5) -4.7 = -6 5 volts. When a swltch IS set to the HI position, the inverted output Offset Voltage 4 of the corresponding buffer IS connected to one input of PROBE TIP V (REFERENCE) r - - - .1.^11___.1__ TWISTED PAIR :::;L . . . . . . . . . . . , . V (OFFSET) . . . . . . . . . . . . . . . . . . . --.-.-.....,.....-. . . . . , . . . . . . . . ............. INPUT-SIGNAL ATTENUATOR 2206-9 --" ---- -- . -" ... . .- ..... ........ ---- . - ... ........... . . Figure 3-2. Equivalent circuit for one channel of P6451 Data Acquisition Probe. A - REV OCT 1982 3-3

gate U1252 or U1254. When a switch is set to the LO posi- tion, the non-inverted buffer output is connected to the gate input. When the data signals for all the channels (including the PROBE QUALIFIER) match the positions of their re- spective channel switches, all of the inputs of gates U1252 and U1254 will be LO. The outputs of the gates (pins 15 and 2 of U1252 and U1254) and the output of EX-IERNAL QUALIFIER switch S1256 are connected together in a "wired-OR" configuratcwhen the inputs of the gates --- and S1256 are all LO, the word signal will be LO. The word signal is connected to the inputs of buffer U1262D, and to the D input of flip-flop U268B. At this point, the operation of the Word Recognizer depeends on the position of the W.R. MODE switch. ASYNCHRONOUS MODE. With the W.R. MODE switch, -. Sl260, set to ASYNC, the path for the word signal is through U1262D and U1262C. Buffer U12620 isolates the -- word signal from the Filter and output circuitry. The Filter circuitry consists of C1267, R1267. With the W5:MODE switch, S1260, set to ASYNC, the path for the word signal is through U1262D and U1262C. Buffer U1262D isolates -~~- the word signal from the Filter and output circuitry. The Fil- ter circuitry consists of C1267, R1267. With the W.R. m---. MODE switch, S1260, set to ASYNC, the path for the word signal is through U1262D and U1262C. Buffer U1262D iso- -n--.m lates the word signal from the Filter and output circuitryLk Filter circuitry consists of C1267, R1267ng edge of the word signal is the active edge, increasing the fall time effectively blocks any pulse narrower than the fall time (e.g., if the fall time is 200 nanoseconds, a 100-nanosecondmse would not pass to the output stage). The buffered word signal is then connected to one input (pin 10) of AND-gate U1262C. With the other input (pin 11) of U1262C held - HI by the W.R. MODE switch, U1262C passes the gated word signal to the output stage. SYNCHRONOUS MODE. With the W.R. MODE switch set to SYNC, the path for the word signal is through D-type flip- flop U268B. With the Reset input (pin 13) LO, the flip-flop is enabled. "['he Q output of U268B is set HI by a LO pulse from the Reset stage of the Trigger circuit. As long as the P word signal is HI, the Q output remains HI. When the word signal goes 10, the next rising edge of the external clock sync signal will drive the Q output LO. The Q output of U268B is connected to the output of U1262C through delay line DL 1262 to form a "wired-OR". Since the output of U1262C is held LO by the LO on pin 11, the 1-0 on the Q output of U268B will allow both outputs to drop to a L . 0 level. This LO signal (gated a signal) is connected to one input (pin 13) of U269C and to the Output stage. Output The Word Recognirer Output stage consists of two output amplifiers: (21208-(21212, and Q1201-(21204-Q1206. Tran- sistors Q1208 and (2121 2 provide a push-pull output signal to -- the mainframe I and - Trigger Out lines. When the gated word signal goes LO, Q1208 turns off and Q1212 turns on, driving --.-.-- plug-in connector pins A13 HI and 813 1.0. The gat- ed word signal is also connected to the base of Q1202. The LO signal increases current through Q1202, cutting off Q1204, and driving the base of Q1206 HI. Emitter-follower Q1206 drives the signal at the W.R. OUT connector HI. Trigger Selector The Trigger Selector stage consists of Q1254, Q1258, U1262A, U12628, (21262, and U269C. The signal connect- ed to the EX'P 'IRIGIQUALIFIER INPUT is compared to a i- 1.4-volt dc level by Q1254.21258. One output of (21254- (21258 is connected through EXT TRIG POLARITY switch S1258 to pin 6 of AND-gate U1262B. When TRIGGER SOURCE switch S1265 is in the EX7' position, the collector of Q1262 is HI. The HI on the collector of Q1262 enables U1262B, which couples the external trigger signal to the Trigger Output line (PI 13, pin 3). When the "'rRIGGER SOURCE swithc is in the CH 0 position, (21262 is cut off (collector LO), disabling U12628. The HI level at pin 5 of U1282A enables the gate which couples the CH 0 signal from pin 3 of U1215A to the Trigger Output line. When the TRIGGER SOURCE switch is in the W.R. (Word Recogniz- er) position, Q1262 is cut off and pin 12 of U269C falls - to a LO level. With pin 12 LO, U269C inverts the gated word signal and couples it to the 'Trigger Output line. MEMORY @ The Memory Circuit stores the input data in sixteen 256-bit RAM'S (random access memories) at a rate set by the Time Base circuit or external clock signal. 'The StoreIDisplay mode of the Memory circuit is controlled by the Trigger circuit. CLOCK QUALIFIER (SN 8086085 and up) The outputs of the Clock Qualifier stage, U1513, are con- nected in a wired-or configuration with the external store signal at pins 6 and 10 of U108A and U108B. All three sig- nals must be LO for data storage to occur. When the CLOCK QUALIFIER selector, S1501, is set to HI, U1513B is enabled, while U1513A is disabled and the clock qualifier signal is clocked into U1513B by the External Clock Sync line from U106C-14. When the qualifying signal is HI, the Q output of U1513B will be LO, allowing data storage. Circuit operation with the CLOCK QUALIFIER selector set L.0 is essentially the same, with the Q output of U1513A providing the qualifying signal. CR1504 disables both U1513A and U1513B when the CI. OCK QUALIFIER selector is set to OFF. REV OCT 1982

I STOREIDISPLAY CLOCK GATE I U110 INPUTS OU I PUT-S * ALSO PINS 12.3, AND 4 X INDICATES EITHER STATE Figure 3-3. Truth Table for Store/Display Clock Gate. U268B in the Word Selector stage of the Word Recognizer circuit. The outputs of U106A and U106B are also con- nected to pins 5 and 9 of gates U108A and U108B, respective1 y. When the SAMPLE INTERVAL switch is in the EXT posi- tion, the external store signal at pins 6 and 10 of U 108A and U108B is LO. With one input of each gate LO, thegates are enabled. (Pins 7 and 11 of U 108 are LO during Store mode.) 'I he output signal from U106A or U 106B is inverted and coupled through U108A or U108B. The outputs of U 108A. U 108B, U 1 1 OA, and U 1 1 OB are connected together in "wired-ORr' configurations. A HI output from any of the gates will drive the output lines HI. When the SAMPLE INTERVAL switch is not in the EX-P position, the external store signal is HI, disabling U108A and U108B. When the 7D01 is in the Store mode, the store signal from the 1 rigger circuit is HI. The store signal is connected to pin 10 of UIIOB and pin 6 of U136B. Exclusive-OR gate U136B inverts the store signal and connects i t to pin 7 of UIIOA and pins 7 and 11 of U108. When the store signal is HI, UIIOB is disabled and U1 1OA is enabled. U1 1OA couples the store clock signal from the Time Base circuit. - Latch Clock The Latch Clock, U 120, U 132A, and U 136A, strobes data into the Data Latch from the Data Selector. The timing of the Latch Clock output depends on the setting of the DATA CHANNELS switch. FOUR CHANNEL. Figure 3-4 shows the timing of the Latch Clock outputs for 4-channel operation. When DATA U l l O PIN 3, 12 Figure 3-4. Latch Clock timing for 4-channel operation. CHANNELS switch S1218 is set for 4-channel operation, pins 12, I I, and 9 of U 120 are held HI. When the Q2 out- put of U 120 (also connected to pin 10, function select input) is LO, the next rising edge of the clock transfers the data at the D0 through D3 inputs to the outputs. When the data from the DATA CHANNELS switch is transferred to the outputs, the 00, 01, and 0 2 outputs go HI (the D3 input is open or LO). A HI level at the S1 input (pin 10) sers U120 into the shift-left mode. Each rising edge of the clock signal moves the data a t each output of U120 to the next output, until the Q2 output returns to a LO level. This occurs every fourth clock pulse. Gate U132A produces a HI output when both the 0 3 output of U120 and the clock signal are LO. The output of U132A is connected through U136A to the clock inputs of the Data Latch stages. Buffer U136A delays the output of U132A to compensate for propagation delays through the circuitry. EIGHT CHANNEL. Figure 3-5 shows the timing of the Latch Clock outputs for 8-channel operation. When the DATA CHANNELS switch is set for 8-channel operation, pins 12 and 9 (D0 and D2) of U 120 are held HI. When the 0 2 output of U 120 is LO, the rising edge of the next clock pulse transfers the data a t the D0 through D3 inputs to the outputs. When the input data is transferred to the outputs, the Q0and Q2 outputs go HI. A HI level at the S1 input (pin 10) sets U120 into the shift-left mode. The next rising edge of the clock signal moves the LO level at the Q1 output to the 0 2 output. With the S1 input LO, U120 is again ready to transfer data from the inputs to the outputs on the next rising edge of the clock signal. The output of U132A is HI when both the Q3 output of U120 and the clock signal are LO. This occurs every second clock pulse.

U110 PIN 3, 12 r[ (CLOCK SIGNAL) Figure 3-5. Latch Clock timing for 8channel operation. SIXTEEN CHANNEL.. When the DATA CHANNELS switch i s set for 16-channel operation, all of the data inputs of U120 are held LO. With all the outputs of U120 LO, the output of U132A is HI when the clock signal is LO. Metmoly Selector The Memory Selector, U130, enables the output of each memory IC, in sequence, during the display time. When the store signal (pin 10) is HI, U130 operates as a 4-bit shift register. The data from Q2 of U 120 is connected to the DL input of U130 (pin 13). Each rising edge of the clock signal a t pin 4 shilis the data at the DL input to the 0 0 output and the data at each output (On) to the next output (On + 1 ). A LO level at an output enables the mem- ory ICs driven by that output (e.g., a LO at Q0enables U258, U358, U458, and U558). When the DATA CHAN- NELS switch is set for 4-channel operation, one output at a time is LO (see Fig. 3-6). In 8-channel operation, two out- puts are LO at the same time (see Fig. 3-7). In 16-channel operation, all four outputs are LO. During the store time, the sto%signal is LO, and all the outputs of U130 are LO. and LF Clock The WE (write enable not) and LF clock signals are the same frequency and polarity; the only difference is that the - WE signal is only active during the store time (store signal HI ). FOUR CHANNEL. When the D A I A CHANNELS switch is set for 4-channel operation, pin 7 of U132B and pin 11 of U132C are held HI, driving their outputs LO. Phe DATA CHANNELS switch also allows pin 11 of U136C and pin 12 PIN 3, 12 SIGNAL) Figure 3-6. Memory Selector timing for 4charinei operation (dis- play time only). of U136D to fall to a LO level. When the 0 1 output of U120 is HI, the outputs of U136C and U136D are HI. I he outputs of U136C, U132C, and U132D and the outputs of U136D and U132B are tied together in "wired-OR" config- - urations. I herefore, when the outputs of U136C and U136D go HI, t h e m and LF clock lines go HI, respectively. EIGHT CHANNEL. When the DATA CHANNELS switch is set for 8-channel operation, the W T and LF Clock stage operates the same as in 4-channel operation except that - pin 11 of U136C and pin 12 of U136D are held HI. When the 0 1 output of U 120 IS LO, the outputs of U 136C and U136D are HI - I - . -"- - - - - -" - --- --I PIN 3, 12 (CLOCK -s SIGNAL) I Figure 3-7. Memory Selector timing for 8-channel operation (dis- play time only). -

SIXTEEN CHANNEL. When the DATA CHANNELS switch is set for 16-channel operation, pin 7 of U1328, pin 11 of U 132C, pin 11 of U 136C, pin 12 of U 136D, and the Q l output of U120 are all LO. With both inputs of U136C and U136D LO, their outputs are LO. With one input of U 132B and U132C LO, the and LF clock lines will be HI when the clock signal (pins 6 and 10) is LO. When the store signal is LO (Display mode), the output of U132D is HI, holding the line HI. Address Counter The Address Counter, U 140 and U 150, selects the memory location where each data bit is stored. The Address Counter is a synchronous, &bit (+256) binary counter, which is reset to zero at the beginning of each store cycle. The A0 through A7 outputs are connected to each memory IC. Data Selector The Data Selector stage selects the channels, and arranges the data to be connected to the memory ICs through the Data Latch. The operation of the Data Selector depends on the setting of the DATA CHANNELS switch. FOUR CHANNEL,. When the DATA CHANNELS switch is set for 4-channel operation, pin 10 of U235 is held HI. With pin 10 HI, U235 functions as a 4-bit shift register. Channel 0 data connected to pin 13 of U235 i s shifted to the 0 0 output on the first rising edge of the clock signal at pin 4. The data at pin 13 moves through the shift register until the first data bit is a t the 0 3 output (four clock pulses). The shift register then has four data bits stored in sequence, ready to be read into the Data Latch. In 4-channel opera- tion, U225 is not used. EIGHT CHANNEL. When the DATA CHANNELS switch is set for 8-channel operation, pin 10 of U235 is LO and pin 9 of U225 is HI. With pin 10 held LO, U235 functions as a 4-bit latch. The channel 0 data connected to pin 12 of U235 is transferred to the Q0 output at pin 14 on the first rising edge of the clock signal at pin 4. The level at the 0 0 output is connected back to the D l input at pin 11 through pins 6 and 1 of U325. The next rising edge of the clock signal transfers the level at the DO input to the 0 0 output, and transfers the level that had been at the 0 0 output to the Q l output. The same operations occur with the channel 4 data at pin 9 of U235, resulting in two bits of channel 0 data ( 0 0 and Q1 outputs) and two bits of channel 4 data (02 and 0 3 outputs) stored in sequence, ready to be read into the Data Latch. SIXTEEN CHANNEL. When the DATA CHANNELS switch i s set for 16-channel operation, pin 9 of U225 and pin 10 of U235 are both LO. With pin 10 held LO, U235 functions as a 4-bit latch. With pin 9 of U225 held LO, the data from channel 8 and channel 12 is connected through pins 5 and 3 of U225 to the D l and D3 inputs of U235, respectively. Each rising edge of the clock signal transfers the data at the inputs of U235 to its outputs. Data Latch I"he Data Latch stage transfers the data from the outputs of the Data Selector to the inputs of the 4 x 256 Bit Memcry on the rising edge of the latch clock signal (pin 4). 4 X 256 Bit Memory The 4 x 256 Bit Memory consists of four RAM's (random access memories) and three gates. The RAM's (U252, U254, U256, and U258) are 256-bit memory units which can store one, two, or four channels of data, depending on how the data is presented by the Data Selector. If the DATA CHAN- NELS switch is set for 4channel operation, the 4 x 256 Bit Memory stores 1024 bits of data from channel 0. When set for 8-channel operation, the 4 x 256 Bit Memory stores 512 bits of data from channel 0 and 512 bits of data from chan- nel 4. When set for 16-channel operation, the 4 x 256 Bit Memory stores 256 bits each from channels 0,4, 8, and 12. The memory location where each bit of data is stored is controlled by the Address Counter. In the Display mode, a LO level on pin 5 enables the 0 out- put of each memory IC in sequence. The outputs of the memory IC's are combined by AND-gates U260A, U260D, and U260B, as controlled by the DA"T'A CHANNELS switch. In 4-channel operation, pin 5 of U260A, pin 12 of U260D, and pin 6 of U260B are HI. Therefore, the data from all four 0 outputs are connected to the channel 0 data output line (J120, pin 13). In 8-channel operation, pins 5 and 6 (U260A and U260B) are HI. With pins 5 and 6 of U260 HI, the outputs of U252 and U254 are connected to pin 13 of J120 and the outputs of U256 and U258 are con- nected to pin 4 of J120 (channel 4 data output line). In 16-channel operation, pins 5, 12, and 6 of U260 are all LO; therefore, the data at the output of U252 is connected to the channel 0 data output line, the output of U254 is con- nected t o the channel 8 data output line, etc. TRIGGER @ The Trigger circuit controls the Store and Display modes of the 7D01 and the position of the displayed data relative to the trigger. Auto Record The Auto Record stage controls the time that a display is presented before the 7D01 returns to the Store mode. The display time is set by the DISPLAY TIME control, R605. Capacitor C606 charges through R604 and R605. After

approximately one time constant, 0606 conducts, discharg- ing C606 and pulling pin 4 of U610A LO. When pin 4 of U610A is LO, pin 3 is HI. The HI a t pin 3 of U610A sets the 0 output (pin 15) of U621B HI and resets thenoutput (pin 3) of U621A HI. 'The n o u t p u t of U621A is connected back to the emitter of 0602. A H l at the emitter of 0602 causes 0602 and 0604 to conduct, disabling the timing circuit for 0606. Therefore, 0606 only operates when the 7D01 is in the Display mode (pin 3 of U621A LO). A HI level pulse a t pin 3 of U610A can also be obtained by pressing the MANUAL push button, S606. NOR-gates U608C and U608D are connected as a set-reset flip-flop, which prevents contact bounce in S605A from affecting the rest of the circuitry. When S605A is pressed, pin 12 of U608D goes HI and pin 10 of U608C goes LO. rhe result- ant LO on pin 15 of U608D is connected to pin 5 of U610A, producing a HI level at pin 3. Trigger Latch The Trigger Latch stage, U615A and U615B, latches on the first trigger signal after reset when P617 is in the First Trig- ger (lower) position, or after reset and one full memory cycle when P617 is set for Full Data (upper position). The trigger signal is connected to pin 6 of U615A. If the reset signal (pin 4) and the trigger disable signal (pin 9) are both LO, the trigger signal clocks the HI level at the data (D) input of U615A to the 0 output (pin 2). The 0 output of U615A is connected to the base of 0620 and the D input of U615B (pin 10). When the 0 output goes HI, 0620 turns on, lighting LED (light-emitting diode) DS620. The HI from the 0 output of U615A is also clocked into U615B on the next rising edge of the hf clock signal (pin 1 I ) , driving the 8 output (pin 14) LO. "Trigger L F ( L o w Frequency) Clock 'The LO level at the aoutput of U615B enables the Trigger LF Clock stage (U611B, U611C, U622, and U608B), which divides the hf clock signal by 4, 2, or 1, depending on the position of the DATA CHANNELS switch. FOUR CHANNEL. When the DATA CHANNELS switch is set to 0-3, the D0, D l , and D2 inputs of U622 are all HI. When the S1 input is LO, the shift register loads the data a t the DQI, D l , and 02 inputs to the 00, 01, and 0 2 outputs, respectively. With the 0 2 output (and therefore the 51 input) HI, the shift register returns to shift-left operation and starts clocking in LO'S from the DL input on the rising edge of the HF clock signal. When the LO from the DL input reaches the 0 2 output (and the S1 input), the shift register loads the HI data from the D0, D l , and D2 inputs. This full cycle requires four HF clock pulses, resulting in a trigger LF clock which is one-fourth the frequency of the HF clock (one clock period HI, three clock periods LO). EIGHT CHANNEL. When the DATA CHANNELS switch is set to 0-8, the D0 and D2 inputs of U622 are HI and the D l input is LO. The first clock pulse loads the data into the shift register, driving the 0 2 output and the S1 input HI. With the S1 input HI, the shift register returns to shift-left operation. The next clock pulse shifts .the LO a t the DL in- put to the 0 8 output and the LO at the 0 1 output to the 0 2 output. The LO at the 0 2 output and the S1 input puts the shift register back into load operation. The third clock pulse loads the data at the D0, D l , and D2 inputs to the outputs. The complete load-shift operation requires two clock pulses, resulting in a trigger LF clock signal which is one-half the HF- clock frequency. SIXTEEN CHANNEL. When the DATA CHANNELS switch is set to 0-15, the D0, D l , and D2 inputs of U622 are all LO, holding the 00, Ql, and 0 2 outputs LO. The HF clock signal is then connected to the trigger LF clock line through U617B (input pins 10 and 11 are both L0,enabling U617B). Trigger Position Counter The 'Trigger Position Counter determines the position of the displayed data, relative to the trigger signal, by providing a delay between the triggering event and the start of Display mode. (If Display mode started immediately after the trigger signal, the memory would contain only data which had been stor- ed before the trigger signal. By delaying the start of Display mode, the memory will contain data stored before and after the trigger signal.) Counters U623 and U624 are loaded with a preset binary number when the S2 inputs are LO. When the trigger signal drives the Q output of U615A (pin 2) HI, the em,--"-, counters start counting trigger LF clock pulses until the C out output of U624 (pin 4) goes LO. 'The LO level at pin 4 of U624 is connected to one input (pin 7) of U632B and to the D input (pin 10) of U619B. Gates U632'gIk~d U632C prevent a very short duration "glitch" on the C out line from being coupled to the rest of the circuit. ~".--**" When the C out output of U624 (pin 4) is LO and the Q0 output (pin 14) is HI, t h e 5 output of U619B (pin 14) is reset HI. The next trigger LF clock pulse clocks the LO level a t the D input (pin 10) into flip-flop U619B, holding the^ P output HI. At this point, the C out output of U624 goes HI and the Q0 output goes LO, resulting in a LO a t the output of U632B (pin 3). With the D input of U619B HI, the next trigger LF clock pulse drives the input (pin 14) back LO. Therefore, the 8 output of U619B goes HI for two trigger LF clock pulses on the terminal count of U624 (all 0 out- puts HI). REV OCT 1982

StoreIDisplay Flip-Flop - When the Boutput of U619B goes HI, the next memory LF clock pulse drives the O output of U619A (pin 2) HI. When the Q output of U619A goes HI, the Q output of U621A (pin 2) is driven HI and the aoutput (pin 3) is driven LO, switching the memory from Store mode to Display mode. The next reset pulse from the Q output of U621 B (pin 15) resets the output of U621A back LO. Trigger Disable FULL DISPLAY. Dual flip-flop U740 prevents the Trigger circuit froni accepting a trigger signal before the Memory circuit has gone through one full store cycle to ensure that - all the data in the memory is new data (data stored during the current store cycle). The Q output of U740A (pin 2) is set HI by the reset pulse applied to the set input (pin 5). _ The HI level at the Q output (pin 2) disables U615A and U615B. I he Q output of U740A (pin 2) stays HI until the LO pulse on the Address Count Carry line toggles U740A. FIRST TRIGGER. The Trigger Disable function can be defeated by moving P617 to the First Trigger (lower) posi- tion. With P617 in the First Trigger position, any data remaining in the memory from a previous store cycle will be blanked out on the display. If the output of U632B goes --" HI before the Address Count Carry pulse arrives at the clock input of U740 (pin 91, the Q output of U740B (pin 15) is set HI, disabling the unblanking stage of the Horizontal Output circuit. This keeps the display blanked until the ------- Address Count Carry pulse switches the Q output (pin 15) LO again, allowing the data to be displayed on the crt. Trigger Intensify "l'he trigger point is shown on the display by an intensified zone, generated by U625 and 0628. Quad exclusive-OR gate U625 detects when the output states of U624 match the data which was loaded into U624 when the unit was triggered. When the outputs of U624 match the data on pins 2,3, and 4 of P632, the output of U625 goes LO. I'he LO signal at the output of U625 turns Q628 on, resulting in an intensified zone on the display. 'The amount of increased intensity can be adjusted by R625. TIME BASE @ The Time Base circuit generates the store clock and display clock signals. The Time Base circuitry consists of a 100MHz Oscillator, a series of counters with divide-by-two and divide- by-five outputs, and data selectors. The 100 MHz Oscillator is controlled by crystal Y800. The output of the 100 MHz Oscillator is connected to data selector U820 and to the input of divide-by-two and divide-by-five counter U810. The store clock signal is selected from the outputs of the frequency-divider counters by the data selectors. The SAM- PLE INTERVAL switch sets the "address" of the desired counter output. rhe display clock signal is taken from the 0 0 (2 ps) output of counter U814. VERTICAL OUTPUT @ The Vertical Output circuit provides the parallel-to-serial conversion and channel offset required to display the stored data on the oscilloscope crt. Channel Counter The Channel Counter, U628, U632A, and U632D, deter- mines the data channel to be coupled through the Parallel- to-Serial Converter to the Vertical Output Amplifier. Four- bit counter U628 counts flag pulses from the Trigger circuit. The output of the Channel Counter depends on the format selected by the DATA CHANNELS switch (shown in Diagram 3). When set for 4-channel operation, pin 12 of U632D and pin 5 of U632A are both HI. A HI level on pin 12 of U632D drives pin 9 HI and pin 15 LO. The HI level on pin 5 of U632A drives pin 2 LO. When set for 8-channel operation, only pin 12 of U632D is HI, holding pin 9 HI and pin 15 LO. The Q2 output of U628 is inverted by U632A. When set for 16-channel operation, pin 12 of U632D and pin 5 of U632A are both LO. The Q2 output of U628 is inverted by U632A. 1 he Q3 output is coupled through U632D to pin 9 and is inverted at pin 15. Parallel-to-Serial Converter The Parallel-to-Serial Converter, U570 and U572, i s actually a 16-channel data selector. The data channel to be connect- ed to the Q output (pin 15) i s determined by the binary count on the address (pins 7, 9, and 10) and enable not (m) lines. Refer to Figure 3-8 for the relationship between the binary output of U628 and the data channel selected by the Parallel-to-Serial Converter. Figure 3-8. Binary output of U628 versus channel displayed.

Channel Offset T'he Channel Offset stage provides the vertical offset fpr each channel of data displayed on the crt of the osci(ljo- scope. The amount of offset is determined by the binaty count at the output of the Channel Counter. Each of (he four output lines control one of the Channel Offset 4 m - and the amount of current each comparator i s Vertical Output Amplifier 1 I'he Vertical Output Amplifier combines the data and channel offset srgnals, and provides a push-pull output signal for the oscilloscope mainframe. The data signal from U570l U572 is coupled through 0676 and 0678 to the base of 0684. 1 he vertical position of the display is set by VERT POS control R680, which controls the offset current through 0694. 'I ransistors 0682 and 0684 convert the single-ended srgrtal a[ the base of 0684 to a push-pull output srgnal at plug-in connector pins A1 1 and B11. HORIZONTAL OUTPUT @ The Horizontal Output circuit generates the X-axis (sweep) and Z-axis (blanking) signals needed to produce a display on the crt of the associated oscilloscope. Sweep Generator When the flag signal (base of (2732) is HI, Q732 and Q750 conduct, discharging (2750. When the flag signal drops, Q732 and Q'750 stop conducting and allow C750 to start charging in a linear negative ramp. I he charge rate of C750 is determined by the current through Q722, which is set by R714, R715, andior R118. Transistors Q714 and Q718 cie- termine whether R714 and/or R715 are in the circuit, de- pending on the position of the D N A CHANNELS switch, S1218. The negative-going ramp is buffered by U752 and coupled through R783 to the emitter of (2784. The position offset current, set by HORIZ P6S control R790, is also cou- pled to the emitter of (2784. The ramp signal is connected through,W84 to the base of Q764. Transistors Q762 and Q764 cdvert the single-ended ramp signal to a push-pull output.bignal at plug-in connector pins A1 1 and B11 to drive the oscilloscope mainframe. Blanking The Blanking stage provides retrace blanking for the display, and blanks the display during Store mode. When the flag pulse goes HI (during display time), the output of U608A (pln 2) goes LO. 1 he LO signal at the output of U608A is coupled through 0744 and 0748 to produce a LO pulse a t plug-in connector pin A l . This blanks the display during retrace. During store mode, the HI level at the base of 0738 drives the base of 0740 HI. With the base of 0740 HI, the collector of 0740 is LO. The LO signal at the collector of 0740 results in a LO pulse at plug-in connector pin A l , which blanks the display. Invalid Mode lndicator I'he Invalid Mode lndicator causes the light bulb behind the SAMPLE INTERVAL switch to blink on and off if the switch is set to a position which exceeds the maximurrr operating speed of the Memory circuit. This occurs when the SAMPLE INTERVAL switch is set to 10 ns or 20 ns during 16-channel operation, or is set to 10 ns during 8- channel operation. Either of these switch combinations cause astable multivibrator 0702-0704 to oscillate. Transis- tor 0708 is driven by the output a t the collector of 0704. When the base of 0708 goes LO, light DS708 turns off. CURSOR @ "1 he Cursor circuit provides an intensified zone on the dis- play and a readout of the logic state (1 or 0) of each dis- played channel a t the cursor position. 1 he position of the cursor on the display is set by the CURSOR COARSE and FlNE POS controls. The Cursor readout can be displayed in 3-bit or 4-bit bytes. The position of the cursor, relative to the trigger, is also shown by the crt readout. Cursor Counter I he CURSOR Positlon controls (COARSE and FlNE POS) are rotary swltches which produce a sequence of pulses for each step. The order of the pulses depends on the dlreciion of switch rotation. I"he output of the FlNE POS switch IS decoded by NAND-gdes U1322 (A, 5, C, and D) to produce a LO pulse on one outpurand a HI level on the other I he outputs (plns 10 and 11) are buffered by U1344C and U1344D and connected to the Count Up and Count Down inputs of UL346& Ihe Carry and Borrow outputs of U1346 are connected through U1344A and U1344B to the Count Up and Count Down Inputs of U1356, along with the out- puts from U1352C and U1352D. The binary count on U 1346, U 1356, and U 1366 changes in Increments of one count for each step of the FINE POS control, or Incre- ments of sixteen counts for each step of the COARSE control The flag pulse from the 1 rigger circuit is connected to the base of 01304, which inverts the flag pulse signal. 'The in- verted flag pulse is buffered by U1322C and ac-coupled to the CountILoad inputs (pin 1) of U1348, U1358, and U1368. The CountlLoad inputs are normally held HI (count) by R1361-R1363. The falling edge of the inverted flag pulse drives the CountlLoad inputs LO (load) to load the count on U 1346, U 1356, and U 1366 into U 1348, U 1358, and U 1368. Counters U 1348, U 1358, and U 1368 REV OCT 1982

then start counting gated display clock pulses from the out- put of U1322B. l he outputs of U1348 and U1358 are connected to the inputs of gate U1372. The A and B out- puts (pins 5 and 9) of U1368 are connected to U1372 through gates U1370B and U1370A. During 4-channel ---- --- operation, both U1370A and U1370B are enabled to pro- vide a maximum count of 1024. Dur~ng 8channel opera- tion, the collector of 01302 is LO, disabling U1370A to prov~de a maximum count of 512. During 16-channel operation, the collector of 01372 IS LO, disabling U1370A and U1370B to provide a maximum count of 256. When all Inputs to U13/2 are HI, ille output (pln 9) goes LO. The LO output of U1372 is inverted by U1334D which turns on 01376. fhe current through 01376 causes the crt display to intensify, providing the cursor intensified zone. I he relative Intensity of the cursor intensified zono is controlled by Cursor Intensity adjustment R1375. Cursor Position Readout The position of the cursor (relative to the trigger) is dis- played by the crt readout on the top of the crt. "Phe cursor position is the number of gated display clock pulses be- tween the trigger location and the cursor position, with a plus or minus sign determined by which pulse occurred first. Four-Decade Counter U1338 and flip-flop U1328B are reset by the flag pulse from the rrigger circuit (through 01304, U 1322C, and U13220). The first 7GG-r- pulse from the Trigger circuit, or the first z v pulse from the output of U 13320, will be coupled through exclusive-OR gate U1322A to the clock input (pin 11) of flip-flop U1328B. The pulse at pin 11 of Ul328B sets the 0 output (pin 9) HI and the ~ o u t ~ u t (pin 8) LO. The HI level on the 0 output of U1328B enables gate U1332A which starts coupling gated display clock pulses to the four- .---- decade counter, U1338. The second pulse (trigger location or cursor position) to arrive at U1322A clocks the 0 output of U1328B back LO, disabling U1332A and stopping the count on U1338. When the 0 output of U1328B switches LO, the n o u t p u t switches HI. The rising edge of the signal at theFoutput of U1328B is coupled through C1328 to the Transfer input (pin 10) of U1338, which transfers the count to the output latches in U1338. The A0Output (pin 6) of U1338 is a current signal for the mainframe crt read- out system during readout time slots 8, 9, and 10 which provides the digits of the Cursor Position readout display (top of crt). The current reference for the output of U1338 is adjusted by R1335. The characters "T'K IG" and a space are generated during timeslots 1, 2, 3,4, and 5 (e.g., "T" is selected by R 1381 and R 1391, "K" is selected by R 1382 and R1396, etc.). The "+" or "--" sign is selected by the state at theaoutput (pin 6) of U1328A during time slot 6. Flip-flop U1328A is clocked by the rising edge of the O output of U1328B. If the cursor position pulse occurs be- fore the trigger location pulse, the D input (pin 2) of U1328A is HI, resulting in a LO at the.Eoutput (pin 6) of U1328A. 'The LO at the T o u t p u t of U1328A turns on -- 01487, producing a "--" sign. If the trigger location pulse occurred first, the a output would be HI, producing a ".+" sign. REV OCT 1982 Cursor Data Readout The serial data signal is inverted by 01316 and coupled to the A input (pin 1) of U 1402. 'The cu?sorposiToi pulse clocks the logic level present at the A input into shift- register U1402. ]"he next ~ ~ ~ s pulse clocks in the logic level from the next channel, until both U1402 and U1408 are filled with data. (Each shift-register output will contain the data at the cursor position from one channel.) The frame pulse (flag + 16) is coupled by 01412 and U1370C to the clock inputs of latches U1422, U1438, U1454, and U1470. The ffame pulse clocks the data at the outputs of U1402 and U1408 to the outputs of the latches. Because the serial data signal was inverted by 01316, the data a t the outputs of the latches will also be inverted. When the output oka latch is LO, a "1" will be selected by the common-base transistor connected to the latch output and the "associated resistors. During 16-channel operation, all sixteen bits are displayed. Curing 8-channel operation, the gate of 01484 is held HI, cutting off the readout signals for channels 8 through 15. During 4-channel operation, the gate of 01484 is HI and the gate of 01436 is HI, cutting off the readout signals for channels 4 through 15. The Cursor Data readout is separated into groups of 4 or 3 bits each. 'The grouping of the Cursor Data is set by BY7^E SELECT jumper P I 493 (BYTE switch S1493, SN B079999 and below) which controls MOS switches U1494 and U 1492C, and U1492D. The MOS switches are electrically closed when the control pin to each switch is H I (ground). - I he MOS switches select the time slots to be used for each Cursor Data bit. Flip-Flop U1410A blanks the Cursor Data readout if the cursor is positioned to the blanked area of the crt display. If the cursor is positioned to a bit which is not displayed on the crt, the sweep gate signal will be LO when the cursor posi- tion pulse occurs. With the Data input (pin 2) of U1410A LO, the cursor position position pulse will clock a LO to the Q output (pin 5) of U141 OA, turning off Q1486 and cutting off (21484, Q1452, and Q1436. The crt display and readout are both blanked during Store mode because no valid information is available a t that time. When the store signal from the Trigger circuit is HI, 01497 and 01498 are on, pulling the collector of 01498 HI and cutting off 01484, 01452, 01436, and 01488. If the 7001 is being used in a four-compartmentmainframe, the Aux Z-Axis signal is inhibited when the B-horizontal compartment is selected, or when the A-horizontal com- partment is being locked out by the mainframe. If the B-horizontal compartment is being displayed, the output of U610C will be HI, cutting off Q1418 and MOS switch U1492B. If the A-horizontal compartment is locked out, the sweep lockout signal will be HI, cutting off 01416 and U1492B.

A holdoff signal to the mainframe is produced by U1410B, 01404, and 01406. The frame pulse toggles the output of U1410B. The output of U1410B is buffered by 01404 and Q1406 and connected to the mainframe. POWER SUPPLIES @ The 7D01 uses the regulated +15, 15, and +5-volt power supplies from the oscilloscope mainframe, and derives the -2 and 4.8-volt supplies from the + I 5 and - 15-volt power supplies. DC-DC Inverter The DC-DC Inverter converts power from the + I 5 and -- 15- volt power supplies to a high-frequency (approximately 25 kHz) square wave. This square wave is applied to the primary winding of a stepdown transformer. The outputs of the transformer are full-wave rectified and filtered to provide the -4.8-volt supply and a regulated --2-volt supply. The 25-kHz drive for the inverter is provided by U918. The frequency and duty cycle are determined by R918, C918, and R919. The output of U918 is coupled through R921 and C921 to the primary winding of T922. The two secon- dary windings of T922 are connected to the inverter power transistors, 0926 and 0928 which drive The center-tapped primary winding of inverter transformer T"942. The four secondary windings of T942 are connected to- gether to form two center-tapped outputs. The outputs are then full-wave rectified and filtered. "Che filtered dc output from one pair of secondary windings provides the 4.8-volt supply. 1 he filtered dc output from the other pair of secon- dary windings is regulated to -2 volts by 0963, 0964, and 0968. Overload protection for the -2 and -4.8-volt supplies is pro- - vided by (2903, Q910, and multivibrator U912. If the -2 or - 4.8-volt supply falls toward ground, Q903 or Q910 turns on, turning Q908 off. With Q908 off, multivibrator U912 disables U918 for approximately 112 second, then allows it to run for - approximately 10 milliseconds. (Under normal load condi- tions, the -2 and -4.8-volt supplies will stabilize in less than 10 milliseconds.) When the loads on the -2 and -4.8-volt supplies are returned to normal, Q903 and Q910 are both off, and Q908 is conducting. With Q908 conducting, multivibrator U912 is disabled and U918 is allowed to run - normally. REV OCT 1982

MAINTENANCE Th~s section of the manual contains information for performing preventive maintenance, troubleshooting, and corrective maintenance. PREVENTIVE MAINTENANCE Preventive maintenance consists of cleaning, visual inspection, lubrication, etc. Preventive maintenance performed on a regular basis may prevent instrument breakdown and will improve the reliability of the instrument. The severity of the environment to which the instrument is subjected determines the frequency of maintenance. A convenient time to perform preventive maintenance is preceding adjustment of the instrument. CLEANING 'Phe instrument should be cleaned as often as operating con- ditions require. Accumulation of dirt on components acts as an insulating blanket and prevents efficient heat dissipa- tion which can cause overheating and component breakdown. A void the use of chemical cleaning agents which migh t damage the plastics used in this instrumen t. In particular, avoid chemicals that contains ben- zene, toluene, x ylene, acetone, or similar solvents. Exterior Loose dust accumulated on the front panel can be removed with a soft cloth or small brush. Dirt that remains can be removed with a soft cloth dampened in a mild detergent and water solution. Abrasive cleaners should not be used. Interior Dust in the interior of the instrument should be removed occasionally due to its electrical conductivity under high- humidity conditions. The best way to clean the interior is to blow off the accumulated dust with dry, low-pressure air. Remove any dirt which remains with a soft brush or acloth dampened with a mild detergent and water solution. A cotton-tipped applicator is useful for cleaning in narrow spaces. VISUAL INSPECTION The instrument should be inspected occasionally for such defects as broken connections, improperly seated semicon- ductors, damaged circuit boards, and heat-damaged parts. The corrective procedure for most visible defects is obvious; however, particular care must be taken if heat-damaged components are found. Overheating usually indicates other trouble in the instrument; therefore, it is important that the cause of overheating be corrected to prevent recurrence of the damage. LUBRICATION Generally, there are no components in the instrument that will require lubrication during the life of the instrument. Toggle Switches These switches are lubricated and sealed prior to leaving the factory, and cannot be repaired. If a switch becomes electri- cally noisy or otherwise defective, it should be replaced. Part numbers are given in the Replaceable Electrical Parts list for ordering these switches. Cam Switches In most cases, the factory lubrication of these switches should be adequate for the life of the instrument. T'he switch contacts are designated to operate dry for the life of the switch. If the switch has been disassembled for replacement of switch sub-parts, a lubrication kit containing the necessary lubricating materials and instructions is available through any Tektronix Field Office. Order Tektronix Part 003-0342- 01. General Electric Versilube @ silicone grease may be applied sparingly so that the lubricant does not get on the contacts. Refer to Figure 4-1 for lubrication instructions.

SEMICONDUCTOR CHECKS a Apply lubricant to the drum journals and mating surface in the mounting bearings. @ Apply lubricant to the wear surface of the index wheel. (j) Apply lubricant to the index roller and roller guide in the front bearing. A thin film should be applied to the inner face of the detent springs if more than one spring is replaced. @ Ensure that some lubricant is present at the interface between the bearing and retainer clip. Figure 4-1. Lubrication procedure for a typical cam switch. Periodic checks of semiconductors in the instrument are not recommended. The best check of semiconductor performance is actual operation in the instrument. More details on checking semiconductor operation are given under trou bleshooting.

TROUBLESHOOTING The following information is provided to help troubleshoot the instrument. Information contained in other sections of the manual should be used along with the following information to aid in locating the defective component. An understanding of the circuit operation is very helpful in locating troubles, particularly where integrated circuits are used. TROUBL ESHOOTING EQUIPMENT I-he following equipment, in addition to that listed in the Performance Check and Adjustment section, is useful for troubleshooting the 7D01 Logic Analyzer unit. Transistor Tester Description. Dynamic-type tester Purpose: Test setmiconductors. Recommended Tektronix types: 576 Curve Tracer, 5771177 Curve Tracer system, 7CTlN Curve I racer unit and a 7000-series oscilloscope system, or a 5CT1 N Curve I'racer unit and a 5000-series oscilloscope. - Multiimeter - Description. Voltmeter, 10 megohm input impedance and a range from 0 to a t least 50 volts dc, accuracy, w~thin 0.1%. Ohmmeter, 0 to 20 megohms. rest probes should be insulated to prevent acc~dental short~ng. Purpose: Check voltage and resistance. Test Oscilloscope Description: Frequency response, dc to 100 megahertz minimum; vertical deflection factor, 5 millivolts to 5 volts/- - division. A IOX, 10 megohm voltage probe should be used to reduce circuit loading. Purpose: Check operating waveforms. Plug-In Extender Description: I wo types of extenders are available. 1. Flexible Plug-In Extender. Tektron~x Part 067- 0616-00 (two required). 2. Rigid Plug-In Extender. Tektronix Part 067- 0589-00 (two required). Purpose: Allows plug-~n operation outside the mainframe. TROUBLESHOOTING TECHNIQUES Troubleshooting Procedure This troubleshooting procedure is arranged to check the simple trouble possibilities before proceeding with extensive troubleshooting. 1 he first few checks ensure proper connec- tion, operation, and adjustment. If the trouble is not located by these checks, the remaining steps aid in locating the defective component. When the defective component is located, i t should be replaced using the replacement proce- dure given under Corrective Maintenance. 1. CHECK CONTROL SETTINGS. Incorrect control settings can indicate a trouble that does not exist. If there is any question about the function or operation of any con- trol, see the Operating Instructions section. 2. CHECK ASSOCIATED EQUIPMENT. Before proceed- ing with troubleshooting, check that the equipment used with this instrument i s operating correctly. Check that the signal is properly connected and that inter-connecting cables are not defective. Also check the power source. If the trouble persists, this instrument is probably at fault. 3. VISUAL CHECK. Visually check the portion of the instrument in which the trouble is located. Many troubles can be located by visible indications such as unsoldered connections, broken wires, damaged circuit boards, damaged components, etc. 4. CHtCK INST HUMENT ADJUSTMENT. Check the adjustment of this instrument, or the affected circuit if the trouble appears in one circuit. The apparent trouble may only be a result of misadjustment. Complete adjustment instructions are given in the Performance Check and Adjust- ment section. 5. ISOLATE TROUBLE TO A CIRCUIT. To isolate trouble to a circuit, note the trouble syrrrptom. The symp. tom often identifies the circuit in which the trouble is located. When trouble symptoms appear in more than one

circuit, check the affected circuits by taking voltage and waveform readings. Also check for the correct output sig- nals at the front-panel connectors with a test oscilloscope. Incorrect operation of all circuits often indicates trouble in the power supply. Check for correct voltages of the indivi- dual supplies. A defective component elsewhere in the instrument can appear as a power-supply trouble and may also affect the operation of other circuits. 6. CHECK VOLTAGES AND WAVEFORMS. Often the defective component can be located by checking for the correct voltage or waveform in the circuit. Refer to check 9 (Check Power Supplies). 7. CHECK INDIVIDUAL COMPONENTS. The following procedures describe methods of checking individual compo- nents. Two-lead components that are soldered in place are best checked by first disconnecting one end. This isolates the measurement from the effects of surrounding circuitry. C A U T I O N 7b avoid component damage, disconnect the power source before removing or replacing semiconductors. Transistors. A good check of transistor operation is actual performance under operating conditions. A transistor can be effectively checked by substituting a new component or one that has been checked previously. However, be sure that circuit conditions are not such that a replacement transistor might also be damaged. If substitute transistors are not available, use a dynamic tester. Static-type testers are not recommended, since they do not check operation under simulated operating conditions. Integrated Circuits. IC's (integrated circuits) can bechecked with a voltmeter, test oscilloscope, or by direct substitution. A good understanding of circuit operation is desirable when troubleshooting circuits using IC's. Use care when checking voltages and waveforms around the IC's so that adjacent leads are not shorted together. A convenient means of clip- ping a test probe to the 14- and 16-pin IC's is with an IC test clip. This device also serves as an extraction tool. The lead configuration for the semiconductors used in this instrument are shown on a pullout page in the front of the diagrams section. Pin 1 of the IC is indicated by a square pad on the back of the circuit board. Diodes. A diode can be checked for an open or shorted condition by measuring the resistance between terminals with an ohmmeter scale having a low internal source cur- rent, such as the R X l K scale. rhe resistance should be very high in one direction and very low when the meter leads are reversed. Do not use the ohmmeter on a scale that has high internal current. High currents may damage the diode. The cathode end of each glass-encased diode is indicated by a stripe, a series of stripes, or a dot. The cathode and anode ends of metal-encased diodes are identified by the diode symbol marked on the case. Resistors. Check resistors with an ohmmeter. See the Re- placeable Electrical Parts list for the tolerance of the resis- tors used in this instrument. Resistors normally do not need - to be replaced unless the measured value varies widely from that specified. - Inductors. Check for open inductors by checkingcontinuity _ with an ohmmeter. Shorted or partially shorted inductors can usually be found by checking the waveform response when high-frequency signals are passed through the circuit. Partial shorting often reduces high-frequency response (roll off). Capacitors. A leaky or shorted capacitor can usually be detected by checking resistance with an ohmmeter on the - highest scale. Do not exceed the voltage rating of the capa- citor. The resistance reading should be high after initial charge of the capacitor. An open capacitor can best be de- - tected w ~ t h a capacitance meter or by check~ng ~f the capacitor passes ac signals. 8. REPAIR AND ADJUST. If any defective parts are lo- cated, follow the replacement procedures given in Correc- - tive Maintenance. Be sure to check the performance of any circuit that has been repaired or had any electrical compo- nents replaced. 9. CHECK POWER SUPPLIES. If incorrect operation of - the power supply is suspected, perform the following checks in the order listed. ,Y"-zJ ) C A U T I O N 2 - To avoid equipment damage, disconnect the power source before performing the cable continuity check. -

Cable Continuity Check. Connect the leads of an ohmmeter NOTE 1 between the following test points to determine the inter- connecting cable dc continuity (set the ohmmeter sensitivity on the R X 1 scale). Use a dc voltmeter with 0.1 % accuracy to check each supply voltage, and check ripple with a test oscilloscope. Vol rages are measured be tween A the power supply test poin ts and chassis ground. Check that each power supply vol tage is within the range given in Table 4- 7. The mainframe a. Check for dc continuity from pins 1 and 2 of P933 on provides &e + 75, - 15, and +5 volt supplies. -- the Power Supply board to the +15 V test point on the The other two supply voltages (-2 V and -4.8 V) lnterface board. See Figure 4-2 for circuit board locations. are generated within the 7007. b. Check for dc continuity from pins 3 and 4 of P933 of the Power Supply board to the -1 5 V test point on the Interface board. See Figure 4-2 for circuit board locations. Operating Voltages Check. Connect the 7D01 Logic Analy- zer to the mainframe via two plug-in extenders, and apply power. Load the power supply as follows: a. Connect the probe(s) to the 7D01 front-panel connectors. b. Set the RECORD control fully clockwise (detent) into the * position. c. Press the MANUAL TRIGGER button; a display should appear on the mainframe crt. +5 V TEST POINT R916 100 52 TABLE 4-1 Power Supply ~olerances' Figure 4-3. Power supply +5 volt test point location. - ' Checked under full load (refer to text). -\ Test Point Location Interface Board Power Supply Board Test Point TP 982 TP 986 See Fig. 4-3 TP 968 TP 948 . Output Voltage Range Approx. + 1 5 V Approx. -1 5 V Approx. +5 V -1.9 to -2.1 V -4.8 to -4.925 V Power Supply Approximate Ripple Pea k-to-Peak 50 mV . 100 mV Mainframe 7001 +15 V -15 V +5 V -2 V -4.8 V

CORRECTIVE MAINTENANCE Corrective maintenance consists of component replacement and instrument repair. Special techniques required to replace components in this instrument are given here. OBTAINING REPLACEMENT" PARTS All electrical and mechanical part replacements can be obtained through your Tektronix Field Office or represen- tative. However, many of the standard electronic compo- nents can be obtained locally in less time than is required to order thein from rektronix, Inc. Before purchasing or ordering replacement parts, check the parts list for value, tolerance, rating, and description. NOTE When selecting replacement parts, i t is important to remember that the physical size and shape of a component may affect its performance in the instrumen t, particularly at high frequencies. All parts should be direct replacements unless it is known that a different component will not ad- versely affect instrument performance. Some parts are manufactured or selected by Tektronix, Inc. to satisfy particular requirements, or are manufactured for -I.ektronix, Inc. to our specifications. Most of the mechani- cal parts used in this instrument have been manufactured by Tektronix, Inc. To determine the manufacturer of parts, refer to parts list, Cross Index Mfg. Code Number to Manufacturer. When ordering replacement parts from Tektronix, Inc., include the following information: 1. lnstrument type. 2. lnstrument serial number. 3. A description of the part (if electrical, include circuit number). 4. I'ektronix part number. To avoid electrical shock, disconnect the instru ment from the power source before soldering. SOLDERING TECHNIQUES The reliability and accuracy of this instrument can be main- tained only if proper soldering techniques are used when repairing or replacing parts. General soldering techniques, which apply to maintenance of any precision electronic equipment, should be used when working on this instru- ment. Use only 60140 rosin-core, electronic-grade solder. The choice of soldering iron is determined by the repair to be made. When soldering on circuit boards, use a 15- to 25-watt pencil-type soldering iron with a 118-inch wide, wedge-shaped tip. Keep the tip properly tinned for best heat transfer to the solder joint. A higher wattage soldering iron may separate the wiring from the base material. Avoid excessive heat; apply only enough heat to remove the com- ponent or to make a good solder joint. Also, apply only enough solder to make a firm solder joint; do not apply too much solder. The Word Recognizer, Memory, Output, and Cursor circuit boards in this instrument are multilayer type boards with a conductive path (s) laminated between the top and bottom board layers. All soldering on these boards should be done with extreme care to prevent breaking the connections to the center conductor(s); only experienced maintenance personnel should attempt repair of these boards. For metal terminals, (e.g., coaxial connector ground lug, etc.) a higher wattage-rating soldering iron may be required. Match the soldering iron to the work being done. For example, if the component is connected to the chassis or other large heat-radiating surface, i t will require a 40-watt or larger soldering iron. The following technique should be used to replace a com- ponent on a circuit board: 1. Grip the component lead with long-nose pliers. Touch the soldering iron to the lead at the solder connection. Do not lay the iron directly on the board, as it may damage the board. 2. When the solder begins to melt, gently pull the lead out. If unable to pull the lead without using force, try removing the other end of the component as it may be more easily removed.

NOTE The reason that some component leads seem troublesome to remove is due to a bend placed on each lead during the manufacturing process. The purpose of the bent leads is to hold the componen t in place during a flow soldering manufacturing process that solders all com- ponents at one time. If a component lead is extremely difficult to remove, it may be helpful to straighten the leads on the back side of the board with a small screwdriver or pliers while heating the soldered connection. Desolder the component from the circuit board using heat on the component lead so that the solder will stay behind on the board. If it is desired to remove solder from a circuit board hole for easier installation of a new component, a solder-removing wick should be used for this purpose. 3. Bend the leads of the new component to fit the holes in the board. If the component is replaced while the board is mounted in the instrument, cut the leads so they will just protrude through the board. Insert the leads into the holes in the board so the component is firmly seated against the board (or as positioned originally). If it does not seat pro- perly, heat the solder and gently press the component into place. 4. Touch the iron to the connection and apply a small amount of solder to make a firm solder joint. To protect heat-sensitive components, hold the lead between the com- ponent body and the solder joint with a pair of long-nose -I pliers or other heat sink. 5. Clip the excess lead that protrudes through the board (if - not clipped in step 3). 6. Clean the area around the solder connection with a flux- --. remover solvent. Be careful not to remove information printed on the board. 7 COMPONENT REMOVAL AND REPLACEMENT To avoid electrical shock, disconnect the instru- men t from the power source before replacing '7 comp onen ts. -\ The exploded-view drawing associated with the Replaceable Mechanical Parts list may be helpful in the removal or dis- assembly of individual components or subassemblies. Com- -1 ponent locations and circuit board locations are shown in the Diagrams and Circuit Board Illustrations section. \ A B C 114" SCREW 5/16" SCREW 5/16" SCREW I i P ,XP I - - E D I- - 7116" SCREW W/NUT 7/16" SCREW 2206-13 Figure 4-4. Locations of securing screws on the Memory circuit board.

Circuit Boards If a circuit board is damaged beyond repair, replace the en- tire board assembly. Part numbers are given in the Replace- able Electrical Parts list for completely wired boards. A7 CLOCK QUALIFIER CIRCUIT BOARD (SN B8086085 and up). To remove the circuit board: 1. Disconnect the 5-wire and 6-wire multi-pin connectors from the cirucit board. 3. Note colors of all multi-pin connectors and P number to which each connects. Note wire color on single-conductor shielded cables and connector to which each is connected. 4. Disconnect all cables that terminate on Memory circuit board. 5. Remove 5 screws (A, 6, C, D and E on Fig. 4-4) from Memory circuit board. Two delay lines will now come loose from Memory board. 6. Remove board by pulling away from, and toward rear of instrument. 2. ~ e n ~ o v e 2 screws from frame rail (located On top of the 7. Reverse order or removal to complete circuit board re- rail). placement. Refer to Figure 4-5 for multi-pin connector and P number orientation. 3. Remove the board by pulling away from the instrument. A5 INTERCONNECT CIRCUIT BOARD. "To remove the cir- 4. Reverse order of removal to replace circuit board. cuit board: A2 MEMORY CIRCUIT BOARD. To remove the circuit 1. Note color of all multi-pin connectors and P number to board: which each connects. 1. Remove the CLOCK QUALIFIER (SN 8086085 and up) 2. Disconnect all cable connectors that terminate on Inter- circuit board as previously outlined. connect circuit board. 2. If the MEMORY circuit board is to be replaced, note color 3. Remove 4 screws (6, C, D, and E on Fig. 4-4) from Mem- and position of the 5 wires soldered to the board from ory circuit board. PI502 on the CLOCK QUALIFIER circuit board. Remove the 5 wires and solder onto the new MEMORY circuit board. 4. Disconnect P530 from Memory circuit board. Figure 4-5. Multi-pin connector and P number orientation for the Memory circuit board. REV OCT 1982 -

6. Move Memory circuit board away from frame to allow clearance for Interconnect circuit board removal. Carefully remove lnterconnect circuit board from bottom of instrument. 7. Note color and position of the 4 wires soldered to Inter- connect circuit board. 8. Unsolder and remove the 4 wires. 9. Reverse order of removal to complete circuit board replacement. A3 OUTPUT CIRCUIT BOARD. To remove the circuit board : 1. Remove knob from SAMPLE INTERVAL switch. 2. Note color of all multi-pin connectors and P number to which each connects. Note wire color on single-conductor Figure 4-6. Locations of securing screws on the Interface circuit board. shielded cables and connector to which each is connected. 3. Disconnect all cables that terminate on Output circuit 5. Remove 4 screws (A, 6, C, and D on Fig. 4-6) securing board. Interface circuit board and plug-in connector from rear panel. 4. Remove 4 screws (A, B, C, and D on Fig. 4-7). Figure 4-7. Locations of securing screws on the Output circuit board.

, . & * . . a . . * * . . . ' . * . * f 9 , '% 4 .>?\; SCREWS WIHEX NU 7 B v r( 2206-19 b ITS ,- Figure 4-8. Locations of securing screws and shield on the Power Supply circuit board. Maintenance-7DO1 (SN B020000 & up) 6. Reverse order of removal to complete circuit board replacement. A6 POWER SUPPLY CIRCUIT BOARD. To remove the circuit board: 1. Remove Output circuit board as previously outlined. 2. Remove 5 screws (A, 6, C, D, and E on Fig. 4-8) in order listed. 3. Remove the 4 screws with hex head nuts which secure power supply plug-in connector to rear panel. 4. Note color of all multi-pin connectors and P number to which each connects. 5. Pull Power Supply circuit board (with plug-in connector attached) away from instrument far enough to disconnect all cables that terminate on board. 6. To replace Power Supply circuit board, reverse order of removal. A4 CURSOR CIRCUIT BOARD. To remove the circuit board: 1. Note color of all multi-pin connectors and P number to which each connects. 2. Disconnect all cables that terminate on Cursor circuit board. ,, 5. Lift rear of board away from side, and pull straight to- ward rear of instrument until SAMPLE INTERVAL switch 3. Remove 2 flat-head screws (A and 6, Fig. 4-9) which shaft is clear of front panel. secure Cursor circuit board to rear panel. D lARE STANDOFF S rWEEN THE CURSC MORY CIRCUIT BC UHlNti S C ND B LOC I REAR PI I - C HEXAGONAL STANDOFF SPACER (BETWEEN THE CURSOR AND OUTPUT CIRCUIT BOARDS) Figure 4-9. Locations of securing screws on the Cursor circuit board. 4-1 1

4. Remove 1 screw (C, Fig. 4-9) that secures Output board to hexagonal standoff spacer. 5. Remove 2 screws (Dl Fig. 4-9) that secures Memory board and frame rail to square standoff spacer. 6. Push Cursor circuit board downward from instrument top far enough to remove screw and hexagonal standoff spacer from board. 7. Remove Cursor circuit board up through top of instrument. 8. To replace Cursor circuit board, reverse order of removal. A1 WORD RECOGNIZER CIRCUIT BOARD. To remove the circuit board: 1. Note color of all multi-pin connectors and P number to which each connects. 2. Disconnect all cables that terminate on Word Recognizer circuit board. Wires that are soldered directly to controls can be traced and multi-pin connectors removed at opposite end. 3. Remove all front-panel knobs from control-switch shafts. Pull on small, gray, center knob to remove (no set screw). 4. Remove securing nuts with washers from RECORD and FILTER control shaft bushings. 5. Disengage the 7001 release latch spring from frame rail. 6. Loosen and remove front panel by gently prying it away from sub panel with small screwdriver. 7. Remove 8 screws which secure front sub panel to frame rails (2 screws in each corner). 8. Pull sub panel with attached Word Recognizer circuit board away from instrument. 9. Remove 4 hex nuts (A, B, C, and Dl Fig. 4-10) and 2 flat head screws (E and F, Fig. 4-10) from front sub panel. 10. Remove Word Recognizer circuit board by pulling it directly away from sub panel. 11. Reverse order of removal to complete circuit board rep1 acemen t. 7 Switches 7 Several types of switches are used in this instrument. Con- tact alignment and spacing is critical to the operation of the cam switch. Therefore, a defective cam switch should be replaced as a unit or repaired only by personnel experienced c' with these types of switches. Your local Tektronix Field Office or representative can provide additional repair infor- mation. The following special maintenance information i s - provided for switch replacement. CAM SWITCH. The cam switch used in this instrument 7 consists of a rotating cam which mates with contacts on the adjacent circuit board. These contacts are activated by lobes on the cams as the switch is rotated. A cam switch can be ,, disassembled for inspection, cleaning, repair, or replacement (see CAUTION below); however, it is recommended that the switch be removed and replaced as a unit. - C A U T I O N E3 Repair of a cam switch should be undertaken - on/y by experienced main tenance personnel. Switch alignment and con tact spacing must be care fully maintained for proper operation. A cam switch repair kit is available (Tektronix T part 040-054 1-00) which contains special alignment tools for use in repairing or replac- 4 \ ing the switch contacts. For information or assistance on main tenance of cam switches, con tact your local Tek tronix Field Office or represen ta tive. Figure 4-10. Locations of hex nuts and screws on front sub panel which secure the Word Recognizer circuit board. 1

Use the following procedure to remove and replace a cam switch: 1. Remove Output circuit board following instructions - given previously. 2. Remove four screws that secure switch to circuit board. 3. Remove cam-switch assembly from board. -1 o replace the cam switch, reverse the order of removal. TOGGLE SWITCHES. Most of the toggle switches in this instrument are soldered to the Word Recognizer circuit board. To replace a toggle switch, remove the Word Recog- nizer circuit board following instructions given previously. Refer to the Corrective Maintenance portion of this section for special instructions in soldering on multilayer type circurt boards. Seniiconductors Semiconductors should not be replaced unless actually defective. If removed from their sockets during routine maintenance, return them to their original sockets. Un- necessary replacement of semiconductors may affect the adjustment of this instrument. When semiconductors are replaced, check the operation of the part of the instrument which may be affected. -- l o avoid component damage, power must be turned off before removing or replacing semiconductors. Replacement devices should be of the original type or a - direct replacement. The lead configurations of the semi- conductor devices used in this instrument are shown in the Diagrams and Circuit Board l llustrations section. When re- placing, check the manufacturer's basing diagram for cor- - rect basing. Semiconductors which have heat radiators dse silicone grease to increase heat transfer. Replace the silicone grease when replacing these semiconductors. Handle silicone grease with care. Avoid getting silicone grease in eyes. Wash hands thoroughly after use. An extracting tool should be used to remove the 14- and 16-pin integrated circuits to prevent damage to the pins. This tool i s available from Tektronix, Inc. Order Tektronix Part 003-0619-00. If an extracting tool i s not available when removing one of these integrated circuits, pull slowly and evenly on both ends of the device. Try to avoid having one end of the integrated circuit disengage from the socket before the other, as the pins may be damaged. Interconnecting Pins Two methods of interconnection are used to connect the circuit boards with other boards and components. When the interconnection i s made with a coaxial cable, a special end- lead connector plugs into a socket on the board. When the interconnection is made with a wire lead, an end-lead con- nector is used which mates with an interconnecting pin soldered into the board. The following information provides the removal and replacement procedure for the various types of interconnecting methods: COAXIAL-TYPE END-LEAD CONNECTORS. Replace- ment of the coaxial-type end-lead connectors requires special tools and techniques; only experienced maintenance personnel should attempt to remove and replace these connectors. It is recommended that the cable be replaced as a unit. For cable part numbers, see the Replaceable Me- chanical Parts list. An alternative solution i s to refer the replacement of the defective connector to your local Tektronix Field Office or representative. END-LEAD PIN CONNECTORS. The pin connectors used to connect the wires to the interconnecting pins are clamped to the ends of the associated leads. To remove and replace damaged end-lead pin connectors, remove the old pin con- nector from the end of the lead and clamp the replacement connector to the lead. Some of the pin connectors are grouped together and mounted in a plastic holder; the overall result is that these connectors are removed and installed as a multi-pin con- nector. The first end-lead pin (pin number 1) is soldered to a square pad to provide correct orientation of the multi-pin connector. Be sure the arrow on the multi-pin connector is aligned with this square pad when the connector is replaced. If the individual end-lead pin connectors are removed from the plastic holder, note the color of the individual wires for replacement. ClRCUl I-BOARD PINS. A circuit-board pin replacement kit including the necessary tools, instructions, and replace- ment pins i s available from Tektronix, Inc. Order Tektronix Part 040-0542-00. Replacement of circuit-board pins on multi-layer boards is not recommended; refer such repairs to your local Tektronix Field Office or representative.

1 C A U T I O N 5 - Only experienced service personnel should re- place circuit-board pins on multi-layer boards. Therefore, refer repairs of the Word Recognizer, Memory, Output, and Cursor circuit boards to your local Tektronix Field Office or rep resen ta rive. To replace a damaged pin which is mounted on a single- layer circuit board, first disconnect any pin connectors. Then (using Soldering Techniques given earlier in this section), unsolder the damaged pin and pull it from the board with a pair of pliers, leaving the ferrule in the hole, if possible (see Fig. 4-1 1 ). If the ferrule remains in the circuit board, remove the spare ferrule from the replacement pin and press the new pin into the hole in the circuit board. If the ferrule is removed with the damaged pin, clean out the hole using a solder-removing wick and a scribe. Then press the replacement pin with attached spare ferrule into the hole. Position the replacement pin in the same manner as the old pin. Solder the pin to the circuit board on each side of the board. If the old pin was bent at an angle to mate with a connector, carefully bend the new pin to the same angle. Replace the pin connector. Sample Interval Indicator Incandescent Bulb and 'TRIG'D LED Lights are mounted on the sub-panel using a plastic sleeve. Unsolder the lead wires and pull the bulb out of the sleeve from the rear of the sub-panel. ADJUSTMENT AFTER REPAIR +- REPLACEMENT PIN +--- SPARE FERRULE Figure 4-1 1. Exploded view of circuit-board pin and ferrule. After any electrical component has been replaced, the adjustment of that particular circuit should be checked, as well as other closely related circuits. See Section 5 for a complete adjustment procedure.

PERFORMANCE CHECK AND ADJUSTMENT PRELIMINARY INFORMATION TEST EQUIPMENT REQUIRED Adjustment Interval The test equipment listed in Table 5-1 is required for a To maintain instrument accuracy, check the performance complete performance check and adjustment of this instru- of the 7D01 every 1000 hours of operation, or every six ment. Detailed operating instructions for test equipment months if used infrequently. Before complete adjustment, are omitted in this procedure. Refer to the test equipment thoroughly clean and inspect this instrument as outlined in instruction manual if more information is needed. section 4, Maintenance. Tektronix Field Service Special fixtures are used only where they facilitate instru- Tektronix Field Service Centers and the Factory Service ment adjustment. These fixtures are available from Tek- Center provide instrument repair and adjustment services. tronix, Inc. Order by part number from Tektronix Field Contact your Tektronix Field Office or representative for Offices or representatives. further information. Using This Procedure This Performance Check and Adjustment procedure can be used either for complete adjustment or as a check of instru- ment performance. Completion of each step in the proce- dure ensures that the instrument i s correctly adjusted and operating within specified limits. Instrument performance only can be checked by omitting the last step (adjustment step) in the procedure. A check mark (4) preceding a CHECK indicates that the limit given is a performance requirement as listed under Specification in section 1, General Information. Description ---- - 1. Test oscilloscope system --,-- 2. DC voltmeter The test equipment listed in the Examples of Applicable Test Equipment column, Table 5-1, is required to check and adjust this instrument. The Performance Check and Adjustment procedure is based on the first item of equip- ment given as an example. If other equipment is substituted, control settings or setups may need to be altered. If the exact item of equipment given as an example is not avail- able, refer to the Minimum Specifications column to deter- mine if other equipment may be substituted, then check the Purpose column. If you determine that your measure- ment requirements will not be affected, the item and corresponding step(s) can be deleted. TABLE 5-1 Test Equipment """ 'Tektronix 7000-series, 4-com- partment mainframe with crt readout. Bandwidth, at least 200 MHz; fastest calibrated sweep rate, to at least 2 nsldiv. -- Range, k2 V to + I 5 V; accu- recy, within 1%. Set input pulse width and provide display for 7D01. Check threshold voltage. "-~,- Examples of Applicable Test Equipment .-- em.- " .*me-,- --. -- a. TEKTRONIX 7'704A Oscilloscope System with 7A19 Amplifier unit and 7B80 Time Base unit. -----=- --- a. TEKTHONIX DM 502 Digital Multi-Meter.' I b. TEKTRONIX 7D13 Digi- tal ~ u l t i - ~ e t e r . ' 3. Pulse generator Pulse duration, 10 ns to 300 ns; pulse period, 20 ns to 1 ps; output amplitude, 0 V dc to 3 V dc; rise time, 2 ns or less. Check Minimum Data and External Clock Pulse Widths. a. TEKTRONIX PG 502 250 MHz Pulse en era tor.' I Used with TM 500-series power module. Used in 7000-series oscilloscope mainframe.

TABLE 5-1 (CONT.) Test Equipment Examples of Applicable D 5. 50-ohm BNC cable 4. Plug-in extender3 (2 required) 6. BNC "T" adapter Fits Tektronix 7000-series Provides access to internal plug-in units. adjustments. Connects pulse generator to test oscilloscope amplifier unit for measuring pulse width. 7. BNC-to-binding post adapter -.- 8. Screwdriver a. Tektronix part 067- 0616-00 Calibration Fixture. a. Tektronix part 012-0076. 00. to 2 BNC female Connectors: BNC male to Connects probe leads to dual binding post. Pulse Generator signal. ---.-- I 3-inch shaft, 3132-inch bit. Adjust Variable ^I"hreshold -- Bused for calibration only; NOT used for performance check. Tektronix part 103-0030- - a. Tektronix part 103-0035- - a. Xcelite R-3323. .- REV A JUN 1980 -

PRELIMINARY PROCEDURE (SN 5086085 - UP) CLOCK QUALIFIER . . . . . . Off HORlZ NOTE POS . . . . . . . . Midrange MAG . . . . . . . . X I The performance of this instrument can be checked at 1 - any ambient temperature from 0" to 40°C unless \: & ( r L < ~ l l ) 'HRESHOLD . . . . . . otherwise stated. Adjustments must be performed at VOLTAGE TTL an atrrbient temperature between i 20" and 30° for specified accuracy. 1. Before installing the 7D01 i n the test oscilloscope system, check the Cursor Byte selection jumper, P1493. It should be in the 4-bit position (see Fig. 2-3).1 2. Install the '7D01 in center two plug-in compartments, right vertical and A horizontal, of test oscilloscope system 3. Press the appropriate Mode switches for the compart- ments used by the 7D01. 4. Connect a P6451 Data Acquisition Probe to top Data- Input Connector (Channels 0-7 and External Clock). 5. Set the 7D01 front-panel controls as follows: VERT . . . . . . . . POS Midrange MAG . . . . . . . . X I RECORD DISPLAY . . . . . . . . TIME O= (fully clockwise detent) EXT CLOCK POLARITY . . . . . .I SAMPLE INTERVAL . . . . . . l ps DATA CHANNELS . . . . .O-3 DATA POSITION . . CENTER TRIG SOURCE . . . CH 0 EXS' TRlG POLARITY . . . . . . WORD RECOGNIZER W.R. MODE . . . ASYNC FILTER . . . . . . . MIN CH 0-15 . . . . . . X (center) EXTERNAL QUALIFIER . . . . . . X (center) PROBE QUALIFIER . . . . . . X (center) 6. Apply power to test equipment and allow at least 30 minutes warm-up time before continuing this procedure. 7. This completes the preliminary procedure. REV A JUN 1980

PRELIMINARY PROCEDURE (SN 8886884 - below) NOTE The performance of this instrument can be checked at any ambient temperature from 0" to +40° C unless othenvise stated. Adjust- ments must be performed at an ambient femperature between +20° and +30° C for specified accuracy. 1. Install 7D01 in center two plug-in compai.trnents (right vertical and A horizontal) of test oscilloscope system. 2. Connect a P6451 Data Acquisition Probe to top Data- Input Connector (Channels 0-7 and External Clock). 3. Set 7D01 front-panel controls as follows: VERT . . . . . . . . POS .Midrange MAG . . . . . . . .X 1 RECORD DISPLAY SAMPLE INTERVAL.. . . . .lps DATA CHANNELS.. . . . .O-3 DATA POSITION. . . . . . .CENTER 'TRIG SOURCE. . . .CH 0 EXT TRIG POLARITY.. . ...I WORD RECOGNIZER W.R. MODE. . . .ASYNC FILTER . . . . . .MIN CH 0 through 15 . . . . . . . . . .X (center) EXTEHNAL QUALIFIER . . .X (center) PROBE QUALIFIER . . .X (center) 4, Install amplifier unit and time-base unit in left vertical and B horizontal compartments, respectively. TIME . . . . . . . (fully clockwise detent) 5. Connect 50-ohm BNC cable from amplifier unit input CURSOR connector to BNC "T" adapter. BYTE. . . . . . . .4 BIT HORlZ . . . . . . . . POS .Midrange MAG . . . . . . . .X 1 6. Connect BNC "T" adapter to pulse generator output and to BNC-to-dual binding post adapter. THRESHOLD VOLTAGE. . . . . . .T'TL 7. Apply power to test equipment and allow at least 15 E X I CLOCK minutes warm-up time before continuing this procedure. . . . . . POLARITY .I REV A JUN 1980

PERFORUAHCE CHECK AND ADJIISWEMT PROCEDURE J 1. CHECK DISPLAY (SN B086085 - Up) q. Install the 7D01 in the center two compartments of the test oscilloscope system and apply power. a. Press RECORD MANUAL RESET and MANUAL TRIGGER push-button switches (in that order) toobtain display. r. Repeat part a. s. Change DATA CHANNELS to 0- 1 5. b. Adjust test oscilloscope intensity and focus controls as desired. d t. CHECK----That the Cursor Data readout displays 16 zeros in four groups of three bits each and one group of four bits. d c. CHECK-That displayed traces are between 7.5 and 10 divisions long with HORlZ MAG control in X I position. u. Repeat part n v. Change the internal Cursor Byte selection jumper, P1493, to the .$-bit position (see Fig. 2-3). d. Change HORlZ MAG control to X I 0 position (fully clockwise). w. Change DATA CHANNELS to 0-3 position. 4 e. CHECK.-That ends of displayed traces can be posi- tioned on screen with HOR lZ POS control. x. repeat part q f. Change HORIZ MAG control back to X I position. y. CHECK That the Trigger ir~tensified zone is approximately centered on the displayed traces 4 g. CHECK -That horizontal position of displayed traces does not move more than one division when the DATA CHANNELS switch is changed to 0-15 position. z. Change the DATA POSITION switch to POST TRIG d aa. CHECK--.-That the Trigger intensified zone moves toward the left end of the displayed traces. d h. CHECK--With DATA CHANNELS switch in 0-15 position, that display contains 16 traces divided into four groups of four traces each. ab. Change the DATA POSITION switch to PRE TRIG. t/ ac. CHECK---That the Trigger intensified zone moves toward the right end of the displayed traces. i. Change VERT MAG control to X5 position (fully clockwise). ad. Change the DATA POSITION switch back to CENTER. .\/ j. CHECK-That any of the 16 displayed traces can be positioned on screen with the VERT POS control. k. Change VER'T MAG control back to X I position (fully counterclockwise). 4 I. CHECK .'That Cursor intensified zone can be posi- tioned to any bit of the displayed traces with the CUR- SOR COARSE and FINE POS controls in 16-bit increments (COARSE) and I-bit increments (FINE POS) as displayed by the Cursor Position readout (top of crt). d 1A. CHECK DISPL..AY (SN 6086084 - below) .\/ tn. CHECK-That Cursor Data readout (bottorn of crt) displays sixteen 0's in four groups of four digits each. NOTE (SN B086085 - Below) n. Turn off the power for the test oscilloscope system and remove the 7D01. To set pulse generator output, set test oscillo- scope vertical and horizontal mode to display amplifier unit and time-base unit. Set pulse generator as specified and switch test oscillo- scope back to display 700 1. o. Change the internal Cursor Byte selection jumper, P1493, to the 3-bit position (see Fig. 2-3). P. Set DATA CHANNELS to 0-3. Perfotsnance Requirement check; see introductory information. REV A JUN 1980

a. Press RECORD MANUAL RESET and MANUAL 4 m. CHECK--"That Cursor Data readout (bottom of crt) TRIGGER push-button switches (in that order) toobtain displays sixteen 0's in four groups of four digits each. - display. n. Change CURSOR BYTE switch to 3 BIT position. b. Adjust test oscilloscope intensity and focus controls as desired. o. CHECK--That Cursor Data readout displays sixteen 0's in five groups (one 4-bit group and four 3-bit groups). 4 c. CH ECK-T hat displayed traces are between 7.5 and 10 divisions long with HORlZ MAG control in X I position. p. Change CURSOR BYTE switch back to 4 BIT position. d. Change HORlZ MAG control to X I 0 position (fully clockwise). q. Change DATA CHANNELS switch back to 0-3 position. d e. CHECK -That ends of displayed traces can be posi- tioned on screen with HORlZ POS control. r. CHECK-That I rigger intensified zone is approxi- mately centered on the displayed traces. f. Change HORlZ MAG control back to X I position. s. Change DA1'A POSITION switch to POST TRIG. 4 g. CHECK--That horizontal position of displayed traces does not move more than one division when the DATA 4 t. CHECK-That Trigger intensified zone moves toward CHANNELS switch is changed to 0-15 position. the left end of the displayed traces. .\/ h. CHECK-With DATA CHANNELS switch in 0-15 position, that display contains 16 traces divided into four groups of four traces each. u. Change DATA POSITION switch to PRE TRIG. 4 v. CHECK That Trigger intensified zone moves toward the right end of the displayed traces. i. Change VERT MAG control to X5 position (fully clockwise). w. Change DATA POSITION switch back to CENTER. j. CHECK-That any of the 16 displayed traces can be positioned on screen with the VER'T POS control. k. Change VERT MAG control back to X1 position (fully counterclockwise). 2. CHECK THRESHOLD VOLTAGE a. Connect dc voltmeter between THRESHOLD VOL T- AGE MONITOR pin jack and chassis ground. .\/ b. CHECK--That Threshold Voltage can be adjusted 4 I. CHECK That Cursor intensified zone can be posi- -12 or to at least +12 with VAR tioned to any bit of the displayed traces with the CUR- SOR COARSE and FINE POS controls in 16-bit screwdriver adjustment. increments (COARSE) and I-bit increments (FINE POS) as displayed by the Cursor Position readout (top of crt). c. Disconnect dc voltmeter from 7D01. Performance Requirement check; see introductory information. REV A JUN 1980 -

4 3. CHECK MINIMUM EXTERNAL CLOCK PULSE WIDTH a. Install the vertical amplifier and horizontal time-base plug-ins in the Left Vert and B Horiz compartments respectively. b. Connect a 50RBNC cable from the vertical amplifier INPUT connector to a BNC "-1'" adapter. c. Connect the BNC "T" adapter to the pulse generator OUTPUT connector. d. Connect a BNC-to-dual binding post adapter to the other side of the BNC "T" adapter. e. Set the pulse generator for output waveform as follows: LO Level . . . . . . . 0.0 V HlLevel . . . . . . +-2.0v HI Level Pulse Duration . . . . . . . 10 ns Pulse Period . . . . . 1.0 ps Back Term . . . . . . . Out - EXT CLOCK PQLARITY -F- - / I / . I 6'"\7f 5-5' m. Set the pulse generator for output waveform as follows: COMP . . . . . . . . . . IN LO Level . . . . . . . 0.0 V HI Level . . . . . . +2.O V LO Level Pulse Duration . . . . . . . 10 ns Pulse Period . . . . . 1.0 us Back Term . . . . . . . Out n. Repeat parts i. through k., substitute part m. for part e. o. Change EXT CLOCK POLARITY switch to 1 position. .J pr-/ J A - c 4 d To set the pulse generator output, set the test osc~llo- 4 4. CHECK MINIMUM SAMPLE INTERVAL a. Set pulse generator for output waveform as follows: LO Level . . . . . . . .0.0 V . . . . . . . HI Level .at least +2.0 V HI Level Pulse Duration . . . . . . . .5 ps Pulse Period . . . . . .10 ps BACK TERM . . . . . In scope Vertical and Horizontal Mode switches to dis- b. Disconnect CH 0 probe lead from test oscilloscope play the vertical and horizontal plug-ins. Set the pulse calibrator and connect to pulse generator output. generator as specified, switch the test oscilloscope system to display the 7001 signals. c. Disconnect C probe lead from pulse generator output. -- f. Connect the C probe lead (External Clock) to pulse generator output, the CH 0 probe lead to the test oscillo- scope 4 volt, I khz output, and the GND probe lead to ground. - g. Change RECORD DISPLAY TIME control tols posi- tion (fully counterclockwise) and SAMPLE INTERVAL switch to EX'" position. h. Adjust 7DO1 VERP and HORlZ controls as desired. - i. CHECK-For stable display of CH 0 signal with the rising edge of the CH 0 signal centered on the trace. (Adjust pulse amplitude ~f necessary.) j. Change DATA CHANNELS switch to 0-7 and repeat parts e. and i. k. Change DATA CHANNELS switch to 0-1 5 and repeat parts e. and i., except adjust the Pulse Duration for 20 ns. d. Change SAMPLE INTERVAL switch to 10 ns ~osition. e. Change DATA CHANNELS switch to 0-3 position. 4 f. CHECK-For stable display of CH 0 signal. (Adjust pulse amplitude if necessary.) g. Change DATA CHANNELS switch to 0-7 h. Change SAMPLE l N T f RVAL switch to 20 ns. 4 i. Repeat part f. j. Change DATA CHANNELS switch to 0-15. k. Change SAMPLE INTtRVAL switch to 50 ns. I. Change EXT CLOCK POLARITY switch to J position and change DATA CHANNELS switch to 0-3. I. Repeat part f. (Disregard any noise on channels 8-15). - "- J~erfotmance Requirement check; see introductory information. REV OCT 1982 5-7

d 5. CHECK MINIMUM DATA PULSE WIDTH 4 k. Repeat part g. - a. Set pulse generator for output waveform as follows: LO Level . . . . . . . .0.0 V HI Level . . . . . . . .at least +2.0 V HI Level Pulse Duration . . . . . . . . I 5 ns Pulse Period. . . . . ,101~s I. Change pulse generator pulse duration to 20 ns. - - m. Change WORD RECOGNIZER CH 4 through CH 7 switches to HI. BACK TERM . . . . . Out d n. Repeat part g. - b. Change SAMPLE INTERVAL switch to 10 ns. c. Change DATA CHANNELS switch to 0-3. .\/ d. CHECK-For at least one HI pulse stored on CH 0 display. o. Change WORD RECOGNIZER CH 0 through CH 7 - switches to X. p. Disconnect P6451 probe from top Data-Input Con- -- nectar (Channels 0-7 and External Clock) and connect to bottom Data-Input Connector (Channels 8-15 and Probe Qualifier). -. .\/ 6. CHECK MINIMUM TRIGGER PULSE WIDTH a. Change TRIGGER SOURCE switch to EXT position. q. Change WORD RECOGNIZER CH 8 through CH 15 - switches to H I. b. Disconnect 50-ohm cable from amplifier unit input and connect to 7D01 EXT TRIGIQUALIFIER INPUT. d r. Repeat part g. d c. CHECK-That TRIG'D light is on and remains on. d 7. CHECK WORD RECOGNIZER FILTER d. Disconnect 50-ohm cable from EXT TR IGIQUALI- a. Change pulse generator pulse duration to 300 ns. - FlER INPUT and reconnect to amplifier unit input. b. Rotate WORD RECOGNIZER FILTER control to e. Change pulse generator pulse duration to 10 ns. >300 ns (fully clockwise). - f. Change TRIGGER SOURCE switch to W.R. and 4 c. CHECK-That THIG'D light is out and remains out. - WORD RECOGNIZER CH 0 switch to HI. c L/,Fid h& U - T f k . ] /f17"u c2B04 pals< &/dl-& i / ~ n / t s b i l l , pc '.P:f 0 - d g. CHECK hat T HIG'D light is on and remains on. d 8. CHECK RECOGNIZER OUTPUT a. Change WORD RECOGNIZER FILTER control to MIN (fully counterclockwise). - h. Copnect all oae-rdata channel ~ r a b e leads (Channels 1 through 7) to pulse generator output. b. Disconnect 50-ohm cable from pulse generator out- put and connect to W. R. OUT connector. I. Change pulse generator pulse duration to 15 ns. d c. CHECK-For output pulse of at least +0.95 V ampli- j. Change WORD RECOGNIZER CH 1, CH 2, and CH 3 tude and a baseline-level from ground reference of switches to H I. +50 mV or less (into 50-ohm load). --- -. - J~erformance Requirement check; see introductory informatiun. 5-8 REV OCT 1982

FEST WINV AND BtFORE YOU BEGIN, see Ai,W)S.,faENT LOe;AfIwj in the Diagrams section. 9. DISPLAY ADJUSTMENTS a. Turn off power to test oscilloscope and remove 7D01. b. Install two plug-in extenders in center plug-in com- partments of test oscilloscope. c. Connect plug-in extenders to proper plug-in connect- ors on rear panel of 7001. d. Apply power to test oscilloscope. e. Remove P6451 Data Acquisition Probe from the Data Input connector. f. Rotate RECORD DISPLAY TIME control to fully clockwise detent position (m). g. Press the RECORD MANUAL RESET and MANUAL TRIGGER push buttons (in that order). h. Adjust test oscilloscope intensity, focus, and readout controls for a well-defined crt display. i. Identify the trigger intensified zone by switching the DATA POSITION t o POST TRIG and back to CENTER position. j. Adjust R625 for desired contrast of the trigger intensi- fied zone (if necessary). k. Identify the cursor intensified zone by rotating the CURSOR COARSE control. I. Adjust R1375 for desired contrast of the cursor in- tensified zone (if necessary). m. Rotate the CURSOR FINE POS control and check that the least significant digit of the Cursor Position readout (TRIG + XXXX) can be set to all digits between 0 and 9. n. If the Cursor Position readout skips and/or repeats any number, remove the 7D01 and plug-in extenders from the test oscilloscope and connect to another Tek- tronix 7000-series oscilloscope (if available). Then repeat part m. (If the test oscilloscope is not the one normally used with the 7D01, the second check and following adjustment should be made in the oscil- loscope mainframe in which the 7D01 is normally used.) o. If the Cursor Position readout still skips and/or repeats numbers, carefully adjust R1335 and repeat part m. This completes the Performance Check and Ad- justment procedure for the 7D01.

REPLACEABLE ELECTRICAL PARTS PARTS ORDERING INFORMATION Replacement parts are available from orthrough your IocalTektronix, Inc. Field Office or representative. Changes to Tektronix instruments are sometimes made to accommodate lmproved components as they become available, and to give you the benefit of the latest circuit improvements developed in our engineering department. It is therefore important, when ordering parts, to include the following information in your order: Part number, instrument type or number, serial number, and modification number if applicable. If a part you have ordered has been replaced with a new or improved part, your local Tektronix, Inc. Field Office or representative will contact you concerning any change in part number. Change information, if any, is located at the rear of this manual SPECIAL NOTES AND SYMBOLS XOOO Part flrst added at t h ~ s ser~al number OOX Part removed after this serial number ITEM NAME In the Parts List, an ltem Name is separated from the description by a colon (:). Because of space limitations, an ltem Name may sometimes appear as incomplete. For further Item Name identification, the U.S. Federal Cataloging Handbook H6-1 can be utilized where oossible. ABBREVIATIONS ACTR ASSY CAP CER CKl- COMP CONN ELCTL r ELEC INCAND LED NONWIR ACTUATOR ASSEMBLY CAPACITOR CkHAMlC CIRCUIT COMPOSITION CONNEC7 OR ELECTROLYTIC ELECT HlCAL INCANDESCENT LIGHT EMIT I-ING DIODE NON WIREWOUND PLSTC OTZ RECP RES R F SEL SEMICOND SENS VAR WW XFMR XTAL PLASTIC QUARTZ RECEPTACLE RESISTOR RADIO FREQUENCY SELEC l t D SEMICONDUCTOR SENSITIVE VARIABLE WIREWOUND l HANSFORMER CRYSTAL

CROSS INDEX-MFR. CODE NUMBER TO MANUFACTURER Mfr. Code 00853 01121 01295 Manufacturer - -- "- -- SANGAMO ELECTRIC CO , S. CAROLINA DIV. ALLEN-BRADLEY COMPANY TEXAS INSTRUMENTS, INC., SEMICONDUCTOR GROUP PULSE ENGINEERING, INC. SPECTROI, ELECTRONICS CORPORATION RCA CORPORATION, SOLID STArE DIVISION GENERAL ELECTRIC COMPANY, SEMI-CONDUCTOR PRODUCTS DEPARLMEN I' AVX CERAMICS, DIVISION OF AVX CORP. MOTOROLA, INC., SEMICONDUCTOR PROD. DIV. FAIRCHILD SEMICONDUCTOR, A DIV. OF FAIRCHILD CAMERA AND INSTRUMENT CORP. WNERAL ELECTRIC CO., MINIATURE LAMP PRODUCfS DhPARTMENT C AND K COMPONENTS, INC. CLAROSTAT MFG. CO., INC. 11T SLMICONDUCTORS ELECTRO CUBE INC. ITT SEMICONDUCTORS, A DIVISION OF INTER NMLONAL TELEPHONE AND TELEGRAPH CORP. CORNING GLASS WORKS, ELECTRONIC COMPONENTS DIVISION NATIONAL SEMICONDUCTOR CORP. BOURNS, INC., TRIMPOT PRODUCTS DIV. ADVANCED MICRO DEVICES MIDWEST COMPONENTS INC. HEWLETT-PACKARD COMPANY CENTKE ENGLNLERING INC. XCITON CORPORATION NICHICONI~RLCAICORP. SPRAGUE ELECTRIC CO. TUSONIX INC. ERIE TECHNOLOGICAL PRODUCTS, INC. BECKMAN INSTRUMENTS, INC., HELIPOT DIV. STACKPOLE CARBON CO. TEKTRONIX, INC. GRAYHILL, INC. MALLORY CAPACITOR CO., DIV. OF P. R. MALLORY AND CO., INC. RADIO MATERIALS COMPANY, DIV. OF P.R. MALLORY AND COMPANY, INC. DALE ELECTRONICS, INC. PCA ELECTRONICS Address "-- C~ty, State, ZIP --- -- P 0 BOX 128 PICKENS, SC 29671 1201 2ND STREET SOUTH MILWAUKEE, WI 53204 P 0 BOX 5012, 13500 N CENTRAL EXPRESSWAY DALLAS, TX 75222 7250 CONVOY COURT SAN DIEGO, CA 92111 17070 EAST GALE AVENUE CITY OF INDUSTRY, CA 91745 ROUTE 202 SOMERVILLE, NY 08876 ELECTRONICS PARK SYRACUSE, NY 13201 - P 0 BOX 867, 19TH AVE. SOUTH MYRTLE BEACH, SC 29577 5005 E MCDOWELL RD,PO BOX 20923 PHOENIX, AZ 85036 464 ELLIS STREET MOUNTAIN VIEW, CA 94042 NELA PARK CLEVELAND, OH 441 12 103 MORSE STREET WATERTOWN, MA 02172 LOWER WASHINGTON STREET DOVER, NH 03820 3301 ELECTRONICS WAY - P 0 BOX 3049 WEST PALM BEACH, FL 33402 1710 S. DEL MAR AVE. SAN GABRIEL, CA 91776 - P.O. BOX 168, 500 BROADWAY LAWRENCE, MA 01841 550 HIGH STREET 2900 SEMICONDUCTOR DR. 1200 COLUMBIA AVE. 901 THOMPSON PL. P. 0. BOX 787 1981 PORT CITY BLVD. 640 PAGE MILL ROAD 2820 E COLLEGE AVENUE 5 HEMLOCK STREET 6435 N PROESEL AVENUE 87 MARSHALL ST. 2155 N FORBES BLVD 644 W. 12TH ST. 2500 HARBOR BLVD. P 0 BOX 500 561 HILLGROVE A m . , PO BOX 3029 E. WASHINGTON STREET P. 0. BOX 372 4242 W BRYN MAWR P. 0. BOX 609 16799 SCHOENBORN ST. BRADFORD, PA 16701 SANTA CLARA, CA 95051 RIVERSIDE, CA 92507 SUNNYVALE, CA 94086 MUSKEGON, MI 49443 PAL0 ALTO, CA 94304 STATE COLLEGE, PA 16801 LATHAM, NY 12110 CHICAGO, IL 60645 NORTH ADAMS, MA 01247 TUCSON, AZ 85705 ERIE, PA 16512 FULLERTON, CA 92634 ST. MARYS, PA 15857 BEAVERTON, OR 97077 373 LA GRANGE, IL 60525 INDIANAPOLIS, IN 46206 CHICAGO, IL 60646 COLUMBUS, NE 68601 SEPULVEDA, CA 91343 REV AUG 1982

Tektron~x Ser~allModel No Ckt No Part No Eff - "- Dscont - - - - Mfr Code Mfr Part Number -- - - - - - - Name & Description CKT BOARD ASSY:WORD RECOGNIZER CKT BOARD ASSY:WORD RECOGNIZER CKT BOARD ASSY:WORD RECOGNIZER CKT BOARD ASSY:MEMORY CKT BOARD ASSY:MEMORY CKT BOARD ASSY:MEMORY B020000 B020275 B087200 BlOOOOO B020000 B020275 CKT BOARD ASSY:OUTPUT CKT BOARD ASSY:OUTPUT CKT BOARD ASSY :OUTPUT CKT BOARD ASSY:OUTPUT CKT BOARD ASSY:CURSOR CKT BOARD ASSY:CURSOR CKT BOARD ASSY:CURSOR CKT BOARD ASSY:CURSOR CKT BOARD ASSY:CURSOR CKT BOARD ASSY:CURSOR CKT BOARD ASSY:INTERCONNECT CKT BOARD ASSY:INIERCONNECT A6 670-4286-00 B020000 B020274 A6 670-4286-01 B020275 B039999 A6 670-4286-02 B040000 B069999 A6 670-4286-03 B070000 B079999 A6 670-4286-04 B080000 B099999 A6 670-4286-05 BlOOOOO CKT BOARD ASSY:POWER SUPPLY CKT BOARD ASSY:POWER SUPPLY CKT BOARD ASSY:POWER SUPYLY CKT BOARD ASSY:POWEK SUPPLY CKT BOARD ASSY:POWER SUPPLY CKT BOARD ASSY:POWER SUPPLY CKT BOARD ASSY:CLOCK QUALIFIER CAP.,FXD,CER DI:27PF,+/-5.4PF,500V CAP.,FXD,CER DZ:O.lUF,+80-20%,12V CAP.,FXD,CEK DI:O.lUF,+80-20%,12V CAP.,PXD,MICA D:16.8PF,+/-0.5PF,50OV CAP.,FXD,CER DI:25PF,2%,200V CAP. ,FXD ,CER DI:O.lUF ,+80-20% ,12V CAP.,FXD,CER DI:O.lUF,+80-20%,12V CAP.,FXD,CER DI:O.lUF,+80-20%,12V CAP. ,FXD ,CER Dl :O. 1UF ,+80-20%, 12V CAP.,FXD,CER DI:O.lUF,+BO-20%,12V CAP.,FXD,CER DI:O.lUF,+80-20%,12V CAP.,FXD,CER DI:O.O1UF,lO%,lOOV CAP.,FXD,CER DI:0.01UF,10%,100V CAP. ,FXD,CEK DI:100PF,10%,100V CAP.,FXD,CER DI:100PF,10%,100V CAP.,FXD,CER DI:O.lUF,20%,50V CAP.,FXD,ELCTLT:lOOUF,+50-10%,10V CAP.,FXD,CEK DI:O.OlUF,+80-20%,150V REV AUG 1982

(SN 8020000 & up) Tektronix SeriallModel No. Part No. Eff Dscoili Mfr Code Mfr Part Number Name & Description Ckt No CAP.,FXD,ELCTLT:lOOUF,+50-10%,10V CAP.,FXD,ELCTLf:100UF,+50-10%,10V CAP.,FXD,CEK ~ 1 : 1 0 ~ ~ , + / - 0 . 2 5 ~ ~ , 5 0 0 ~ CAP. ,PXD,CER DI:O.OlUF,lO% ,100V CAP.,FXD,CER DI:O.OlUF,+80-20%,15OV CAP.,kXD,CER DI:O.lUF,+80-20%,12V CAP.,hXD,CEK DI:O.OlUF,+80-20%,150V CAP.,FXD,CER DI:O.OlUF,+80-20%,15OV CAP.,bTXD,ELCTLT:22UF,20%,15V CAP. ,FXD,ELCTLT:22UF,20%,15V CAP.,kXD,CER DI:O.OlUF,+80-20%,15OV CAP.,FXD,ELCTLT:2UF,+75-10%,25V XBOlOOOO BOZO000 B079999X B020000 B079999X CAP. ,FXD,CCR DI:O.OlUF,10%,50V CAP. ,FXD,ELCTLT:22UF ,20% ,15V CAP.,TXD,CER DI:330PF,5%,500V CAP. ,FXD,CEK DI:O.O01UF,5%,100V CAP.,FXD,ELCTLT:2UF,+50-10%,150V CAP.,FXD,LLCTLT:47UFI+50-10%,16V CAP.,FXD,ELCTLT:22OUF,+50-10%,1OVDC C A P . , F X D , L L C I L T : ~ ~ O U F , + ~ ~ O - ~ ~ % , ~ ~ V CAP. ,FXD,ELCTLT: 2 2 0 ~ ~ ,+5O-lo%, 1OVDC C A P . , F X D , E L C ~ ~ , ~ : ~ ~ O U F , + ~ ~ - ~ O % , ~ ~ V D C CAP.,YXD,ELCTLT:220UF,+50-10%,10VDC CAP.,FXD,CEK DI:O.OlUF,+80-20%,150V CAP.,FXD,ELCTLT:22UF,20%,15V CAP.,YXD,ELCTLT:lUF,20%,35V CAP.,FXD,CER DI:O.OlUF,+80-20%,15OV CAP. ,FXD ,ELLrl,T : 1OOUF ,20%,20V CAP.,FXD,ELLTLr:lOOUF,+50-10%,25V CAP.,FXD,ELCTLT:loOUF,+50-10%,25V CAP.,t;XD,FLCTLI':100UF,+50-10%,25V CAP.,FXD,CER DI:O.OlUF,+80-20%,15OV CAP. , FXD , ET.CTLT : 100UF, 20%, 20V CAP.,FXD,ELCTLT:100UF,+50-10%,25V C A P . , F X D , ~ L C T L T : ~ O O U F , + ~ O - ~ O % , ~ ~ V CAP.,FXD,CER D1:10OPF,+/-20PF,500V CAP.,FXD,CER DI:O.lUF,+80-20%,50V CAP. ,FXD,F81.CTLT:47UF,+50-10% ,16V CAP.,FXD,CER DI:35PF,10%,500V CAP.,FXD,CER DI:390PF,10%,500V CAP.,FXD,CER DI:0.47UF,20%,50V CAP.,bLXU,CER DI:O.O22UF,+80-20%,25V REV AUG 1982

Tektronix SerialIModel No. Part No. Eff Dscont Mfr Code Mfr Part Number .- -- - - - - - - - - --- - - Ckt No. Name & Description ---.---...--..--m.---- " - CR105 CR106 CRllO CRlll CR112 CR113 CR114 CR115 CR116 CR117 CR118 CR119 SEMICOND DLVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA ShMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SIT,ICON,3OV,l5OMA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SLMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEV1Ca:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVLCE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:GE,25V,40MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICr::SJI.ICON,30V,150MA SEMICOND DEVICE:GE,25V,40MA SEMICOND DEVICL:SILICON,30V,150MA SEMICOND DEVICE : STT.ICON ,30V, 150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEV1CE:SXI.ICON,30V,150MA SEMICOND DEVPCE:SXI,ICON,30V,150MA SEMICOND DEVICh:SILICON,30V,150MA REV OCT 1982

Tektronix SerialIModel No. Part No. Eff Dscont Mfr Code Mfr Part Number Ckt No. CR738 CR750 CR753 CR754 CR764 CR904 Name & Description SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEViCE:SILICON,15V,HOT CARRIER SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:GE,25V,40MA SOMICOND DEVICE:SILICON,30V,150MA BOlOlOO B079999X SEMICOND DEVICE:SILICOW,30V,l5OMA SEMICOND DEVICE:SILICON,30V,150MA SbMICOND DEVICE:SILICON,30V,150MA SOMICOND DEVICE:GE,25V,40MA SEMICOND DEVICE:GE,25V,40MA SEMICOND DEVICE:SILICON,600V,lA BOlOlOO B079999X BOlOlOO B079999X XB080000 XB070000 XB070000 XB040000 SEMICOND DEVICE:SILICON,600V,lA SEMICOND DEVICE:SILICON,20V,5A SSMICOND DEVICE:SILICON,20V,5A SEMICOND DEVICE:SILICON,20V,5A SLMICOND DEVICE:SILICON,20V,5A SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SCMICOND DEVICE:Gb,25V,40MA SEMICOND DEVICE:SIT.ICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:Gh,25V,40MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SLMICOND DLVICE:SILICON,15V,HOT CARRIER SEMICOND DEVlCE:SILICON,30V,15OMA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SII,ICON,30V,15OMA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVLCE:GE,25V,40MA SEMICOND DEVlCE:SILICON,30V,150MA SEMICOND DEVLCh:SILICON,30V,150MA SEMICOND DEVICE:SII,ICON,30V,150MA SEMICOND DEV1LE:SlLICON,30V,150MA SEMICOND DEVICE:SXI,ICON.30V.150MA . . SEMICOND DEVICE:STLICON,30V,150MA SEMICOND DEVICE:GE,25V,40MA SEMICOND DEVICE:SII.ICON,30V,150MA SEMICOND DEVICE:SJI,LCON,30V,150MA SEMICOND DEVICE:SIi4LCON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:Gt,25V,40MA SEMICOND DEVICE:STT,ICON,30V,150MA SEMICOND DEVICE:SLLICON,30V,150MA SEMICOND DEViCE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,15OMA SEMICOND DEVICE:S1LTCON,30V,150MA SEMICOND DEViCE:STLICON,30V,150MA SEMICOND DEVICE:SXLICON,30V,150MA SEMICOND DEVICE:SITAICON,30V,150MA REV, SEB 1981

Tektronix SerialIModel No. Part No. Eff Dscont Mfr Code Ckt No. Name & Description Mfr Part Number SEMICOND DbVICE:SILICON,30V,150MA SbMICOND DEVlCE:S~IAICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA SEMICOND DEVICE:SILICON,30V,150MA DELAY LINE,ELEC:12 NANOSEC,50 OHM DELAY LINE ,ET.EC: 15 NANOSEC ,500HM DELAY LINE,ELEC:lONS,lOO OHM,24 PIN DELAY LINE,ELEC:12.5NS,100 OHM,24 PIN DBL DELAY LINE,ELEC:lONS,lOO OHM,24 PIN DELAY LINE,ELEC:12.5NS,100 OHM,24 PIN DBL DELAY LINE,ELEC:4 NANOSEC,93 OHM DELAY LINE:DUAL,7.5NS & 5.ONS,100 OHM LT EMITTING DIO:GKEEN,565NM,35MA LAMP,INCAND:5V,O.O6A,SEL CORE,EM:TOROID,YEBKI'~E,O.12 OD X 0.07 ID CORE,EM:TOROTD,FERRITE,O.12 OD X 0.07 ID COIL ,RF: 0.3UH COIL,RF:5UH COIL ,RF: 30UH COIL,RF:116UF TRANSISTOR:SILICON,NPN TRANSISTOR:SILICON,NPN TRANSISTOR:SILICON,NPN 'TRANSISTOR: SILICON ,NPN TKANSISTOR:SILICON,NPN TRANSISTOR:SILICON,NPN TRANSISTOR:SILICON,NPN TRANSISTOR:SILICON,PNP TRANSISTOR:SILICON,NPN TRANSISTOR: SJLICON,NPN TRANSISTOR:SILICON,NPN TRANSISTOR:SILICON,NPN REV OCT 1982 +.

Tektronix SerialIModel No. Part No. Eff Dscont Mfr Code Mfr Part Number Name & Descript~on " - -- -- - - -- --- - Ckt No 4740 Q744 Q748 4750 Q754 Q762 SKANSISTOR:SILICON,NPN lKANSISTOR:SILICON,NPN lKANSISIOK:SILICON,PNP TKANSISTOR:SILICON,PNP TRANSISIUK:SILICON,PNP TRANSISTOR: SIT.ICON,PNP TRANSIST0R:STT ICON,PNP TRANSISTOR:SlLICON,NPN TRANSISTOR : S11.ICON ,PNP TRANSISTOR:SILICON,PNP TRANSISI'OR:SILICON,PNP TRANSISTOR:STLICON,NPN,SEL FROM MPS6521 TRANSISTOR:STI,ICON,NPN,SEL FROM MPS6521 TRANSISl'OK:SII.ICON,NPN,SEL EKOM MPS6521 'I'KANSISTOR:SILICON,NPN,SEL FROM MPS6521 TKANSISTOR:SILICON,NPN,SRT~ FROM MPS6521 TKANSIS'TOR: SIT.ICON ,PNP TRANSISTOR: STT,ICON ,NPN TRANSIS'I'OR: SILICON,NPN TRANSISTOR:SII,ICON,NPN,MATCHED TRANSISTOR:SLLICON,NPN TKANSLSTOR:STLICON,NPN 1RANSISTOR:SILICON,NPN,SW FROM MPS6521 TRANSISTOR:SlLICON,PNP lKANSISTOR:SILICON,NPN TKANSISTOR:SlLICON,NPN LKANSISTOR: STX.ICON ,NPN IKANSISTOR:SILICON,NPN TRANSISTOR:STIJICON,PNP TKANSISTOR:SlLICON,PNP,SELEC'I'EL) TXANSISTOR:SITAICON,PNP TRANSISTOR: SIl,ICON,PNP ,SELEC'lCD I'KANSISTOR: S1 I,ICON,PNP I'KANSISTOR: SILICON ,NPN TRANSISTOR:SILfCON,NPN TRANSLSTOR : SILICON ,PNP TRANSISTOR:SILICON,PNP TRANSLS'TOK: SILICON ,PNP T~ANSISTOR:SILICON,PNP TRANSTSTOR:SILICON,PNP TBANSISTOR:SILICON,FE REV AUG 1982

Tektronlx Ser~alIModel No Part No Eff -- -- - - - Dscont -- --- 151-1097-00 151-0342-00 151-0342-00 151-0342-00 151-0342-00 151-0342-00 Mfr Code Mfr Part Number Ckt No 41452 41454 41458 41462 Q1466 Q1470 -- - Name & Descr~pt~on - - - - TRANSISTOR: SILICON ,Et TRANSISTOR:SILICON,PNP TRANSISTOR:SILICON,PNP TRANSISTOR:SILICON,PNP TRANSISTOR:SILICON,PNP TRANSISTOR:SILICON,PNP TRANSISTOR:SILICON,PNP TRANSISTOR:SLLICON,PNP TRANSISTOR:SILICON,PNP TRANSISTOR:SILICON,FE TRANSISTOR: SILICON,NPN TRANSISTOR:S~LICON,PNY R104 R105 R106 R107 R108 Rlll REV OCT 1982

Tektronix SerialIModel No. Ckt No. Part No. Eff Dscont Name & Description Mfr Code Mfr Part Number RES.,FXD,FILM:3.01K OHM,1%,0.125W B020000 B086359 RES.,VAR,NONWIR:2.5 X 1K OHM,10%,0.50W (FURNISHED AS A UNIT WITH R695) B086360 RES.,VAR,NONWIR:2.5 X 1K OHM,lO%,0.50W (FURNISHED AS A UNIT WITH R695) RES.,FXD,FlLM:l.l3K OHM,1%,0.125W REV, SEP 1981

lektronix SerialIModel No. Ckt No. Part No. Eff Dscont Mfr Code Name & Description Mfr Part Number - -- R693 321-0193-00 RES.,FXD,FILM:lK OHM,1%,0.125W R694 321-0173-00 RES.,FXD,FILM:619 OHM,1%,0.125W R695 311-1831-00 B020000 B086359 RES.,VAR,NONWIR:2.5 X 1K OHM,10%,0.50W - . - - - - - - - (FURNISHED AS A UNIT WTIH R680) R695 311-1831-01 B086360 RES.,VAR,NONWIR:2.5 X 1K OHM,10%,0.50W - ----- (FURNISHhD AS A UNIT WITH R680) REV, SEP 1981

Tektronix SerialiModel No. Part No. Eff Dscont Name & Description Mfr Code Mfr Part Number Ckt No RES.,FXD,FlLM:536 OHM,1%,0.125W RES.,EXD,CMPSN:36 OHM,5%,0.25W RES.,VAR,NONWIR:2.5 X 1K OHM,10%,0.50W (FURNISHED AS A UNIT WITH R790) RES.,VAR,NONWIR:2.5 X 1K OHM,10%,0.50W (FURNISHED AS A UNIT WITH R790) RES.,VAR,NONWIR:2.5 X 1K OHM,10%,0.50W (FURNLSHED AS A UNIT WITH R788) RES.,VAR,NONWIR:2.5 X 1K OHM,10%,0.50W (FURNISHED AS A UNIT WITH R788) RES.,FXD,CMPSN:5.1K OHM,5%,0.25W REs,NTklK,FxD,~1:(7)50 OHM,5%,0.125W RES.,PXD,CMPSN:IOO OHM,5%,0.25W RES.,FXD,WW:l.l OHM,5%,3W RES. ,FXD,Fll.M: 1K OHM, 1%,0.125W RES.,FXD,FlLM:9.76K OHM,1%,0.125W RES.,FXD,CMPSN:390 OHM,5%,0.25W RES.,FXD,CMPSN:lK OHM,5%,0.25W REV, SEP 1981

Tektronix SerialIModel No. Part No. Eff Dscont Mfr Code Mfr Part Number Ckt No. Name & Description -- -- REV, SEP 1981

(SN B020000 & up) Mtr Code Tektronix SeriallModel No. Part No. Eff Dscont - - Name & Descr~pt~on - - - - - -- - - - - - Mfr Part Number - "- Ckt No R1329 R1331 R1331 R1332 R1332 R1333 R1333 R1335 R1336 R1339 R1340 R1341 R1342 R1343 R1344 R1345 R1349 R1350 R1351 R1352 R1353 R1354 R1361 R1363 R1364 R1370 R1371 R1372 R1373 R1374 R1375 R1376 R1381 R1382 R1383 R1384 R1385 R1386 R1391 R1392 R1393 R1394 RES.,FXD,CMPSN:lOK OHM,5%,0.25W RES. ,FXD,CMPSN:lOQ OHM,5%,0.25W RES.,FXD,CMPSN:4.7K OHM,5%,0.25W RES.,FXD,CMPSN:ZZO OHM,5%,0.25W RES.,FXD,CMPSN:6.2K OHM,5%,0.25W RES.,FXD,CMPSN:15K OHM,5%,0.25W REV AUG 1982 -\

Tektron~x Ser~allModel No Part No Eff Dscont - " Mfr Code "- 01121 01121 01121 01121 91637 01121 Ckt No Mfr Part Number -. - - - - - - -- - - - CB5115 CB1015 CB1035 CB1345 MFF1816G14302F CB1015 REV, SEP 1981

Mfr Code Mfr Part Number ." Tektronix SerialIMode Part No. Eff 315-0102-00 315-0103-00 315-0101-00 321-0310-00 315-0104-00 315-0104-00 I No. Dscont Name & Description Ckt No. -. . R1486 R1487 R1488 R1490 R1491 R1493 RES. ,FXD,CMPSN:lK OHM,5%,0.25W RES.,FXD,CMPSN:lOK OHM,5%,0.25W RES.,FXD,CMPSN:lOO OHM,5%,0.25W KES.,FXD,b'LLM:16.5K OHM,1%,0.125W RES.,FXD,CMPSN:lOOK OHM,5%,0.25W RES.,FXD,CMPSN:lOOK OHM,5%,0.25W RES.,FXD,FILM:16,5K OHM,1%,0.125W RES.,kXD,FILM:16.5K OHM,1%,0.125W RES. ,EXD,CMPSN:lK OHM,5%,0.25W RES.,FXD,CMPSN:lZK OHM,5%,0.25W RES.,k'XU,CMPSN:lOK OHM,5%,0.25W RES.,E'XD,CMPSN:lOK OHM,5%,0.25W RES. ,VAR,NONWLK:lOK OHM,lW RES.,VAR,NONWLR:lOK OHM,lW SWITCH,PUSH:T,NO CONlACT,RED BU'I'I'ON SWITCH,TOGGLE:SPTT,O.4A,20V SWITCH,TOGGTE:SPTT,O.4A,20V SWITCH,TOGGLE:SPTl,O.4A,20V SWITCH .TOGGI,E : SPi'l ,0.4A, 20V SWITCH,TOGGLE:SPl'I,O.4A,20V SWITCH,TOGGLE : SPTT ,O .4A,20V SWITCH,TOGGLE:SPT'I,0.4A,20V SWITCH,TOGGJ,E : SPl T ,0.4A, 20V SWITCH,TOGGLE:SPTT,O.4A,20V SWITCH,TOGGLE:SPT1,0.4A,20V SWITCH,TOGGLE:SPTT,O.4A,20V SWITCH ,TOGGLE : SPTT, 0.4A, 20V SWITCH,TOGGLE:SPTT,O.4A,20V SWITCH,TOGGLE:SPTT,O.4A,20V SWITCH,TOGGLE:SPTT,O.4A,20V B079999X SWITCH,TOGGLE:SPDT,O.4A,20VDC SWITCH ,TOGGl.E : SPtl"l' ,O. 4A, 20V 09353 7101 SHCBBE 09353 7103SYCBBE TRANSFORMER,RF:BASE DRIVE POT CORE XFMR,PWR,SDN,RF:POT CORE B100265 MICROCIRCUIT,LI:QUAD DIFF LINE RECEIVER MICROCIRCUi'I',DI:QUAD DIFF LINE RECEIVER B100265 MICKOCIRCUl'T,DI:DUAL 3-IN,3-OUT GATE REV AUG 1982

Tektron~x Ser~alIModel No Part No Eff -- -- - - - - - Dscont 156-0757-01 B100266 156-0757-00 B020000 B100265 156-0757-01 B100266 156-0638-00 B020000 B100265 156-0638-01 B100266 156 0638-00 B020000 B100265 Mf r Name & Description Code Mfr Part Number Ckt No - -- U108 UllO UllO u120 u120 U130 MICROCiKCU1'1,DI:DUAL 3-IN,3-OUT OR NOR MICROClRCUIT,DI:DUAL 3-IN,3-OUT GAlb MILKOCIRCUIT,DI:DUAL 3-IN,3-OUT OR NOR MICROCiRCUIT,DI:FOUR-BIT UNIV SHIFT RGTR MICROCIRCUL'1,DI:FOUR-BIT UNIVSHih1 RGlK MICROCIRCUIT,DI:FOUR-BIT UNIV SHIFT RGTR MICROCIKCUI1,DI:FOUR-BIT UNIVSHihl RGZK MICROCIRCUIT,DI:QUAD 2-INPUT NOR GATE MICROCIRCUIT,DI:QUAD 2-INP NOR GATL,SCRN MICROCIRCUlI,DI:QUAD EXCLUSIVE-OR COMP MICROClKCUIT,DI:QUAD EXCL OR CMPlK MICROCIRCUIT,DI:UNlVLRSAL,HEXlU~CIMAL CNlR MICROClKCUI~1,DI:UNIV HEX CNTK,SCKN MICROCIRCUI'I*,DI:UNIVEKSAL,HEXlDECIMAL CNTR MICROCIRCUIT,DI:UNIV HEX CNTR,SCRN MICROCIRCUIT,DI:QUAD 2 INPUT MUXILATCH MICROCIRCUIT,DI:QUAD 2 INPUT MUX/LATCH MICROCIRCUIT,DI:FOUR-BIT UNIV SHIFT RGTR MICROCIRCUIT,DI:FOUR-BIT UNIVSHIFT RGTR MICROCIRCUI'I*,DI:FOUR-BIT UNlV SHIFT RGTR MICROCIRCUIT,DI:FOUR-BIT UNIVSHIFT RGTR MICROCIRCUIT,DI:256 BIT RAM MICROCIRCUIT,DI:256 X 1 STATIC RAM MICKOCIRCUIT,DI:256 BIT RAM MICROCIRCUIT,DI:256 X 1 STATIC RAM MICKOCIRCUIT,DI:256 BIT RAM MICROCIRCUIT,DI:256 X 1 STATIC RAM MICROClKCUIl,D1:256 BIT RAM MICROCIRCUIT,DI:256 X 1 STATIC RAM MICKOCIRLUlT,DI:QUAD AND GATh,2-INP MICBOCIRCUIT,DI:QUAD AND GATE2 INP,SCRN MICROCIRCUIT,DI:DUAL D MA-SLAVE FLIP-FLOP MICROCIRCUIT,DI:DUAL D-TYPE M/S,FF,SCRN MICROCIRCUIT,DI:THIPLL 2-3-2 INPUT GATh MICROCIRCUl'~,DI:ZKIPLE 2-3-2 INPUT GAIT MICROCIRCUlT,DI:FOUR-BIT UNIV SHIFT RGTR MICROCIRCUIT,DI:FOUK-BIT UNIVSHIFT RGTK MICROCIRCUIT,DI:FOUR-BIT UNIV SHIFT RGTR MICROCIRCUlT,DI:FOUR-BIT UNIVSHIYl RGlK MICROCIRCUIT,DI:756 B11 RAM MICROCIRCUIY,DI:256 X 1 STAllL RAM MICROCIRCUIT,DI:256 BIT RAM MICROCIRCUIT,DI:256 X 1 STATLC RAM MICROCIRCUIT,DI:256 BIT RAM MICROCLKCUIT,DI:256 X 1 STATIC RAM MICROCIRCUIT,DI:256 BIT RAM MICROCIRCUIT,DI:256 X 1 STATIC RAM MICROCIRCUIT,DI:QUAD 2 INPUT MUXILATCH MICROCIRCUIZ,DI:QUAD 2 INPUT MUXILATCH MICROCIRCUIT,DI:FOUR-BIT UNIV SHIFT RGTR MICROCIRCUIT,DI:FOUR-BIT UNIVSHIFT RGTR MICROCIRCUIT,DI:FOUR-BIT UNlV SHIFT RGTR MICROCIRCUIT,DI:YOUR-BIT UNIVSHIFT RGTR MICROCIRCUIT,DI:256 BIT RAM MICROCIRCUIT,DI:256 X 1 STATIC RAM MICROCPRCUIT,DI:256 BIT RAM REV OCT 1982

C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C m m m m u u u u m m m m m m m m m m m m m m m m m m m m m m m m m V I V I ~ V I ~ ~ V I ~ V I V I V I V I V I ~ V I W ~ P P C C C C P r - 0 O V I V I P C W W N N N N N N N N N N N ~ r r r r r r r r o o u u u u m m w V I V I V I V I V I V I 0 C C W w m m V 1 L n V I 0 V I o o o O N N O O N N m m w m e C w w N N r r a a u u m m o o m m N N o o o o m m m m P P N N m m m w o o m m m m c Z 0 C r r C r c . V I V I V I V I V I V I m m m m m m I I I I I I 0 0 0 0 0 0 N N N V V N w w w w m w O O O N N O I I I I I I 0 0 0 0 0 0 O N O N O N r r r r r r V I V I V I V I V I V I m m m m m m I I I I I I 0 0 0 0 0 0 N N N N N O I w a a o o r - 0 V l V l V l V l 0 I I I I I I 0 0 0 0 0 0 O N O N O N r r r r r r VImVIVILnVI m m m m m m I I I I I I 0 0 0 0 0 0 m m m m m m m V l V l V l V l L n u u u u u u I I I I I I 0 0 0 0 0 0 O N O N O N r r r r r r V I V I W V I V I V I i - O - + m m m m m m I I I I I I 2 5 0 0 0 0 0 0 P m m m m m z; V I V I V I V I V I V I 1 O 2 m u u u u u I I I I I I 0 0 0 0 0 0 X O N O N O N . . . LnVIVI m m m I l l 0 0 0 m m N C C O NNVI I l l 0 0 0 W O N . . . . . . V I ~ V l V l V l V l m m m m m m I I I I I I 0 0 0 0 0 0 N N N O I r n N o o o m m o V I o o m m V I I I I I I I 0 0 0 0 0 0 O N O V O N 2% m m m m w w m m w m m w m w m m m w m m m m m m m m m m m m m m m m m m m m m m m w m m m t a w m a t a m w m m m m w - 0 - O r 0 - O r O r O r O r O r O r O r O r O r O r O r O r O r O r o r o r O r O r O r O r o r o r O r O r O r O N 0 N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O N O El 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O O O O O N O N O N O N O N O N O N O N O N O N O N O N O N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 m o m o m o m o m o m o m o m o m o m o m o m o m ' 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 m o m o m o m o m o m o m o m o m o m o m o m o m m 3 5 3 n n n m m m 8 8 8 H U H m m m n n o c c c H H H .??? 5 5 5 3 3 5 n C I n n n n m m m m m m 0 0 0 0 0 0 n n n n n n H C H U H H m m m m m m n n o n 0 n C C G C C C H H H H H H H H c ; e e H b';.F'b'b'b H W H H H H 3 3 5 5 3 3 n n n n n n m m m m m m 0 0 0 0 0 0 n o n n n n H H Y H U H m m s a m m m n n n n n n c c c c c c H H H U H H "H "H "e e H H " " " 3 5 3 5 5 5 n n n n n n m m m m m m 0 0 0 0 0 0 n n n n n n U C H H H H m m m m m 0 n n n n n n C C C C C C C I H H H U U e e e e e c 3 " " " " " " Z S S Z S Z 5 3 5 5 3 5 n n n n n n m m m m m m 0 0 0 0 0 0 n n n n n n H H H H H U m m m m 7 Q m n n n n n n C C C C C C + H C I H + H e r i r r e e r i " " " " " " w u u w u u H H H H H H ............ m m m . o . 0 N c c m r r r + > m H H H 0 u Z Z Z m m m + p X Z Z r 5 5 k W o m r r r o o e r j H c ; P P P r H c r j c : e ' d ' d ' d m m c r r r ~ - n M M l r N X X X H I m m m z ~ m n z Z X X X X X H H U H H H n n n n o n m m m m m m 0 0 0 0 0 0 n n n n n n H H H C - U H P m S W m D o n n n n n C C C C C C C I H H H H H e r j r ; + e t j " " " " " " w u w t l w u H H H H H H ............ N N N N N N V l V l m V l V l V l m m m m m m , 5 5 3 3 3 3 n n n n n n m m m m m m 0 0 0 0 0 0 n n n n n n H H H H H H m m m m m m o n o n n o C C C C C C C I H H H C I H e H "e "e "6 H .." u w w u w w H H H H H H ............ w w w w w . 0 V 1 O O O O C r n C C C C P m ? ? 5 P ? b X X X X X Z H H H H H H n n n n n n m m p m m m 0 0 0 0 0 0 n n n n n n , H C I H H H H m x m m m m n n n n n n C C C C C C H H W W H C I H H e e - c ; " " " " " " Z ~~~~~~ H H H H H H W ............ 3 O N N N N N ; C D 'd I % .d .d % n n n n n n C C C C C C H H H U H H e e c 3 4 r j e " - - - - - b u w H H H ...... tluuuuu H H H H H H ............ t l ~ w ~ b b H H H H H H ............ P !D N H H 4 4 N l H H l I I H O O A A U Z Z Z 21 . Z R F 5 L W H m m z * P -3 r3 0 z z x m m m o w a m z m r r o r u m m p o w w r r c j P H U P P ~ e m m c < - m m m m m ~ l=ltbt;lidtbP e H H H H a m H H H H U P C C C C C I X Z Z Z Z P H H H H H < C C C M m m w ~ m x m r x r x u W H n j H Z H w e w ' d H H " m m m o m o m n r ? o c 3 0 m W H l i H Z m m 53i5Y72 I 'd I W W ' C m m m I I E g5g;;5 m m m z z m " w w - w w w c c w E;"w E; H H " w L C l m v o G I m I n 1 P P n w m w e 4 m r z r m m z g % ~ N M A A I x z z g I Hn'd'dr m z * c r j F'd Z P U P 0 0 'd c ~ m m z r m l e o m n m o m x r r l r x x - m z o 2 " s g w ' P W z m F i w a o n t ' o m 56 g a z n n z Z Z O + + e m m m L 6 n m 3 2 " m n m Z m o o o o o o o o o m m o m m m m m o o m o m o m m m o m m o o m m m m o o o o o o o o o o o o o o o o o o o o o j n ~ O P P P C C P P C P O O P 0 0 O O O P P O C O C O O O C O O C P O 0 0 0 P C P P P C P C C C P C C C C C C P C P C o u u u u u u u u u o o u o o o o o u u o u 0 u 0 0 0 u o o u u o o o o u u u uuuuu-4 u u u u u u u u u u u u o r r r r r r r r r o o r o o o o o r r o r o r o o o r o o r r o o o o r r r r r r r r r r r r r r r r r r r r r j g T a w w W W W W W W w a a w w w w w w w w a w w w a w w w w w w w a a w w w w w w w w w w w W W W W W W w w w w w w I 0 0 0 0 0 0 r r r r r r C C C C P C C C C P P C r r r r r r c o o o o o In o r r r r r [ a ) C C C C C C -7 r c P P e c - / d r r r r r I Z I '= - I I ; ~ I w o o 0 0 c o o r 0 m . . . r r r r b I l l I 0 0 0 0 o r 0 N

(SN BO2OhlOO & up) Tektron~x Ser~aliModel No Part No Eff .- Dscont 156-0642-00 B020000 B099999 156-0642-01 BlOOOOO 156-0642-00 B020000 B099999 156-0642-01 BlOOOOO 156-0642-00 B020000 B099999 156-0642-01 BlOOOOO Mfr Code Ckt No. ---- - U812 U812 U814 U814 U816 U816 Name & Descr~pt~on - - - - - MICROCIRCUIT,DI:BI-QUINARY CNTR MICROCIRCUIT,DI:BI QUINARY CNTR,SCRN MICROCIRCUIT,DI:BI-QUINARY CNTR MICROCIRCUIT,DI:BI QUINARY CNTR,SCRN MICROCIRCUIT,DI:BI-QUINARY CNlK MICROCIRCUIT,DI:BI QUINARY CNTH,SCRN Mfr Part Number - MC10138L 156-0642-01 MC10138L 156-0642-01 MC10138L 156-0642-01 156-0642-00 B020000 B099999 156-0642-01 BlOOOOO 156-0640-00 B020000 B099999 156-0640-01 BlOOOOO 156-0637-00 B020000 B099999 156-0637-01 BlOOOOO MICROCIRCUIT,DI:BI-QUINARY CNTK MICROCIRCUIT,DI:BI QUINARY CNTR,SCRN MICKOCIRCUIT,DI:8 LINE MULTIPLEXER MICROCIRCUIT,DI:8 LINE MULTlPL,EXER MICROClRCUlT,DI:DUAL 4 TO 1 MULTJPI,EXER MICROCIRCUIT,DI:DUAL 4 TO 1 MUX 156-0642-00 B020000 B099999 156-0642-01 BlOOOOO 156-0637-00 B0.20000 B099999 156-0637-01 BlOOOOO 156-0402-00 XB080000 B099999 156-0402-03 BlOOOOO MICROCIRCUIT,DI:BZ-QUINARY CNTR MICROCIRCUIT,DI:BI QUINARY CNIR,SCRN MICROCIRCUIT,DI:DUAL 4 TO 1 MULTIPLEXER MICROCIRCU1'1,DI:DUAL 4 TO 1 MUX MICROCIRCUIT,LI:TIMER MICROCIRCUIT ,LI:TIMER ,TES'IEl) 156-0402-00 B020000 B099999 156-0402-03 BlOOOOO 156-0369-00 B020000 B100219 156-0369-03 B100220 156-0369-00 B020000 B100219 156-0369-03 B100220 MICROCIRCUlT,LI:IIMLR MICROCIRCUI'I ,LI :TIMER,'rESSrhU MICROCIRCUIT,DI:TKIPLE LINE RECEIVER MICROCIRCUIT,DI:TRIPLE LINE RECEIVEK,SCRN MICROCIRCUIT,DI:TRIPLB LINE RECEIVER MICROCIRCUIT,DI:TRIPLE LINE RECElVLK,SCRN MICROClRCUIT,DI:IKIPLE LINE KECEIVEK MICROCIRCUIT,DI:TRXPLE LINE RECEIVER,SCRN MICROCIRCUIT,DI:TKlPEE LINE RECElVhR MICKOCIRCUIT,DI:TRIPLO LINE RECEIVbR,SCRN MICROCIRCUIT,DI:TRIPLE LINE RECEIVER MICROCIRCUIT,DI:TRIPLE LINE RECElVtK,SCRN MICKOCIRCUIT,DI:TRIPLE LINE RECEIVER MICROCIRCUIT,DI:TKIPLE LINE RECEIVER,SCRN MICROCIRCUIT,DI:DUAL 4-5 IN ORINOR MICKOCZKCUIT,DI:DUAL 4/5 INP OR NOR GATE MICROCIRCUIT,DI:DUAL 4-5 IN ORINOR MICROCIRCUlT,DI:DUAL 415 INP OR NOR GATE MICROCIKCUlT,DI:QUAD AND GATE,2-INP MICROCIRCUIT,DI:QUAD AND GATE2 INP,SCKN MICROCIRCUIT,LI:OPERATIONAL AMPLIFIER MICROCIRCUl'I',LI:OPERATIONAL AMPLIFIEK MICROClHCUIT,DI:QUAD 2-INPUT EXCL OR GATES MICROCIKCUIT,DI:QUAD 2-IMP EXCL OR GATE MICROCIRCUI1,DI:DUAL D-TYPE,FLIP-FLOP MICROCIRCUIT,DI:DUAL D-TYPE FLIP-FLOP MICROCIRCUIT,DI:DUAL D FLIP-FLOP MICROCIRCUIT,DI:QUAD 2-INPUT NAND GATb MICROCIRCUIT,DI:QUAD 2-INP NAND GATE MICROCIRCUIT,DI:QUAD 2-INPUT NOR GATE MICROClKCUIT,DI:QUAD 2-INP NOR GATE MICROCIRCUIT,DI:MONOLITHIC,4 DECADE COUNTER MICROCIRCUIT,DI:4 DECADE COUNTER MICROCIRCUlT,DI:QUAD 2-INPUT NAND GATE MICROCIRCUIT,DI:QUAD 2 INPVI' NAND GATb,CHK MICROCIRCUIT,DI:QUAD 2 INPUT AND GATE MICROCIRCUIT,DI:QUAD 2-INP AND GATE,SEL MICROCIRCUIT,DI:SYN 4-B,UP-DOWN BINARY CTR MICROCIRCUIT,DI:SYN 4-B UP/DNBIN,CNTR,SEL REV OCT 1982

V l P C C C - \ D a m - W C C N N c c c c c c r r C r - C C C W W W W 0 O U . I . l U N N N N O O c c c c c c r r r t - r - W W W W W W VlVlVlVlCP O \ O \ N N ~ C O . . . . W W W W W W m m m m V l w c w m m m m c o r r r r r V l u l u l V l W m m m m m I I I I I r o o 0 0 N m m m m C C C P P . l C C C C I I I I I 0 0 0 0 0 O W O W O e r r r r r V l V l V l V l V l V l m m m m m m I I I I I I 0 0 0 0 0 0 W W W W W W U ) \ D \ D \ D U ) U ) N N N N N N I I I I I I 0 0 0 0 0 0 W O W O W O - C . r r r c V l V l i n U I V l W m m m m m m I I I I I I 0 0 0 0 0 0 W W W W V l V l r ~ ~ o m m u ~ N N ~ ~ N N I I I I I I 0 0 0 0 0 0 W O W O N O L n V l W W V l W m m m m m m I I I I I I 0 0 0 0 0 0 V l V l C C W W U U - J U ~ ~ ~ N N N N N N I I I I I I 0 0 0 0 0 0 N O W O N O W V l W W V l V l m m m m m m I I I I I I 0 0 0 0 0 0 m m m m m m N N N N N N rDiDU.JU)\D I I I I I I 0 0 0 0 0 0 C O N O - 0 X m m m m m O - 0 - 0 O ON ON 0 0 0 0 0 O N O N O O C O P O O C O C O EgzgE'g O N O N O N 0 0 0 0 0 0 N O N O N O P O P O P O C O C O C O z g z g z g O N O N O N 0 0 0 0 0 0 N O N O N O C O C O P O P O P O C O z g z g z g O N O N O N 0 0 0 0 0 0 N O N O N O C O C O C O C O C O C O z g z g z g O N O N O N 0 0 0 0 0 0 N O N O N O P O P O C O C O C O C O z g z g z g O N O N O N 0 0 0 0 0 0 N O N O N O P O C O P O C O C O P O r r r 0 0 0 0 0 0 N N N C C P W W W z z z 0 0 0 0 N N N 0 0 P C C W W W z z z 0 0 0 0 0 0 N N N P C P W W W . . 0 0 0 0 0 0 N N N * P C W W W 3 5 3 3 5 3 n n n n n n m m m a a m 0 0 0 0 0 0 nnC?nnn H H + H H H w m m m m m n n n n n n C C C C C C H H , - l H H H H H @ c ? * H " " " " . . " a w w w a a H H H H H H . . . . . . . . . . . . A A A A A A c c c c c c P P P X - P P u w w a w a r r r r r r P P P P P P c j H c j H H H n n n n n n x ~ m x x a 5 5 5 5 5 5 o n n o n o m m m m m m 0 0 0 0 0 0 nnC)nnn H H H H H H m m a m a m n n c n n n C C C C C C H C I I - H H H i r i r - ' r i H H " " " " " " w w w a a a H H H H H H . . . . . . . . . . . . ~ ~ w u c o c w C C C C X - P P P W W W W F F H H r r a w H H P P I K m ::FzE$ a x n a ~ n a m w ~ E E A W F F O n r r H H r P 0 H Z Z mm'd'd-. l P P l a w m m w m m y r r 5 5 5 5 5 5 C i o n C ? C i C ) m m m m z 7 c O O O O O C n n n n n n H H H H F H m m m a m m n n n n o n c c c c c c C I H H H H H H e e H H - I c n n n n n m z * l a m m o o o o o o n n n o n n H H C H ~ ~ H m m a m m m n n n n n n c c c c c c n n c ) n n a m m x m 0 0 0 0 0 n n n n n H H H F H m m m m m n n n n n C C C C C -~~ " " " " " " w a w a a w H H H H H H . . . . . . . . . . . . " " " " " " w w w a a a H H H H H H . . . . . . . . . . . . m m A A W W 4 4 C C O O Z Z P P x a w x m C C I l N N N X N m m I 'd " H H ' d P C C Z Z L W w ' e ' e ' d m m - . ~ c e m m a w ~ c i m r z o H H m f Z Z H P H Z P P P W z z z m r - m w u r m 2 E n o " m H P P X - m u m m c r r j c r r j r z e m m z m - n m n n cj r e x m v2 t*: . . . . , . , . , . . . . . . . . . . . W O A A A C C C C C P X - P P P r u a a a m m r r ~ ~ W W C C m m l P P U H H H W a H +3 z z C d ' e N N m w c c I I I l r r H r j H H m m z z H H Z Z W ' C * P P P c r r z z z c j m a * Z Z E E o n a P -.I P P z W a ~ e o a a say t- P r r rt, m m * 0 0 0 r-' c c m F -; r3 z WWCncnWW 0 0 4 4 0 0 x z z x E R P c G K N I I N a m m w a @ m m c c m m ' d m m m a ' d m m mm--.l rnrr. m e a t r ~ e ri*aoc?crrj +?.?zsg?& m r z r m - m r m m r m n u m m z z m m C H P m H H Z m m - I z z - 4 z : n m n H m n + m r e 7c m r m m w m P H H H H ~ r r r r ClPX-PP Z j i - Z d Y mP2;rlm E E E E m m m m ? S ? E m r m c j c n c n m x m x ? m m m m m 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w w U ) \ D \ D 0 w 0 w 0 w r C r C r C N W N W N W U ) W U ) W \ D W V l W l l c n W V l W o w o m ~ m r P u 0 4 0 N W N O O O U 3 w m o r o m m m m c n m Z Z Z Z Z Z u.l.l.Juu P P C C P C m r m r m r C m C . m r m U r V r U C Vl .I Vl U Ln u Z W Z W Z l l c n a z w z w z W W W 0 0 0 m m m P l C P P P n o m m r r r ~ r r m m m u W W O 0 P N W W O O 4 1 Z - P 0 z + 0 0 m m m r Z Z V l P 2 E V U m U U U P C I C P P r r o n r r m m m C m m C C N U ) r r L P L L E E m U m m - 4 . I l C I I C P o n o o r r m r w L ] W m m N \ D V l W - + . . U W 0 0 U ) U ) 1 4 1 1 U . I 0 0 0 z N W O . . . . . V l V l W V l W m m m m m I I I I I r o o 0 0 N m m m m C C P C P U P C P C I I I I I 0 0 0 0 0 O W O W O

INSTRUMENT OPTIONS Your instrument may be equipped with one or more instrument options. A brief description of each available option is given in the following discussion. Option information is also incorporated into the appropriate sections of the manual. Refer to Table 7-1 and the "i'able of Contents for location of option information. Conversion kits, for most options, are available and can be installed at a later time. For further information on instrument options, see your Tektronix Catalog or contact your 'Tektronix Field Office. OPTION 49 Deletes one P6451 Data Acquisition Probe from the standard accessories furnished with the 7D01 TABLE 7-1 I Option Information Locator lnstrument Options ~ "" Manual Section. Location of Information --.--- " " .... "" - -- Option 49 7 Instrument Options (Delete One P6451 Probe) Instrument t- All information is contained in this Options section.

Symbols and Reference Designators Electrical components shown on the diagrams are in the following units unless noted otherwise: Capacitors = Values one or greater are in picofarads (pF). Values less than one are in microfarads (pF). Resistors = Ohms (a). Symbols used on the diagrams are based on ANSl Standard Y32.2-1975. Logic symbology is based on ANSl Y32.14-1973 in terms of positive logic. Logic symbols depict the logic function performed and may differ from the manufacturer's data. The following prefix letters are used as reference designators to identify components or assemblies on the diagrams. Assembly, separable o r repairable (circuit board, etc.) Attenuator, fixed or variable M o t o r Battery Capacitor, fixed o r variable Circuit breaker Diode, signal o r rectifier Delay line Indicating device (lamp) Spark Gap Fuse Filter Heat dissipating device (heat sink, heat radiator, etc.) Heater H y b r i d circuit Connector, stationary p o r t i o n Relay Inductor, fixed or variable Inductor/resistor combination Meter Connector, movable p o r t i o n Transistor o r silicon-controlled rectifier Resistor, fixed o r variable The following special symbols are used on the diagrams: VERTICAL AMPLIFIER @ Thermistor S w i t c h Transformer Thermocouple Test p o i n t Assembly, inseparable o r non-repairable (integrated circuit, etc.) Electron tube Voltage regulator (zener diode, etc.) Crystal Phase shifter Cam Switch Closure Chart l nternal Screwdriver Adjustment Test Voltage Plug to E.C. Board Panel Adjustment Plug Index Modified Component-See Parts List Refer to Waveform Refer to Diagram Number SEL Value Selected at Factory Coaxial Connector Panel Connector Assembly Number Board Name Etched Circuit Board Outlined in Black Schematic Name and Number

UNlJUNCTlON TRANSISTOR DIODE Figure 8-1. Semiconductor lead configuration. REV A. JAN 1979

2E C130 1E J138 2E C150 2C R107 5 J C252 3 A C356 4F R l l l 2E C445 4 H P I 1 2 3 A C456 4G P113 5G R113 2F C560 2K R114 5G C911 4 K P I 1 8 5G R115 5G C935 5 A P I 3 9 2 H CR105 2G P212 5B CR106 2G C R l l O 5G P224 511 C R l l l 5G R126 5F CR112 5G R141 3 K CR113 5G CR114 5G CR115 5F CR116 5G R223 5G CR117 5G R241 4 8 CR118 5G CR119 5E CR120 5F CR121 5E CR122 5F CR123 5E CR124 6F DL224 5C DL424 51 side. 1

Figure 8-4. AB-Interconnect circuit board, as viewed with board installed. " "- %ID IORD .~ g I I a I ) C ! I 1 I I 1 1 4 .. -- "- REV. B FEB 1977 ... " CKT GRID NO COORD " R521 45 R531 45 R541 4K R551 35 R561 2K U106 2G U108 2G UllO 2F U120 2D U130 2E U132 2D -. CKT GRID NO COORC .." -,... ""-.- U435 41 U445 4H U452 3F U454 3F U456 3H U458 3H U460 21 U535 45 U545 4J U552 31 U554 31 U556 3J U136 2C U140 28 U550 2C U225 4C U235 4C U245 4 8 U252 38 U254 3C U256 3C U258 3D U260 2H U268 5J U269 55 U335 4D U345 4E U352 3D U354 3E U356 3E U358 3F U425 41 - U558 3J U560 2J U570 21 U572 21

REV. A FEB 197'7 I kigure 8-5. A3-Output circuit board, component si e. ' i 8 t I