Neoway N720 Hardware User's Manual
Read Online
Read the Neoway N720 Hardware User's Manual online using the built-in PDF viewer.
Text of the manual
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
i
Copyright
Copyright © 2018 Neoway Technology Co., Ltd. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without
prior written consent of Shenzhen Neoway Technology Co., Ltd.
is the trademark of Shenzhen Neoway Technology Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.
Notice
This document provides guide for users to use the N720.
This document is intended for system engineers (SEs), development engineers, and test engineers.
The information in this document is subject to change without notice due to product version update
or other reasons.
Every effort has been made in preparation of this document to ensure accuracy of the contents, but all
statements, information, and recommendations in this document do not constitute a warranty of any
kind, express or implied.
Shenzhen Neoway provides customers complete technical support. If you have any question, please
contact your account manager or email to the following email addresses:
[email protected]
[email protected]
Website: http://www.neoway.com
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
ii
Revision Record
Version
Changes
Revised By
Date
V1.0
Initial draft
Li Qiusheng
2016-04
V1.1
Added bands information of different areas
Dong Liuting
2016-09
V1.2
Modified pin the description
Dong Liuting
2016-10
V1.3
Deleted UIM2
Added band information of different areas
Modified some pin definition: RING is changed to
the 13th pin, LIGHT is changed to the 83rd pin
Dong Liuting
2016-12
V1.4
Modified recommended circuit 1 for UART.
Added recommend circuit 2 for UART
Wang Qiang
2017-02
V1.5
Added LTE B12 to the US version
Added memory and dimensions tolerance
Modified the description of the PWRKEY and
RESET pins
Dong Liuting
2017-07
V1.6
Updated variants and bands
Added SDIO, PCM, and I2C
Added GNSS parameters
Modified some description
Dong Liuting
2018-01
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
iii
Contents
1 Introduction to N720 ......................................................................................................... 1
1.1 Overview ............................................................................................................................................ 1
1.2 Block Diagram ................................................................................................................................... 2
1.3 Features .............................................................................................................................................. 3
2 Application Interfaces ...................................................................................................... 5
2.1 Specifications and Pin Definition ....................................................................................................... 5
2.2 Pin Description ................................................................................................................................... 6
2.3 Power Control Interfaces .................................................................................................................. 14
2.3.1 VBAT ...................................................................................................................................... 14
2.3.2 VDDIO_1P8 ............................................................................................................................ 18
2.3.3 ON/OFF .................................................................................................................................. 18
2.3.4 RESET .................................................................................................................................... 20
2.4 USB Interface ................................................................................................................................... 21
2.5 UIM Card Interface .......................................................................................................................... 22
2.6 GPIO Interfaces ................................................................................................................................ 23
2.6.1 UART ...................................................................................................................................... 24
2.6.2 ADC ........................................................................................................................................ 26
2.6.3 NET_LIGHT ........................................................................................................................... 27
2.6.4 DTR ......................................................................................................................................... 27
2.6.5 RING Signal Indicator ............................................................................................................ 28
2.7 AUDIO Interfaces ............................................................................................................................. 29
2.7.1 PCM ........................................................................................................................................ 29
2.7.2 I2C ........................................................................................................................................... 31
2.8 WLAN Interfaces ............................................................................................................................. 31
2.8.1 SDIO ....................................................................................................................................... 31
2.8.2 WLAN Control ........................................................................................................................ 33
2.9 Commissioning Interfaces ................................................................................................................ 35
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
iv
2.9.1 FORCE_USB_BOOT ............................................................................................................. 35
3 RF Interface ....................................................................................................................... 36
3.1 2G/3G/4G RF Design and PCB Layout ............................................................................................ 36
3.2 GNSS RF Design and PCB Layout .................................................................................................. 38
3.2.1 GNSS Impedance .................................................................................................................... 38
3.2.2 Active GNSS Antenna Design ................................................................................................. 38
4 Electrical Features and Reliability ............................................................................... 40
4.1 Electrical Features ............................................................................................................................ 40
4.2 Temperature Features ....................................................................................................................... 40
4.3 ESD Features .................................................................................................................................... 41
5 RF Feature ......................................................................................................................... 42
5.1 Operating Band ................................................................................................................................. 42
5.2 TX Power and RX Sensitivity .......................................................................................................... 43
5.3 GNSS Features ................................................................................................................................. 44
6 Mechanical Feature ......................................................................................................... 45
6.1 Dimensions ....................................................................................................................................... 45
6.2 PCB Foot Print ................................................................................................................................. 46
7 Mounting and Packaging ............................................................................................... 47
7.1 Mounting the Module onto the Application Board ........................................................................... 47
7.2 Packaging ......................................................................................................................................... 47
8 SMT Temperature Curve ............................................................................................... 48
9 Abbreviations ................................................................................................................... 49
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
v
Table of Figures
Figure 1-1 N720 block diagram ............................................................................................................... 3
Figure 2-1 N720 module pin definition (Top View) ................................................................................ 5
Figure 2-2 Current peaks and voltage drops .......................................................................................... 14
Figure 2-3 Capacitors used for the power supply .................................................................................. 15
Figure 2-4 Reference design of power supply control ........................................................................... 15
Figure 2-5 Reference design of power supply controlled by p-MOSFET ............................................. 16
Figure 2-6 Reference designs of separated power supply ...................................................................... 17
Figure 2-7 Push switch control .............................................................................................................. 18
Figure 2-8 MCU control ........................................................................................................................ 18
Figure 2-9 N720 power-on/off sequence ............................................................................................... 19
Figure 2-10 N720 power-off sequence .................................................................................................. 19
Figure 2-11 Reset controlled by button ................................................................................................. 20
Figure 2-12 Reset circuit with triode separating .................................................................................... 20
Figure 2-13 N720 reset sequence ........................................................................................................... 20
Figure 2-14 USB circuit......................................................................................................................... 21
Figure 2-15 Reference design of SIM card interface ............................................................................. 22
Figure 2-16 UIM connector encapsulation ............................................................................................ 23
Figure 2-17 Reference design of the UART interface ........................................................................... 24
Figure 2-18 Recommended level shifting circuit 1 ................................................................................ 25
Figure 2-19 Recommended level shifting circuit 2 ................................................................................ 26
Figure 2-20 LED indicator driven by transistor ..................................................................................... 27
Figure 2-21 RING indicator for incoming call ...................................................................................... 28
Figure 2-22 RING indicator for SMS .................................................................................................... 28
Figure 2-23 PCM connection ................................................................................................................. 29
Figure 2-24 PCM synchronization timing ............................................................................................. 29
Figure 2-25 PCM data input timing ....................................................................................................... 30
Figure 2-26 PCM data output timing ..................................................................................................... 30
Figure 2-27 SDIO connection ................................................................................................................ 32
Figure 2-28 SDIO SDR timing .............................................................................................................. 32
Figure 2-29 SDIO DDR timing ............................................................................................................. 33
Figure 2-30 32KHz clock signal timing ................................................................................................ 34
Figure 2-31 Reference design of the fast boot interface ........................................................................ 35
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
vi
Figure 3-1 Reference of antenna matching design................................................................................. 36
Figure 3-2 Recommended RF PCB design ............................................................................................ 37
Figure 3-3 Encapsulation specifications of Murata RF connector ......................................................... 37
Figure 3-4 RF connections ..................................................................................................................... 37
Figure 3-5 GNSS RF structure .............................................................................................................. 38
Figure 3-6 Power supply reference for active antenna .......................................................................... 39
Figure 6-1 Dimensions of N720 ............................................................................................................ 45
Figure 6-2 N720 PCB foot print (Top View) ......................................................................................... 46
Figure 8-1 Temperature curve ................................................................................................................ 48
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
vii
Table of Tables
Table 1-1 N720 baseband and wireless features ...................................................................................... 3
Table 2-1 N720 dimensions ..................................................................................................................... 5
Table 2-2 N720 pin description ............................................................................................................... 6
Table 2-3 GPIO ...................................................................................................................................... 23
Table 2-4 Timing parameters of PCM interface .................................................................................... 30
Table 2-5 Timing parameters of SDIO interface ................................................................................... 33
Table 2-6 Timing parameters of 32KHz clock signal ............................................................................ 34
Table 4-1 N720 electric features ............................................................................................................ 40
Table 4-2 Temperature feature ............................................................................................................... 40
Table 4-3 N720 ESD features ................................................................................................................ 41
Table 5-1 N720 operating band ............................................................................................................. 42
Table 5-2 N720 RF power and RX sensitivity ....................................................................................... 43
Table 5-3 GNSS parameters .................................................................................................................. 44
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
1
1 Introduction to N720
1.1 Overview
N720 is an industrial-grade 4G module developed on Qualcomm platform. Its dimensions are 30 mm x 28
mm x 2.8 mm. This module has an ultra-wide operating temperature range of -40 °C to +85 °C and
electrostatic capacity of 8 kV. N720 is well applicable to develop wireless meter reading terminal,
in-vehicle computers, POS, industrial routers, and other IoT terminals with the following features:
ARM Cortex-A7 processors, 1.3 GHz main frequency, 256 KB L2 cache, 28 nm process technology
GSM/GPRS/EDGE &CDMA2000 1x/1xAdvanced/1xEV-DOrA &&WCDMA R99 to
DC-HSPA+&&TD-SCDMA<E Cat4
USB2.0/ UIM/ADC/UART/GNSS (optional) /SDIO/PCM/I2C
N720 series include the following versions to meet the band requirements in different areas:
Module
Version
Area
Category
Band
N720
CA
China
Cat4
FDD-LTE: B1, B3, B5, B8
TDD-LTE: B38, B39, B40, B41
TD-SCDMA: B34, B39
UMTS: B1, B8
EV-DO: BC0
CDMA 1x: BC0
GSM/GPRS/EDGE: 900/1800 MHz
CB
China/India
Cat4
FDD-LTE: B1, B3, B5, B8
TDD-LTE: B38, B39, B40, B41
TD-SCDMA: B34, B39
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
CC
China
Cat4
FDD-LTE: B1, B3, B8, B28
TDD-LTE: B38, B39, B40, B41
TD-SCDMA: B34, B39
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
EA
Europe
Cat4
FDD-LTE: B1, B3, B5, B7, B8, B20
TDD-LTE: B40
UMTS: B1, B8
GSM/GPRS/EDGE: 850/900/1800/1900 MHz
EB
Europe
Cat4
FDD-LTE: B1, B3, B5, B7, B8, B20
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
2
TDD-LTE: B38
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
NA
North America
Cat4
FDD-LTE: B2, B4, B5, B7, B12, B17
UMTS: B2, B4, B5
GSM/GPRS/EDGE: 850/900/1800/1900 MHz
A
US ATT
Cat4
FDD-LTE: B2, B4, B12, B17
UMTS: B2, B4, B5
V
US Verizon
Cat4
FDD-LTE: B4, B13
AU
Australia/New
Zealand/the
Philippines
Cat4
FDD-LTE: B1, B3, B5, B7, B28
TDD-LTE: B40
UMTS: B1, B5
TWN
Taiwan
Cat4
FDD-LTE: B1, B3, B7, B8, B28
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
IN
India
Cat4
FDD-LTE: B3, B5
TDD-LTE: B40
1.2 Block Diagram
Figure 1-1 shows the block diagram of N720.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
3
Figure 1-1 N720 block diagram
VBAT
Power
Manager
RF transceiver
MCP
19.2 M
crystal
RF Section
Base Band
I2C
Digital Interface
USB
UART
SIM
PC
ANT_MAIN
ANT_AUX
ANT_GNSS
PWRKEY
RESET
ADC
UIM
PCM
SDIO
1.3 Features
Table 1-1 N720 baseband and wireless features
Specifications
Description
Power supply
VBAT: 3.3V to 4.3V; Typical value: 3.8 V
Current in sleep mode
< 4 mA
Standby current
< 20 mA
Operating temperature
-40 °C to +85 °C
Processor
ARM Cortex-A7 processor
Main frequency: 1.3 GHz
256 kB L2 cache
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
4
Memory
RAM: 128 MB or 256 MB
ROM: 256 MB
Band
See Table 1-1.
Rate
GPRS: Max 85.6 Kbps(DL) / Max 85.6 Kbps(U)
CDMA: Max 3.1 Mbps (DL) / Max 1.8 Mbps (UL)
WCDMA: DC-HSPA+, Max 42 Mbps(DL)/Max 5.76 Mbps(UL)
TD-SCDMA: Max 4.2 Mbps(DL)/Max 2.2 Mbps(UL)
FDD-LTE: non-CA cat4, Max 150 Mbps(DL)/Max 50 Mbps(UL)
TDD-LTE: non-CA cat4, Max 130 Mbps(DL)/Max 35 Mbps(UL)
Transmit power
GSM850: +33 dBm (Power Class 4)
EGSM900: +33 dBm (Power Class 4)
DCS1800: +30 dBm (Power Class 1)
PCS1900: +30 dBm (Power Class 1)
EDGE 850 MHz: +27 dBm (Power Class E2)
EDGE 900 MHz: +27 dBm (Power Class E2)
EDGE 1800 MHz: +26 dBm (Power Class E2)
EDGE 1900 MHz: +26 dBm (Power Class E2)
TD-SCDMA:+23 dBm (Power Class 3)
CDMA 1X/EVDO:+23 dBm(Power Class 3)
UMTS: 23 dBm (Power Class 3)
LTE: +23 dBm (Power Class 3)
Antenna feature
2G/3G/4G antenna, 4G diversity antenna, GNSS antenna, 50 Ω impedance
UART
At most 4 Mbps, 1 UART interface
UIM
1 UIM interface, 1.8V/3V dual-voltage adaptive
USB
1 USB2.0 high-speed interface
ADC
2 15-bit ADC interfaces, detectable voltage ranging from 0.1 V to 1.7 V
SDIO
1 SDIO interface, used for WLAN
PCM
1 PCM interface
I2C
1 I2C interface, supports host mode only
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
5
2 Application Interfaces
N720 adopts 100-pin LGA encapsulation package.
2.1 Specifications and Pin Definition
Table 2-1 N720 dimensions
Specifications
N720
Dimensions (H x W x D)
28±0.1 mm x 30±0.1 mm x 2.8±0.1 mm
Weight
5.1 g
Package
100-pin LGA
Figure 2-1 N720 module pin definition (Top View)
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
6
2.2 Pin Description
IO: input/output
DI: Digital input
DO: Digital output
PI: Power input
PO: Power output
AI: Analog input
AO: Analog output
Table 2-2 N720 pin description
Name
Pin
I/O
Function
Level Feature (V)
Power
Domain
Remarks
Power Supply
VBAT
27, 28, 29
PI
Main power supply
Vmax=4.3 V
Maximum supply current of 2A peak.
VDDIO _1P8
45
PO
1.8 V power supply
Vnorm=1.8 V;
Imax=50 mA;
1.8 V
Supply power for IO level shifting circuit.
Leave this pin unconnected if it is not used.
GND
1, 14, 17, 20,
26, 30, 31,
44, 49, 74,
75, 77, 91,
93, 95, 97,
98, 99, 100
GND
Power on/off and reset
RESET
32
DI
Reset input
VIL min=-0.3 V;
VIL max=0.5 V;
VIH min=1.2 V;
1.8 V
Low level triggers the reset.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
7
VIH max=2.1 V
PWRKEY
33
DI
Power ON/OFF
VIL min=-0.3 V;
VIL max=0.5 V;
VIH min=1.2 V;
VIH max=2.1 V
Low level triggers the ON/OFF state.
There is switch diode inside the module.
It is internally pulled up by a 200 kΩ resistor.
The level at the pin is 0.8 when it is left
unconnected.
200KΩ
1.8V
PM
PWRKEY
PON_TRIG
34
DI
PON_TRIG
VIL min=-0.3 V;
VIL max=0.5 V;
VIH min=1.2 V;
VIH max=2.1 V
1.8 V
High level triggers the ON status.
It is connected to ground through an internally
200 kΩ pull-down resistor.
Ground it if it is not used.
UART
UART2_TXD
46
DO
UART data transmit
VOL max=0.45 V;
VOH min=1.35 V;
1.8 V
Data transmission
Leave these pins unconnected if they are not
used.
UART2_RXD
47
DI
UART data receive
VIL min=-0.3 V;
VIL max=0.45 V;
VIH min=1.35 V;
VIH max=2.1 V
1.8 V
UART2_CTS
51
DI
Clear to send
VIL min=-0.3 V;
VIL max=0.45 V;
VIH min=1.35 V;
VIH max=2.1 V
1.8 V
Leave these pins unconnected if they are not
used.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
8
UART2_RTS
52
DO
Request to send
VOL max=0.45 V;
VOH min=1.35 V
1.8 V
UIM
VUIM
35
PO
UIM power supply
output
1.8V USIM:
Vmax = 1.9 V ;
Vmin = 1.7 V
3V USIM:
Vmax = 3.05 V;
Vmin = 2.7 V;
IO max =50 mA
1.8 V/3 V
Compatible with 1.8/3V UIM card
UIM_RESET
38
DO
UIM reset
1.8 V USIM:
VOL max = 0.45 V;
VOH min = 1.35 V
3 V USIM:
VOL max = 0.4 V;
VOH min = 2.6V
1.8 V/3 V
UIM_DATA
36
IO
UIM data
1.8V USIM:
VIL max = 0.6 V;
VIH min = 1.2 V;
VOL max = 0.45 V;
VOH min = 1.35 V
3V USIM:
VIL max = 0.8 V
VIH min = 1.95 V
VOL max = 0.45 V
VOH min = 2.6 V
1.8 V/3 V
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
9
UIM_CLK
37
DO
UIM clock
1.8 V USIM:
VOL max = 0.45 V;
VOH min = 1.35 V
3V USIM:
VOL max = 0.4 V
VOH min = 2.6 V
1.8 V/3 V
UIM_DETECT
39
DI
UIM detect
VIL min = -0.3 V;
VIL max = 0.63 V
1.8 V
USB
VBUS
40
PI
USB voltage test
3.3
V~5.2
V,
typically 5 V
Used for firmware download and data
transmission
Differential trace for DM and DP with 90 Ω
impedance
USB_DM
41
IO
USB data negative
signal
USB2.0
USB_DP
42
IO
USB
data
positive
signal
USB2.0
USB _ID
43
AI
Identify
host
and
device
1.8 V
Leave this pin unconnected if it is not used.
Audio (Optional)
PCM_CLK
9
IO
PCM clock signal
VOL max=0.45V;
VOH min=1.35V
1.8V
The audio function is optional. It requires
PCM, I2C, and I2S_MCLK signals. Leave
these pins unconnected if they are not used.
PCM_DOUT
10
DO
PCM data output
VOL max=0.45V;
VOH min=1.35V
1.8V
PCM_DIN
11
DI
PCM data input
VIL min=-0.3V;
VIL max=0.45V;
VIH min=1.6V;
1.8V
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
10
VIH max=2.1V
PCM_SYNC
12
IO
PCM sync signal
VOL max=0.45V;
VOH min=1.35V;
VIL min=-0.3V;
VIL max=0.45V;
VIH min=1.6V;
VIH max=2.1V
1.8V
I2S_MCLK
64
DO
I2S main clock output
signal
1.8V
Leave this pin unconnected if it is not used.
I2C_SDA
81
IO
I2C data
VOL max=0.45V;
VOH min=1.35V;
VIL min=-0.3V;
VIL max=0.45V;
VIH min=1.6V;
VIH max=2.1V
1.8V
Connected to a 2.2K pull-up resistor internally.
Leave them pin unconnected if they are not
used.
I2C_SCL
82
DO
I2C clock
VOL max=0.45V;
VOH min=1.35V
1.8V
WLAN (Optional)
LTE_COEX_RX_UART
48
DI
WLAN/LTE co-exist
control receive
VIL min=-0.3V
VIL max=0.45V
VIH min=1.35V
VIH max=2.1V
1.8V
Multiplexing
function
of
FORCE_USB_BOOT
Leave this pin unconnected if it is not used.
LTE_COEX_TX_UART
50
DO
WLAN/LTE co-exist
control transmit
VOL max=0.45V;
VOH min=1.35V
1.8V
Leave this pin unconnected if it is not used.
VDDXO_1P8
53
PO
1.8V power supply
output
Vnorm=1.8V
1.8V
Used to connect to the crystalloid of the
external WLAN chipset via a pull-up resistor.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
11
Imax=20mA
Leave this pin unconnected if it is not used.
SDIO_CMD
54
IO
SDIO
IO
control
signal
VIL max = 0.6V
VIH min = 1.3V
VOL max = 0.45V
VOH min = 1.4V
1.8V
Leave this pin unconnected if it is not used.
SDIO_CLK
55
DO
SDIO clock signal
1.8V
Leave this pin unconnected if it is not used.
SDIO_DATA_0
56
IO
SDIO
data
output/input
VIL max = 0.6V
VIH min = 1.3V
VOL max = 0.45V
VOH min = 1.4V
1.8V
Leave this pin unconnected if it is not used.
SDIO_DATA_1
57
IO
SDIO data IO
VIL max = 0.6V
VIH min = 1.3V
VOL max = 0.45V
VOH min = 1.4V
1.8V
Leave this pin unconnected if it is not used.
SDIO_DATA_2
58
IO
SDIO data IO
VIL max = 0.6V
VIH min = 1.3V
VOL max = 0.45V
VOH min = 1.4V
1.8V
Leave this pin unconnected if it is not used.
SDIO_DATA_3
59
IO
SDIO data IO
VIL max = 0.6V
VIH min = 1.3V
VOL max = 0.45V
VOH min = 1.4V
1.8V
Leave this pin unconnected if it is not used.
WAKE_ON_WIRELESS
60
DO
WLAN mode control
signal
VOL max=0.45V
VOH min=1.35V
1.8V
Leave this pin unconnected if it is not used.
WLAN_SLEEP_CLK
61
DO
WIFI
sleep
clock
1.8V
Leave this pin unconnected if it is not used.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
12
signal
WLAN_EN
62
DO
WLAN enable control
VOL max=0.45V
VOH min=1.35V
1.8V
Leave this pin unconnected if it is not used.
WLAN_3V_EN
63
DO
WLAN external LDO
enable control
VOL max=0.45V
VOH min=1.35V
1.8V
Leave this pin unconnected if it is not used.
ADC
ADC2
88
AI
Analog-to-digital
signal conversion
Vmax=1.7 V;
Vmin=0.1 V
1.8 V
15-bit, detectable voltage range: 0.1 V to 1.7 V
ADC1
89
AI
Analog-to-digital
signal conversion
Vmax=1.7 V;
Vmin=0.1 V
1.8 V
RING
RING
13
DO
Incoming call ring
VOL max=0.45 V;
VOH min=1.35 V;
1.8 V
Leave this pin unconnected if it is not used.
Sleep mode control
DTR
79
DI
Sleep mode control
VIL min=-0.3V;
VIL max=0.45V;
VIH min=1.35V;
VIH max=2.1V
1.8V
Leave this pin unconnected if it is not used.
Network indicator
NET_LIGHT
83
DO
Network
status
indicator control
VOL max=0.45 V;
VOH min=1.35 V;
1.8 V
Leave this pin unconnected if it is not used.
Other Pins
FORCE_USB_BOOT
48
DI
External GNSS LNA VIL min=-0.3V;
1.8 V
Leave this pin unconnected if it is not used.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
13
enable
VIL max=0.45V;
VIH min=1.35V;
VIH max=2.1V
ANT_MAIN
76
Main antenna
50 Ω impedance
ANT_GNSS
92
GNSS antenna
50 Ω impedance
ANT_AUX
94
4G diversity aerial
50 Ω impedance
NC
2, 3, 4, 5, 6,
7, 8, 15, 16,
18, 19, 21,
22, 23, 24,
25, 65, 66,
67, 68, 69,
70, 71, 72,
73, 78, 80,
84, 85, 86,
87, 90, 96
NC
Leave them unconnected.
Do not use them.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
14
2.3 Power Control Interfaces
Name
Pin No.
I/O Function
Remarks
VBAT
17/18/19 P
Main power supply input
3.3 V to 4.3 V (typical value: 3.8 V)
VDDIO_1P8 45
P
1.8 V power supply
output
Supply power for IO level shifting circuit.
Load capability: <50 mA
Added ESD protection when using this pin.
RESET
32
DI
Reset input
Low level triggers reset
PON_TRIG
34
DI
PON_TRIG
High level triggers the ON status
PWRKEY
33
DI
Power ON/OFF
Low level triggers the ON status
2.3.1 VBAT
VBAT is the power supply input pin of the module. Its input voltage ranges from 3.3 V to 4.3 V and the
typical value is 3.8 V. In addition to baseband, it supplies power to RF power amplifier. The performance
of the VBAT power supply is a critical path to module's performance and stability. The peak input current
at the VBAT pin can be up to 2A when the signal is weak and the module works at the maximum
transmitting power. The voltage will encounter a drop in such a situation. The module might restart if the
voltage drops lower than 3.3 V.
Figure 2-2 Current peaks and voltage drops
Keep the voltage above 3.3 V
3.3 V
0 ms
3.7 ms
7.4 ms
10.7 ms
T
2A
Voltage
Input
current
3.8 V
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
15
The reference design of the VRTC power supply is shown as below:
Figure 2-3 Capacitors used for the power supply
N720
Close to the module
D1
C1
C2 C3
C4
C5
VBAT
Test point
I_max
Power supply
In Figure 2-3, use TVS at D1 to enhance the performance of the module during a burst. SMF5.0AG
(Vrwm=5 V&Pppm=200 W) is recommended. A large bypass tantalum capacitor (220 μF or 100 μF) or
aluminum capacitor (470 μF or 1000 μF) is expected at C1 to reduce voltage drops during bursts together
with C2 (10 μF ceramics capacitor).In addition, add 0.1 μF, 100 pF, and 33 pF filter capacitors to enhance
the stability of the power supply.
The module might fail to reset or power on/off in remote or unattended applications, or in an environment
with great electromagnetic interference (EMI). A controllable power supply is preferable if used in harsh
conditions. Use the EN pin on the LDO or DC/DC chipset to control the switch of the power supply as
shown in Figure 2-4 if a 5 V power supply is used.
MIC29302WU in Figure 2-4 is an LDO and outputs a maximum current of 3 A to ensure the performance
of the module.
Figure 2-4 Reference design of power supply control
VCC_IN_5V
VBAT
100 uF
TAN
0.1 uF
TVS
5V
10 uF
470uF
TAN
10K
4.75K
VOUT
MIC29302WU
EN
VIN
ADJ
0.1 uF 100pF 33pF
PWR_EN
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
16
The alternative way is to use an enhancement mode p-MOSFET to control the module's power, as shown
in Figure 2-5. When the external MCU detects the exceptions such as no response from the module or the
disconnection of GPRS, power off/on can rectify the module exceptions.
In Figure 2-5, the module is turned on when PWR_EN is set to high level.
Figure 2-5 Reference design of power supply controlled by p-MOSFET
VCC_IN_3.9V
VBAT
10K
100K
33 pF
10 uF
2K
10K
0.1 uF
Q1
R4
C1
C2
C4
C5
C7
R1
R2
10 uF 0.1 uF
R3
Q2
TVS
5V
470 uF
C3
C6
100pF
S
G
D
PWR_EN
Q2 is added to eliminate the need for a high enough voltage level of the host GPIO. In case that the GPIO
can output a high voltage greater than VCC_IN - |VGS (th)|, where VGS (th) is the Gate Threshold
Voltage, Q2 is not needed.
Reference components:
Q1 can be IRML6401 or low Rds (on) p-MOSFET, which has higher, withstand voltage and drain
current.
Q2: a common NPN tripolar transistor, e.g. MMBT3904; or a digital NPN tripolar transistor, e.g.
DTC123. If digital tripolar transistor is used, delete R1 and R2.
C3: 470 μF tantalum capacitor rated at 6.3 V, or 1000 μF aluminum capacitor. If lithium battery is
used to supply power, C3 can be 220 μF tantalum capacitor.
Power Supply Protection
Add TVS diodes (VRWM=5 V) on the VBAT power supply, especially in automobile applications. For
some stable power supplies, Zener diodes can decrease the power supply overshoot. SMF5.0AG from
ONSEMI is an option.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
17
Line Rules
The width of primary loop lines for VBAT on PCB must be able to support the safe transmission of 2 A
current and ensure no obvious loop voltage decrease. Therefore, the loop line width of VBAT is required
2 mm and the ground should be as complete as possible.
Separation
The module works in burst mode that generates voltage drops on power supply. Furthermore, this results
in a 217 Hz TDD noise through power (One of the way generating noise. Another way is through RF
radiation). Analog parts, especially the audio circuits, are subjected to this noise, known as a "buzz noise"
in GSM systems. To prevent other parts from being affected, it is better to use separated power supplies.
The module shall be supplied by an independent power, like a DC/DC or LDO. See Figure 2-6.
DC/DC or LDO should output rated peak current larger than 2 A.
The inductor used in Reference Design (b), should be a power inductor and have a very low resistance.
The value of 10 μH, with average current ability greater than 1.2A and low DC resistance, is
recommended.
Figure 2-6 Reference designs of separated power supply
Other circuit
DC-DC/LDO
N720
DC-DC/LDO
Power
Input
Other circuit
DC-DC/LDO
N720
Power
Input
10 uH
Reference design (a)
Reference design (b)
Never use a diode to make the drop voltage between a higher input and module power. Otherwise,
Neoway will not provide warranty for product issues caused by this. In this situation, the diode will
obviously decrease the module performances, or result in unexpected restarts, due to the forward voltage
of diode will vary greatly in different temperature and current.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
18
EMC Considerations for Power Supply
Place transient overvoltage protection components like TVS diode on power supply, to absorb the power
surges, SMAJ5.0A/C could be a choice.
2.3.2 VDDIO_1P8
VDDIO_1P8 supports output voltages of 1.8 V. It is recommended that VDDIO_1.8 V@50 mA be used
only for interface level shifting and to add ESD to protect while using.
2.3.3 ON/OFF
Power-On
After powering on the VBAT pin, use PWRKEY to start the module by inputting low-level pulse for 100
ms (a value longer than 200 ms is recommended). Do not connect an external large resistor to ground
directly because the PWRKEY pin is internally pulled up by a 200 kΩ resistor. The circuits in Figure 2-7
or Figure 2-8 are recommended to control PWRKEY.
Figure 2-7 Push switch control
Figure 2-8 MCU control
PWRKEY
Q
R1
R2
USER_ON
If the module is powered on but the power-on sequence has not been completed, the states of each pin are
uncertain. The power-on sequence of the module is shown in Figure 2-9.
S1
PWRKEY
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
19
Figure 2-9 N720 power-on/off sequence
VBAT
PWRKEY
RESET_N
t >200ms
VL<0.6V
USB
t >2s
Inactive
Active
Inactive
Inactive
Active
Inactive
UART
If application does not require power-on control, pull the PWRKEY pin down to GND through 1.5 kΩ
resistor. Then the module can start automatically after it is powered on. Leave the PWRKEY pin
unconnected if it is not used. The PON_TRIG pin can trigger the ON status of the module by high level.
Power-off
The module can be powered off in two ways: hardware power off and software power off.
Low-level pulse for 2 seconds on PWRKEY can trigger the power-off status of the module. Leave this pin
unconnected if it is not used.
For how to power off the module through software, please refer to the AT command manual.
If 2.8V/3.3V IO system is adopted, use external triode isolation. For details, refer to 2.3.4 RESET. Figure
2-10 shows the hard power-off sequence.
Figure 2-10 N720 power-off sequence
VBAT
t>2s
PWRKEY
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
20
2.3.4 RESET
The RESET pin is used to reset the module. Low level for more than 1 second at this pin triggers module
reset. This pin is pulled up internally. Its typical high-level voltage is 1.8 V. Leave this pin unconnected if
it is not used. If 2.8 V/3.3 V IO system is used, separate it by adding a triode. Refer to the following
design.
Figure 2-11 Reset controlled by button
RESET
S1
Figure 2-12 Reset circuit with triode separating
Q1
R2
R1
VDD_EXT
RESET
2V8/3V3/3V0
In a circuit shown in Figure 2-12, VDD_EXT=2.8V/3.3V/3.0V, R1=4.7K, R2=47K.
Figure 2-13 shows the reset sequence.
Figure 2-13 N720 reset sequence
VBAT
RESET
1s
10s
Inactive
Active
USB/UART
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
21
2.4 USB Interface
Name
Pin No.
I/O
Function
Remarks
VBUS
40
P
USB voltage test
3.3 V to 5.2 V, typically 5 V
USB_DM
41
IO
USB data negative signal
USB2.0, used for firmware download and
data transmission
USB_DP
42
IO
USB data positive signal
USB_ID
43
AI
Identify host and device
Leave this pin unconnected if it is not used.
USB can be used to download firmware for N720 and establish data communication for commissioning.
If the module is used only as USB device, the recommended USB circuit to use is shown in Figure 2-14.
Figure 2-14 USB circuit
USB_VBUS
USB_DM
USB_DP
USB_ID
GND
USB_ID
USB_DP
USB_DM
USB_VBUS
D1
C1
C2
D2
D3
DNI-18P
USB
connector
N720
Connect a 1 μF and a 22 pF filter capacitors in parallel to the VBUS pin and place them as close to the pin
as possible. TVS diodes are required for the VBUS power line. The junction capacitance of the TVS
protection diodes for USB_DP and USB_DM should be lower than 12 pF as possible. USB data lines
adopt differential trace design, in which the differential impedance is limited to 90 Ω characteristics
impedance. Isolate the traces from other signal traces.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
22
2.5 UIM Card Interface
Name
Pin No.
I/O
Function
Remarks
VUIM
35
PO
UIM power supply
Compatible with 1.8 V/3 V UIM card
UIM_DATA
36
IO
UIM data
A 10 kΩ resistor is required between
VUIM and UIM-DATA.
UIM_CLK
37
DO
UIM clock
UIM_RESET
38
DO
UIM reset
UIM_DETECT
39
DI
UIM detect
A pull-up resistor is recommended
N720 supports 1.8 V/3 V UIM cards. VUIM is the power supply pin of the UIM card and its maximum
load is 30 mA. The UIM_DATA pin is not pulled up internally, so reserve a pull-up resistor externally in
design. UIM_CLK is the clock signal pin, supporting 3.25 GHz of clock frequency. Figure 2-15 shows the
reference design of the UIM card interface.
Figure 2-15 Reference design of SIM card interface
1 uF
UIM_DATA
UIM_CLK
UIM_RST
VUIM
N720
CLK
RST
VCC
VPP
GND
UIM card
DATA
GND
SIM-Det
UIM_DETECT
10KΩ
47KΩ
VDDIO_1P8
ESD protectors, such as ESD diodes or ESD varistors (with a junction capacitance of less than 33 pF), are
recommended to be added on the SIM signals, especially in automotive or other applications with bad
ESD. Replace the ESD diodes with 27 pF to 33 pF capacitors connecting to GND in common applications.
The ESD diodes or small capacitors should be close to UIM card.
N720 supports SIM card detection. UIM_DETECT is 1.8 V interrupt pins. Low level means UIM card
detected while high level mean no UIM card detected.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
23
If N720 is applied to some electrical terminals, MUP-C713(H2.8) is recommended.
Figure 2-16 UIM connector encapsulation
The antenna should be installed far away from the UIM card and UIM card traces, especially to the
built-in antenna.
The UIM traces on the PCB should be as short as possible and shielded with GND copper.
The ESD protection diodes or small capacitors should be close to UIM card on the PCB.
2.6 GPIO Interfaces
N720 supports UART, allowing GPIO configuration to meet requirements for connecting to different
devices. For the open multi-function GPIO interface, please inquiry our technical support engineers. The
level of the module interface is 1.8 V. Table 2-3 lists GPIO pins.
Table 2-3 GPIO
Name
Pin No.
I/O
Function
Remarks
UART2_TXD
46
DO
UART data transmit
Data transmission
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
24
UART2_RXD 47
DI
UART data receive
UART2_CTS
51
DI
Clear to send
UART2_RTS
52
DO
Request to send
ADC2
88
AI
ADC2 input
15-bit, detectable voltage
range: 0.1 V to 1.7 V
ADC1
89
AI
ADC1 input
RING
13
DO
Incoming call ring
Support only host mode
DTR
79
DI
Sleep mode control
NET_LIGHT
83
DO
Network status indicator control
Support only host mode
2.6.1 UART
N720 provides 1 UART interface, which support hardware flow control and 4 Mbps at most. The high
level is 1.8V. Figure 2-17 shows the reference design of the UART interface.
Figure 2-17 Reference design of the UART interface
RXD
TXD
RTS
CTS
MCU_TXD
MCU_RXD
MCU_CTS
MCU_RTS
GND
GND
N720
Client
If the UART does not match the logic voltage of the MCU, add a level shifting circuit outside of the
module as shown in Figure 2-18 (for VIL≤200 mV) and Figure 2-19 (for VIL>200 mV).
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
25
Figure 2-18 Recommended level shifting circuit 1
TXD
VDDIO_1P8
VCC_IO
4.7KΩ
10KΩ
Q1
R2
R3
MCU_URXD
MCU_UTXD
Q2
RXD
10KΩ
R1
4.7KΩ
R4
VDDIO_1P8
VDDIO_1P8
Components:
R2/R4: 2K-10K. The greater the UART baud rate is, the lower the R2/R4 values are.
R1/R3: 4.7K-10K The greater the UART baud rate is, the lower the R/R3R3 value is.
Q1/Q2: MMBT3904 or MMBT2222. High-speed transistor is better.
MCU_UTXD and MCU_URXD are respectively the TX and RX ports of the MCU while TXD and RXD
are respectively the TX and RX ports of the module.
Voltage at VCC_IO is the voltage at the UART of the MCU while voltage at VDDIO_1V8 is the voltage
at the UART of the module.
Figure 2-19 shows another recommended level shifting circuit.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
26
Figure 2-19 Recommended level shifting circuit 2
220pF
TXD
5.6KΩ
47KΩ
4.7KΩ
VDDIO_IP8
2.2KΩ
220pF
47KΩ
10KΩ
Q1
Q2
MCU_URXD
VCC_IO
220pF
RXD
10KΩ
10KΩ
5.6KΩ
VDDIO_IP8
10KΩ
220pF
47KΩ
4.7KΩ
Q1
Q2
MCU_UTXD
VCC_IO
Components:
Q1/Q2: MMBT3904 or MMBT2222. High-speed transistors are better.
MCU_UTXD and MCU_URXD are respectively the TX and RX ports of the MCU, while UTXD and
URXD are respectively the TX and RX ports of the module.
Voltage at VCC_IO is the voltage at the UART of the MCU while voltage at VDDIO_1V8 is the voltage
at the UART of the module.
2.6.2 ADC
N720 provides two ADC channels, and the detectable voltage ranges from 0.1 V to 1.7 V. ADC pin
supports highest precision of 15 bit and it can be used for temperature and other check. If this pin is used
to measure SIM card temperature on power terminals, refer to Neoway GPRS Module ADC User Guide.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
27
2.6.3 NET_LIGHT
NET_LIGHT can output 1.8 V high level. Do not use it to drive LED directly. Drive the LED with a
transistor instead.
Figure 2-20 LED indicator driven by transistor
LIGHT
N720
10KΩ
VCC
470Ω
4.7KΩ
When the module is running, the LED indicator is driven by the NET_LIGHT pin to indicate different
module status with its various blink behaviors. N720 supports multiple blink style and users can configure
it using AT commands.
2.6.4 DTR
Generally, the DTR pin is used to control sleep mode together with AT commands. Enable the sleep mode
function by AT command. Then pulling DTR low will bring the module into sleep mode if the module is
idle. In this mode, the idle current is less than 4 mA, depending on the DRX setting of network.
In sleep mode, the module can respond to the incoming call, SMS, and GPRS data. The host MCU can
also control the module to exit sleep mode by controlling DTR.
Process of entering sleep mode:
1.
Keep DTR high level in normal working mode. Activate the sleep mode by using the
AT+ENPWRSAVE=1 command.
2.
Pull DTR low, and the module will enter sleep mode, but only after process and pending data
finished.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
28
3.
In sleep mode, the external MCP can pull DTR high so that the module will exit from sleep
mode actively. Then the module can transmit data and initiate calls. After processing is finished, pull
DTR low again to take the module back to sleep mode.
4.
In sleep mode, the module can be woken up by the events of incoming voice call, received data,
or SMS. Meanwhile the module will send out the unsolicited messages through the UART.
Upon receipt of the unsolicited messages, the host MCU should pull DTR high firstly, otherwise the
module will resume sleep mode in two minutes after the service processing. Then the host MCU can
process the voice call, received data, or SMS. After processing is finished, pull DTR low again to put
the module into sleep mode.
2.6.5 RING Signal Indicator
Calling: Once a voice call is incoming, UART outputs "RING" character strings and meanwhile the
RING pin outputs 30 ms low pulses in a period of 5 second. After the call is answered, the high level
restores.
Figure 2-21 RING indicator for incoming call
SMS: Upon receipt of SMS, the module outputs one 35 ms low pulse.
Figure 2-22 RING indicator for SMS
5s
30 ms
30 ms
35 ms
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
29
2.7 AUDIO Interfaces
The AUDIO function can be implemented by connecting PCM, I2S_MCLK and I2C signals to an external
Codec chipset.
2.7.1 PCM
Signal
Pin
No.
I/O
Function
Remarks
PCM_CLK
9
IO
AUDIO PCM clock signal
Leave this pin unconnected if it is not used.
PCM_DOUT 10
DO
AUDIO PCM data output
Leave this pin unconnected if it is not used.
PCM_DIN
11
IO
AUDIO PCM data input
Leave this pin unconnected if it is not used.
PCM_SYNC
12
IO
AUDIO PCM sync signal
Leave this pin unconnected if it is not used.
I2S_MCLK
64
DI
I2S main clock
Leave this pin unconnected if it is not used.
The PCM interface supports master and slave mode. Its reference high level is 1.8V. The following figure
shows the PCM connection.
Figure 2-23 PCM connection
PCM_DOUT
PCM_DIN
PCM_SYNC
PCM_CLK
N720 module
CODEC shipset
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
The PCM clock can be up to 2048 KHz. The following figures show the PCM timing.
Figure 2-24 PCM synchronization timing
PCM_SYNC
t(sync)
t(syncd)
t(synca)
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
30
Figure 2-25 PCM data input timing
t(sus
ync)
t(hsync)
t(clk)
t(clkh)
t(clkl)
PCM_CLK
PCM_SYNC
PCM_DIN
MSB
LSB
t(sudin)
t(hdin)
Figure 2-26 PCM data output timing
t(clk)
t(clkh)
t(clkl)
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
t(zdout)
t(susync) t(hsync)
t(pdout)
t(pdout)
Table 2-4 Timing parameters of PCM interface
Timing Parameter
Min.
Typical
Max.
Unit
t(sync)
PCM_SYNC cycle
-
125
-
ns
t(synca)
PCM_SYNC valid time
-
488
-
ns
t(syncd)
PCM_SYNC invalid time
-
124.5
-
ns
t(clk)
PCM_CLK cycle
-
488
-
ns
t(clkh)
PCM_CLK high time
-
244
-
ns
t(clkl)
PCM_CLK low time
-
244
-
ns
t(susync)
Set-up time from PCM_SYNC high
PCM_CLK low
-
122
-
ns
t(sudin)
Set-up time from PCM_DIN high to
PCM_CLK low
60
-
-
ns
t(hdin)
Hold time from PCM_CLK low to
PCM_DIN high
10
-
-
ns
t(pdout)
Delay time from PCM_CLK high to
PCM_DOUT low
-
-
60
ns
t(zdout)
Delay time from PCM_CLK low to
PCM_DOUT high impedance
-
160
-
ns
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
31
I2S_MCLK is the main clock referred by the audio system clock. When the PCM interface is used as the
master device, PCM_CLK is configured as the output clock signal and I2S_MCLK is configured as the
main clock signal of the system. When the PCM interface is used as the slave device, PCM_CLK is
configured as the input clock signal and it should be synchronous to the I2S_MCLK.
2.7.2 I2C
Signal
Pin No.
I/O
Function
Remarks
I2C_SDA
81
IO
I2C data
Connected to the power supply via a pull-up resistor
internally. Leave them pin unconnected if they are
not used.
I2C_SCL
82
DO
I2C clock
The I2C interface complies with I2C Specification, version5.0, October 2012. It supports master mode
only and supports a rate of up to 3.4 Mbps. Its reference high level is 1.8V.
2.8 WLAN Interfaces
2.8.1 SDIO
Signal
Pin No.
I/O
Function
Remarks
SDIO_CMD
54
IO
Control signal of
SDIO interface
Leave this pin unconnected if it is not used.
SDIO_CLK
55
DO
Clock signal of
SDIO interface
Leave this pin unconnected if it is not used.
SDIO_DATA0
56
IO
SDIO data bit 0
Leave this pin unconnected if it is not used.
SDIO_DATA1
57
IO
SDIO data bit 1
Leave this pin unconnected if it is not used.
SDIO_DATA2
58
IO
SDIO data bit 2
Leave this pin unconnected if it is not used.
SDIO_DATA3
59
IO
SDIO data bit 3
Leave this pin unconnected if it is not used.
The SDIO interface of the N720 module supports the SDIO 3.0 interface protocol and supports 1.8V. The
following figure shows the SDIO connection.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
32
Figure 2-27 SDIO connection
N720
WLAN
chipset
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA0
SDIO_DATA0
SDIO_DATA0
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA0
SDIO_DATA0
SDIO_DATA0
GND
GND
The CLK, CMD, DATA0, DATA1, DATA2, and DATA3 signals of SDIO are high-speed signals. On the
PCB, the route impedance should be limited to 50Ω and the traces should be laid on the inner layer and
not be across other traces. It is recommended to keep the traces of CMD, DATA0, DATA1, DATA2, and
DATA3 same length. The CLK trace should not be longer or shorter than the traces of other signals too
much and should be surrounded by ground.
The SDIO interface supports a maximum clock frequency of SDR 200 MHz or DDR 50 MHz, and it is
compatible DS, HS, SDR12, SDR25, SDR50, and SDR104.
The following figures and table shows the sequences and parameters of SDR and DDR modes
respectively.
Figure 2-28 SDIO SDR timing
SD_CLK
Read
Write
t(pddwr)
t(pdcwr)
t(cdvrd)
t(dvrd)
t(csurd)
t(dsurd)
t(chrd)
t(dhrd)
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
33
Figure 2-29 SDIO DDR timing
Command
Read
Command
Write
t(pdcwr)
t(csurd)
t(chrd)
SD_CLK
DATA
Read
DATA
Write
t(dsurd)
t(dhrd)
t(pddwr)
t(pddwr)
Table 2-5 Timing parameters of SDIO interface
Timing Parameter
Min.
Typical
Max.
Unit
SDR mode (max. 200 MHz)
t(cvdrd)
Command valid time
2.4
-
-
ns
t(dvdrd)
Data valid time
2.4
-
-
ns
t(pddwr)
Delay time from data write to transmit
-1.45
-
0.85
ns
t(pdcwr)
Delay time from command write to transmit
-1.45
-
0.85
ns
DDR mode (max. 50 MHz)
t(chrd)
Command hold time
1.5
-
-
ns
t(csurd)
Command set-up time
5.53
-
-
ns
t(dhrd)
Data hold time
1.5
-
-
ns
t(dsurd)
Data set-up time
1.65
-
-
ns
t(pddwr)
Delay time from data write to transmit
2.5
-
6.15
ns
t(pdcwr)
Delay time from command write to transmit
-7.85
-
2.65
ns
2.8.2 WLAN Control
Signal
Pin No.
I/O
Function
Remarks
LTE_COEX_RX_UART
48
DI
WLAN/LTE co-exist
control receive
Multiplexing
function
of
FORCE_USB_BOOT
Leave this pin unconnected if it
is not used.
LTE_COEX_TX_UART
50
DO
WLAN/LTE co-exist
control transmit
Leave this pin unconnected if it
is not used.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
34
VDDXO_1P8
53
PO
1.8V power supply
output
Used
to
connect
to
the
crystalloid of external WLAN
module via a pull-up resistor
Leave this pin unconnected if it
is not used.
WLAN_3V_EN
63
DO
WLAN
external
LDO enable control
Leave this pin unconnected if it
is not used.
WLAN_EN
62
DO
WLAN enable
Leave this pin unconnected if it
is not used.
WLAN_SLEEP_CLK
61
DO
WLAN sleep clock
signal
Leave this pin unconnected if it
is not used.
WAKE_ON_WIRELESS
60
DO
WLAN mode control
signal
Leave this pin unconnected if it
is not used.
LTE_COEX_RX_UART and LTE_COEX_TX_UART are co-exist control signal of LTE and Wi-Fi. They
are used for UART data receive and transmit.
VDDXO_1P8 is connected to the crystalloid of WLAN chipset through a pull-up resistor. The drive
current is lower than 20 mA and other functions are forbidden.
WLAN_EN is the enable signal to control Wi-Fi and it is connected to the ground through a pull-down
resistor. It works at high level.
WAKE_ON_WIRELESS is the communication signal for WLAN mode. This pin supports 1.8V and open
drain. Leave this pin unconnected if the WLAN chipset does not support the function.
WLAN_SLEEP_CLK is the clock output signal of WLAN in sleep mode. The clock frequency is 32.768
KHz. When WLAN enters sleep mode, this pin outputs a low-power 32.768 KHz clock signal to the
WLAN chipset. The following figure and table shows the clock signal timing and parameters respectively.
Figure 2-30 32KHz clock signal timing
Table 2-6 Timing parameters of 32KHz clock signal
Parameter
Signal
Min.
Typical
Max
Unit
Clock frequency
CK1
-
32.768
-
KHz
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
35
Falling time
CK2
1
-
100
ns
Rising time
CK3
1
-
100
ns
Duty ratio
CK4
15
-
85
%
Frequency error
CK5
-200
-
200
ppm
Input high level
CK6
1.45
-
2
V
Input low level
CK7
-0.3
-
0.35
V
2.9 Commissioning Interfaces
To facilitate software update and commissioning, reserve the commissioning interfaces.
2.9.1 FORCE_USB_BOOT
The module can enter the fast boot mode by connecting the FORCE_USB_BOOT pin to VDDIO_1P8V
during the startup. This is the last method to troubleshoot the abnormality that the module cannot start or
operation properly.
Figure 2-31 Reference design of the fast boot interface
FORCE_USB_BOOT
S1
VDDIO_1P8V
10 KΩ
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
36
3 RF Interface
Name
Pin
I/O
Function
Remarks
ANT_MAIN 76
AI/O
2G/3G/4G main antenna
50 Ω characteristic impedance
ANT_GNSS
92
AI
GNSS antenna
ANT_AUX
94
AI
4G diversity aerial
3.1 2G/3G/4G RF Design and PCB Layout
ANT_MAIN and ANT_AUX are the antenna pins of N720. A 50 Ω antenna is required. VSWR ranges
from 1.1 to 1.5. The antenna should be well matched to achieve best performance. It should be installed
far away from high-speed logic circuits, DC/DC power or any other strong disturbing sources.
A 50 Ω antenna is required. VSWR ranges from 1.1 to 1.5. The antenna should be well matched to
achieve best performance.
For multiple-layer PCB, the trace between the antenna pad of module and the antenna connector, should
have a 50 Ω characteristic impedance, and be as short as possible. The trace should be surrounded by
ground copper. Place plenty of via holes to connect this ground copper to main ground plane, at the copper
edge.
For dual-layer PCB, the width of recommended impedance trace is 0.8 mm to 1 mm and the grounding
copper should away from the trace for 1 to 1.5 time of the trace width.
If the trace between the module and connector has to be longer, or built-in antenna is used, add a π-type
matching as shown in Figure 3-1.
Figure 3-1 Reference of antenna matching design
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
37
Big RF solder pad can result in great parasitic capacitance, which will affect the antenna performance.
Remove the copper on the first and second layers under the RF solder pad.
Figure 3-2 Recommended RF PCB design
To adopt RF antenna connections, the GSC RF connector MM9329-2700RA1 from Murata is
recommended. Figure 3-3 shows the encapsulation specifications.
Figure 3-3 Encapsulation specifications of Murata RF connector
RF antenna can also be connected to the module by soldering. In this manner, ensure proper soldering in
case of damage that lowers RF performance. Figure 3-4 shows the pictures of these two connections.
Figure 3-4 RF connections
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
38
3.2 GNSS RF Design and PCB Layout
3.2.1 GNSS Impedance
The 92nd pin is the GNSS interface of the module, which also requires a 50 Ω. The PCB layout for GNSS
is similar to that for GPRS. For details, refer to the previous section. Figure 3-5 shows the internal
structure of the GNSS RF.
Figure 3-5 GNSS RF structure
WTR GPS Interface
SAW
ANT_GNSS
In addition to the basic rules, the GNSS routing has higher requirements because the air wireless GNSS
signal has lower strength, which results in weaker electrical signal after the antenna receives. Weaker
signals are more susceptible to interference. Therefore, active antenna are commonly used for GNSS. The
active GNSS antenna amplifies the weak signals received to stronger signals through the low-noise
amplifier (LNA) and then transmits the signals through the feeder.
If using a passive antenna, add LNA near the feeder because the module does not embed one internally.
If the antenna and layout are not designed reasonably, the GNSS will be insensitive, resulting in long time
on positioning or inaccurate position.
Keep the GPRS and GNSS far away from each other in layout and antenna layout design.
3.2.2 Active GNSS Antenna Design
Ceramic GNSS chip antenna is mainly used. In general, using the active ceramic antenna is recommended.
After the antenna receives GNSS satellite signals, the LNA amplifies them first and then they are
transmitted to the 92nd pin (GNSS_ANT) through the feeder and PCB traces. 50 Ω impedance is required
for both the feeder and PCB traces and the traces should be as short as possible. The power supply of the
active antenna is fed by the 100 nH inductance through the signal traces.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
39
Common active antenna requires 3.3 V to 5 V power supply. Though the active antenna has a low power
consumption, it requires stable and clean power supply. It is recommended that high-performance LDO is
used to supply power for the antenna through a 100 nH inductance, as shown in Figure 3-6.
Figure 3-6 Power supply reference for active antenna
LNA
Active
Antenna
N720
LDO
PWR_input
22 uF
33 pF
100 nH
33 pF
50Ω impedance line
It is recommended that an ESD protection diode is added to the antenna interface in an environment with
great electromagnetic interference and other applications with bad ESD. The ESD protection diode must
have ultra-low capacitance (lower than 0.5 pF). Otherwise, it will affect the impedance of the RF loop or
result in attenuation of RF signals. RCLAMP0521P from Semtech or ESD5V3U1U from Infineon is
recommended.
On the PCB, keep the RF signals and RF components away from high-speed circuits, power supplies,
transformers, great inductors, the clock circuit of single-chip host, etc.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
40
4 Electrical Features and Reliability
4.1 Electrical Features
Table 4-1 N720 electric features
Module Status
Minimum Value
Typical Value
Maximum Value
VBAT
Vin
3.3 V
3.8 V
4.3 V
Iin
/
/
2 A
If the voltage is too low, the module might fail to start. If the voltage is too high or there is a voltage burst
during the startup, the module might be damaged permanently.
If LDO or DC-DC is used to supply power for the module, ensure that it outputs at least 3 A current.
4.2 Temperature Features
Table 4-2 Temperature feature
Module Status
Minimum Value
Typical Value
Maximum Value
Work
-40 °C
25 °C
85 °C
Storage
-45 °C
90 °C
If the module works in temperature exceeding the thresholds, some of its RF performance indicator might
be worse but it can still work properly.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
41
4.3 ESD Features
Electronic products need to pass several ESD tests. The following table shows the ESD capability of key
pins of our module. Add ESD protection to those pins in accordance to the application to ensure product
quality when designing better products.
Humidity: 45%
Temperature: 25 °C
Table 4-3 N720 ESD features
Testing Point
Contact Discharge
Air Discharge
VBAT
±8 kV
±15 kV
GND
±8 kV
±15 kV
ANT
±8 kV
±15 kV
Cover
±8 kV
±15 kV
Others
±2 kV
±4 kV
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
42
5 RF Feature
5.1 Operating Band
Table 5-1 N720 operating band
Operating band
Uplink
Downlink
GSM850
824~849 MHz
869~894 MHz
EGSM900
880~915 MHz
925~960 MHz
DCS1800
1710~1785 MHz
1805~1880 MHz
PCS1900
1850~1910 MHz
1930~1990MHz
CDMA BC0
824~849 MHz
869~894 MHz
UMTS B1
1920~1980 MHz
2110~2170 MHz
UMTS B2
1850~1910 MHz
1930~1990MHz
UMTS B4
1710~1755 MHz
2110~2155 MHz
UMTS B5
824~849 MHz
869~894 MHz
UMTS B8
880~915 MHz
925~960 MHz
UMTS B9
1749.9~1784.9 MHz
1844.9~1879.9 MHz
UMTS B19
869~894 MHz
869~894 MHz
TD-SCDMA B34
2010~2025 MHz
2010~2025 MHz
TD-SCDMA B39
1880~1920 MHz
1880~1920 MHz
FDD-LTE B1
1920~1980 MHz
2110~2170 MHz
FDD-LTE B2
1850~1910 MHz
1930~1990MHz
FDD-LTE B3
1710~1785 MHz
1805~1880 MHz
FDD-LTE B4
1710~1755 MHz
2110~2155 MHz
FDD-LTE B5
824~849 MHz
869~894 MHz
FDD-LTE B7
2500~2570 MHz
2620~2690 MHz
FDD-LTE B8
880~915 MHz
925~960 MHz
FDD-LTE B9
1749.9~1784.9 MHz
1844.9~1879.9 MHz
FDD-LTE B12
699~716MHz
728~746MHz
FDD-LTE B17
704~716 MHz
734~746 MHz
FDD-LTE B19
830~845 MHz
875~890 MHz
FDD-LTE B20
832~862 MHz
791~821 MHz
FDD-LTE B28
703~748 MHz
758~803 MHz
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
43
TDD-LTE B38
2570~2620 MHz
2570~2620 MHz
TDD-LTE B39
1880~1920 MHz
1880~1920 MHz
TDD-LTE B40
2300~2400 MHz
2300~2400 MHz
TDD-LTE B41
2555~2655 MHz
2555~2655 MHz
5.2 TX Power and RX Sensitivity
Table 5-2 N720 RF power and RX sensitivity
Band
Transmitting Power
Receiving Sensitivity
GSM850
33 dBm+2/-2 dBm
<-108 dBm
EGSM900
33 dBm+2/-2 dBm
<-108 dBm
DCS1800
30 dBm+2/-2 dBm
<-108 dBm
PCS1900
30 dBm+2/-2 dBm
<-108 dBm
CDMA BC0
24dBm+1/-1 dBm
<-107 dBm
UMTS B1
24 dBm +1/-3 dBm
<-108 dBm
UMTS B2
24 dBm +1/-3 dBm
<-108 dBm
UMTS B4
24 dBm +1/-3 dBm
<-108 dBm
UMTS B5
24 dBm +1/-3 dBm
<-108 dBm
UMTS B8
24 dBm +1/-3 dBm
<-109 dBm
UMTS B9
24 dBm +1/-3 dBm
<-108 dBm
UMTS B19
24 dBm +1/-3 dBm
<-108 dBm
TD-SCDMA B34
24 dBm +1/-3 dBm
<-109 dBm
TD-SCDMA B39
24 dBm +1/-3 dBm
<-109 dBm
FDD-LTE B1 (10 MHz)
23mdBm+2/-2 dBm
<-97 dBm
FDD-LTE B2 (10 MHz)
23mdBm+2/-2 dBm
<-95 dBm
FDD-LTE B3 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
FDD-LTE B4 (10 MHz)
23 dBm+2/-2 dBm
<-97 dBm
FDD-LTE B5 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
FDD-LTE B7 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
FDD-LTE B8 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
FDD-LTE B9 (10 MHz)
23 dBm+2/-2 dBm
<-96 dBm
FDD-LTE B12 (10MHz)
23 dBm+2/-2 dBm
<-95 dBm
FDD-LTE B17 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
44
FDD-LTE B20 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
FDD-LTE B28 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
TDD-LTE B38 (10 MHz)
23 dBm+2/-2 dBm
<-97 dBm
TDD-LTE B39 (10 MHz)
23 dBm+2/-2 dBm
<-97 dBm
TDD-LTE B40 (10 MHz)
23 dBm+2/-2 dBm
<-97 dBm
TDD-LTE B41 (10 MHz)
23 dBm+2/-2 dBm
<-95 dBm
All the values above are obtained in the lab environment. In actual applications, there might be a
difference because of the network environment.
5.3 GNSS Features
Table 5-3 GNSS parameters
Parameter
Value
GPS L1 operating frequency
1575.42±1.023MHz
GLONASS operating frequency
1597.5~1605.9 MHz
BDS operating frequency
1559.1~1563.1 MHz
Tracking sensitivity
-160dBm (GPS)/-159.5 dBm (GLONASS)/TBD (Beidou)
Capturing sensitivity
-144 dBm (GPS)/-143.5 dBm (GLONASS)
Positioning precision (in air)
< 3m (CEP50)
Hot start (in air)
<2.5s
Cold start (in air)
<35s
Update frequency
1Hz by default
CNRin/CNRout
3 dB
Max. positioning altitude
18000 m
Max. positioning speed
515 m/s
Max. positioning acceleration
4 g
GNSS data type
NMEA-0183
GNSS antenna type
Passive/active antenna
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
45
6 Mechanical Feature
6.1 Dimensions
Figure 6-1 Dimensions of N720
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
46
6.2 PCB Foot Print
Figure 6-2 N720 PCB foot print (Top View)
A test point is reserved at the Silk Area. It is recommended that a layer of white ink is added in case short
circuit. Do not layout any trace under the JTAG pin.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
47
7 Mounting and Packaging
7.1 Mounting the Module onto the Application Board
N720 is compatible with industrial standard reflow profile for lead-free SMT process.
The reflow profile is process dependent, so the following recommendation is just a start point guideline:
Only one flow is supported.
Quality of the solder joint depends on the solder volume. Minimum of 0.12 mm to 0.15mm stencil
thickness is recommended.
Use bigger aperture size of the stencil than actual pad size.
Use a low-residue, no-clean type solder paste.
For information about cautions in N720 storage and mounting, refer to Neoway Module Reflow
Manufacturing Recommendations.
When maintaining and manually desoldering it, use heat guns with great opening, adjust the temperature
to 250 degrees (depending on the type of the solder paste), and heat the module till the solder paste is melt.
Then remove the module using tweezers. Do not shake the module in high temperature when removing it.
Otherwise, the components inside the module might get misplaced.
7.2 Packaging
N720 modules are packaged in sealed bags on delivery to guarantee a long shelf life. Package the modules
again in case of opening for any reasons.
If exposed to air for more than 48 hours at conditions not worse than 30 °C/60% RH, a baking procedure
should be done before SMT. Or if the indication card shows humidity greater than 20%, the baking
procedure is also required. Do not bake modules with the package tray directly.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
48
8 SMT Temperature Curve
Figure 8-1 Temperature curve
X: Time (s) Y: Temperature (°C)
Technical parameters:
Ramp up rate: 1 to 4 °C/sec
Ramp down rate: -3 to -1 °C/sec
Soaking zone: 150-180 °C, Time: 60-100 s
Reflow zone: >220 °C, Time: 40-90 s
Peak temperature: 235-250 °C
Do not use the kind of solder paste different from our module technique.
The melting temperature of solder paste with lead is 35 °C lower than that of solder paste without lead.
It is easy to cause faulty joints for BGA inside the module after second reflow soldering.
When using only solder pastes with lead, please ensure that the reflow temperature is kept at 220 °C
for more than 45 seconds and the peak temperature reaches 240 °C.
Neoway will not provide warranty for heat-responsive element abnormalities caused by improper
temperature control.
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
49
9 Abbreviations
ADC
Analog-Digital Converter
CPU
Central Processing Unit
DTR
Data Terminal Ready
EGSM
Enhanced GSM
ESD
Electro Static Discharge
GPRS
General Packet Radio Service
GSM
Global Standard for Mobile Communications
IMEI
International Mobile Equipment Identity
LED
Light Emitting Diode
PCB
Printed Circuit Board
RF
Radio Frequency
SIM
Subscriber Identification Module
UART
Universal asynchronous receiver-transmitter
