Hitachi SH7760 Solution Engine2 Overview

Overview (MS7760CP01P) 1st Edition Hitachi ULSI Systems Co., Ltd. MS7760CP01P-M

improvement. 2. Information contained in this manual is correct and reliable, but Hitachi ULSI Systems shall not be held responsible for damage due to the use of information, product or circuit or infringement of property rights or other rights. 3. This manual does not grant users the property rights and other rights of the third party or Hitachi ULSI Systems. 4. No part of this manual may be transcribed or duplicated without the written permission of Hitachi ULSI Systems. 5. The appearance of the product shown in this manual may slightly differ from that of the actual product.

Thank you for your purchasing our MS7760CP01P board (simply called Solution Engine2 in this manual). Read the following notes and cautions before using Solution Engine2. Solution Engine2 Components Confirm that the following components are all contained after unpacking. Product model: MS7760CP01P • Solution Engine2 main unit (CPU board, LCD board, debug board and I/O board) • AC adapter • RS-232C cable • CD-ROM (Software, Solution Engine2 User’s Manual (This Manual)) • Big-endian monitor EPROM • Software License Agreement • User Registration Card

If ignored, there is a risk of death or heavy injury. If ignored, there is a risk of injury or equipment damage. • If smoke or abnormal smell arises from the board, stop using Solution Engine2, disconnect the AC adapter immediately from the receptacle and turn off Solution Engine2. • Don’t disassemble or modify Solution Engien2 to avoid a risk of high-voltage electric shock or fire. • Don’t drop water or liquids onto Solution Engine2 to avoid a risk of electric shock or fire. When water or liquid is dropped onto the board, disconnect the AC adapter immediately from the receptacle, and wipe it with a soft cloth to avoid a risk of electric shock or fire. • Don’t fall objects (line or solder scrap) onto Solution Engine2. If an object is dropped into it, disconnect the AC adapter immediately from the receptacle, turn off Solution Emgine2, and remove the object from the inside of the board to avoid a risk of electric shock or fire. • Use a dedicated AC adapter that comes standard with Solution Engine2 to avoid a risk of electric shock, abnormal heat or fire. • Don’t use inflammable liquids (alcohol, benzine or thinner) for cleaning the board to avoid a risk of fire. • Don’t place a heavy item on the AC adapter cord. To avoid a risk of electric leakage, fire or electric shock, don’t allow the AC adapter cord to be damaged or modified. • Don’t unplug the AC adapter cord with wet hand to avoid a risk of electric shock. When unplugging the cord, grasp and pull the plug instead of the cord. Don't pull the AC adapter cord to avoid a risk of cord damage, electric shock or fire.

electric shock, abnormal heat or fire. • To power an external device from Solution Engine2's internal power supply, don’t supply a current over the permissible level of each power supply. If the supplied current exceeds the permissible current level, there is a risk of electric shock, abnormal heat or fire. • When Solution Engine2 is powered and used for a long time, it may be heated up to a temperature of about 50ºC. Though this is not a fault with Solution Engine2, there is a risk of low-temperature burn injury if skin touches it for a long time. • Don’t use or store Solution Engine2 in a place subject to direct sunlight or near the heater to prevent Solution Engine2 from being deformed due to heat. • Don’t store Solution Engine2 in a dusty or humid place. • Turn off the power before connecting cables or equipment. When this caution is ignored, a fault may occur with Solution Engine2. • When connecting the AC adapter to the receptacle, check the polarity and connection beforehand to avoid a risk of electric shock, fire or fault. • Don’t distribute or permit the use of Solution Engine2 to those who may use it for purposes that may disturb or threaten international peace or security and don’t use it by yourself for malicious purposes. When exporting the purchased Solution Engine2, observe the foreign exchange law and take appropriate action.

conditions (normal environmental conditions, normal usage). The following lists the cases where Solution Engine2 must be repaired for value regardless of the period of free guarantee. - System malfunctions due to natural disasters. - System modification by users - System malfunction due to incorrect use • Solution Engin2 is specifically designed to serve various evaluation purposes prior to product development. Don't incorporate it into the product itself. We do not guarantee the performance of Solution Engine2 when used inside a product. Others • The product names in this manual are trademarks or registered trademarks of the respective manufacturers.

Notes on Using the MS7760CP01P 1. System Configuration ………………………8 1.1 Solution Engine2 Features ………………………8 1.2 Solution Engine2 Configuration ………………………8 1.3 Solution Engine2 Appearance ………………………10 1.4 Solution Engine2 Specification ………………………14 2. Installation ………………………16 2.1 Host System Connection ………………………16 2.2 AC Adapter Connection ………………………18 2.3 Turning ON or OFF Solution Engine2 ………………………19 2.4 Using the Debug Board ………………………20 3. Description of Switches ………………………23 3.1 CPU Board Switch ………………………23 3.2 LCD Board Switch ………………………25 4. Memory Map ………………………26 4.1 Memory Map for T-Engine Only ………………………26 4.2 Memory Map during Debug Board Connecti on ………………………27

5.1 PCMCIA ………………………29 5.2 USB Host ………………………33 5.3 UART ………………………35 5.4 LCD ………………………38 5.5 Sound Generator ………………………42 5.6 SIM Card Interface ………………………45 6. Power Supply Controller ………………………48 6.1 Power Supply Controller Function ………………………48 6.2 Serial Communication between the SH7760 and Power Supply Controller ………………………49 6.3 RTC (Real-time Clock) Function ………………………55 6.4 Touch Panel Function ………………………65 6.5 Key Switch Control ………………………85 6.6 Power Supply Control ………………………93 6.7 LED Control ………………………95 6.8 LCD Front Light Control ………………………96 6.9 Reset Control ………………………97 6.10 Infrared Remote Control ………………………98 6.11 Serial EEPROM Control ………………………104 6.12 Electronic Volume Control ………………………106 6.13 Initial Values in thePower Supply Control Registers ………………………107

7.1 SH7760 External Interrupts ………………………110 8. Solution Engine2 Extension Slots ………………………111 8.1 Extension Slot Specifications ………………………111 8.2 Extension Slot Signals ………………………112 9. Daughter Board Design Guide ………………………113 9.1 Daughter Board Dimensions ………………………113 9.2 Daughter Board Power Supply ………………………113 9.3 Daughter Board Stack ………………………114 9.4 Daughter Board WAIT#Output ………………………114 9.5 Extension Slot AC Timing ………………………115 10. Monitor Program Usage ………………………117 10.1 Monitor Program Usage ………………………117 10.2 List of Monitor Program Fubctions ………………………126 10.3 Command Description ………………………127

1.1 Solution Engine2 Features The following summarizes the main features of Solution Engine2. (1) The manual covers all information about Solution Engine2, including the circuit diagrams, connector specifications and internal logic of FPGA employed on this board. (2) The peripheral LSI chips (PCMCIA controller and sound generator chips) are commercially available. (3) This board contains the PCMCIA controller, sound generator chip, SIM card connector, etc., so that application systems can be developed taking advantage of them. (4) This board contains two SH7760 buses (address bus and data bus) and one extension slot subject to control signal output so that users can connect user-specific hardware. 1.2 Solution Engine2 Configuration Figure 1.1 shows a Solution Engine2 system configuration and Figure 1.2 a Solution Engine2 block diagram. Besides Solution Engine2 and its accessories, prepare any user-specific devices as needed. Figure 1.1 Solution Engine2 System Configuration ATA card, etc. Host System AC adapter(accessory) Solution Engine2 RS-232C cable (accessory) USB mouse, etc. USB host Earphones Headphone SIMcard

CPU SH7760 SH Local Bus 8bit SDRAM P 16bit 32bit 16bit PC Card USB IIS CPG UART(2Ch) PCMCIA BSC 3.3V 1.5V CLK Card 5V SIM 5.6V IIC INTC LCD board interfce SIM H HP/MIC LCD1 LCD2 Serial AC adapter Sound Generator chip UDA1342TS H8/3048B RTC SROM Supply voltage generation Power supply control Address decoder LCDC Flash Memory Bus Buffer Extension bus interface USBH

Solution Engine2 consists of four boards: CPU, LCD, debug and I/O. Figure 1.3 is an external view of the Solution Engine2. Figures 1.4 to 1.7 show the appearances of the respective boards (CPU, LCD, debug and I/O boards). Figure.1.3 Solution Engine-External View LCD Board CPU Board I/O Board Debug Board

CN1 CN2 CN3 CN5 CN4 SW2 SW1 SW3 Contrast control volume LCD interface connector1 LCD interface connector2 LCD interface connector3 CPU board interface connector2 CPU board interface connector1 Rear view LCD Front view Infrared remote control reception Push-button switch3 Cursor switch1 Push-button switch2

PC Card slot SW1 CN9 CN5 CN6 CN10 CN3 SW2 SW3 CN1 SW 5 SW4 LED3 SH7760 CN4 CN1 CN15 CN17 CN16 Infrared remote control transmission LED 8-bit DIP switch System reset switch H8/3048-ONE write connector Extension slot Serial interface connector I/O board interface connector1 SIM card connector I/O board interface connector2 Rear view Earphones/microphones connection connector Headphones connection connector LCD board interface connector1 LCD board interface connector2 Power-on switch Reset switch NMI switch AC adapter connection connector USB HOST interface connector Front view Note: The “CN15” connector is used to test the board prior to shipping from the factory. NO connection must be made to this connector.

Figure 1.7 I/O Board-External View J1 TP1 TP2 TP3 EPROM 8-bit LED 16-bit LED Extension slot EPROM connection jumper switch H-UDI connector CN2 CN1 CN11 CN3 CN10 CN9 CN8 CN6 CN7 CN5 CN4 CN1 CN2

Table 1.1 summarizes the Solution Engine2 function specifications and Table 1.2 the power supply, dimensions and environmental specifications. In addition, Table 1.3 summarizes the permissible currents that can be supplied to the outside by Solution Engine2 supply voltages. Table 1-1 Solution Engine2 Function Specifications Item Specification Remarks CPU SH7760 Model name: HD6417760BP200D (Hitachi) Input clock: 16.6667MHz Operating clock (Internal): 200MHz (x 12) (External): 66MHz (x 4) Package: 256-pin BGA Flash Memory Capacity: 8MB MBM29DL6409TN (Fujitsu) x 2 SDRAM Capacity: 64MB EDS2516APTA-75 (ELPIDA) x 2 PC Card I/F One slot Controller: MR-SHPC-01 V2T (Marubun) Package: 48-pin TQFP Serial interface 2ch Controller: ST16C2550CQ48 (EXAR) Package: 48-pin TQFP ChA: H8/3048F-ONE interface ChB: Monitor for debugging Sound Model name: UDA1342TS (Phillips) Package: 28-pin SSOC Earphone/microphone: 1ch Headphone output: 1ch - Microphone input Impedance: 2.2O - Sensitivity: -51dB/Pa Headphone output Impedance: 32O The SH7760 internal SSI is used to transfer data. The SH7760 internal SSI used to set a mode. USB Host 1ch Controller: SH7760 internal USB host TFT color LCD module Model name: NL2432DR22-02V (NEC) Display color: 262, 144 colors Display area: 240 (H) x 320 (V) Controller: SH7760 internal LCDC Power supply controller H8/3084F-ONE Model name: HD64F3048BVTE25 (Hitachi) Operating frequency: 7.3728Mhz Package: 100-pin TQFP Power supply control/RTC/Tablet interface The infrared remote control and SH7760 are interfaced via the serial chA. RTC Model name: ADS7843 (TI) Package: 16-pin SSOP Via the H8/3048F-ONE Touch panel interface Model name: ADS7843 (TI) Package: 16-pin SSOP Via the H8/3048F-ONE (Mounted on the LCD board) Serial EEPROM Capacity: 512 bytes Model name: S-29391AFJA (SII) Via the H8/3048F-ONE Infrared remote control Transmission Model name: GL100MNOMP (Sharp) Transmission carrier: 38kHz Reception Model name: GP1UC101 (Sharp) Reception carrier: 38kHz Via the H8/3048F-ONE

Item Specifications Environment Operating condition - Temperature: 10-35°C - Humidity: 30 to 85%RH (no dew condensation) - Ambient gas (no corrosive gas) Operating voltage DC 5.6V Dissipation current 600mA Dimensions CPU board: 120mm x 75mm LCD board: 120mm x 75mm Debug board: 101mm x 75mm I/O board: 101mm x 75mm Table 1.3 Permissible Current Supply to the Outside by Solution Engine2 Supply Voltages Supply voltage Permissible current Devices subject to permissible current supply 5V 250mA - PCMCIA card power supply - USB bus power - Extension slot 3.3V 250mA - PCMCIA card power supply - Extension slot [Notes] (1) Table 1.2 shows the maximum dissipation current of T-Engine (comprising the CPU board, LCD board, debug board and I/O board) without external devices. (2) Table 1.3 shows the sum of permissible current in all the powered devices on Solution Engine2. Accordingly, when a current of 100mA is used for the PCMCIA card supply voltage (5V), the currents of the USB bus power or extension slot is 150mA (250mA to 100mA). This is true for the supply voltage 3.3V. (3) When the PCMCIS card, etc. is powered from the internal power supply of Solution Engine2, the current must not exceed the permissible current of each power supply shown in Table 1.3. Otherwise, there is a risk of electric shock, heat, or fire.

To use the monitor program, connect the host interface connector (CN1) of Solution Engine2 to the host system with an RS-232C cross cable (accessory). Figure 2.1 shows a host system connection method. Figure 2.2 shows the pins of a serial interface connector. Table 2.1 shows the signals of the serial interface connector. Figure 2.1 Host System Connection Method Figure 2.2 Serial Interface Connector Pin Layout Solution Engine2 Host system RS-232 cross cable (accessory) 1 15 CN1

Pin No Signal name I/O Remarks 1 GND - 2 TxD Output TXB(UART) 3 RxD I RXB(UART) 4 GND - 5 RTS O RTSB(UART) 6 CTS I CTSB(UART) 7 GND - 8 Reserved - ISP TCK(*) 9 Reserved - GND(*) 10 Reserved - ISP TMS(*) 11 Reserved - ISP Plug(*) 12 Reserved - ISP BScan(*) 13 Reserved - ISP TDI(*) 14 Reserved - ISP TDO(*) 15 Reserved - Vcc(3.3V) (*) * These pins are only used to test the board when it is shipped from the factory. Don’t use these pins for other purposes.

Figure 2.3 shows an AC adaptor connection method. As shown in Figure 2-3, connect the plug to the AC adaptor connector of Solution Engine2 (1), then connect the adaptor cord to the receptacle (2). Figure 2.3 AC Adapter Connection [Notes] (1) Don’t put a heavy item on the AC adapter cord. To avoid a risk of electric leakage, fire or electric shock, don’t allow the AC adapter cord to be damaged or modified . (2) Don’t unplug the AC adapter cord with wet hand to avoid a risk of electric shock. When unplugging the cord, grasp and pull the plug instead of the cord. Don’t pull the AC adapter cord to avoid a risk of cord damage, electric shock or fire. (3) When connecting the AC adapter to the receptacle, check the polarity and connection beforehand to avoid a risk of electric shock, fire or fault. AC adapter Solution Engine2 (2) Connect the AC adapter cord to the receptacle. (1) Connect the plug. Power jack (CN14) AC 110V

To turn on or off Solution Engine2, press the Power Switch (SW2) on the CPU board. To turn it on, press and hold down this switch for 0.5 seconds or more. To turn it off, press and hold down this switch for 4 seconds or more until Solution Engine2 is powered off. 2.4 Debug Board Usage 2.4.1 Debug Board Function If the debug board has been connected to Solution Engine2, the following functions can be implemented. (1) Run the program stored in the EPROM on the debug board to refresh the flash memory on the Solution Engine2 or the H8/3048-ONE firmware. For details of refreshing, refer to 10. "Flash Memory Refresh." (2) All 8-bit LEDs on the debug board can be turned on or off from the SH7760 board. The software execution state can be monitored by controlling the ON/OFF state of these LEDs. (3) The settings of the 16-bit switches on the SH7760 debug board can be read. These 16-bit switches can be used to control various kinds of operation conditions. (4) The H-UDI debugger (to be connected to the H-UDI and AUD pins of the SH7760) can be used.

Figure 2.4 shows a debug board connection method. Connect the debug board to the extension slot (CN4) on the Solution Engine2 board. Figure 2.4 Debug Board Connection [Notes] When connecting the debug board or detaching the EPROM, turn off Solution Engine2 in advance. When attaching the EPROM again, check the connecting direction. Figure 2.5 EPROM Connection Solution Engine2 Extension slot (CN2) Connection Extension slot (CN1) TP1 J1 CN2 CN1 TP2 TP3 EPROM EPROM TP1 J1 CN2 CN1 TP2 TP3

Table 2.2 describes a method for setting the EPROM selection jumper switch (J1) on the debugger board. For details of a memory map during debug board connection, refer to 4. “Memory Map.” Table 2.2 Setting the EPROM Selection Jumper Switch (J1) Jumper switch Setting Description Debug board resources are assigned to area 0 on the SH7760 board as shown below. (Factory setting) - The EPROM mounted on the debug board is assigned to an address range from h’00000000 to h’001FFFFF. - The 8-bit LEDs mounted on the debug board are assigned to an address range from h’00400000 to h’007FFFFF. - The 16-bit LEDs mounted on the debug board are assigned to an address range from h’00800000 to h’00BFFFFF. - The flash memory of Solution Engine2 is assigned to an address range from h’01000000 to h’017FFFFF. J1 Debug board resources are assigned to area 0 on the SH7760 board as shown below. - The flash memory of Solution Engine2 is assigned to an address range from h’00000000 to h’007FFFFF. - The EPROMs mounted on the debug board are assigned to an address range from h’01000000 to h’011FFFFF - The 8-bit LEDs mounted on the debug board are assigned to an address range from h’01400000 to h’017FFFFF. - The 16-bit LEDs mounted on the debug board are assigned to an address range from h’01800000 to h’01BFFFFF. 1 2 Pins 1 and 2: OPEN 1 2 Pins 1 and 2 are short-circuited.

The low-order 8 bits (D7 to D0) of the SH7760 data bus are connected to the 8-bit LEDs placed on the debug board. The 8-bit LEDs can be turned on or off by writing data to an area assigned for the LEDs through D7 to D0. When a value of 1 is written to a bit, the corresponding LED is turned off. When a value of 0 is written to the bit, it is turned on. 2.4.5 16-bit Switch on the Debug Board The 16 bits (D15 to D0) of the SH7760 data bus are connected to the 16-bit switches placed on the debug board. The ON/OFF state of the 16-bit switches can be known by reading data from an area assigned for each of the switches through D15 to D0. When a value of 1 is read from a bit, the corresponding switch is set to OFF. When a value of 0 is read from the bit, it is set to ON. 2.4.6 H-UDI Debugger Connection The debug board allows the H-UDI debugger to be connected to the pin 36 (CN2) of the H-UDI (Hitachi-User Debug Interface) connector. Connect the H-UDI and AUD pins of the SH7760 board to the H-UDI connector. Figure 2.4 shows a method for connecting the H-UDI debugger. Connect an H-UDI debugger cable to the H- UDI connector (CN2) of the debug board. Note that the following H-UDI debugger can be connected to Solution Engine2. For details on the H-UDI debugger connection/setup procedure, refer to the pertinent manual of the product. - RENESAS Technology Corporation E10A Emulator Model name: HS7600KCM02H (PCMCIA) Model name: HS7760KCI02H (PCI) - Hitachi ULSI Systems Co., Ltd. MY-ICE EZ emulator Figure 2.6 H-UDI Debugger COnnection [Notes] (1) Solution Engine2 permits the connection of only the H-UDI debugger that uses the AUD and H-UDI pins of the SH7760 board. J1 CN2 Connection Host system Debug board H-UDI debugger Solution Engine2 CN2 Maker: Hirose Model name: DX10M-36SEE (36 pins)

Figure 3.1 shows the locations of switches (SW1 to SW5) on the CPU board. In addition, this section gives a brief description of each switch in (1) to (5). Figure 3.1 CPU Board Switches (SW1 to WS5) (1) Power Switch (SW1) This switch turns on or off the Solution Engine2 unit. To turn on the Solution Engine2 unit, press and hold down this switch for 0.5 seconds or more. To turn it off, press and hold down this switch for 4 seconds or more when Solution Engine2 is being powered. (2) Reset Switch (SW2) This switch resets Solution Engine2. To reset devices other than the H8/3048-ONE, press this switch. To reset and restart Solution Engine2, release this switch. In this case, the values of H8/3048-ONE internal registers are not initialized. Among the control registers, the values of those that can be accessed by SH7760 are initialized but the others are not (i.e., their values are retained). For more details, refer to 6.13 “Initial Values of the Power Supply Controller Register.” (3) NMI Switch (SW3) This switch controls the SH7760 NMI pin. Press this switch and the SH7760 NMI pin will go “Low.” Release this switch, and the NMI pin will go “High.” SW1 Power-on switch CN9 CN5 CN6 CN10 CN3 SW2 SW3 Reset switch NMI switch CN1 SW5 SW4 LED3 8-bit DIP switch System reset switch SH7760 CN4 CN1 CN15 Rear view CN17 CN16 Front view

Figure 3.2 shows the setting of an 8-bit DIP switch. This DIP switch is connected to the pins ID0 to ID5 and MD5 of the ID register. Be sure to turn off the power-on switch before setting the DIP switch. (a) Switches SW5-1 to SW5-6 are connected to pins ID0 to ID5 (input pins). ON: The input pin goes “Low.” OFF: The input pin goes “High.” (Factory setting) (b) The SW5-7 switch is used to set the power-on condition of Solution Engine2. ON: Solution Engine2 is powered when power supply takes place through the AC adapter. OFF: Solution Engine2 is powered when the power-on switch is pressed. (Factory setting) (c) The SW5-8 switch is connected to SH7760's pin MD5. The SW5-8 switch is used to set the type of endian for SH7760 operation. ON: The MD5 pin goes “Low” to set the big endian for SH7760 operation. OFF: The MD5 pin goes “High” to set the little endian for SH7760 operation. (Factory setting) Figure 3.2 Setting the 8-bit DIP Switch (5) System Reset Switch (SW4) The system reset switch controls the hardware reset for Solution Engine2. All devices on Solution Emgine2 are reset while this system reset switch is pressed and held down. Solution Engine2 is turned off when this switch is released. It is turned on and activated when the power-on switch is pressed. However, Solution Emgine2 is turned on and activated if this switch is released so long as the SW5-7 switch is set ON. ON 1 2 3 4 5 6 7 8 SW5-1 SW5-8 [OFF setting] SW5-n SW5-n [ON setting]

The states of the cursor switch (SW1) and push-button switches (SW2 and SW3) are signaled to the SH7760 through the power supply controller. For details, refer to 6. “Power Supply Controller.”

4.1 Memory Map for the Solution Engine2 Board Table 4.1 shows an SH7760 memory map for the Solution Engine2 board without expansion board. Table 4.1 SH7760 Memory Map for Solution Engine2 without Expansion Board Area No. Bus width Space Space name Device Remarks CS0 area 16bit h’00000000 ~ h’00FFFFFF Flash memory area 8MB MBM29DL640E-90TN (Fujitsu) x 1 h’01000000 ~ h’03FFFFFF - Unused area CS1 area 16bit h’04000000 ~ h’ 07FFFFFF Board control register area 16B Board control register CS2 area 8/16/32bit h’08000000 ~ h’0BFFFFFF Extension area (CS2) 64MB Extension slot (CS2 area) Extension slot CS2# assert CS3 area 32bit h’0C000000 ~ h’0FFFFFFF SDRAM area 64MB EDS2516APTA-75(ELPIDA) x 2 CS4 area 8/16/32bit h’10000000 ~ h’13FFFFFF Extension area (CS4) 64MB Extension slot (CS4 area) Extension slot CS4# assert CS5 area 8/16/32bit h’14000000 ~ h’17FFFFFF Extension area (CS5) 64MB Extension slot (CS5area) Extension slot CS5# assert CS6 area 16bit h’18000000 ~ h’19FFFFFF PCMCIA area Card controller Model name: MR-SHPC-01 V2T (Marubun) This device is simply called SH-PCIC. h’1A000000 ~ h’1A7FFFFF UART area (ChA) UART Model name: ST16C2550CQ48 (EXAR) This device is simply called UART. This device is used for interface with H8/3048- ONE. h’1A800000 ~ h’1AFFFFFF UART area (ChB) Same as above This device is used for serial interface with the host. h’1B000000 ~ h’1BFFFFFF ID register area This area is used to read out the setting of a DIP switch. CS7 area - h’1C000000 ~ h’1FFFFFFF - - Reserved

Table 4.2 shows a memory map for the SH7760 when the debug board is connected to the Solution Engine2 board and the jumper switch (J1) on the debug board is short-circuited. Table 4.2 also shows a memory map for the SH7760 when the debug board is connected to the Solution Engine2 board and the jumper switch (J1) on the debug board is open. Table 4.2 Memory Map during Debug Board Connection (J1: Short-circuited) Area No. Bus width Space Space name Device Remarks CS0 area 16bit h’00000000 ~ h’003FFFFF EPROM area 256kB M27C800-100F1(ST Micro) x 1 Resource on the debug board h’00400000 ~ h’007FFFFF Debug LED area 1B 8-bit debug LED h’00800000 ~ h’00BFFFFF Switch area 2B 8-bit switch x 2 h’00C00000 ~ h’00FFFFFF - Unused area h’01000000 ~ h’01FFFFFF Flash memory area 8MB MBM29DL640E-90TN(Fujitsu) x 1 h’02000000 ~ h’03FFFFFF - Unused area CS1 area 16bit h’04000000 ~ h’07FFFFFF Board control register area 16B Board control register CS2 area 8/16/32bit h’08000000 ~ h’0BFFFFFF Extension area (CS2) 64MB Extension slot (CS2 area) Extension slot CS2# assert CS3 area 32bit h’0C000000 ~ h’0FFFFFFF SDRAM area 64MB EDS2516APTA-75(ELPIDA) x 2 CS4 area 8/16/32bit h’10000000 ~ h’13FFFFFF Extension area (CS4) 64MB Extension slot (CS4 area) Extension slot CS4# assert CS5 area 8/16/32bit h’14000000 ~ h’17FFFFFF Extension area (CS5) 64MB Extension slot (CS5 area) Extension slot CS5# assert CS6 area 16bit h’18000000 ~ h’19FFFFFF PCMCIA area Card controller Model name: MR-SHPC-01 V2T (Marubun) This device is simply called SH-PCIC. h’1A000000 ~ h’1A7FFFFF UART area (ChA) UART Model name: ST16C2550CQ48 (EXAR) This device is simply called UART. This device is used for interface with H8/3048- ONE. h’1A800000 ~ h’1AFFFFFF UART area (ChB) Same as above This device is used for serial interface with the host. h’1B000000 ~ h’1BFFFFFF ID register area This area is used to read the setting of a DIP switch. CS7 area - h’1C000000 ~ h’1FFFFFFF - - Reserved

Area No. Bus width Space Space name Device Remarks CS0 area 16bit h’00000000 ~ h’00FFFFFF Flash memory area 8MB MBM29DL640E-90TN (Fujitsu) x 1 h’01000000 ~ h’013FFFFF EPROM area 256kB M27C800-100F1(ST Micro) x 1 Resource on the debug board h’01400000 ~ h’017FFFFF Debug LED area 1B 8-bit debug LED h’01800000 ~ h’01BFFFFF Switch area 2B 8-bit switch x 2 h’01C00000 ~ h’01FFFFFF - Unused area h’02000000 ~ h’03FFFFFF - Unused area CS1 area 16bit h’04000000 ~ h’07FFFFFF Board control register area 16B Board control register CS2 area 8/16/32bit h’08000000 ~ h’0BFFFFFF Extension area (CS2) 64MB Extension slot (CS2 area) Extension slot CS2# assert CS3 area 32bit h’0C000000 ~ h’0FFFFFFF SDRAM area 64MB EDS2516APTA-75 (ELPIDA) x 2 CS4 area 8/16/32bit h’10000000 ~ h’13FFFFFF Extension area (CS4) 64MB Extension slot (CS4 area) Extension slot CS4# assert CS5 area 8/16/32bit h’14000000 ~ h’17FFFFFF Extension area (CS5) 64MB Extension slot (CS5 area) Extension slot CS5# assert CS6 area 16bit h’18000000 ~ h’19FFFFFF PCMCIA area Card controller Model name: MR-SHPC-01 V2T (Marubun) This device is simply called SH-PCIC. h’1A000000 ~ h’1A7FFFFF UART area (ChA) UART Model name: ST16C2550CQ48 (EXAR) This device is simply called UART. This device is used for interface with H8/3048- ONE. h’1A800000 ~ h’1AFFFFFF UART area (ChB) Same as above This device is used for serial interface with the host. h’1B000000 ~ h’1BFFFFFF ID register area This area is used to read the setting of a DIP switch. CS7 area - h’1C000000 ~ h’1FFFFFFF - - Reserved

5.1 PCMCIA 5.1.1 Block Description Figure 5.1 shows the PCMCIA control block. As shown in Figure 5.1, the PCMCIA control block contains a controller (MR-SHPC-01 V2 from Marubun), a 68-pin PC card interface connector (CN3) and a power supply controller IC (TPS2211DB from TI). This controller interfaces with the card(s) conforming to the PC Card Standard 97 and has the following features: • Internal memory windows (2 windows) and I/O window (one window) •Card access timing adjustment function • One-step read/write buffer • Endian internal control circuit • Support for 5.0V/3.3V cards • External buffer not required • Internal interrupt steering function • Power-down function • Internal suspend function There are four kinds of controller interrupts (SIRQ3 to SIRQ0). Inputs to the H7760 are made by the IRL codes. For details, refer to Marubun’s MR-SHPC-01 V2 Manual. Marubun Homepage: http://www2.marubun.co.jp Figure 5.1 PCMCIA Controk Block Marubun PCMCIA controller MR-SHPC-01 V2T /SIRQ3 /SIRQ2 /SIRQ1 /SIRQ0 CARD slot CN3 PC Card I/F Power supply control register (TPS2211IDB) /CVCC3 /CVCC5 CVPP0 CVPP1 CARD PW GOOD VCC(+5.0Vv/+3.3V/0V) VPP(+5.0Vv/+3.3V/0V) Card VCC FPGA SH7760 /IRL3 /IRL2 /IRL1 /IRL0 +3.3V +5.0V System VCC System bus I/F

Table 5.1 summarizes the pins of a 68-pin PC card interface connector (CN3). Table 5.1(1) PC Card Interface Connector Signal Pins Memory card I/O card Pin Signal name I/O Function Signal name I/O Function 1 GND - Ground GND - Ground 2 D3 I/O Data bit 3 D3 I/O Data bit 3 3 D4 I/O Data bit 4 D4 I/O Data bit 4 4 D5 I/O Data bit 5 D5 I/O Data bit 5 5 D6 I/O Data bit 6 D6 I/O Data bit 6 6 D7 I/O Data bit 7 D7 I/O Data bit 7 7 CE1# I Card enable CE1# I Card enable 8 A10 I Address bit 10 A10 I Address bit 10 9 OE# I Output enable OE# I Output enable 10 A11 I Address bit 11 A11 I Address bit 11 11 A9 I Address bit 9 A9 I Address bit 9 12 A8 I Address bit 8 A8 I Address bit 8 13 A13 I Address bit 13 A13 I Address bit 13 14 A14 I Address bit 14 A14 I Address bit 14 15 WE# I Write enable WE# I Write enable 16 READY O Ready IREQ# O Interrupt request 17 Vcc - Supply voltage Vcc - Supply voltage 18 VPP1 - Programmed supply voltage VPP1 - Programmed supply voltage 19 A16 I Address bit 16 A16 I Address bit 16 20 A15 I Address bit 15 A15 I Address bit 15 21 A12 I Address bit 12 A12 I Address bit 12 22 A7 I Address bit 7 A7 I Address bit 7 23 A6 I Address bit 6 A6 I Address bit 6 24 A5 I Address bit 5 A5 I Address bit 5 25 A4 I Address bit 4 A4 I Address bit 4 26 A3 I Address bit 3 A3 I Address bit 3 27 A2 I Address bit 2 A2 I Address bit 2 28 A1 I Address bit 1 A1 I Address bit 1 29 A0 I Address bit 0 A0 I Address bit 0 30 D0 I/O Data bit 0 D0 I/O Data bit 0 31 D1 I/O Data bit 1 D1 I/O Data bit 1 32 D2 I/O Data bit 2 D2 I/O Data bit 2 33 WP O Write protect IOIS16# O 16-bit I/O port 34 GND - Ground GND - Ground

Memory card I/O card Pin Signal name I/O Function Signal name I/O Function 35 GND - Gorund GND - Gorund 36 CD1# O Card detection CD1# O Card detection 37 D11 I/O Data bit 11 D11 I/O Data bit 11 38 D12 I/O Data bit 12 D12 I/O Data bit 12 39 D13 I/O Data bit 13 D13 I/O Data bit 13 40 D14 I/O Data bit 14 D14 I/O Data bit 14 41 D15 I/O Data bit 15 D15 I/O Data bit 15 42 CE2# I Card enable CE2# I Card enable 43 VS1# O Voltage sense VS1# O Voltage sense 44 RFU - Reserved IORD# I I/O read 45 RFU - Reserved IOWR# I I/O write 46 A17 I Address bit 17 A17 I Address bit 17 47 A18 I Address bit 18 A18 I Address bit 18 48 A19 I Address bit 19 A19 I Address bit 19 49 A20 I Address bit 20 A20 I Address bit 20 50 A21 I Address bit 21 A21 I Address bit 21 51 Vcc - Supply voltage Vcc - Supply voltage 52 VPP2 - Programmed supply voltage VPP2 - Programmed supply voltage 53 A22 I Address bit 22 A22 I Address bit 22 54 A23 I Address bit 23 A23 I Address bit 23 55 A24 I Address bit 24 A24 I Address bit 24 56 A25 I Address bit 25 A25 I Address bit 25 57 VS2# O Voltage sense VS2# O Voltage sense 58 RESET I Card reset RESET I Card reset 59 WAIT# O Bus cycle extension WAIT# O Bus cycle extension 60 RFU - Reserved INPACK# O Input port response 61 REG# I Register selection REG# I Register selection 62 BVD2 O Battery voltage detection SPKR# O Audio digital waveform 63 BVD1 O Battery voltage detection STSCHG# O Card status change 64 D8 I/O Data bit 8 D8 I/O Data bit 8 65 D9 I/O Data bit 9 D9 I/O Data bit 9 66 D10 I/O Data bit 10 D10 I/O Data bit 10 67 CD2# O Card detection CD2# O Card detection 68 GND - Ground GND - Ground

Table 5.2 shows a map for the PCMCIP controller registers. Each of the controller registers must be accessed in words. Table 5.2 PCMCIA Control Registers Address Initial value Register name H’B83FFFE4 H’0000 Mode register H’B83FFFE6 H’000C Option register H’B83FFFE8 H’03BF Card status register H’B83FFFEA H’0000 Interrupt factor register H’B83FFFEC H’0000 Interrupt control register H’B83FFFEE H’0000 Card voltage control register 1 H’B83FFFF0 H’07FC Memory window 0 Control register 1 H’B83FFFF2 H’07FC Memory window 1 Control register 1 H’B83FFFF4 H’07FC I/O window Control register 1 H’B83FFFF6 H’0000 Memory window 0 Control register 2 H’B83FFFF8 H’0000 Memory window 1 Control register 2 H’B83FFFFA H’0000 I/O window Control register 2 H’B83FFFFC H’0000 Card control register H’B83FFFFE H’5333 Chip information register

5.2.1 Block Description Figure 5.2 shows the USB host control block. As shown in Figure 5.2, the SH7760 contains an internal USB host controller. This internal controller supports USB Version 1.1 and OpenHCI, and has the following features: • Compatibility with the OpenHCI Version 1.0 register set. • Conforming to the USB Version 1.1 • Providing a route hub function • Supporting the low speed (1.5Mbps) and full speed (12MB) modes • Supporting the overcurrent detection function • Supporting up to 127 end points • Enabling the entire SDRAM area of area 3 (connected to the CPU) to be used for transfer data and descriptors For more details, refer to the pertinent SH7760 Hardware Manual. Figure 5.2 USB Host Control Block USB_PENC USB_OVC USB_DM USB_DP USB host controller USB power supply control driver +5V GND -DATA +DATA SH7760 USB Type A connector (CN7)

Figure 5.3 shows the pins of the USB host connector (CN7). Figure 5.3 USB Host Connector (CN7) Pins 5.2.3 Register Map Table 5.2 shows a register map for the SH7727 internal USB host controller registers. Table 5.3 USB Host Controller Register Address Initial value Register name H’FE340000 H’00000010 HcRevision register H’FE340004 H’00000000 HcControl register H’FE340008 H’00000000 HcCommandStatus register H’FE34000C H’00000000 HcInterruptStatus register H’FE340010 H’00000000 HcInterruptEnable register H’FE340014 H’00000000 HcInterruptDisable register H’FE340018 H’00000000 HcHCCA register H’FE34001C H’00000000 HcPeriodCurrentED register H’FE340020 H’00000000 HcControlHeadED register H’FE340024 H’00000000 HcControlCurrentED register H’FE340028 H’00000000 HcBulkHeadED register H’FE34002C H’00000000 HcBulkCurrentED register H’FE340030 H’00000000 HcDonrHeadED register H’FE340034 H’00002EDF HcFmInterval register H’FE340038 H’00000000 HcFrameRemaining register H’FE34003C H’00000000 HcFmNumber register H’FE340040 H’00000000 HcPeriodicStart register H’FE340044 H’00000628 HcLSThreshold register H’FE340048 H’02001202 HcRhDescriptorA register H’FE34004C H’00000000 HcRhDescriptorB register H’FE340050 H’00000000 HcRhStatus register H’FE340054 H’00000100 HcRhPortStatus1 register H’FE341000 ~ H’FE342FFF - Shared memory area 1 2 3 4 GND +DATA -DATA VBUS Signal name 4 3 2 1 Pin No Model name: 20-5041-004-100-834 Maker: Kyocera Elco CN7: USB host connector (TYPEA)

controller (ST16C2550 from EXAR), RS232C interface driver and 15-pin connector (CN1). This controller uses the clock pulses (7.3728MHz) supplied from the power supply controller (H8/3048F-ONE) for operations, and determines a baud rate (transfer rate) using these pulses as reference. This controller has been provided with a 2-channel UART device. Channel A is used to communicate with the power supply controller (H8/3048F-ONE). Because channel B is connected to a 15-pin RS-232C connector (CN1), it can be used as a debug interface if it is connected to a PC. In addition, channel A (INTA) inputs the controller interrupts to the SH7760 IRL9 and channel B (INTB) inputs them to the SH7760 IRL11. For more details, refer to EXAR’s ST16C2550 Manual. EXAR Homepage: http://www.exar.com Figure 5.4 Serial Interface Block Serial controller (ST16C2550) INTB INTA Chanel B FPGA SH7760 /IRL3 /IRL2 /IRL1 /IRL0 Address bus Data bus Control signal RS-232C I/F driver (SP3223ECY) 15 pin Serial connector (CN1) Chanel B XTAL SCI chanel 1 Power supply controller (H8/3048F-ONE) CK EXTAL 7.3728MHz OSC2

Figure 5.5 shows the pins of a 15-pin serial interface connector (CN1). Figure 5.5 15-pin Serial Interface Connector Pins 5.3.3 Register Map Tables 5.4 and 5.5 show register maps for the serial interface controller registers. Each of the serial interface controller registers must be accessed in words. If access takes place in words, data in the low order 8 bits (D7 to D0) will become effective. Table 5.4 Serial Interface Control Register Map (Channel A) Address Initial value Register name (at resd) Register name (at write) Remarks H’BA000000 - RHR (Receive Holding Register) THR (Transfer Holding Register) LCR bit7=0 H’BA000000 - DLL (LSB of Divisor Latch) DLL (LSB of Divisor Latch) LCR bit7=1 H’BA000002 H’00 IER (Interrupt Enable Register) IER (Interrupt Enable Register) LCR bit7=0 H’BA000002 - DLM (MSB of Divisor Latch) DLM (MSB of Divisor Latch) LCR bit7=1 H’BA000004 H’01 ISR (Interrupt Status Register) FCR (FIFO Control Register) H’BA000006 H’00 LCR (Line Control Register) LCR (Line Control Register) H’BA000008 H’00 MCR (Modem Control Register) MCR (Modem Control Register) H’BA00000A H’60 LSR (Line Status Register) N.A H’BA00000C H’X0 MSR (Modem Status Register) N.A H’BA00000E H’FF SPR (Scratchpad Register) SPR (Scratchpad Register) 1 15 CN1: 15-pin serial connector Model name: RMC-EA15MY-OM15-MC1 Moker: Honda Tsushin Kogyo Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND CTS RTS GND RxD TxD GND 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Signal name Pin No

Address Initial value Register name (at resd) Register name (at write) Remarks H’BA800000 - RHR (Receive Holding Register) THR (Transfer Holding Register) LCR bit7=0 H’BA800000 - DLL (LSB of Divisor Latch) DLL (LSB of Divisor Latch) LCR bit7=1 H’BA800002 H’00 IER (Interrupt Enable Register) IER (Interrupt Enable Register) LCR bit7=0 H’BA800002 - DLM (MSB of Divisor Latch) DLM (MSB of Divisor Latch) LCR bit7=1 H’BA800004 H’01 ISR (Interrupt Status Register) FCR (FIFO Control Register) H’BA800006 H’00 LCR (Line Control Register) LCR (Line Control Register) H’BA800008 H’00 MCR (Modem Control Register) MCR (Modem Control Register) H’BA80000A H’60 LSR (Line Status Register) N.A H’BA80000C H’X0 MSR (Modem Status Register) N.A H’BA80000E H’FF SPR (Scratchpad Register) SPR (Scratchpad Register)

internal LCD controller and an LCD panel (TFT liquid crystal panel) mounted on the LCD board that can display 16-bit RGB data with a resolution of QVGA (240 x 320). In addition, the SRAM allocated to area 3 is used for the LCD display VRAM (Video RAM). Display data is stored in the order of coordinates (0,0), (1,0), … (239, 319) from the address set in the LCD controller register (LDSARU). On the LCD panel display, data at the upper left corner is handled as data on the origin (0,0) and data at the lower right corner is handled as data on the coordinates (239,319). The front light on the LCD panel can be turned on or off by the power supply controller. For details on front light control, refer to 6. “Power Supply Controller.” In addition, refer to the pertinent SH7760 Hardware Manual for details on the LCD controller. Figure 5.6 LCD Control Block LCD Board LCD controller Video RAM (SDRAM) SH7760 Data bus (0,0) (239,319) SW2 SW1 SW3 Touch panel signal Front light control signal Key switch signal LCD board connection connector (CN6) LCD board connection connector (CN5) LCD data bus LCD controlasignal Power supply controller (H8/3048F-ONE) CPU board connection connector (CN2) CPU board connection connector (CN1)

Figure 5.7 shows the pins of the LCD interface connectors (CN5 and CN6). Tables 5.6 and 5.7 summarize the signals of these interface connectors. Figure 5.7 LCD Interface Connector (CN5/CN6) Pins Table 5.6 LCD Interface Connector (CN5) Signals Pin No. Signal name I/O Remarks Pin No. Signal name I/O Remarks 1 VBAT - Power supply 21 LCD13 OUT LCDC 2 VBAT - Power supply 22 LCD14 OUT LCDC 3 VBAT - Power supply 23 LCD15 OUT LCDC 4 VBAT - Power supply 24 GND - Power supply 5 N.C - Unused 25 GND - Power supply 6 LCD0 OUT LCDC 26 CL1 OUT LCDC 7 LCD1 OUT LCDC 27 CL2 OUT LCDC 8 LCD2 OUT LCDC 28 DON OUT LCDC 9 LCD3 OUT LCDC 29 M_DISP OUT LCDC 10 LCD4 OUT LCDC 30 FLM OUT LCDC 11 LCD5 OUT LCDC 31 VEPWC OUT LCDC 12 LCD6 OUT LCDC 32 VCPWC OUT LCDC 13 LCD7 OUT LCDC 33 NC - Unused 14 GND - Power supply 34 GND - Power supply 15 GND - Power supply 35 GND - Power supply 16 LCD8 OUT LCDC 36 IR_IN IN Remote control 17 LCD9 OUT LCDC 37 3.3V - Power supply 18 LCD10 OUT LCDC 38 3.3V - Power supply 19 LCD11 OUT LCDC 39 3.3V - Power supply 20 LCD12 OUT LCDC 40 3.3V - Power supply CN5: LCD interface connector Model name: FH12-40S-0.5SH Maker: Hirose Electric Co., Ltd. 1 24 1 40 CN5 CN6 CN6: LCD interface connector Model name: FH12-24S-0.5SH Maker: Hirose Electric Co., Ltd.

Pin No. Signal name I/O Remarks Pin No. Signal name I/O Remarks 1 GND - Power supply 13 ~PAD_CS OUT PAD I/F 2 GND - Power supply 14 ~PAD_IRQ IN PAD_I/F 3 KEY_IN0 IN KEY_I/F 15 PAD_DIN OUT PAD_I/F 4 KEY_IN1 IN KEY_I/F 16 PAD_DOUT IN PAD_I/F 5 KEY_IN2 IN KEY_I/F 17 PAD_DCLK OUT PAD_I/F 6 KEY_IN3 IN KEY_I/F 18 ~RESET OUT Reset 7 KEY_IN4 IN KEY_I/F 19 ~LCD_FLON OUT LCD Power supply 8 KEY_OUT0 OUT KEY_I/F 20 ~LCD_PWRDY IN LCD Power supply 9 KEY_OUT1 OUT KEY_I/F 21 GND - Power supply 10 KEY_OUT2 OUT KEY_I/F 22 GND - Power supply 11 GND - Power supply 23 3.3VSB - Power supply 12 GND - Power supply 24 3.3VSB - Power supply

Table 5.8 shows a register map for the SH7760 internal LCD controller. Table 5.8 LCD Controller Registers Address Initial value Register name H’FE300C00 H’0101 Input clock register H’FE300C02 H’0109 Module type register H’FE300C04 H’000C Data format register H’FE300C06 H’0000 Scan mode register H’FE300C08 H’0C000000 Data fetch start address register for data on the display top H’FE300C0C H’0C000000 Data fetch start address register for data on the display bottom H’FE300C10 H’0280 Fetch data line address offset register for display data H’FE300C12 H’0000 Palette control register H’FE300800~ H’FE300BFC - Palette data register H’FE300C14 H’4F52 Horizontal character count register H’FE300C16 H’0050 Horizontal synchronization signal register H’FE300C18 H’01DF Vertical display line count register H’FE300C1A H’01DF Vertical total line count register H’FE300C1C H’01DF Vertical synchronization signal register H’FE300C1E H’000C AC modulation signal toggle line count register H’FE300C20 H’0000 Interrupt control register H’FE300C24 H’0010 Power management mode register H’FE300C26 H’F60F Power supply control sequence duration register H’FE300C28 H’0000 Control register

5.5.1 Block Description Figure 5.8 shows the sound generator control block. As shown in Figure 5.8, this control block contains an SH7760 internal serial sound interface (SSI) and an audio CODEC (UDA1342TS from Phillips) so that sound can be output to headphones connected to an output mini-jack (CN9) or it can be input to earphones connected to an I/O mini-jack (CN10). In addition, headphone output takes place with the quality of stereo output while earphone I/O takes place with the quality of monaural I/O that uses only the Rch. This control block is connected to an electronic volume so that sound output volume can be controlled via the generator. The electronic volume is controlled by the power supply controller. For details, refer to 6. “Power Supply Controller.” In addition, Solution Engine2 has the following characteristics for microphone input and headphone output: - Microphone input Impedance: 2.2KO Sensitivity: -51dB/Pa - Headphone output Impedance: 32O For more details, refer to the pertinent SH7760 Hardware Manual and Phillips UDA1342TS Manual. Phillips Homepage: http://www.semiuconductors.phillips.com Figure 5.8 Sound Generator Control Block SH7760 Audio CODEC (UDA1342TS) DATAO BCK WS DATAI SYSCLK L3CLOCK L3DATA IIS Ch0 SDATA SCK WS CLK 22.5792MHz OSC4 Rch output Lch output Rch input Amplifier Electronic volume Power supply controller (H8/3048F-ONE) Rch Lch Sound output mini-jack (CN9) Sound I/O mini-jack (CN10) SCL SDA I2C Ch0 IIS Ch1 SDATA SCK WS CLK

Figure 5.9 shows the pins of the sound generator I/O mini-jack (CN9, CN10). Tables 5.9 and 5.10 list the signals of the sound generator I/O mini-jack (CN9, CN10). Figure 5.9 Sound Generator I/O Mini-jack (CN9, CN10) Table 5.9 Sound Generator I/O Mini-jack (CN9) Signals Pin No Signal name 1 GND 2 R-IN 3 R-OUT 4 MIC-IN 5 HP_SENSE Table 5.10 Sound Generator I/O Mini-jack (CN10) Signals Pin No Signal name 1 GND 2 L-OUT 3 R-OUT 4 HP_SENSE 5 NC 1 5 3 4 2 CN9,CN10: Sound generator I/O mini-jack ( 2.5) Model name: HSJ1602-010011 Maker: Hoshiden Corporation

Table 5.11 shows a register map for the SH7760 internal serial sound interface (SSI). Table 5.11 SSI Control Registers Register abbreviation Address R/W Initial value Access size SSICR0 H’FE680000 R/W H’0000 0000 32 SSISR0 H’FE680004 R/W H’0200 0003 32 SSITDR0 H’FE680008 R H’0000 0000 32 SSIRDR0 H’FE68000C R H’0000 0000 32 SSICR1 H’FE690000 R/W H’0000 0000 32 SSISR1 H’FE690004 R/W H’0200 0003 32 SSITDR1 H’FE690008 R H’0000 0000 32 SSIRDR1 H’FE69000C R H’0000 0000 32

5.6.1 Block Description Figure 5.11 shows the SIM card interface control block. As shown in Figure 5.11, this control block contains an SH7760 internal SIM card module (SIM), a power supply/level converter (LTC1555LEGN-1, 8) and an 8-pin connector (CN4) to enable communications with the SIM card inserted into the SIM card interface connector (CN4). SIM card reset can be controlled through SIM SIM_RST control. The following methods can be used for reset control. • “Low” output from SIM_RST: The SIM card reset pin is set to “Low.” (Reset) • “High” output from SIM_RST: The SIM card reset pin is set to “High.” (Normal) Power supply to the SIM card is controlled through the power supply controller (H8/3048f-ONE). The SIM card is being powered while Solution Engine2's power is turned on. Before inserting or removing the SIM card, be sure to turn off the Solution Engine2 unit. For more details, refer to the pertinent SH7760 Hardware Manual. Figure 5.11 eTROM Interface Control Block SH7760 Power supply/level converter (LTC1555LEGN-1.8) VCC Smart card module (SIM) SIM_CLK SIM_D SIM_RST CLK SIM card interface connector (CN4) I/O VCC RST Power supply controller (H8/3048F-ONE)

Figure 5.12 shows the pins of the SIM card interface connector (CN4) and Table 5.12 lists the signals of that connector. Figure5.12 SIM Card Interface Connector (CN4) Pins Table 5.12 SIM Card Interface Connector (CN4) Signals Pin No Signal name 1 C1:VCC 2 C2:RST 3 C3:CLK 4 C4:*1 5 C5:GND 6 C6:VPP 7 C7:I/O 8 C8: *1 *1 Don’t use the pins 4 and 8 because they must be connected to the board test connector (CN13). 1 3 4 2 CN4: SIM card interface connector Model name: 04-5036-008-110-862 Maker: Kyocera Elco 5 6 7 8

Table 5.13 shows a register map for the SH7760 internal SIM card module (SIM). Table 5.13 SIM Card Module Register Map Address Initial value Register name H’FE480000 H’20 Serial mode register H’FE480002 H’07 Bit rate register H’FE480004 H’00 Serial control register H’FE480006 H’FF Transmit data register H’FE480008 H’84 Serial status register H’FE48000A H’00 Received data register H’FE48000C H’01 Smart card mode register H’FE48000E H’00 Serial control 2 register H’FE480010 H’0000 Wait time register H’FE480012 H’00 Guard extension register H’FE480014 H’0173 Sample register

6.1 Power Supply Controller Functions The H8/3048F-ONE power supply controller (simply called the power supply controller) provides the following control functions by firmware stored in the internal memory. The following functions can be controlled through the UART ChA from the SH7760. Figure 6.1 shows a power supply control block diagram. (1) RTC (real-time clock) function (2) System power supply (3.3V/5/0V) ON/OFF control function (3) Touch panel coordinate position read function (4) Key switch input function (5) Infrared remote control transmission/reception function (6) Electronic volume (7) Serial EPROM read/write function These functions can be controlled through the UART chA from SH7760. Figure 6.1 Power Supply Control Block Diagram [Notes] Though the power supply controller's I/O port is connected to the /RTSA and /CTSA pins of the UART controller (ST16C2550) through the circuit, the power supply controller does not execute hardware control during communications with SH7760. For details of communications between SH7760 and the power supply controller, refer to 6.2 “Serial Communications between SH7760 and the Power Supply Controller.” H8/3048F-ONE SH7727 ST16C2550CQ48 (UART) /CTSA /RTSA RXA TXA EXTAL P82(/IRQ2) P27 TXD0 RXD0 CK RV5C348A(RTC) ADS7843E (Touch panel) /IRQ1 P50 /INT CE S I SO CLK LCD DIN DOUT DCLK /PENIRQ /CS LCD board /IRQ0(P80) P51 Cursor switch• iSW1• j Push-button switch (SW2,3) P22 P21 P20 P14 P13 P12 P11 P10 P A 4 Power-on switch NMI switch Reset switch /IRQ3(P83) PA2 P A 1 P30• ` P37 P66 8 8-bit LED Power supply (battery monitoring) VOUT2 VOUT1 ADP_IN VOLT AMP SIGN H8_SW2 H8_SW1 P17 P16 PA6 AN0 AN1 PA5 P25 P24 BUS P62 PINT11 P61 NMI P44 P45 P46 LTC1555LEGN M0 M1 M2 eTRON socket P60 Reset circuit /RESET P40 P41 P42 P43 1.8V ON/OFF (Vcc) -SH7727 CPU core - SH7290 CPU core 3.3V ON/OFF (VCC3A) -SH7727 -SDRAM(SH7727) -FLASH(SH7727) 3.3V ON/OFF (VCC3B) -UART -PCMCIA -USB HUB -Sound generatorIC -SIM card Reset signal for devices other thanH8/3048F 5V ON/OFF (5V) -USB power supply -Sound generator amplifier -ATA card power supply H8 reset circuit /RESET PB6 29391AFJA(EEPROM) CS D0 D1 /SK P52 P53 TXD1 RXD1 SCK1 TIOCA3(PB0) TIOCA4(PB2) TIOCB2(PA7) /IRQ4(P94) LCD board L E D Infrared remote control Transmission Receiving unit /CS SCLK DIN MAX5413ECD (electronic volume) DIPSW5-8

This section describes how serial communications take place between SH7760 and the power supply controller. 6.2.1 Serial Format This subsection describes a format for serial communications between SH7760 and the power supply controller. (1) Mode: Start-stop (2) Baud rate: 38400 bits/second (3) Stop bit: 1 bit (4) Start bit: 1 bit (5) Parity bit: None (6) LSB first

This subsection describes a procedure for reading the power supply controller registers. (1) SH7760 issues a read command to a power supply controller. (2) The power supply controller returns a response to SH7760. [Note] (1) Don’t issue multiple commands continually from SH7760. Note that the next command must be issued after a response to the preceding command has been returned from the power supply controller. 6.2.3 Read Command Figure 6.2 shows a read command format. SH7760 sends a start code, a function code and a register address, in this order, as a read command. (1) Start code (1 byte) (2) Function code (1 byte or 2 byte) (3) Register address (2byte) Figure 6.2 Read Command (1) Start code The code is fixed at 0x20. (2) Function code • A 1-byte function code specifies the size of data to be read in the lower 4 bits when the upper 4 bits of a function code are 1000. Figure 6.3 shows a function command where the upper 4 bits are 1000. D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 Size of data Figure 6.3 Function Command (1 Byte) • A 2-byte function code specifies the size of data to be read in the lower 12 bits when the upper 4 bits of a function code are 1001. Figure 6.4 shows a function command where the upper 4 bits are 1001. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 Size of data Figure 6.4 Function Command (2 Byte) (3) Register Address The register address specifies the address of the register to be read

Figure 6.5 shows the response format for the read command. The power supply controller returns an ACK code, a function code, a register address and target data, in this order, as a response. (1) ACK code (1 byte) (2) Function code (1 byte or2 byte) (3) Register address (2 byte) (4) Data (N byte) Figure 6.5 Normal Response during a Read Operation (1) ACK code This code is fixed at ACK (0x06). (2) Function code The same function code as for the read command returns. (3) Register address The address of a register subject to a read operation returns. (4) Data Read data returns. The size of this data is equal to the value specified in the function code. 6.2.5 Error Response during a read Operation Figure 6.6 shows the error response format for the read command. The power supply controller returns a NAK code and an error code in this order as a response at error occurrence. (1) NAK code (1 byte) (2) rror code (1 byte) Figure 6.6 Error Response during a Read Operation (1) NAK code This code is fixed at NAK (0x15). (2) Error code Table 6.1 summarizes the error codes. Table 6.1 Error Codes Error No Error type 0x01 Communications error 0x02 Invalid function code 0x03 Invalid register number 0x04 Register size error 0x05 Data size error

This subsection describes the procedure for writing to a controller control of the power supply controller from SH7760. (1) SH7760 issues a write command to the power supply controller. (2) The power supply controller returns a response the SH7760. [Note] (1) Don’t issue multiple commands continually from SH7760. Note that the next command must be issued after a response to the preceding command has been returned from the power supply controller. 6.2.7 Write Command Figure 6.7 shows the write command format. SH7760 sends a start code, a function code, a register address and data, in this order, as a write command. (1) Start code (1 byte) (2) Function code (1 byte or 2 byte) (3) Register address (2byte) (4) Data (N byte) Figure 6.7 Read Command (1) Start code This code is fixed at 0x20. (2) Function code • A 1-byte function code specifies the size of data to be written in the lower 4 bits when the upper 4 bits of a function code are 1100. Figure 6.3 shows a function command where the upper 4 bits are 1100. D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 Size of data Figure 6.8 Function Command (1 Byte) • A 2-byte function code specifies the size of data to be written in the lower 12 bits when the upper 4 bits of a function code are 1101. Figure 6.9 shows a function command where the upper 4 bits are 1101. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 Size of data Figure 6.9 Function Command (2 Byte) (3) Register Address The register address specifies the address of the register to be written. (4) Data This field specifies the size of data to be written. This data size is equal to that specified in the function code.

Figure 6.10 shows the response format for the write command. The power supply controller returns an ACK code, a function code, a register address and target data, in this order, as a response for the write command. (1) ACK code (1 byte) (2) Function code (1 byte or 2 byte) (3) Register address (2 byte) (4) Data (N byte) Figure 6.10 Normal Response during a Write Operation (1) ACK code This code is fixed at ACK (0x06). (2) Function code The same code as for the write command returns. (3) Register address The address of a register subject to a write operation returns. (4) Data Write data returns. The size of this data is equal to the value specified in the function code. However, note that no data returns for IRRSFDR subject to infrared remote control and EEPDR subject to serial EEPROM control.

Figure 6.11 shows an error response format for the write command at error occurrence. The power supply controller returns a NAK code and an error code in this order as an error response. (1) NAK code (1 byte) (2) Error No. (1 byte) Figure 6.11 Error Response during a Write Operation (1) NAK code This code is fixed at NAK (0x15). (2) Error code Table 6.2 summarizes the error codes. Table 6.2 Error Codes Error No Error type 0x01 Communication error 0x02 Invalid function code 0x03 Invalid register number 0x04 Register size error 0x05 Data size error

This section describes the RTC functions. Table 6.1 summarizes the RTC registers. For detailed description of each register, refer to 6.3.1 to 6.3.17. (1) Function for counting the seconds, minutes, hour, day of the week, month and year (BCD code) (2) RTC start/stop function (3) Alarm interrupt function (4) 1sec/0.5sec cyclic interrupt function (5) Automatic correction function for leap years (6) Effective range of operation from January 1, 2000 to December 31, 2099 Table 6.3 RTC Registers Register Abbreviation Address R/W Size Remarks RTC control register RTCCR 0x0000 R/W 1 byte RTC status register RTCSR 0x0001 R/W 1 byte Second counter SECCNT 0x0002 R/W 1 byte Minute counter MINCNT 0x0003 R/W 1 byte Hour counter HRCNT 0x0004 R/W 1 byte Day-of-the-week counter WKCNT 0x0005 R/W 1 byte Day counter DAYCNT 0x0006 R/W 1 byte Month counter MONCNT 0x0007 R/W 1 byte Year counter YRCNT 0x0008 R/W 1 byte Second alarm counter SECAR 0x0009 R/W 1 byte Minute alarm counter MINAR 0x000A R/W 1 byte Hour alarm counter HRAR 0x000B R/W 1 byte Day-of-the-week alarm counter WKAR 0x000C R/W 1 byte Day alarm counter DAYAR 0x000D R/W 1 byte Month alarm counter MONAR 0x000E R/W 1 byte RTC/Touch panel/Key input/Power supply status register RTKISR 0x0090 R/W 1 byte

Address: 0x000, Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 CNTS SECCAF 0.5secI 1secI ARI START R R R/W R/W R/W R/W R/W R/W (1) START START bit Setting 0 RTC start (Initial value) 1 RTC stop [Note] Don’t write to any counter while the START bit is set to “0.” Rewrite each counter after setting the START bit to “1.” (2) ARI ARI bit Setting 0 No alarm interrupt is generated. (Initial value) 1 An interrupt is generated at intervals of 1 second. (3) 1secI 1secI bit Setting 0 No interrupt is generated at intervals of 1 second. (Initial value) 1 An interrupt is generated at intervals of 1 second. (4) 0.5secI 0.5secI bit Setting 0 No interrupt is generated at intervals of 0.5 second. (Initial value) 1 An interrupt is generated at intervals of 0.5 second. (5) SECCAF SECCAF bit Setting 0 No carry has been generated in the second counter (SECCNT). 1 A carry has been generated in the second counter (SECCNT). [Zero-clear condition] The counter is cleared with zeros when the SECCAF bit is set to “1.”

1 The setting (value) of each counter is updated. [Zero-clear condition] The counter is cleared with zeros when counter update is complete. This clear operation is automatically performed. [Note] Don’t write to any counter while the START bit is set to “0.” Set the CNTS bit to “1” after updating the value of each counter with the START bit set to “1.”

Address: 0x001, Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0.5secF 1secF ARF 0 R R R R R/W R/W R/W R (1) ARF ARF bit Setting 0 The setting of each alarm register with the AR bit set is not the same as that of each counter register. (Initial value) 1 The setting of each alarm register with the AR bit set is identical to that of each counter register. At this time, an interrupt occurs if the ARI bit is set to “1.” [Clear condition] This counter is cleared when “0” is written with the ARF bit set to “1.” (2) 1secF 1secF bit Setting 0 A second has not elapsed yet. (Initial value) 1 A second has elapsed. [Clear condition] This counter is cleared when “0” is written with the 1secF bit set to “1. ” (3) 0.5secF 0.5secF bit Setting 0 A half second has not elapsed yet. (Initial value) 1 A half second has elapsed. [Clear condition] This counter is cleared with zeros when “0” is written with the 0.5secF bit set to “1.”

Address: 0x002, Initial value: 0xXX (Not defined) D7 D6 D5 D4 D3 D2 D1 D0 0 10 seconds 1 second R R/W R/W R/W R/W R/W R/W R/W The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 00 to 59. When the value changes from 59 to 00, a carry is generated in the minute counter. 6.3.4 Minute Counter (MINCNT) Address: 0z0003 Initial value: 0xXX (Not defined) D7 D6 D5 D4 D3 D2 D1 D0 0 10 minutes 1 minute R R/W R/W R/W R/W R/W R/W R/W The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 00 to 59. When the value changes from 59 to 00, a carry is generated in the hour counter. 6.3.5 Hour Counter (HRCNT) Address: 0x0004, Initial value: 0xXX (Not defined) D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 hours 1 hour R R R/W R/W R/W R/W R/W R/W The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 00 to 59. When the value changes from 59 to 00, a carry is generated in the day counter and the day-of-the-week counter.

Address: 0x0005 Initial Value: 0xXX (Not defined) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Septinary increnental counter R R R R R R/W R/W R/W Counting takes place within a range from 0x00 to 0x06. • The following shows the correspondence between the day of the week and the value of the septinary incremental counter. (D2.D1.D0) = (0.0.0) ------ Sunday (D2.D1.D0) = (0.0.1) ------ Monday (D2.D1.D0) = (0.1.0) ------ Tuesday (D2.D1.D0) = (0.1.1) ------ Wednesdady (D2.D1.D0) = (1.0.0) ------ Thursday (D2.D1.D0) = (1.0.1) ------ Friday (D2.D1.D0) = (1.1.0) ------ Saturday 6.3.7 Day Counter (DAYCNT) Address: 0x0006 Initial value: 0xXX (Not defined) D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 days 1 day R R R/W R/W R/W R/W R/W R/W The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 1 to 31 (January, March, July, August, October and December), 1 to 30 (April, June, September and November), 1 to 28 (February in normal year) or 1 to 29 (February in leap year). 6.3.8 Month Counter (MONCNT) Address: 0x0007 Initial value: 0xXX (Not defined) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 October Janualy R R R R/W R/W R/W R/W R/W The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 1 to 12. When the counter value changes from 12 to 1, a carry is generated in the year counter.

Address: 0x0008 Initial value: 0xXX (Not defined) D7 D6 D5 D4 D3 D2 D1 D0 10 yars 1 year R/W R/W R/W R/W R/W R/W R/W R/W The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 0 to 99. In this range, 00, 04, ..., 92 and 96 are leap years.

If the AR bit (D7) of each alarm is set to “1,” counters will be compared with alarm registers. This comparison is performed only for alarm registers with the AR bit (D7) set to “1” and an alarm interrupt is generated only at correct correspondence. • Correspondence between the alarm registers and counters Second alarm register (BCD code): second counter Minute alarm register (BCD code): minute counter Hour alarm register (BCD code): Hour counter Day-of-the-week alarm register (0x00 to 0x07): Day-of-the-week counter Day alarm register (BCD code): Day counter Month alarm register (BCD code): Month counter 6.3.11 Second Alarm Register (SECAR) Address: 0x0009 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 10 seconds 1 second R/W R/W R/W R/W R/W R/W R/W R/W The alarm value must be a BCD (Binary Coded Decimal) code between 00 and 59. 6.3.12 Minute Alarm Register (MINAR) Address: 0x000A Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 10 minutes 1 minute R/W R/W R/W R/W R/W R/W R/W R/W The alarm value must be a BCD (Binary Coded Decimal) code between 00 and 59.

Address: 0x000B Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 0 10 hours 1 hour R/W R R/W R/W R/W R/W R/W R/W The alarm value must be a BCD (Binary Coded Decimal) code between 00 and 23. 6.3.14 Day-of-the-Week Alarm Register (WKAR) Address: 0x000C, Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 0 0 0 0 Septinary counter value R/W R R R R R/W R/W R/W The alarm value must be set within a range from 0x00 to 0x06. • Day of theweek and septinary counter value (D2.D1.D0) = (0.0.0) ------ Sunday (D2.D1.D0) = (0.0.1) ------ Monday (D2.D1.D0) = (0.1.0) ------ Tuesday (D2.D1.D0) = (0.1.1) ------ Wednesdady (D2.D1.D0) = (1.0.0) ------ Thursday (D2.D1.D0) = (1.0.1) ------ Friday (D2.D1.D0) = (1.1.0) ------ Saturday 6.3.15 Day Alarm Register (DAYAR) Address: 0x000D Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 0 10 days 1 day R/W R R/W R/W R/W R/W R/W R/W The alarm value must be a BCD (Binary Coded Decimal) code between 1 and 31 (January, March, May, July, August, October and December), between 1 and 30 (April, June, September and November), between 1 and 28 (February in normal year) or between 1 and 29 (February in leap year).

Address: 0x000E Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 AR 0 0 October January R/W R R R/W R/W R/W R/W R/W The alarm value must be a BCD (Binary Coded Decimal) code between 01 and 12. 6.3.17 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR) This status register indicates the RTC, touch panel or key input status. The following is a brief description of RTC-related status bits. Address: 0x0090 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 IRRIF POWERIF KEYIF TPIF RTCIF R R R R/W R/W R/W R/W R/W (1) RTCIF RTCIF bit Setting 0 The ARF, 1secF and 0.5secF bits of the RTC register are all set to “0.” (Initial value) 1 One of the ARF, 1secF ad 0.5secF bits of the RTC register is set to “1.” [Clear condition] This register is cleared when “0” is written with the RTCIF bit set to “1.”

This section describes the touch panel functions. In addition, Table 6.4 summarizes the touch panel registers. For details of each register, refer to 6.4.1 to 6.4.32. (1) The A/D conversion value of the X or Y position sensed by pen touch is output. (2) Pen touch ON/OFF interrupt function • Sampling takes place at intervals of 20msec to 100msec. When the results (A/D conversion value of the X or Y position) obtained three times from sampling are approximate to each other, a pen touch ON interrupt is generated for SH7760. In addition, when the touch panel is turned off, a pen touch OFF interrupt is generated. (3) To keep the pen touch “ON,” sampling is performed at intervals of 20msec to 100msec and a pen touch ON interrupt is generated if the results obtained from sampling are approximate to each other. (4) Calibration function • Calibration is performed when two points on the touch panel are touched with the pen. • After completion of calibration, the X and Y positions are converted into the LCD drawing dot positions for output.

Register Abbreviation Address R/W Size Remarks Touch panel control register TPLCR 0x0020 R/W 1 byte Touch panel status register TPLSR 0x0021 R/W 1 byte Touch panel sampling control register TPLSCR 0x0022 R/W 1 byte X position A/D register XPAR 0x0024 R 2 byte Y position A/D register YPAR 0x0026 R 2 byte X position dot register XPDR 0x0028 R 2 byte Y position dot register YPDR 0x002A R 2 byte XA position dot register XAPDR 0x002C R/W 2 byte YA position dot register YAPDR 0x002E R/W 2 byte XB position dot register XBPDR 0x0030 R/W 2 byte YB position dot register YBPDR 0x0032 R/W 2 byte XC position dot register XCPDR 0x0034 R/W 2 byte YC position dot register YCPDR 0x0036 R/W 2 byte XA position A/D register XAPAR 0x0038 R/W 2 byte YA position A/D register YAPAR 0x003A R/W 2 byte XB position A/D register XBPAR 0x003C R/W 2 byte YB position A/D register YBPAR 0x003E R/W 2 byte XC position A/D register XCPAR 0x0040 R/W 2 byte YC position A/D register YCPAR 0x0042 R/W 2 byte DX dot register DXDR 0x0044 R/W 2 byte DY dot register DYDR 0x0046 R/W 2 byte X position dot calculation A/D value XPARDOT 0x0048 R/W 2 byte X position A/D value 1 XPARDOT1 0x004A R/W 2 byte X position A/D value 2 XPARDOT2 0x004C R/W 2 byte X position A/D value 3 XPARDOT3 0x004E R/W 2 byte X position A/D value 4 XPARDOT4 0x0050 R/W 2 byte Y position dot calculation A/D value YPARDOT 0x0052 R/W 2 byte Y position A/D value 1 YPARDOT1 0x0054 R/W 2 byte Y position A/D value 2 YPARDOT2 0x0056 R/W 2 byte Y position A/D value 3 YPARDOT3 0x0058 R/W 2 byte Y position A/D value 4 YPARDOT4 0x005A R/W 2 byte RTC/Touch Panel/Key Input/Power Supply Status Register RTKISR 0x0090 R/W 1 byte

Address: 0x0020 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 PEN_ONRE PEN_OFFI PEN_ONI TP_STR R R R R R/W R/W R/W R/W (1) TP_STR TP_STR bit Setting 0 The touch panel is disabled. (Initial value) 1 The touch panel is enabled. (2) PEN_ONI PEN_ONI bit Setting 0 A pen touch ON interrupt is not generated. (Initial value) 1 A pen touch ON interrupt is generated. (3) PEN_OFFI PEN_OFFI bit Setting 0 A pen touch OFF interrupt is not generated. (Initial value) 1 A pen touch OFF interrupt is generated. (4) PEN_ONRE PEN_ ONRE bit Setting 0 A pen touch ON interrupt is not generated when pen touch continues. (Initial value) 1 A pen touch ON interrupt is generated when pen touch continues.

Address: 0x0021 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 PEN_OFFIF PEN_ONIF 0 R R R R R R/W R/W R (1) PEN_ONIF PEN_ONIF bit Setting 0 The touch panel has not been pen-touched. (Initial value) 1 The touch panel has been pen-touched. The touched positions on the touch panel are output to the X position A/D register, Y position A/D register, X position dot register and Y position dot register. At this time, a pen touch ON interrupt is generated if the PEN_ONI bit is set to “1.” [Clear condition] This register is cleared when 0 is written with the PEN_ONIF bit set to “1.” (2) PEN_OFFIF PEN_OFFIF bit Setting 0 The touch panel has not been pen-touched (pen touch OFF). (Initial value) 1 At this time, a pen touch OFF interrupt is generated if the PEN_OFFI bit is set to “1.” [Clear condition] This register is cleared when 0 is written with the PEN_OFFIF bit set to “1.”

The touch panel sampling control register sets a sampling interval for the touch panel. Address: 0x0022 Initial value: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 160msec 140msec 120msec 100msec 80msec 60msec 40msec 20msec R/W R/W R/W R/W R/W R/W R/W R/W A sampling interval for the touch panel can be set within a range from 20msec to 160msec (unit: 20msec). When a bit is set to “1,” the corresponding sampling interval from 20msec to 160msec is set. Note that only the following values can be specified. • Correspondence between the setting values and sampling intervals 0x01: 20msec 0x02: 40msec 0x04: 60msec 0x08: 80msec 0x10: 100msec 0x20: 120msec 0x40: 140msec 0x80: 160msec

Address: 0x0024 Initial value: 0x000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 XA_D11 XA_D10 XA_D9 XA_D8 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 XA_D7 XA_D6 XA_D5 XA_D4 XA_D3 XA_D2 XA_D1 XA_D0 R R R R R R R R The X position A/D register indicates the A/D conversion result of a pen-touched X position on the touch panel. 6.4.5 Y Position A/D Register (YPAR) Address: 0x0026 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YA_D11 YA_D10 YA_D9 YA_D8 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 YA_D7 YA_D6 YA_D5 YA_D4 YA_D3 YA_D2 YA_D1 YA_D0 R R R R R R R R The Y position A/D register indicates the A/D conversion result of a pen-touched Y position on the touch panel.

Address: 0x0028 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 XD_D15 XD_D14 XD_D13 XD_D12 XD_D11 XD_D10 XD_D9 XD_D8 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 XD_D7 XD_D6 XD_D5 XD_D4 XD_D3 XD_D2 XD_D1 XD_D0 R R R R R R R R The X position dot register indicates the dot position of a pen-touched X position on the touch panel. Use the output value of this register after calibration. The output value is not settled without calibration. 6.4.7 Y Position Dot Register (YPDR) Address: 0x002A Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YD_D15 YD_D14 YD_D13 YD_D12 YD_D11 YD_D10 YD_D9 YD_D8 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 YD_D7 YD_D6 YD_D5 YD_D4 YD_D3 YD_D2 YD_D1 YD_D0 R R R R R R R R The Y position dot register indicates the dot position of a pen-touched Y position on the touch panel. Use the output value of this register after calibration. The output value is not settled without calibration.

Address: 0x002C Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 XAD_D15 XAD_D14 XAD_D13 XAD_D12 XAD_D11 XAD_D10 XAD_D9 XAD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XAD_D7 XAD_D6 XAD_D5 XAD_D4 XAD_D3 XAD_D2 XAD_D1 XAD_D0 R/W R/W R/W R/W R/W R/W R/W R/W The XA position dot register indicates the X dot position of point A when calibration takes place. 6.4.9 YA Position Dot Register (YAPDR) Address: 0x002E Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YAD_D15 YAD_D14 YAD_D13 YAD_D12 YAD_D11 YAD_D10 YAD_D9 YAD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YAD_D7 YAD_D6 YAD_D5 YAD_D4 YAD_D3 YAD_D2 YAD_D1 YAD_D0 R/W R/W R/W R/W R/W R/W R/W R/W The YA position dot register indicates the Y dot position of point A when calibration takes place.

Address: 0x0030 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 XBD_D15 XBD_D14 XBD_D13 XBD_D12 XBD_D11 XBD_D10 XBD_D9 XBD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XBD_D7 XBD_D6 XBD_D5 XBD_D4 XBD_D3 XBD_D2 XBD_D1 XBD_D0 R/W R/W R/W R/W R/W R/W R/W R/W The XB position dot register indicates the X dot position of point B when calibration takes place. 6.4.11 YB Position Dot Register (YBPDR) Address: 0x0032 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YBD_D15 YBD_D14 YBD_D13 YBD_D12 YBD_D11 YBD_D10 YBD_D9 YBD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YBD_D7 YBD_D6 YBD_D5 YBD_D4 YBD_D3 YBD_D2 YBD_D1 YBD_D0 R/W R/W R/W R/W R/W R/W R/W R/W The YB position dot register indicates the Y dot position of point B when calibration takes place.

Address: 0x0034 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 XCD_D15 XCD_D14 XCD_D13 XCD_D12 XCD_D11 XCD_D10 XCD_D9 XCD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XCD_D7 XCD_D6 XCD_D5 XCD_D4 XCD_D3 XCD_D2 XCD_D1 XCD_D0 R/W R/W R/W R/W R/W R/W R/W R/W The XC position dot register indicates the X dot position of point C when calibration takes place. This register will be functionally enhanced in future. Don’t access this register. 6.4.13 YC Position Dot Register (YCPDR) Address: 0x0036 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 YCD_D15 YCD_D14 YCD_D13 YCD_D12 YCD_D11 YCD_D10 YCD_D9 YCD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YCD_D7 YCD_D6 YCD_D5 YCD_D4 YCD_D3 YCD_D2 YCD_D1 YCD_D0 R/W R/W R/W R/W R/W R/W R/W R/W The YC position dot register indicates the Y dot position of point C where calibration takes place. This register will be functionally enhanced in future. Don’t access this register.

Address: 0x0038 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 XAA_D11 XAA_D10 XAA_D9 XAA_D8 R R R R R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XAA_D7 XAA_D6 XAA_D5 XAA_D4 XAA_D3 XAA_D2 XAA_D1 XAA_D0 R/W R/W R/W R/W R/W R/W R/W R/W The XA position A/D register indicates the X position A/D conversion result of point A subject to calibration/ 6.4.15 YA Position A/D Register (YAPAR) Address: 0x003A Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YAA_D11 YAA_D10 YAA_D9 YAA_D8 R R R R R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YAA_D7 YAA_D6 YAA_D5 YAA_D4 YAA_D3 YAA_D2 YAA_D1 YAA_D0 R/W R/W R/W R/W R/W R/W R/W R/W The YA position A/D register indicates the Y position A/D conversion result of point A subject to calibration

Address: 0x003C Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 XBA_D11 XBA_D10 XBA_D9 XBA_D8 R R R R R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XBA_D7 XBA_D6 XBA_D5 XBA_D4 XBA_D3 XBA_D2 XBA_D1 XBA_D0 R/W R/W R/W R/W R/W R/W R/W R/W The XB position A/D register indicates the X position A/D conversion result of point B subject to calibration. 6.4.17 YB Position A/D Register (YBPAR) Address: 0x003E Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YBA_D11 YBA_D10 YBA_D9 YBA_D8 R R R R R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YBA_D7 YBA_D6 YBA_D5 YBA_D4 YBA_D3 YBA_D2 YBA_D1 YBA_D0 R/W R/W R/W R/W R/W R/W R/W R/W The YB position A/D register indicates the Y position A/D conversion result of point B subject to calibration.

Address: 0x0040 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 XCA_D11 XCA_D10 XCA_D9 XCA_D8 R R R R R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XCA_D7 XCA_D6 XCA_D5 XCA_D4 XCA_D3 XCA_D2 XCA_D1 XCA_D0 R/W R/W R/W R/W R/W R/W R/W R/W The XC position A/D register indicates the X position A/D conversion result of point C subject to calibration. This register will be functionally enhanced in future. Don’t access this register. 6.4.19 YC Position A/D Register (YCPAR) Address: 0x0042 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 YCA_D11 YCA_D10 YCA_D9 YCA_D8 R R R R R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YCA_D7 YCA_D6 YCA_D5 YCA_D4 YCA_D3 YCA_D2 YCA_D1 YCA_D0 R/W R/W R/W R/W R/W R/W R/W R/W The YC position A/D register indicates the Y position A/D conversion result of point C subject to calibration. This register will be functionally enhanced in future. Don’t access this register

Address: 0x0044 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 DX1_D15 DX1_D14 DX1_D13 DX1_D12 DX1_D11 DX1_D10 DX1_D9 DX1_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 DX1_D7 DX1_D6 DX1_D5 DX1_D4 DX1_D3 DX1_D2 DX1_D1 DX1_D0 R/W R/W R/W R/W R/W R/W R/W R/W The DX dot register holds a value obtained by multiplying the number of dots per data (X position A/D conversion result at calibration) by 1,000. The power supply controller outputs a dot position of the X position to be stored in the X position dot register (XPDR) from the values set in the DX dot register (DXDR), XA position dot register (XAPDR) and XA position A/D register (XAPAR). When the DX dot register (DXDR) has been set to “0,” the dot position is not calculated. 6.4.21 DY Dot Register (DYDR) Address: 0x0046 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 DY1_D15 DY1_D14 DY1_D13 DY1_D12 DY1_D11 DY1_D10 DY1_D9 DY1_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 DY1_D7 DY1_D6 DY1_D5 DY1_D4 DY1_D3 DY1_D2 DY1_D1 DY1_D0 R/W R/W R/W R/W R/W R/W R/W R/W The DY dot register (DY1DR) holds a value obtained by multiplying the number of dots per data (Y position A/D conversion result at calibration) by 1,000. The power supply controller outputs a dot position of the Y position to be stored in the Y position dot register (YPDR) from the values set in the DY dot register (DYDR), YA position dot register (YAPDR) and YA position A/D register (YAPAR). When the DY dot register (DY1DR) has been set to “0,” the dot position is not calculated.

Address: 0X0048 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 XD_D9 XD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XD_D7 XD_D6 XD_D5 XD_D4 XD_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The X position dot calculation A/D value register (XPARDOT) holds an AD value of X position dot calculation. This A/D value is obtained by calculating the mean of the previous four XPARDOT values and clearing the low order 3 bits with zeros. 6.4.23 X Position Dot Calculation A/D Value 1 (XPARDOT1) Address: 0x004A Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 XD1_D9 XD1_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XD1_D7 XD1_D6 XD1_D5 XD1_D4 XD1_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The X position dot calculation A/D value 1 register (XPARDOT1) holds an XPARDOT value before sampling. 6.4.24 X Position Dot Calculation A/D Value 2 (XPARDOT2) Address: 0x004C Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 XD2_D9 XD2_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XD2_D7 XD2_D6 XD2_D5 XD2_D4 XD2_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The X position dot calculation A/D value 2 register (XPARDOT2) holds an XPARDOT value before sampling.

Address: 0x004E Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 XD3_D9 XD3_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XD3_D7 XD3_D6 XD3_D5 XD3_D4 XD3_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The X position dot calculation A/D value 3 register (XPARDOT3) holds an XPARDOT value before sampling. 6.4.26 X Position Dot Calculation A/D Value 4 (XPARDOT4) Address: 0x0050 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 XD4_D9 XD4_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 XD4_D7 XD4_D6 XD4_D5 XD4_D4 XD4_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The X position dot calculation A/D value 4 register (XPARDOT4) holds an XPARDOT value before sampling. 6.4.27 Y Position Dot Calculation A/D Value (YPARDOT) Address: 0x0052 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 YD_D9 YD_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YD_D7 YD_D6 YD_D5 YD_D4 YD_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The Y position dot calculation A/D value register (YPARDOT) holds an A/D value of Y position dot calculation. This A/D value is obtained by calculating the mean of the previous four YPARDOT values and clearing the following 3 bits with zeros.

Address: 0 x0054 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 YD1_D9 YD1_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YD1_D7 YD1_D6 YD1_D5 YD1_D4 YD1_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The Y position dot calculation A/D value 1 register (YPARDOT1) holds a YPARDOT value before sampling. 6.4.29 Y Position Dot Calculation A/D Value 2 (YPARDOT2) Address: 0x0056 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 YD2_D9 YD2_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YD2_D7 YD2_D6 YD2_D5 YD2_D4 YD2_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The Y position dot calculation A/D value 2 register (YPARDOT2) holds a YPARDOT value before sampling 6.4.30 Y Position Dot Calculation A/D Value 3 (YPARDOT3) Address: 0x0058 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 YD3_D9 YD3_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YD3_D7 YD3_D6 YD3_D5 YD3_D4 YD3_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The Y position dot calculation A/D value 3 register (YPARDOT3) holds a YPARDOT value before sampling.

Address: 0x005A Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 YD4_D9 YD4_D8 R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 YD4_D7 YD4_D6 YD4_D5 YD4_D4 YD4_D3 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The Y position dot calculation A/D value 4 register (YPARDOT4) holds a YPARDOT value before sampling. 6.4.32 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR) This status register indicates the RTC, touch panel, or key input status. Below is a brief description of the status bits related to the touch panel. Address: 0x0090 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 IRRIF POWERIF KEYIF TPIF RTCIF R R R R/W R/W R/W R/W R/W (1) TPIF TPIF bit Setting 0 The PEN_ONIF, PEN_OFFIF, CAIF and CAEF bits of the touch panel status registered are all set to “0.” (Initial value) 1 One of the PEN_ONIF, PEN_OFFIF, CAIF and CAEF bits of the touch panel status register is set to “1.” [Clear condition] This bit is cleared when “0” is written with the TPIF bit set to “1.”

The power supply controller supports 2-point touch panel calibration. Figure 6.11shows the points of the drawing coordinates and A/D conversion coordinates that are necessary for calibration. Figure 6.11 Points of the Drawing Coordinates and A/D Conversion Coordinates T-Engine Board LCD Point A Point B Origin of A/D convertion coordinates A/D conversion coordinates: x axis Origin of drawing coordinates Drawing coordinates: x axis Drawing coordinates: y axis SW1 SW2 SW3 A/D conversion coordinates: x axis

(2) When point A is pen-touched, it is signaled by a pen touch interrupt. The A/D conversion result of the pen-touched point A is written to the registers XAPAR and YAPAR. (3) Next, when point B is pen-touched, it is signaled by a pen touch interrupt. The A/D conversion result of the pen- touched point B is written to the registers XBPAR and YBPAR. (4) Calibration takes place according to data in the above steps (1) to (3). Using the following expression, the SH7760 calculates the number of dots per data of the X position A/D conversion result and that of the Y position A/D conversion result. Number of dots per data of the X position A/D conversion result (DX) DX = (DXA – DXB) / (TXB – TXA) Where TXA < TXB, DXA > DXB Number of dots per data of the Y position A/D conversion result (DY) DY = (DYA – DYB) / (TYB- TYA) Where TYA < TYB, DYA > DYB DXA: X position drawing dot point of point A (XAPDR) DXB: X position drawing dot point of point B (XBPDR) TXA: X position A/D conversion result of point A (XAPAR) TXB: X position A/D conversion result of point B (XBPAR) DYA: Y position drawing dot point of point A (YAPDR) DYB: Y position drawing dot point of point B (YBPDR) TXA: Y position A/D conversion result of point A (YAPAR) TXB: Y position A/D conversion result of point B (YBPAR) (5) The above calculation results are multiplied by 1,000, their decimal places are rounded, and the resulting integers are written to the registers DXDR and DYDR. DX dot register (DXDR) = DX x 1,000 (rounding the decimal places) DY dot register (DYDR) = DY x 1,000 (rounding the decimal places) (6) The power supply controller uses data stored in the registers DXDR, DYDR, XAPDR, YAPDR, XAPAR, and YAPAR to calculate dot position data (XPDR, YPDR) of the pen-touched point on the LCD. The power supply controller uses the following expression to calculate dot position data. X position dot register (XPDR) XPDR = (DXA – (DX x (TXD – TXA)) / 1,000 Y position dot register (YPDR) YPDR = (DYA – (DY x (TYD – TYA)) / 1,000 DXA: XA position dot register (XAPDR) data DX: DX1 dot register (DXDR) data TXA: XA position A/D register (XAPAR) data TXD: X position A/D register (XPAR) data DYA: YA position dot register (YAPDR) data DY: DY dot register (DYDR) data TYA: YA position A/D register (YAPAR) data TYD: X position A/D register (YPAR) data The power supply controller outputs data stored in the X position A/D register (XPAR) and Y position A/D register (YPAR). When the values stored in the DX dot register (DXDR) and DY dot register (DYDR) are not 0, the power supply controller outputs the data derived from the above expressions to the X position dot register (XPDR) and Y position dot register (YPDR). When either value is 0, it does not use the above expression for calculation and outputs only XPAR and YPAR data.

Figure 6.12 shows the Solution Engine2 switches under control by the power supply controller. The power supply controller controls the switches SW1 to SW3 on the CPU board and the switches SW1to SW3 on the LCD board. Figure 6.12 Solution Engine 2 Switch Power-on switch SW1 Reset switch SW2 SW1 SW2 Solution Engine 2 LCD NMI switch SW3 SW2 CPU board switch SW1 SW2 SW3 Application switch

(1) Power-on switch (SW1) • When the SH7760 is being powered, a power-on switch interrupt occurs for the SH7760 if the power-on switch is pressed and held for 2 seconds or more. • When Solution Engine2 is OFF, it is turned ON if the power-on switch is pressed and held for 0.5 seconds or more. • When Solution Engine2 is ON, it is turned OFF if the power-on switch is pressed and held for 2 seconds or more. (2) Reset switch (SW2) Solution Engine2 is turned OFF when the reset switch is pressed. (3) NMI switch (SW3) An NMI interrupt occurs for the SH7760 when the NMI switch is pressed. 6.5.2 LCD Board Switch Control (Application Switch) (1) Cursor switch (SW1) and push-button switches (SW2 and SW3) on the LCD board • The cursor switch and push-button switches are subject to sampling at intervals of 10msec. When consecutive three samplings indicate that the same key is being pressed, key bit pattern data of the cursor switch and push-button switches are output. • If the switch is turned ON, a key ON interrupt occurs. If the switch is turned OFF, a key OFF interrupt occurs. • When the same switch is pressed and held, an auto repeat interrupt occurs at intervals of 100 to 450msec (unit: 50msec).

Table 6.5 summarizes the key switch registers. For details of each register, refer to 6.5.4 to 6.5.8. Table 6.5 Key Switch Registers Register Abbreviation Address R/W Size Remarks Key control register KEYCR 0x0060 R/W 1 byte Key auto repeat time register KATIMER 0x0061 R/W 1 byte Key input status register KEYSR 0x0062 R/W 1 byte Key bit pattern register KBITPR 0x0064 R/W 2 byte RTC/Touch panel/Key input/Power supply status register RTKISR 0x0090 R/W 1 byte

Address: 0x0060 Initial value: 0x20 D7 D6 D5 D4 D3 D2 D1 D0 0 0 NMIE PONSWI ARKEYI KEY_OFFI KEY_ONI KEY_STR R R R/W R/W R/W R/W R/W R/W (1) KEY_STR KEY_STR bit Setting 0 An application switch key input is disabled. (Initial value) 1 An application switch key input is enabled. (2) KEY_ONI KEY_ONI bit Setting 0 An application switch ON interrupt is disabled. (Initial value) 1 An application switch key ON interrupt is enabled. (3) KEY_OFFI KEY_OFFI bit Setting 0 An application switch OFF interrupt is disabled. (Initial value) 1 An application switch key OFF interrupt is enabled. (4) ARKEY ARKEY bit Setting 0 An application switch auto repeat interrupt is disabled. (Initial value) 1 An application switch auto repeat interrupt is enabled. (5) PONSWI PONSWI bit Setting 0 A power-on switch interrupt is disabled. (Initial value) 1 A power-on switch interrupt is enabled. (6) NMIE NMIE bit Setting 0 An NMI interrupt is disabled for the SH7760 even when the NMI switch is pressed. 1 An NMI interrupt is enabled for the SH7760 when the NMI switch is pressed. (Initial value)

Address: 0x0061 Initial value: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 450msec 400msec 350msec 300msec 250msec 200msec 150msec 100msec R/W R/W R/W R/W R/W R/W R/W R/W This register sets the auto repeat interrupt generation time. The auto repeat interrupt generation time is set at intervals of 100msec to 450msec (unit: 50msec). When one of the bits (100msec to 450msec) is set, the corresponding auto repeat interrupt generation time is set. 6.5.6 Key Bit Pattern Register (KBIPR) Address: 0x0064 Initial value: 0x0000 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 SW2 0 SW3 R R R R R R R R D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SW1-5 (Decided) SW1-4 (↓) SW1-3 (↑) SW1-2 (←) SW1-1 (→) R R R R R R R R This register stores the bit pattern of the application switch (SW1 to SW3) key input status. (1) SWn SWn bit Setting 0 Application switch key input: OFF (Initial value) 1 Application switch key input: ON

Address: 0x0062 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 PONSWF ARKEYF KEY_OFFF KEY_ONF 0 R R R R/W R/W R/W R/W R (1) KEY_ONF KEY_ON bit Setting 0 An application switch key has not been turned on. (Initial value) 1 An application switch key has been turned on. At this time, if the KEY_ONI bit is set to “1,” a key ON interrupt occurs. [Clear condition] This bit is reset when “0” is written with the KEY_ONF bit set to “1.” (2) KEY_OFFF KEY_OFFF bit Setting 0 An application switch key is ON or OFF. (Initial value) 1 An application switch key has changed from ON to OFF. (Initial value) At this time, if the KEY_OFFI bit is set to “1,” a key OFF interrupt occurs. [Clear condition] This bit is cleared when “0” is written with the KEY_OFFI bit set to “1.” (3) ARKEYF ARKEYF bit Setting 0 The same application switch key is not ON for the time specified in the key auto repeat time register. (Initial value) 1 The same application switch is ON for the time specified in the key auto repeat time register. At this time, if the ARKEYI bit is set to “1”,” repeat interrupt occurs. [Clear condition] This bit is cleared when “0” is written with the ARKEYF bit set to “1.”

1 The power-on switch has been turned on for 2 sec or more. At this time, if the PONSWI bit is set to “1,” a power-on interrupt occurs. [Clear condition] This bit is cleared when “0” is written to the PONSWF bit set to “1.” [Supplementary description on application switch key input] (1) When multiple keys are pressed at the same time, the corresponding bits are all set to “1,” and a KEY_ONF interrupt occurs so long as it is enabled. (2) If data in the key bit pattern register changes when multiple keys are pressed at the same time, a KEY_ONF interrupt occurs so long as it is enabled. - Example - This KEY_ONF interrupt occurs when the state with switches SW1 and SW2 pressed simultaneously changes to one with switches SW1 and SW3 pressed simultaneously. (3) When multiple keys are released in the state with the keys pressed and held, a KEY_OFFI interrupt occurs so long as it is enabled. (4) When multiple keys are released, the key states immediately before key release are retained in the key bit pattern register.

This status register indicates the RTC, touch panel, or key input status. Below is a brief description of the status bits for key input. Address: 0x0090 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 IRRIF POWERIF KEYIF TPIF RTCIF R R R R/W R/W R/W R/W R/W (1) KEYIF KEYIF bit Setting 0 The PONSWF, ARKEYF, KEY_OFFF, and KEY_ONF bits of the key input status register are all set to “0.” (Initial value) 1 One of the PONSWF, ARKEYF, KEY_OFFF, or KEY_ONF bits of the key input status register is set to “1.” [Clear condition] This bit is cleared when “0” is written with the KEYIF bit set to “1.”

This section describes the power supply control functions. Table 6.6 summarizes the power supply controller registers. In addition, refer to 6.6.1 to 6.6.3 for details of each register. (1) Solution Engine2 is turned ON or OFF. (2) When Solution Engine2 is OFF, it is turned ON if the power-on switch is pressed for 2sec or more. (3) Solution Engine2 can be turned OFF from the SH7760. (4) If the DIP switch (SW7) is se to ON, Solution Engine2 is also turned ON at the same time the power supply controller is turned ON. Table 6.6 Power Control Registers Register Abbreviation Address R/W Size Remarks System power control register 1 SPOWCR1 0x0070 R/W 1 byte System power control register 2 SPOWCR2 0x0071 R/W 1 byte

Address: 0x0070 Initial value: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 SPOWER R R R R R R R R/W (1) SPOWER SPOWER bit Setting 0 System power supply: OFF 1 System power supply: ON (Initial value) 6.6.2 System Power Control Register 2 (SPOWCR2) Address: 0x0071 Initial value: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 SFPOWER R R R R R R R R/W (2) SFPOWER SFPOWER Setting 0 Solution Engine2 is turned OFF by SH7760 control. 1 Solution Engine2 is turned OFF by pressing the power-on switch. (Initial value) 6.6.3 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR) This status register indicates the RTC, touch panel, or key input status. Below is a brief description of the status bits for power control. Address: 0x0090 Initial value: 0x00 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 IRRIF POWERIF KEYIF TPIF RTCIF R R R R/W R/W R/W R/W R/W (1) POWERIF This bit will be functionally enhanced in the future. Don’t access this register. When read, this bit is always 20.”

This section describes the LED control functions. Table 6.7 summarizes the LED controller registers. Though SH7760 Solution Engine2 has not been provided with LED1 to LED8, LED control is executed. (1) Controlling the ON/OFF State of LEDs (LED1 to LED8) on the CPU board Table 6.7 LED Controller Registers Register Abbreviation Address R/W Size Remarks LED register LEDR 0x00A0 R/W 1byte 6.7.1 LED Register (LEDR) Address: 0x00A0 Initial value: 0xXX D7 D6 D5 D4 D3 D2 D1 D0 LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 R/W R/W R/W R/W R/W R/W R/W R/W (1) LEDn LEDn bit Setting 0 LEDn is turned OFF. 1 LEDn is turned ON. LEDn is turned ON for the H8/3048F-ONE firmware version at the power-on sequence.

This section describes the LCD light control functions. In addition, Table 6.8 summarizes the front light control registers. (1) Controlling the ON/OFF state of the LCD front light Table 6.8 LCD Front Light Registers Register Abbreviation Address R/W Size Remarks LCD front light registers LCDR 0x00A1 R/W 1byte 6.8.1 LCD Front Light Register (LCDR) Address: 0x00A1 Initial value: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 FRONTL R R R R R R R R/W (1) FRONTL FRONTL bit Setting 0 The LCD front light is turned ON. 1 The LCD front light is turned OFF (Initial value)

This section describes the reset control functions. Table 6.9 summarizes the reset control registers. (1) Solution Engine2 reset is controlled. Table 6.9 Reset Registers Register Abbreviation Address R/W Size Remarks Reset control register RESTCR 0x00A2 R/W 1 byte 6.9.1 RESTCR Register (RESTCR) Address: 0x00A2 Initial value: 0x02 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 SWRES SORES R R R R R R R/W R/W (1) SORES SORES bit Setting 0 Solution Engine2 is not restarted by reset. (Initial value) 1 Solution Engine2 is restarted by reset. If this bit is set to “1,” Solution Engine2 is restarted. (2) SWRES SWRES bit Setting 0 Devices other than the power supply controller are reset with the reset switch (SW2). 1 All the devices covering the power supply controller are reset with the reset switch (SW2). (Initial value)