iC-Haus iC-TW29 Manual 

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 1/28 FEATURES  Any output resolution with any input resolution  Independently-programmed ABZ, UVW, and BiSS resolutions  Absolute data interface for external revolution counters  BiSS C-Mode interface (Encoder Profiles 3, 3S, and 4)  26-bit singleturn position and 32-bit revolution count via SPI  Four capture registers for coded reference marks and touch-probe applications  Eccentricity compensation  Input frequency up to 700 kHz  AB output frequency of up to 12.5 MHz  Differential RS422 line driver outputs for ABZ or UVW  Simultaneous single-ended outputs for ABZ, UVW, BiSS  Automatic compensation of amplitude, offset, and phase errors  Digital filtering for ultra-low output jitter  Encoder Link interface for in-field re-configuration  Internal EEPROM and oscillator  LED intensity control by PWM output  Low latency (2.4 µs or 5.0 µs)  Pin-compatible with iC-TW28 APPLICATIONS  Rotary and linear incremental or absolute encoders  Magnetic or optical sin/cos sensor interface  Brushless motor commutation (2...64 poles)  Imbedded motion control PACKAGES 32-pin QFN 5 mm x 5 mm x 0.9 mm RoHS compliant BLOCK DIAGRAM Interpolated Angle (IA) SPI Interface xSS SCK SO SI Interpolator ZERO Channel SIN+ SIN– COS+ COS– ZERO+ ZERO– 26-Bit Gearbox Includes Filter, Hysteresis, and Eccentricity Correction Zero Gating Window (ZW) ABZ with Output Freq. Limiter Normalized Angle (NR) Revolution Count (RC) UVW BiSS Slave with Encoder Profile and EDS UVW Scan Absolute Data Interface (ADI) Revolution Count (RC), Cycle Count (CC), and Sync Bits I/O Multiplexer A+ A– B+ B– Z+ Z– Auto Calibration, Auto Adaption, LED Control, Startup, ID, EEPROM xCALIB xIRQ LED Position Capture BiSS Control Data Encoder Link Monitors: Status/Fault, Temp., Sin/Cos Amplitude, Excessive Error, Excessive Adaption GPIO IA CC RC AVDD AVSS DVDD DVSS IOVDD IOVSS iC-TW29 Copyright © 2019, 2020 iC-Haus http://www.ichaus.com

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 2/28 DESCRIPTION The iC-TW29 is a system-on-chip for encoder appli- cations. The integration of a 14-bit interpolator with a 26-bit gearbox and a resolution-enhancing digital filter provides a complete solution for arbitrary resolution single and multiturn encoders. Independent I/O mod- ules with individually programmed resolutions provide BiSS C, standard encoder quadrature (ABZ), or com- mutation (UVW) outputs separately or in combination. The iC-TW29 accepts 20 mV to 2 V differential sin/- cos input signals directly from magnetic or optical sensors—no external signal conditioning is required in most applications. The differential zero input ac- cepts a wide range of digital and analog index gating sources such as Hall or MR sensor bridges. Auto- matic calibration and adaption (correction during op- eration) of sensor offset, sin/cos amplitude match, and phase quadrature provide and maintain minimum angular error and jitter. Additionally, automatic calibra- tion of gain, offset, and phase of the zero input allows for rapid commissioning. The gearbox tracks input cycles (up to 4096 per rev- olution) and provides output resolutions of up to 26 bits per revolution. Auto-calibrated eccentricity com- pensation increases achievable angular accuracy by correcting for off-center optical discs or magnetic pole- wheels. When combined with an external revolution counting device (such as the iC-PVL) communicating via its absolute data interface, the iC-TW29 provides a complete BiSS multiturn absolute encoder solution. The differential zero input can be used with a tra- ditional index sensor to generate an incremental Z output or to clear the gearbox counter in singleturn absolute applications. It can also be used as a po- sition capture input with a four-word FIFO to allow decoding distance-coded reference marks in hosted applications. In addition to industry-standard incremental ABZ quadrature output, the iC-TW29 also provides UVW commutation output modes for 1 to 32 pole-pair mo- tors as well as BiSS and SPI interfaces. The BiSS in- terface provides BiSS encoder profiles 3, 3S (safety), or 4 as well as optional electronic data sheet EDS SE functionality. BiSS passthrough mode allows a host processor to implement any BiSS encoder profile or EDS. Extensive status/fault and signal quality monitoring capabilities allow detection and notification of poor operating conditions. The iC-TW29 is configured via the bi-directional BiSS, SPI, or Encoder Link interfaces. Encoder link uses the incremental quadrature outputs to implement a SPI-like serial interface for field re-configuration or diagnostics. The iC-TW29 requires minimal external components for operation. An EEPROM for storage of configu- ration and calibration data, and RS422 line drivers for the ABZ or UVW outputs are already integrated on-chip. An external line driver/receiver is required for BiSS applications. An integrated power-on reset cir- cuit can be overridden by an external hardware reset signal if necessary. General notice on application-specific programming Parameters defined in the datasheet represent supplier’s attentive tests and validations, but - by principle - do not imply any warranty or guarantee as to their accuracy, completeness or correctness under all application conditions. In particular, setup conditions, register settings and power-up have to be thoroughly validated by the user within his specific application environment and requirements (system responsibility). For magnetic sensor systems: The chip’s performance in application is impacted by system conditions like the quality of the magnetic target, field strength and stray fields, temperature and mechanical stress, sensor alignment and initial calibration. For optical sensor systems: The chip’s performance in application is impacted by system conditions like the quality of the optical target, the illumination, temperature and mechanical stress, sensor alignment and initial calibration.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 3/28 CONTENTS PACKAGING INFORMATION 4 PIN CONFIGURATION QFN32-5x5 . . . . . 4 PACKAGE DIMENSIONS . . . . . . . . . . . 5 PIN FUNCTIONS . . . . . . . . . . . . . . . 6 ABSOLUTE MAXIMUM RATINGS 8 THERMAL DATA 8 ELECTRICAL CHARACTERISTICS 9 OPERATING REQUIREMENTS 13 SPI Interface . . . . . . . . . . . . . . . . . . 13 Encoder Link Interface . . . . . . . . . . . . 14 BiSS Interface . . . . . . . . . . . . . . . . . 15 ADI Interface . . . . . . . . . . . . . . . . . . 16 FUNCTIONAL BLOCK DIAGRAM 17 ELECTRICAL CONNECTIONS 20 Power and Ground . . . . . . . . . . . . . . . 22 Reference Outputs . . . . . . . . . . . . . . . 22 xCALIB Input . . . . . . . . . . . . . . . . . . 22 SIN and COS Inputs . . . . . . . . . . . . . . 22 ZERO Inputs . . . . . . . . . . . . . . . . . . 23 ABZ Outputs . . . . . . . . . . . . . . . . . . 24 UVW Outputs . . . . . . . . . . . . . . . . . . 24 xRST Input . . . . . . . . . . . . . . . . . . . 24 xIRQ . . . . . . . . . . . . . . . . . . . . . . . 24 LED Output . . . . . . . . . . . . . . . . . . . 24 BiSSEN Input . . . . . . . . . . . . . . . . . . 24 General-Purpose I/O . . . . . . . . . . . . . . 24 SPI Port . . . . . . . . . . . . . . . . . . . . . 25 Reserved Pins . . . . . . . . . . . . . . . . . 25 CONFIGURATION AND CALIBRATION 26 Introduction . . . . . . . . . . . . . . . . . . . 26 Default Configuration . . . . . . . . . . . . . 26 Input Configuration and Calibration . . . . . . 26 ABZ/UVW Configuration . . . . . . . . . . . . 26 BiSS/SSI Configuration . . . . . . . . . . . . 27

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 4/28 PACKAGING INFORMATION (Compatible with iC-TW28) PIN CONFIGURATION QFN32-5x5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN FUNCTIONS No. Name Function 1 SIN+3 + Differential Sine Input 2 SIN–3 – Differential Sine Input 3 AVDD +3.3 V Analog Power Supply Input 4 COS+3 + Differential Cosine Input 5 COS–3 – Differential Cosine Input 6 AVSS Analog Ground 7 ZERO+4 + Differential Zero (Index) Input 8 ZERO–4 – Differential Zero (Index) Input 9 VREF ADC Reference Voltage Output 10 VC Bias Output (VDD/2) 11 Reserved1 Must be connected to ground 12 Reserved1 Must be connected to ground 13 GPIO3 General Purpose I/O 14 xRST4 Reset Input (low active) 15 xCALIB4 Auto-Calibration Input (low active) 16 xIRQ4 Interrupt Request (active-low) Input/Output or Fault Output 17 Z– – Differential RS422 Z Output or Multifunction I/O 18 Z+ + Differential RS422 Z Output or Multifunction I/O 19 IOVSS I/O Ground 20 B– – Differential RS422 B Output or Multifunction I/O 21 B+ + Differential RS422 B Output or Multifunction Output 22 IOVDD +3.3 V I/O Power Supply Input 23 A– – Differential RS422 A Output or Multifunction I/O 24 A+ + Differential RS422 A Output or Multifunction I/O 25 DVDD +3.3 V Digital Power Supply Input 26 LED4 LED Intensity Control Output or General-Purpose I/O 27 DVSS Digital Ground 28 SO SPI Slave Output (Master Input) 29 SI3 SPI Slave Input (Master Output) 30 SCLK3 SPI Clock Input 31 xSS4 SPI Slave Select Input 32 BISSEN5 BiSS Interface Enable TP2 Backside paddle IC top marking: = product code, = assembly code (subject to changes), = date code (subject to changes); 1 Must be connected to ground. 2 Must be connected to a ground plane at AVSS potential. Can also be used to connect DVSS. 3 Do not allow to float. Connect to ground via 10 kΩresistor if not used. 4 Do not allow to float. Connect to 3.3 V or ground via 10 kΩresistor if not in use. Alternatively, program MAIN_CFG.zero = 1 for internal biasing. 5 Connect to 3.3 V (to DVDD for to enable BiSS interface) or ground (to DVSS to disable BiSS interface). Do not allow to float.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 5/28 PACKAGE DIMENSIONS 5 5 TOP 0.40 3.65 3.65 0.22 0.50 BOTTOM 0.90 ±0.10 SIDE R0.15 3.60 4.90 3.60 4.90 0.30 0.50 0.70 RECOMMENDED PCB-FOOTPRINT drb_qfn32-5x5-6_pack_1, 10:1 All dimensions given in mm. Tolerances of form and position according to JEDEC MO-220.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 6/28 PIN FUNCTIONS No. Name I/O Function Description 1 SIN+ Analog in Sine Input + Differential sine signal input. For single ended sensors SIN– must be biased to an appropriate DC level. 2 SIN– Analog in Sine Input – 3 AVDD Supply Analog Power Supply +3.1 V to +3.6 V supply voltage input for analog circuitry. AVDD should be tied together with DVDD and IOVDD and supplied from a clean source. 4 COS+ Analog in Cosine Input + Differential cosine signal input. For single ended sensors COS– must be biased to an appropriate DC level. 5 COS– Analog in Cosine Input – 6 AVSS Ground Analog Ground AVSS must be tied to high quality ground, usually a solid PCB plane. 7 ZERO+ Analog in Zero Input + Differential Zero Gating Input. If single ended signal sources are used, the unused terminal (either ZERO+ or ZERO–) must be tied to an appropriate DC bias. 8 ZERO– Analog in Zero Input – 9 VREF Analog out Bias Output Decouple with 100 nF capacitor to AVSS. Do not inject noise into this pin as it directly impacts ADC conversion quality. 10 VC Analog out Bias Output Decouple with 100 nF capacitor to AVSS. Do not inject noise into this pin as it directly impacts ADC conversion quality. 11 Reserved Digital in Test Input Reserved pins; must be connected to DVSS for normal operation. 12 Reserved Digital in Test Input 13 GPIO Digital in/out General-Purpose I/O Connect to AVSS if not used. 14 xRST Digital in, active low Reset Input The device is held in reset (low power mode) as long as xRST is low. 15 xCALIB Digital in, active low Calibration Control Device enters calibration mode on falling edge of CALIB. This pin must be tied high if not used. 16 xIRQ Digital out, active low or input IRQ or Fault Output or IRQ input Interrupt request output to external micro controller or interrupt re- quest input. Output can also be used to directly drive a fault LED in stand-alone applications. Can be configured as push-pull or open-drain. 17 Z– Digital/RS422 out Z– or W– Output In ABZ output modes these are the differential Z outputs. In UVW output modes these are the W outputs. In BiSS mode (BISSEN pin high), pin Z+ is the data input SLI. If daisy chaining is not required, Z+ can be grounded (IOVSS). In other modes, these are multifunction I/O. 18 Z+ Digital/RS422 out Z+ or W+ Output 19 IOVSS Ground I/O Ground All ground pins must be connected to a high quality ground, usually a solid PCB plane. 20 B– Digital/RS422 out B– or V– Output In ABZ output modes these are the differential B outputs. In UVW output modes these are the V outputs. In BiSS mode (BISSEN pin high), pin B+ is the data output SLO. In other modes, these are multifunction I/O. In Z test mode these show the Z gating window. 21 B+ Digital/RS422 out B+ or V+ Output 22 IOVDD Supply Output Drivers Power Supply +3.1 V to +3.6 V voltage terminal supplying all pin output drivers includ- ing the RS422 drivers and LED current. IOVDD and DVDD must be the same voltage level. IOVDD can require up to 100mA depending on loads. It is usually sufficient to tie IOVDD to the same supply as AVDD and DVDD. 23 A– Digital/RS422 out A– or U– Output In ABZ output modes these are the differential Z outputs. In UVW output modes these are the W outputs. In BiSS mode (BISSEN pin high), pin A+ is the clock input MA. In other modes, these are multifunction I/O. In Z test mode these show the un-gated Z signal once per input period. With Encoder Link active, A+ is the ELCLK input and A– is ELIN input or ELOUT output. 24 A+ Digital/RS422 out A+ or U+ Output 25 DVDD Supply Digital Power Supply +3.1 V to +3.6 V supply voltage terminal for digital circuits. DVDD should be tied together with AVDD and IOVDD to a high quality supply. 26 LED Digital input or output LED PWM Output Used to supply the illumination LED of optical sensors to maintain constant intensity and constant Sin/Cos sensor amplitude. Can be configured as push-pull or open-drain. If not required for LED control, it is a general purpose I/O. 27 DVSS Ground Digital Ground Pin must tied to high quality ground, usually a solid PCB plane. 28 SO Digital out SPI Slave Output Connect to SPI master MI pin.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 7/28 PIN FUNCTIONS No. Name I/O Function Description 29 SI Digital in SPI Slave Input Connect to SPI master MO pin. 30 SCLK Digital in SPI Slave Clock Input Connect to SPI master clock output pin. 31 xSS Digital in SPI Slave Select Input Connects to SPI master slave select output pin. 32 BISSEN Digital in BiSS Interface Enable Connect to DVDD to enable the BiSS/SSI interface. The I/O pins A+, B+, Z+ are used for MA, SLO, SLI.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 8/28 ABSOLUTE MAXIMUM RATINGS These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these values damage may occur. Item Symbol Parameter Conditions Unit No. Min. Max. G001 VDD Voltage at DVDD, AVDD, and IOVDD Referenced to DVSS, AVSS, and IOVSS respectively –0.3 4.1 V G002 Vpin Pin Voltage at any pin Referenced to DVSS, AVSS, and IOVSS –0.3 AVDD + 0.3 V G003 Ipin Input Current into any pin –2 2 mA G004 Vesd1 ESD Susceptibility HBM, 100 pF discharged through 1.5 kΩ 4 kV G005 Tj Junction Temperature –40 150 °C THERMAL DATA Item Symbol Parameter Conditions Unit No. Min. Typ. Max. T01 Ta Operating Ambient Temperature Range –40 125 °C T02 Rthja Thermal Resistance Chip to Ambient QFN32-5x5 surface mounted to PCB according to JEDEC 51 40 K/W T03 Ts Storage Temperature –40 150 °C All voltages are referenced to pin AVSS unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 9/28 ELECTRICAL CHARACTERISTICS Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated Item Symbol Parameter Conditions Unit No. Min. Typ. Max. Total Device 001 VDD Permissible Supply Voltage AVDD, DVDD, IOVDD 3.1 3.6 V 002 IAVDD Supply Current into AVDD AVDD, DVDD, IOVDD = 3.3 V, fin = 1 kHz, inter = x256, ABZ and UVW outputs active 15 mA 003 IDVDD Supply Current into DVDD AVDD, DVDD, IOVDD = 3.3 V, fin = 1 kHz, inter = x256, ABZ and UVW outputs active 25 mA 004 IIOVDD Supply Current into IOVDD RS422 drivers enabled (MAIN_CFG.rs422 = 1); quadrature outputs terminated with 120 Ω 85 mA quadrature outputs open 2 mA 005 IRST Reset Current (IAVDD + IDVDD + IIAVDD) xRST low 1 µA Signal Inputs and Amplifiers: SIN+, SIN–, COS+, COS– 101 Vin() Permissible Input Voltage Refer to Figure 1 Low Input Range (MAIN_CFG.input = 0 or 1) 0.35 AVDD – 1.1 V High Input Range (MAIN_CFG.input = 3) 1.0 AVDD V For High Input Range and MAIN_CFG.input = 2 refer to Figure 1. 102 Ain()diff Permissible Differential Input Amplitude, Max(SIN+ – SIN–) or Max(COS+ – COS–) Refer to Figure 2 Low Input Range (MAIN_CFG.input = 0 or 1) 20 700 mVpp High Input Range (MAIN_CFG.input = 2 or 3) 65 2000 mVpp 103 Vcm() Permissible Input Common Mode Range, (SIN+ + SIN–)/2 or (COS+ + COS–)/2 Refer to Figure 3 Minimum gain (MAIN_CFG.input =/ 3) 0.7 AVDD – 1.45 V Maximum gain (MAIN_CFG.input =/ 3) 0.35 AVDD – 1.1 V Minimum gain (MAIN_CFG.input = 3) 2.0 AVDD V Maximum gain (MAIN_CFG.input = 3) 1.0 AVDD V 104 fin() Sin/Cos Input Frequency 700 kHz 105 Vos() Amplifier Input Offset Voltage ±15 mV 106 Ilk() Input Leakage Current ±50 nA 108 OFFcorr Correctable Input Offset Voltage As percentage of input signal amplitude; input offset voltage is the sum of sensor offset plus amplifier offset (item 105); ±25 % (step size: 3.9 mV / gain) 109 Acorr Correctable Balance (Amplitude) Mismatch Max(Asin, Acos) / Min(Asin, Acos), where Asin and Acos are the SIN/COS input amplitudes respectively. (step size 0.02%) ±25 % 110 PHIcorr Correctable Phase Error (step size 0.015°) ±26 ° 111 Rin()diff Differential Input Resistance Low Input Range (MAIN_CFG.input = 0) 10 1000 MΩ Low with Loss Detect. (MAIN_CFG.input = 1) 0.220 MΩ High Input Range (MAIN_CFG.input = 2 or 3) 0.640 MΩ Zero Signal Inputs and Amplifier: ZERO+, ZERO– 201 Vin() Permissible Input Voltage 0 AVDD V 202 Vcm() Permissible Input Common Mode Voltage Refer to Figure 3 Minimum gain (MAIN_CFG.zero = 0) 0.7 AVDD – 1.45 V Maximum gain (MAIN_CFG.zero = 0) 0.35 AVDD – 1.1 V Minimum gain (MAIN_CFG.zero = 1) 2.0 AVDD V Maximum gain (MAIN_CFG.zero = 1) 1.0 AVDD V 203 Vos() Input Referenced Offset Voltage ±20 mV 204 Ilk() Input Leakage Current ±50 nA 205 OFFcorr Correctable Input Offset Voltage As percentage of input signal amplitude; input offset voltage is the sum of sensor offset plus amplifier offset (item 105); ±100 % (step size 60 mV / gain)

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 10/28 ELECTRICAL CHARACTERISTICS Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated Item Symbol Parameter Conditions Unit No. Min. Typ. Max. 206 Rin()diff Differential Input Resistance MAIN_CFG.zero = 0 10 1000 MΩ MAIN_CFG.zero = 1 0.620 MΩ Converter Performance 304 INL Integral Nonlinearity (over one input SIN/COS cycle) Refer to Figure 5, 1 Vpp-diff SIN/COS input with compensated offset, gain and phase 0.2 ° 305 DNL Differential Nonlinearity (over one input SIN/COS cycle Refer to Figure 5, 1 Vpp-diff SIN/COS input with compensated offset, gain and phase 0.1 ° 307 tAB Output Phase A vs. B Refer to Figure 4 25 % 308 twhi Duty Cycle at Output A, B Refer to Figure 4 50 % 309 AArel Relative Angle Accuracy Refer to Figure 4, at conditions of 305 2 % 310 tMTD Time Between AB Edges (Minimum Transition Distance) Refer to Figure 4, ABLIMIT = 0 1/fosc 20 ns Internal Oscillator 401 fosc Oscillator Frequency Tj = 27 °C; AVDD, DVDD = 3.1 V 48 51 MHz AVDD, DVDD = 3.6 V 48 52 MHz 402 TCf Temperature Coefficient 225 ppm/K Internal EEPROM 501 Nwrite Permissible Number of Write Cycles Tj = –40 °C...85 °C 1000 502 Tjw Write Temperature Range –40 85 °C 503 Tjr Read Temperature Range –40 125 °C 504 DRTraw Raw Data Retention Time 10 years 505 DRTact Actual Data Retention Time (with error correction) Tj = 85 °C 50 years Reset and Start-Up: xRST 601 DVDDonoff DVDD Power-On/Off Threshold xRST tied to DVDD 2.5 2.7 3.0 V 603 tstart Startup Time Valid EEPROM configuration, START.wait = 0 2 ms Digital Input Pins: xRST, xCALIB, A+/– (Encoder Link active), A– and B– (BiSS mode), SI, SCLK, xSS,GPIO, BISSEN 701 Vt()hi Input Logic Threshold High DVDD = 3.6 V 1.9 V 702 Vt()lo Input Logic Threshold Low DVDD = 3.3 V 0.8 V 703 Ilk() Input Leakage Current at SI, SCLK, xSS ±50 nA 704 f(SCLK) Permissible SPI Clock Frequency at SCLK TEST.spi = 0 20 MHz TEST.spi = 1 40 MHz 705 tRQ Request Time at MA (A+) BiSSEN = high; for SSI data output to SLO, 24 / fosc see Figure 9 Digital Output Pins: xIRQ, SO, A+/A–, B+/B–, Z+/Z– (CMOS drivers enabled: MAIN_CFG.rs422 = 0), Z– (BiSS mode) 801 I()max Permissible Output Current Per pin, indefinite ±10 mA 802 Vout()hi Output Voltage High I() = –4 mA, 2.4 V MAIN_CFG.irqpp = 1 (for xIRQ push-pull) 803 Vs()hi Saturation Voltage High Vs()hi = IOVDD - V(); I() = -4 mA, 0.7 V MAIN_CFG.irqpp = 1 (for xIRQ push-pull) 804 Vs()lo Saturation Voltage Low I() = 4 mA 0.7 V 805 Isc()hi Short-Circuit Current High Any pin shorted to DVSS –30 –16 mA 806 Isc()lo Short-Circuit Current Low Any pin shorted to DVDD 16 30 mA 807 tr() Rise Time DVDD = 3.3 V, CL = 50 pF, 10% →90% VDD 20 ns 808 tf() Fall Time DVDD = 3.3 V, CL = 50 pF, 10% →90% VDD 20 ns 809 tout() Slave Timeout at SLO (B+) BiSSEN = high; for BiSS & SSI, see Figure 11; BiSS_CFG0.at = 0 (fixed) 1024 / fosc BiSS_CFG0.at = 1 (adaptive) 8 / fosc tinit + 1024 4 / fosc / fosc

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 11/28 ELECTRICAL CHARACTERISTICS Operating conditions: AVDD = DVDD = IOVDD = 3.1...3.6 V, Tj = –40...+125 °C, reference point AVSS unless otherwise stated Item Symbol Parameter Conditions Unit No. Min. Typ. Max. RS422 Drivers: A+/A–, B+/B–, Z+/Z– (RS422 drivers enabled: MAIN_CFG.rs422 = 1) 901 Idrv() Nominal RS422 Driver Current RL() = 120 Ωbetween + and – terminals 20 27 mA 902 Isc()hi Short Circuit Current High + or – pin shorted to IOVSS –55 mA 903 Isc()lo Short-Circuit Current Low + or – pin shorted to IOVDD 35 mA LED Output (enabled: LED_CFG.en = 1) A01 I()max Permissible Output Current for continuous operation ±15 mA A02 Vout()hi Output Voltage High VDD = 3.3 V, Tj = 27 °C, I() = –10 mA 2.7 V A03 Vs()hi Saturation Voltage High Vs()hi = DVDD – V(LED); I() = –10 mA 1 V A04 Vs()lo Saturation Voltage Low I() = 10 mA 1 V A05 Isc()hi Short-Circuit Current High LED pin shorted to DVSS –40 mA A06 Isc()lo Short-Circuit Current Low LED pin shorted to DVDD 40 mA Bias Outputs: VC, VREF B01 VC Bias Voltage VC I(VC) = 0 50 %AVDD B02 dVREF ADC Reference Voltage VREF versus VC dVREF = V(VREF) - V(VC); I(VREF) = 0 –1.1 –1 –0.9 V Temperature Sensor C01 Tacc Temperature Sensor Accuracy ±5 °C Tj = 100 °C ±2 °C 0 V AVDD MAIN_CFG.input = 2 AVDD SIN– or COS– SIN+ or COS+ 0.35 V 0 V 0.35 V 1.1 V 1.1 V 0 V AVDD AVDD SIN– or COS– SIN+ or COS+ 0.35 V 0 V 0.35 V MAIN_CFG.input = 3 AVDD – 1.1 AVDD – 1.1 AVDD – 1.1 AVDD – 1.1 1.0 V 1.0 V MAIN_CFG.input = 0 or 1 Figure 1: Input Voltage Range (Vin())

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 12/28 SIN+% COS+% SIN–% COS–% 0 V Maximum Input Voltage Minimum Input Voltage Max. Input Amplitude (700 mV) 0 V Maximum Input Voltage Maximum Input Amplitude (2 V) SIN+% COS+% SIN–% COS–% Low Input Range (MAIN_CFG.input = 0 or 1) High Input Range (MAIN_CFG.input = 3) 2.2 V 0.35 V AVDD AVDD 1.0 V Minimum Input Voltage Figure 2: Differential Input Amplitude (Ain()diff), Max(SIN+ – SIN–) or Max(COS+ – COS–) 0 V 1.85 V 0.7 V 2.2 V 0.35 V AVDD Minimum Gain Maximum Gain MAIN_CFG.input ≠ 3 or MAIN_CFG.zero = 0 MAIN_CFG.input = 3 or MAIN_CFG.zero = 1 0 V 2.0 V 1.0 V AVDD Minimum Gain Maximum Gain Figure 3: Input Common Mode Range, (SIN+ + SIN–)/2, (COS+ + COS–)/2, or (ZERO+ + ZERO–)/2 A B tMTD t whi T (100 %) AArel tAB ABrel Figure 4: Description of AB output signals 0° 360° 180° Converter Error INL: The maximum absolute error. DNL: The maximum step between two consecutive samples. Ideal converter Actual converter Angular Position Figure 5: Definition of integral and differential nonlin- earity

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 13/28 OPERATING REQUIREMENTS: SPI Interface Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C Item Symbol Parameter Conditions Unit No. Min. Max. SPI Interface Timing I001 tC1 Permissible Clock Cycle Time (See spec. item 704) TEST.spi = 0 50 ns TEST.spi = 1 25 ns I002 tD1 Clock Signal Lo Level Duration TEST.spi = 0 15 ns TEST.spi = 1 7.5 ns I003 tD2 Clock Signal Hi Level Duration TEST.spi = 0 15 ns TEST.spi = 1 7.5 ns I004 tS1 Setup Time: xSS lo before SCLK lo →hi 80 ns I005 tH1 Hold Time: xSS lo after SCLK hi →lo 50 ns I006 tW1 Wait Time: between xSS lo →hi and xSS hi →lo 200 ns I007 tS2 Setup Time: SI stable before SCLK lo →hi 5 ns I008 tH2 Hold Time: SI stable after SCLK lo →hi 10 ns I009 tP1 Propagation Delay: SO stable after xSS hi →lo 60 ns I010 tP2 Propagation Delay: SO high impedance after xSS lo →hi 25 ns I011 tP3 Propagation Delay: SO stable after SCLK hi →lo 20 ns xSS SCLK SI SO tW1 tD1 tD2 tS1 TSI(hold) TSI(set) TSO(prop) tH1 TSO(float) Hi-Z Figure 6: SPI Timing

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 14/28 OPERATING REQUIREMENTS: Encoder Link Interface Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C Item Symbol Parameter Conditions Unit No. Min. Max. Encoder Link Activation Sequence Timing I101 T1 Activation Sequence Interval 1 A+ > 2.4 V, A– > 2.4 V 0.25 2 ms I102 T2 Activation Sequence Interval 2 A+ < 0.8 V, A– > 2.4 V T1 – 10% T1 + 10% ms I103 T3 Activation Sequence Interval 3 A+ < 0.8 V, A– < 0.8 V T1 – 10% T1 + 10% ms I104 T4 Activation Sequence Interval 4 A+ > 2.4 V, A– < 0.8 V T1 – 10% T1 + 10% ms Encoder Link Interface Timing (after activation) I105 fclk(A+) ELink Clock Frequency Signal driven into A+ 1.0 MHz I106 tD1(A+) ELink Clock Signal Hi Level Duration Signal driven into A+ 200 ns I107 tD2(A+) ELink Clock Signal Lo Level Duration Signal driven into A+ 200 ns I108 tS(A–) ELink Input Setup Time Signal driven into A– 200 ns I109 tH(A–) ELink Input Hold Time Signal driven into A– 200 ns I110 tP(A–) ELink Output Propagation Delay Signal driven out on A– 200 ns A+ A– External driver starts to overpower iC- TW29 by forcing A+ and A– high. T1 0.25–2 ms T2 T1 ±10% T3 T1 ±10% T4 T1 ±10% iC-TW29 stops driving A+ and A–. Encoder Link interface is now active. Normal operation. iC-TW29 is driving quadrature signals on A+ and A–. Figure 7: Encoder Link Activation Sequence ELCLK (A+) ELIN (A–) ELOUT (A–) TELCLK(high) TELCLK(low) TELIN(hold) TELIN(set) TELOUT(prop) Figure 8: Encoder Link Read and Write Timing

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 15/28 OPERATING REQUIREMENTS: BiSS Interface Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C Item Symbol Parameter Conditions Unit No. Min. Max. SSI protocol (BiSSEN pin high and BISS_CFG0.ssi = 1) I201 tframe Permissible Frame Repetition * indefinite I202 tC Permissible Clock Period With tRQ according to I205 250 ns I203 tL1 Clock Signal Hi-Level Duration 125 tout ns I204 tL2 Clock Signal Lo-Level Duration 125 tout ns I205 tRQ Request Time Clock low-level duration at MA input (due to Elec. Char. 705) 500 ns I206 tP3 Output Propagation Delay 50 ns I207 tout Slave Timeout see Elec. Char. 809 BiSS C protocol (BiSSEN pin high and BISS_CFG0.ssi = 0) I208 tframe Permissible Frame Repetition * indefinite I209 tC Permissible Clock Period 100 ns I210 tL1 Clock Signal Hi-Level Duration 50 tout ns I211 tL2 Clock Signal Lo-Level Duration 50 tout ns I212 tbusy Processing Time 240 ns I213 tP3 Output Propagation Delay 50 ns I214 tout Slave Timeout see Elec. Char. 809 I215 tS1 Setup Time: SLI stable before MA hi →lo 25 ns I216 tH1 Hold Time: SLI stable after MA hi →lo 10 ns Note: * Allow tout to elapse. tP3 DATA tC DATA tout tframe tL2 tRQ DATA DATA DATA MA SLO tL1 Figure 9: SSI protocol timing MA SLO tC DATA tframe tL2 tL1 ACK tbusy tout tP3 START START DATA ACK SLI tS1 tH1 Figure 10: BiSS protocol timing SLO MA tinit tout Figure 11: BiSS slave timeout

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 16/28 OPERATING REQUIREMENTS: ADI Interface Operating conditions: AVDD = DVDD = IOVDD = +3.1...+3.6 V, AVSS = DVSS = IOVSS = 0 V, Tj = –40...125 °C Item Symbol Parameter Conditions Unit No. Min. Max. BiSS Protocol (ADI_CFG.biss = 1) I301 tframe Clock Frame Repetition Note: This value can vary during operation. 1 3 ms I302 tC Clock Period ADI_CFG.freq = 0 5.9 7.7 µs ADI_CFG.freq = 1 0.59 0.77 µs I303 tL1, tL2 Clock Signal Hi/Lo Level Duration 50 % tC I304 tbusy Permissible Processing Time relative to clock period ∞ % tC I305 tP0 Permissible Propagation Delay (Line Delay Compensation) not supported (data is captured on next rising clock edge) 0 ns I306 ∆tP Permissible Propagation Delay Variance not supported (refer to tS and tH) % tC I307 tS Setup Time: Data stable before clock edge lo →hi without line delay compensation (tP0 = 0) 100 ns I308 tH Hold Time: Data stable after clock edge lo →hi without line delay compensation (tP0 = 0) 0 ns I309 tout Permissible Slave Timeout tC µs SSI Protocol (ADI_CFG.biss = 0) I310 tframe Clock Frame Repetition Note: This value can vary unpredictably during operation. 1 3 ms I311 tC Clock Period ADI_CFG.freq = 0 5.9 7.7 µs ADI_CFG.freq = 1 0.59 0.77 µs I312 tL1, tL2 Clock Signal Hi/Lo Level Duration 50 % tC I313 tS Setup Time: Data stable before clock edge lo →hi 100 ns I314 tH Hold Time: Data stable after clock edge lo →hi 0 ns I315 tout Permissible Slave Timeout tC µs Clk Out (A-) Data In (B-) tH START DATA tC tS DATA tout tframe tL2 tL1 ACK tbusy tP0 Figure 12: ADI timing with BiSS protocol tH DATA tC tS DATA tout tframe tL2 tL1 DATA DATA DATA Clk Out (A-) Data In (B-) Figure 13: ADI timing with SSI protocol

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 17/28 FUNCTIONAL BLOCK DIAGRAM Interpolated Angle (IA) SPI Interface xSS SCK SO SI Interpolator ZERO Channel SIN+ SIN– COS+ COS– ZERO+ ZERO– 26-Bit Gearbox Includes Filter, Hysteresis, and Eccentricity Correction Zero Gating Window (ZW) ABZ with Output Freq. Limiter Normalized Angle (NR) Revolution Count (RC) UVW BiSS Slave with Encoder Profile and EDS UVW Scan Absolute Data Interface (ADI) Revolution Count (RC), Cycle Count (CC), and Sync Bits I/O Multiplexer A+ A– B+ B– Z+ Z– Auto Calibration, Auto Adaption, LED Control, Startup, ID, EEPROM xCALIB xIRQ LED Position Capture BiSS Control Data Encoder Link Monitors: Status/Fault, Temp., Sin/Cos Amplitude, Excessive Error, Excessive Adaption GPIO IA CC RC Figure 14: Functional Block Diagram The iC-TW29 uses a modular architecture as shown in Figure 14. Differential sine and cosine sensor signals are con- verted to a 14-bit interpolated angle (IA) within one input cycle by the interpolator. The interpolator also provides complete analog and digital error correction for the input signals to ensure lowest angular error and jitter. A sophisticated digital filter with fixed or variable bandwidths improves performance with noisy inputs. The zero channel generates the zero gating window (ZW) from analog or digital zero or index sensors which can be used to generate a traditional once-per-revo- lution Z output. The ZERO input can also be used to reset the gearbox counter and to capture the current full absolute position of the iC-TW29. The gearbox tracks the input cycles within a revolution and provides a normalized 26-bit output representing the angle within one output revolution (NR). This is synchronized with the revolution count (RC) and the cycle count (CC) from the absolute data interface (ADI) or SPI port to form the complete absolute position. A programmable noise and jitter filter increases angle res- olution by two or more bits depending on configuration. Hysteresis and eccentricity correction The full absolute position value of the iC-TW29 can be captured and read out over the SPI port. This posi- tion capture takes place on the rising edge of the zero gating window and can also be configured to generate an interrupt. The most recent four absolute position values are saved in a FIFO. This allows touch-probe or distance-coded index applications to be easily imple- mented. Traditional encoder quadrature (ABZ) outputs are avail- able as RS-422 compatible differential or single-ended signals depending on device configuration. The ABZ output resolution (edges or AB cycles per revolution) is programmable and independent of the input resolution (input cycles per revolution). The zero gating window (ZW) from the zero signal path can be used to gener- ate a programmable-width Z output synchronized with the AB outputs. The Z output can also be synthesized from absolute position data when the ZERO input is not used. The ABZ output module incorporates a programmable AB output frequency limiter that guarantees a minimum separation time between AB edges. This is useful to avoid counting errors with PLCs or counters with input frequency limits less than the 12.5 MHz maximum AB output frequency of the iC-TW29.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 18/28 When the AB output frequency is being limited, the AB outputs lag behind the sin/cos inputs. If this condition is temporary or transient, the AB outputs catch up when the limiter is no longer active. If this condition persists, however, a fatal fault is generated and the iC-TW29 stops operating. The AB output frequency limiter can also be programmed to activate xIRQ. 3-phase UVW outputs for commutation of brushless motors with up to 64 poles (32 pole pairs) per revolution are also available as RS-422 compatible differential or single-ended signals depending on device configura- tion. A BiSS Slave interface provides BiSS C-Mode bidirec- tional communication of output angle (with indepen- dently programmable resolution), revolution count, and configuration data. Encoder Profiles 3, 3S (Safety), and 4 are implemented in the iC-TW29 or a custom profile may be defined using a host processor. BiSS com- mand requests are handled directly by the iC-TW29 for stand-alone applications or can be passed through to an external microprocessor via the SPI port in hosted applications. The BiSS interface can be configured to implement BiSS Standard Encoder Electronic Data Sheet (EDS) SE. This allows the BiSS master to read the encoder configuration over the BiSS interface at startup. In hosted applications, the host processor can implement any BiSS EDS. UVW scan mode allows external UVW signals to be read by the iC-TW29 and sent to the BiSS master with the BiSS single cycle data (BP4 or custom encoder pro- file only). This allows commutation of a brushless motor over BiSS before absolute position is synchronized. The absolute data interface (ADI) is a BiSS/SSI master for reading revolution and cycle count information from an external absolute position system (such as iC-PVL). Up to four synchronization bits can be used. The I/O multiplexer determines which signals are trans- ferred to the output pins. One of 23 output modes (combinations of output types) can be selected. Up to two different output types may be used simultaneously. The SPI port is available for use by an external host processor for initial calibration or general communica- tion. The iC-TW29 provides comprehensive monitoring func- tions for status and faults, chip temperature and sin/cos input signal quality. The status/fault monitor monitors 16 internal conditions, each of which can be individually configured to activate a fault output to notify an external system during opera- tion. The fault output is the active-low interrupt request output (xIRQ) pin. In stand-alone applications, xIRQ can be used to directly drive a fault LED. In hosted applications, xIRQ is typically used to interrupt the host when a fault occurs. In addition, real-time status and fault information is available over the SPI and BiSS interfaces. The iC-TW29 incorporates an on-chip temperature sen- sor. The temperature monitor can provide real-time chip temperature data to a host processor or BiSS mas- ter. The temperature monitor can be configured to activate a status bit when chip temperature exceeds a programmable limit. This condition can also activate xIRQ. The sin/cos amplitude monitor continuously monitors the amplitude of the sin/cos input signals by calculating the quantity √ sin2 + cos2. If the input amplitude is out- side configured limits, a status bit is activated and an interrupt can be generated. The excessive error monitor continuously calculates the residual offset, balance, and phase error of the cor- rected sin/cos signals. These residues represent the uncorrected signal error of the sin and cos channels, and are typically zero (or near zero) when auto adaption is used. If any of the error residues exceeds configured limits, a status bit is set and an interrupt can be gen- erated. In applications where auto adaption cannot be used, the residues allow sensor signal quality to be monitored by a host processor. The excessive adaption monitor continuously compares the current offset, balance, and phase correction pa- rameter values to baseline values store in the EEPROM during device configuration. If any of the correction val- ues deviate from the base values (due to auto adaption) by more than the configured limits, a status bit is set and an interrupt can be generated. Auto calibration is used at initial device commissioning to automatically determine gain, offset, channel bal- ance, and phase compensation values for the sin, cos, and zero channels. Auto calibration is initiated using the xCALIB input pin or via a serial command. Cali- brated values can be stored in the internal EEPROM for use on subsequent startups. Auto adaption maintains optimal offset, channel bal- ance, and phase compensation values for the sin and cos channels during operation to ensure maximum in- terpolator accuracy and lowest jitter under all operating conditions.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 19/28 A configurable LED intensity control uses the calcu- lated sin/cos amplitude value to control the intensity of an optical sensor LED via the pulse-width modulated LED output (pin 26). This maintains the sin/cos signals at their calibrated amplitude in the presence of LED ageing and varying application conditions. Device startup can proceed automatically for stand-alone applications or under the control of a host processor in hosted applications. In general, outputs are not enabled until the appropriate position (relative or absolute) is established. Device and chip identification is provided in the form of a unique factory-programmed chip serial number as well as a chip ID and revision code. In BiSS applica- tions, user-programmable manufacturer ID, product ID, device serial number, and production date are avail- able. The iC-TW29 incorporates an internal write-protected EEPROM to store configuration and initial calibration data for use at startup. In addition to a standard check- sum on the EEPROM data, sophisticated data encoding allows detection and correction of single-bit errors and detection of two-bit errors for enhanced application se- curity. The EEPROM can be unlocked using the SPI, BiSS, or encoder link interfaces. The Encoder Link interface provides read/write access to the iC-TW29’s internal registers using the A+ and A– outputs in ABZ or UVW output modes. This is useful for field reconfiguration or diagnostics of products incorpo- rating the iC-TW29. Encoder Link can only be used for configuration and diagnostics, it cannot be used to read position. Encoder Link can be disabled to eliminate tampering with finished products.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 20/28 ELECTRICAL CONNECTIONS The basic electrical connections for an incremental stand-alone application with differential ABZ outputs are shown in Figure 15. Other than the sin/cos sensor, only a few bypass capacitors and other components are required for operation. Application Hint The input voltages must not exceed the chip’s supply voltage (3.3 V). VREF VC 100 nF 1µF AVDD AVSS 3.3V SIN+ SIN– COS+ COS– Sensor iC-TW29 xSS SCLK SI SO SPI Configuration Port xCALIB Calibration Button 100 nF 1µF IOVDD 3.3V IOVSS A+ A– B+ B– Z+ Z– 1µF DVDD DVSS 3.3V BISSEN ZERO+ ZERO– xRST 3.3V xIRQ Fault LED Differential RS422 ABZ Outputs GPIO RESERVED RESERVED 3.3V 120 Ω 120 Ω 120 Ω xSS SCLK MOSI MISO 3.3V Figure 15: Typical Electrical Connections For Incremental Stand-Alone Application

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 21/28 The basic electrical connections for an absolute mul- titurn stand-alone application using BiSS are shown in Figure 16. An external RS422-compatible driver/re- ceiver, such as the iC-HF, and a 5 V-to-3.3 V level shifter, such as the TXS0104E, is required. An external mul- titurn device, such as the iC-PVL, is connected to the absolute data interface. VREF VC 100 nF 1µF AVDD AVSS 3.3V SIN+ SIN– COS+ COS– Sensor iC-TW29 xSS SCLK SI SO SPI Configuration Port xCALIB Calibration Button 100 nF 1µF IOVDD 3.3V IOVSS SLI (Z+) Clk Out (A–) Data In (B–) GPIO (Z–) 1µF DVDD DVSS 3.3V BISSEN ZERO+ ZERO– xRST 3.3V xIRQ Fault LED BiSS Slave Interface GPIO RESERVED RESERVED 3.3V xSS SCLK MOSI MISO 3.3V iC-HF X4 X3 X2 X6 X5 X1 CLK+ 120 Ω DATA+ DATA– CLK– Q4 NQ4 Q5 NQ5 Q2 NQ2 Q6 NQ6 Q3 NQ3 120 Ω 3.3V Regulator VDD VDDS 5V GND GNDS 0V MA+ SLI+ MA– SLI– 120 Ω 120 Ω 120 Ω SLO+ SLO– MA (A+) SLO (B+) OEN FMSEL1 FMSEL2 Absolute Data Interface 5VS B1 B2 B3 A1 A2 A3 B4 A4 VCCB OE GND VCCA TXS0104E Figure 16: Typical Electrical Connections For Absolute BiSS Stand-Alone Application Alternatively, resistive voltage dividers can be used instead of an explicit level shifter chip. In this case, val- ues of 470 Ωand 560 Ωare recommended to drive MA (A+), SLI (Z+), and Data In (B–). This will add 15 mA of current consumption. The BiSS interface is enabled by connecting the BiS- SEN input pin to 3.3 V as shown. The iC-HF is used in BiSS bus structure mode. See the iC-HF data sheet for more information.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 22/28 The basic electrical connections for an incremental hosted application using a single iC-TW29 are shown in Figure 17. Multiple iC-TW29s can also be bussed or chained together using the same SPI port on the host processor. Differential RS422 ABZ Outputs 120 Ω 120 Ω 120 Ω VREF VC 100 nF 1µF AVDD AVSS 3.3V SIN+ SIN– COS+ COS– Sensor iC-TW29 xSS SCLK SI SO xCALIB 100 nF 1µF IOVDD 3.3V IOVSS A+ A– B+ B– Z+ Z– 1µF DVDD DVSS 3.3V BISSEN ZERO+ ZERO– xRST xIRQ GPIO RESERVED RESERVED Host µP OUTx IRQx xCS SCLK MO MI 3.3V Figure 17: Typical Electrical Connections For Hosted Application Power and Ground The iC-TW29 requires a high quality ground and clean 3.3 V power supplies. There are three sepa- rate power/ground pin pairs, one each for the analog (AVDD/AVSS), digital (DVDD/DVSS), and I/O (IOVD- D/IOVSS) circuitry. In most cases, it is sufficient to connect all three power pins to the same low-impedance power source, prefer- ably an on-board voltage regulator. Likewise, the three ground pins can usually be connected to the same solid ground plane on the PC board. If necessary, separate voltage regulators can be used to power each section to provide enhanced noise immunity. In all cases, each power pin should have a dedicated 1µF decoupling capacitor placed as close to the iC-TW29 as possible. Reference Outputs The reference outputs VREF and VC must each be decoupled to ground with separate 100 nF capacitors placed as close to the iC-TW29 as possible. VC should not be used to bias external circuitry or the sin/cos or ZERO inputs with single-ended sensors. xCALIB Input The active-low xCALIB input is used to activate the au- to-calibration feature of the iC-TW29. A push-button and pull-up resistor can be connected to this input as shown for easy manual calibration. xCALIB can also be controlled by a host processor output, if desired. If push-button calibration is not required, xCALIB should be connected to 3.3 V to avoid spurious calibration. SIN and COS Inputs The iC-TW29 connects directly to magnetic (such as iC-SM2L or iC-SM5L) and optical (such as iC-LSHB or iC-PT...H series) sensors providing differential sin/cos outputs, as shown in Figure 18 and Figure 19.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 23/28 SIN+ SIN– COS+ COS– iC-TW29 AVDD PSIN NSIN PCOS NCOS iC-SMxL Sensor Figure 18: Magnetic Sensor Connection SIN+ SIN– COS+ COS– iC-TW29 5V PA NA PB NB iC-PT…H Sensor ZERO+ PZ ZERO– NZ Figure 19: Optical Sensor Connection Nominal differential signal amplitudes between 20 mV and 2.0 V in two ranges can be accommodated. ZERO Inputs The iC-TW29 can interface to a wide range of differen- tial or single-ended index or zero sensors to provide a Z output which is synchronized with the AB outputs or to reset the gearbox counter. Optical sensors usually provide differential zero or index signals along with the sin/cos signals. In magnetic systems, a separate zero sensor is usually required. Digital zero sensors (Hall, MR, and others) typically pro- vide a single-ended active-low signal via an open-drain output that pulls low in the presence of a magnetic field. Connect active-low (open drain) digital index sensors to the iC-TW29 ZERO– input and connect the ZERO+ in- put to VDD/2 using a resistive voltage divider as shown in Figure 20. ZERO+ ZERO- DVDD iC-TW29 Digital Hall active low AVDD Figure 20: Digital Index Sensor Connection Analog-output zero sensors, such as MR bridges, can also be used with the iC-TW29 as shown in Figure 21. iC-TW29 MR Index Sensor ZERO+ ZERO- Figure 21: Analog Index Sensor Connection To produce a Z output once every input cycle, connect ZERO+ to 3.3 V and ZERO– to ground. This is use- ful in on-axis applications where one input revolution produces only one input cycle. If no Z output from the iC-TW29 is required, connect ZERO+ to ground and ZERO– to 3.3 V.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 24/28 ABZ Outputs The iC-TW29 can be configured to provide differential ABZ outputs capable of driving 20 mA into a terminated RS422 line. The A+, A–, B+, B–, Z+, and Z– outputs can be directly connected to the RS422 line as shown in Figure 22. 120 Ω 120 Ω 120 Ω A+ A– B+ B– iC-TW29 Z+ Z– A+ B+ Z+ A– B– Z– Figure 22: ABZ Output Connection The three signal pairs should be terminated with a 120 Ω resistor at the far (receiving) end of the cable as shown. The RS422-compatible line driver can be disabled to save power for local or short-run applications. In this case, termination resistors should not be used. UVW Outputs The iC-TW29 can be configured to provide differential UVW outputs or simultaneous single-ended ABZ and UVW outputs. xRST Input The iC-TW29 contains a built-in power-on-reset (POR) circuit that controls the safe startup of the device. In most applications, no external components are required and xRST can be connected directly to 3.3 V. Alternatively, an RC network with recommended values of 47 kΩand 100 nF can be connected to the active-low xRST input to extend device reset in case of a slow-ris- ing supply as shown in Figure 23. DVDD xRST iC-TW29 47 kΩ 100 nF Figure 23: xRST Connection In stand-alone applications, it is recommended to al- ways provide for an RC network on the PC board and only populate the capacitor if required. Without the capacitor, the resistor provides the necessary pull-up. In hosted applications, the xRST input is best controlled by the host. For battery-powered applications, the host can hold xRST low to reduce power consumption (low power mode). See spec. item 005. xIRQ In stand-alone applications, xIRQ functions as an ac- tive-low fault output. It can be used to directly drive an LED with an appropriate current-limiting resistor for fault indication. In hosted applications, xIRQ can be connected to an interrupt request input on the host processor. In this way, when a warning or fault occurs, the host processor can query the iC-TW29 to determine what action to take. xIRQ can also be configured as an external fault input. xIRQ can be configured as an open-drain output allow- ing a wired-OR connection of multiple iC-TW29s to a single interrupt request input on the host processor. Finally, xIRQ can be configured as an external interrupt request input. LED Output The iC-TW29 can be configured to provide LED inten- sity control for optical sensors. The LED output func- tions as a high-current output to drive the illumination LED used with an optical sensor. If the LED intensity control functionality is not needed, the LED output can be configured for use as gener- al-purpose I/O. BiSSEN Input The BiSSEN input is used to enable the TW29’s BiSS interface. Connect BiSSEN to 3.3 V to enable the BiSS interface; connect BiSSEN to ground to disable the BiSS interface. Regardless of the EEPROM configu- ration data, the I/O pins A+, B+, Z+ are used for MA, SLO, SLI. General-Purpose I/O The GPIO pin can be configured as a general-purpose input or output. If configured as an input, it can be further configured as a BiSS position preset input. In this case, a push-button and pull-up resistor can be connected to this input for easy manual presetting.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 25/28 SPI Port The iC-TW29 provides a standard SPI (Serial Periph- eral Interface) slave port that can be used for device configuration and communication with a host proces- sor. Connect the SPI port pins to the host processor as shown in Figure 24. SO SI SCLK xSS xCS SCLK MO MI iC-TW29 Host µP or µC 3.3V Figure 24: SPI Port Connection If the host processor or microcontroller can be discon- nected, the SPI port pins must be pulled up or down as shown in Figure 24. Do not allow any of the SPI port pins to float. Although Figure 24 shows a single-device application, multiple iC-TW29’s can also communicate over a single SPI channel to a host processor. Reserved Pins All reserved pins must be tied to ground as shown in Figures 15, 16, and 17 for proper operation.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 26/28 CONFIGURATION AND CALIBRATION Introduction The iC-TW29 uses a modular architecture. This means that only the enabled modules and required features need to be configured. For example, if ABZ outputs are not enabled, the ABZ output module does not need to be configured. Configuration values for enabled modules and required features must be written to the TW29’s internal EEP- ROM using the BiSS or SPI ports or the Encoder Link in- terface before the device can be used. For stand-alone applications, the easiest way to accomplish this is to use one of the iC-TW29 demo boards and the free Graphical User Interface (GUI) software. The iC-TW29 EVAL TW29_1D evaluation board im- plements the iC-TW29 and a USB interface for direct communication with the GUI software for ABZ and UVW applications. The iC-TW29 EVAL TW29_3D evaluation board implements the iC-TW29 and a USB interface for direct communication with the GUI software for BiSS and SSI applications. Using one of these boards, a functional prototype encoder can be quickly assembled and configured. See the iC-TW29 EVAL TW29_1D and 3D datasheet for more information. The TW29_1D evaluation board includes a break-away programmer that can be used for prototype develop- ment to configure an external iC-TW29 via the SPI or Encoder Link interfaces using the free GUI software. In series production, this programmer can be employed to download pre-engineered configurations to iC-TW29s embedded in products. In hosted applications (where the SPI port is used to communicate with the host processor), the iC-TW29 must be configured via the host, or through the BiSS or Encoder Link interfaces. The remainder of this section assumes use of a TW29_1D (ABZ) or TW29_3D (BiSS) demo board in a rotary application with or without a zero sensor. The GUI software is used for configuration and calibration via SPI communication. Default Configuration To ensure known starting conditions, load the default configuration file using the File menu in the GUI. This sets all parameters to their default or recommended values and disables the monitors to avoid nuisance faults during configuration and calibration. Once the iC-TW29 is configured and calibrated, the monitors and other advanced features can be enabled as needed. Click on the EEPROM block in the block diagram on the main GUI window to open the EEPROM tab and save the default configuration to EEPROM. Finally, restart the iC-TW29 by clicking the play button (▷) on the main GUI window. Input Configuration and Calibration Click on the AFE-IPO (Analog Front End and Interpo- lator) tab. Select the signal range that corresponds to the attached sin/cos and zero sensors. In general, use low range for passive sensors (like AMR and un-ampli- fied Hall) and high range for powered (amplified Hall or photo diode) sensors. See Figures 2 and 3 for more information on signal ranges. The other parameters can be left at their default values. In the Calibration tab, check "Auto calibrate sine/cosine offsets, gains, and phase" and "Automatically store calibrated values to EEPROM." If a zero sensor is con- nected, also check "Auto calibrate zero analog offset and gain" and "Auto calibrate IA phase shift." With the sin/cos and zero (if used) sensors generating signals, click the Auto-calibration "Start" button in the GUI or the xCALIB button on the demo board to begin auto calibration. When the values in the signal path diagram on the Calibration tab have settled to non-zero values, click the Auto-calibration "Stop" button. This stops auto calibration and stores the calibrated values to EEPROM. With the sensors still generating signals, click the Adap- tion tab. The Sine and Cosine Amplitude bar graphs should show signal amplitudes of 2400±100. If not, change the input range settings (AFE-IPO tab) as re- quired and re-run auto calibration. Once the signal path has been successfully calibrated, enable auto adaption in the adaption tab for offset, bal- ance, and phase as required. Save these configuration values to EEPROM using the EEPROM tab. With auto adaption enabled and the sensors generating signals, the correction values on the signal path diagram in the calibration tab should be changing by small amounts. In the Gearbox tab, set the Revolution Counter Length as required. The default is 16 bits. If revolution count- ing is not needed, the counter can be left at the default value or set to zero. Set the Input Cycles per Revolution to match the num- ber of sin/cos cycles generated by the sensor per output revolution. Save these values to EEPROM. The other parameters in this tab can be left at their default values.

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 27/28 ABZ/UVW Configuration To provide differential and line driver ABZ or UVW out- puts, the iC-TW29 must not be in BiSS mode. Confirm that BISSEN = 0 in the main GUI window. This is the case with the TW29_1D demo board. In the I/O tab, select the desired functionality of the positive and negative outputs. For example, for differ- ential RS-422 ABZ outputs, select "A+, B+, Z+" for the positive outputs, select "A–, B–, Z–" for the negative outputs, and enable the RS422 line driver. The other parameters in this tab can be left at their default values. In the ABZ/UVW tab, enter the resolution for the AB out- puts as the desired number of increments (edges) per output revolution. Enter the desired number of UVW cy- cles per output revolution if the UVW outputs are used. The other parameters in this tab can be left at their de- fault values. Save the configuration to EEPROM using the EEPROM tab, and restart the iC-TW29 by clicking the play button (▷) in the main GUI window. BiSS/SSI Configuration To use BiSS or SSI output, the iC-TW29 must be in BiSS mode. Confirm that BISSEN = 1 in the main GUI window. This is the case with the TW29_3D demo board. The default BiSS configuration uses BP3 (Standard Encoder Profile), 4 096 increments per singleturn revo- lution, and no multiturn bits. This configuration may be changed as desired, but the iC-TW29 must be restarted by clicking the play button (▷) in the main GUI window for any changes to be recognized by the BiSS Master. iC-Haus expressly reserves the right to change its products and/or specifications. A Datasheet Update Notification (DUN) gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.com/DUN and is automatically generated and shall be sent to registered users by email. Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source. The data specified is intended solely for the purpose of product description and shall represent the usual quality of the product. In case the specifications contain obvious mistakes e.g. in writing or calculation, iC-Haus reserves the right to correct the specification and no liability arises insofar that the specification was from a third party view obviously not reliable. There shall be no claims based on defects as to quality in cases of insignificant deviations from the specifications or in case of only minor impairment of usability. No representations or warranties, either expressed or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus products are not designed for and must not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (Safety-Critical Applications) without iC-Haus’ specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems. iC-Haus products are not designed nor intended for use in military or aerospace applications or environments or in automotive applications unless specifically designated for such use by iC-Haus. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. Software and its documentation is provided by iC-Haus GmbH or contributors "AS IS" and is subject to the ZVEI General Conditions for the Supply of Products and Services with iC-Haus amendments and the ZVEI Software clause with iC-Haus amendments (www.ichaus.com/EULA).

WITH INTERPOLATION AND BiSS INTERFACE Rev C1, Page 28/28 ORDERING INFORMATION Type Package Options Order Designation iC-TW29 32-pin QFN, 5 mm x 5 mm, thickness 0.9 mm, RoHS compliant iC-TW29 QFN32-5x5 ABZ Evaluation Board and SPI Programmer PCB, approx. 50 mm x 123 mm iC-TW29 EVAL TW29_1D BiSS Evaluation Board PCB, approx. 50 mm x 123 mm iC-TW29 EVAL TW29_3D iC-TW29 GUI Evaluation software for Windows PC (entry of IC parameters, file storage, and transfer to DUT) For download link refer to www.ichaus.com/tw29 Please send your purchase orders to our order handling team: Fax: +49 (0) 61 35 - 92 92 - 692 E-Mail: [email protected] For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Tel.: +49 (0) 61 35 - 92 92 - 0 Am Kuemmerling 18 Fax: +49 (0) 61 35 - 92 92 - 192 D-55294 Bodenheim Web: http://www.ichaus.com GERMANY E-Mail: [email protected] Appointed local distributors: http://www.ichaus.com/sales_partners