Congatec COM Express conga-TS175 Operation & User’s Manual

7th Generation Intel® Core™ i7, i5, i3 and Xeon processor with either QM175, HM175, or CM238 Chipset User’s Guide Revision 1.6

TSKLm16 2/71 Revision History Revision Date (yyyy-mm-dd) Author Changes 0.1 2017-03-13 AEM • Preliminary release 1.0 2017-08-01 AEM • Updated sections 2.5 “Power Consumption” and 2.6 “Supply Voltage Battery Power” • Updated sections 10 “Resource List” and 11 “BIOS Setup Description” 1.1 2018-05-07 AEM • Corrected the unit of measurement in table 5 “Power Consumption Values” • Corrected a typographic error in section 6.1.11 “General Purpose Serial Interface” • Corrected the pin numbers of USB ports 0 and 1 in table 16 “USB SignalDescriptions” 1.2 2018-08-24 AEM • Updated the cooling diagrams and heatspreader thermal imagery in section 4 “Cooling Solutions” 1.3 2018-10-12 AEM • Added note about recommended boot mode in section 2.2 “Supported Operating Systems” • Changed Intel 100 series PCH to Intel PCH 1.4 2019-04-25 AEM • Updated all cross references • Updated section 2.3 “Mechanical Dimensions” • Updated sections 4 .1 “CSA Dimensions”, 4.2 “CSP Dimensions”, 4.3 “HSP Dimensions” • Updated sections 11.3 “Updating the BIOS“ and 11.4 “Supported Flash Devices” 1.5 2020-05-08 AEM • Updated section 4 “Cooling Solutions” • Corrected the resolutions for three independent displays in table 7 “Maximum Supported Resolutions” • Updated the link for power supply implementation guidelines in section 6.1.13 “Power Control” • Added note about the minimum pulse width required for proper button detection in table 24 “Power and System Management Signal Descriptions” • Added information about congatec MLF file to section 11 “BIOS Setup Description”. • Corrected typographic error in section 11.5 “Supported Flash Devices” • Deleted section 12 “Industry Specifications” • Restructured the whole document 1.6 2021-04-19 AEM • Updated table 2 “conga-TS175 Variants, table 3 “Feature Summary”, table 8 “Maximum Supported Resolutions” and table 16 “TMDS Signal Descriptions” • Updated section 3 “Block Diagram” and section 6.1.3 “Display Interfaces • Deleted section 6.1.3.2 “HDMI” and section 6.1.3.4 “DVI” • Added note to table 16 “TMDS Signal Descriptions”

TSKLm16 3/71 Preface This user’s guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-TS175. It is one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should be used include the following: COM Express™ Design Guide COM Express™ Specification The links to these documents can be found on the congatec AG website at www.congatec.com Disclaimer The information contained within this user’s guide, including but not limited to any product specification, is subject to change without notice. congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec AG assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information contained herein or the use thereof. Intended Audience This user’s guide is intended for technically qualified personnel. It is not intended for general audiences. Lead-Free Designs (RoHS) All congatec AG designs are created from lead-free components and are completely RoHS compliant.

TSKLm16 4/71 Electrostatic Sensitive Device All congatec AG products are electrostatic sensitive devices. They are enclosed in static shielding bags, and shipped enclosed in secondary packaging (protective packaging). The secondary packaging does not provide electrostatic protection. Do not remove the device from the static shielding bag or handle it, except at an electrostatic-free workstation. Also, do not ship or store electronic devices near strong electrostatic, electromagnetic, magnetic, or radioactive fields unless the device is contained within its original packaging. Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty. Symbols The following symbols are used in this user’s guide: Warning Warnings indicate conditions that, if not observed, can cause personal injury. Caution Cautions warn the user about how to prevent damage to hardware or loss of data. Note Notes call attention to important information that should be observed. Trademarks Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property of their respective trademark holders. These trademark holders are not affiliated with congatec AG, our products, or our website.

TSKLm16 5/71 Copyright Notice Copyright © 2017, congatec AG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from congatec AG. congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied “as-is”. Warranty congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited warranty (“Limited Warranty”) per the terms and conditions of the congatec entity, which the product is delivered from. These terms and conditions can be downloaded from www.congatec.com. congatec AG may in its sole discretion modify its Limited Warranty at any time and from time to time. The products may include software. Use of the software is subject to the terms and conditions set out in the respective owner’s license agreements, which are available at www.congatec.com and/or upon request. Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec’s option and expense. Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer. Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged or replaced product is shipped by congatec, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to congatec’s direct customer only and is not assignable or transferable. Except as set forth in writing in the Limited Warranty, congatec makes no performance representations, warranties, or guarantees, either express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade. congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec shall not otherwise be liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive remedy against congatec, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the product only.

TSKLm16 6/71 Certification congatec AG is certified to DIN EN ISO 9001 standard. Technical Support congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products can be easily used and implemented. We request that you first visit our website at www.congatec.com for the latest documentation, utilities and drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support department by email at [email protected] Terminology Term Description GB Gigabyte GHz Gigahertz kB Kilobyte MB Megabyte Mb Megabit kHz Kilohertz MHz Megahertz TDP Thermal Design Power PCIe PCI Express SATA Serial ATA PEG PCI Express Graphics PCH Platform Controller Hub eDP Embedded DisplayPort DDI Digital Display Interface HDA High Definition Audio N.C Not connected N.A Not available TBD To be determined C E R T I F I C A T I O N I S O 9 0 0 1 TM

TSKLm16 7/71 Contents 1 Introduction .............................................................................10 1.1 COM Express™ Concept .........................................................10 1.2 Options Information .................................................................11 2 Specifications ...........................................................................12 2.1 Feature List ..............................................................................12 2.2 Supported Operating Systems ................................................13 2.3 Mechanical Dimensions ...........................................................13 2.4 Supply Voltage Standard Power ..............................................14 2.4.1 Electrical Characteristics ..........................................................14 2.4.2 Rise Time .................................................................................14 2.5 Power Consumption ................................................................15 2.6 Supply Voltage Battery Power .................................................16 2.7 Environmental Specifications ...................................................17 3 Block Diagram ..........................................................................18 4 Cooling Solutions .....................................................................19 4.1 CSA Dimensions ......................................................................20 4.2 CSP Dimensions .......................................................................21 4.3 HSP Dimensions .......................................................................22 4.4 Heatspreader Thermal Imagery ...............................................23 5 Onboard Temperature Sensors ................................................24 6 Connector Rows .......................................................................26 6.1 Primary and Secondary Connector Rows .................................26 6.1.1 PCI Express™ ...........................................................................26 6.1.2 PCI Express Graphics (PEG) .....................................................26 6.1.3 Display Interfaces .....................................................................27 6.1.3.1 DisplayPort (DP) .......................................................................28 6.1.3.2 LVDS/eDP .................................................................................29 6.1.3.3 VGA..........................................................................................29 6.1.4 SATA™ .....................................................................................29 6.1.5 USB ..........................................................................................30 6.1.6 Gigabit Ethernet .....................................................................30 6.1.7 High Definition Audio (HDA) Interface ....................................30 6.1.8 LPC Bus ....................................................................................30 6.1.9 I²C Bus .....................................................................................31 6.1.10 ExpressCard™ .........................................................................31 6.1.11 General Purpose Serial Interface .............................................31 6.1.12 GPIOs .......................................................................................31 6.1.13 Power Control ..........................................................................31 6.1.14 Power Management .................................................................35 7 Additional Features ..................................................................36 7.1 congatec Board Controller (cBC) .............................................36 7.1.1 Board Information ....................................................................36 7.1.2 General Purpose Input/Output ................................................36 7.1.3 Watchdog ................................................................................36 7.1.4 I2C Bus ......................................................................................36 7.1.5 Power Loss Control ..................................................................37 7.1.6 Fan Control ..............................................................................37 7.2 OEM BIOS Customization ........................................................37 7.2.1 OEM Default Settings ..............................................................37 7.2.2 OEM Boot Logo .......................................................................38 7.2.3 OEM POST Logo .....................................................................38 7.2.4 OEM BIOS Code/Data .............................................................38 7.2.5 OEM DXE Driver ......................................................................38 7.3 congatec Battery Management Interface ................................39 7.4 API Support (CGOS) ................................................................39 7.5 Security Features ......................................................................39 7.6 Suspend to Ram .......................................................................39 8 conga Tech Notes ....................................................................40 8.1 Intel® Processor Features .........................................................40 8.1.1 Adaptive Thermal Monitor and Catastrophic Thermal Protection 40 8.1.2 Intel® Turbo Boost Technology ................................................41 8.1.3 Intel® Virtualization Technology ...............................................41

TSKLm16 8/71 8.1.4 Thermal Management .............................................................42 8.1.5 Processor Performance Control ...............................................42 8.2 ACPI Suspend Modes and Resume Events ..............................43 8.3 DDR4 Memory .........................................................................43 9 Signal Descriptions and Pinout Tables .....................................44 9.1 Connector Signal Descriptions ................................................45 9.2 Boot Strap Signals ...................................................................66 10 System Resources ....................................................................67 10.1 I/O Address Assignment ..........................................................67 10.1.1 LPC Bus ....................................................................................67 10.2 PCI Configuration Space Map .................................................68 10.3 I2C ............................................................................................69 10.4 SM Bus .....................................................................................69 11 BIOS Setup Description ...........................................................70 11.1 Navigating the BIOS Setup Menu ...........................................70 11.2 BIOS Versions...........................................................................70 11.3 Updating the BIOS ...................................................................71 11.4 Recovering from External Flash ...............................................71 11.5 Supported Flash Devices .........................................................71

TSKLm16 9/71 List of Tables Table 1 COM Express™ 2.1 Pinout Types ............................................10 Table 2 conga-TS175 Variants ..............................................................11 Table 3 Feature Summary .....................................................................12 Table 4 Measurement Description ........................................................15 Table 5 Power Consumption Values .....................................................16 Table 6 CMOS Battery Power Consumption ........................................16 Table 7 Cooling Solution Variants .........................................................19 Table 8 Maximum Supported Resolutions ............................................28 Table 9 Wake Events .............................................................................43 Table 10 Signal Tables Terminology Descriptions ..................................44 Table 11 Connector A–B Pinout .............................................................45 Table 12 Connector C–D Pinout .............................................................47 Table 13 PCI Express Signal Descriptions (general purpose) .................49 Table 14 PCI Express Signal Descriptions (x16 Graphics) .......................50 Table 15 DDI Signal Description .............................................................52 Table 16 TMDS Signal Descriptions .......................................................54 Table 17 DisplayPort (DP) Signal Descriptions .......................................55 Table 18 Embedded DisplayPort Signal Descriptions ............................56 Table 19 CRT Signal Descriptions ...........................................................57 Table 20 LVDS Signal Descriptions .........................................................57 Table 21 Serial ATA Signal Descriptions .................................................58 Table 22 USB 2.0 Signal Descriptions .....................................................58 Table 23 USB 3.0 Signal Descriptions .....................................................59 Table 24 Gigabit Ethernet Signal Descriptions.......................................60 Table 25 Intel® High Definition Audio Link Signals Descriptions ............60 Table 26 ExpressCard Support Pins Signal Descriptions ........................61 Table 27 LPC Signal Descriptions ...........................................................61 Table 28 SPI BIOS Flash Interface Signal Descriptions ...........................61 Table 29 Miscellaneous Signal Descriptions ...........................................62 Table 30 General Purpose I/O Signal Descriptions ................................62 Table 31 Power and System Management Signal Descriptions .............63 Table 32 General Purpose Serial Interface Signal Descriptions ..............64 Table 33 Module Type Definition Signal Description .............................64 Table 34 Power and GND Signal Descriptions .......................................65 Table 35 Boot Strap Signal Descriptions ................................................66 Table 36 PCI Configuration Space Map .................................................68

TSKLm16 10/71 1 Introduction 1.1 COM Express™ Concept COM Express™ is an open industry standard defined specifically for COMs (computer on modules). Its creation makes it possible to smoothly transition from legacy interfaces to the newest technologies available today. COM Express™ modules are available in following form factors: • Mini 84 mm x 55 mm • Compact 95 mm x 95 mm • Basic 125 mm x 95 mm • Extended 155 mm x 110 mm Table 1 COM Express™ 2.1 Pinout Types Types Connector Rows PCIe Lanes PCI IDE SATA Ports LAN ports USB 2.0/ USB 3.0 Display Interfaces Type 1 A-B Up to 6 - 4 1 8 / 0 VGA, LVDS Type 2 A-B C-D Up to 22 32 bit 1 4 1 8 / 0 VGA, LVDS, PEG/SDVO Type 3 A-B C-D Up to 22 32 bit - 4 3 8 / 0 VGA,LVDS, PEG/SDVO Type 4 A-B C-D Up to 32 1 4 1 8 / 0 VGA,LVDS, PEG/SDVO Type 5 A-B C-D Up to 32 - 4 3 8 / 0 VGA,LVDS, PEG/SDVO Type 6 A-B C-D Up to 24 - 4 1 8 / 4* VGA,LVDS/eDP, PEG, 3x DDI Type 10 A-B Up to 4 - 2 1 8 / 0 LVDS/eDP, 1xDDI * The SuperSpeed USB ports (USB 3.0) are not in addition to the USB 2.0 ports. Up to 4 of the USB 2.0 ports can support SuperSpeed USB. The conga-TS175 modules use the Type 6 pinout definition and comply with COM Express 2.1 specification. They are equipped with two high performance connectors that ensure stable data throughput. The COM (computer on module) integrates all the core components and is mounted onto an application specific carrier board. COM modules are legacy-free design (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application. These functions include, but are not limited to a rich complement of contemporary high bandwidth serial interfaces such as PCI Express, Serial ATA, USB 2.0, and Gigabit Ethernet. The Type 6 pinout provides the ability to offer PCI Express, Serial ATA, and LPC options thereby expanding the range of potential peripherals. The robust thermal and mechanical concept, combined with extended power-management capabilities, is perfectly suited for all applications. Carrier board designers can use as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™

TSKLm16 11/71 modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use of different performance class or form factor size modules. Simply unplug one module and replace it with another; no redesign is necessary. 1.2 Options Information The conga-TS175 is currently available in seven variants. The table below shows the different configurations available. Table 2 conga-TS175 Variants Part-No. 045950 045951 045952 045953 045954 Processor Intel® Core™ i7-7820EQ 3.0 GHz Quad Core™ Intel® Core™ i5-7440EQ 2.9 GHz Quad core Intel® Core™ i5-7442EQ 2.1 GHz Quad Core™ Intel® Core™ i3-7100E 2.9 GHz Dual Core™ Intel® Core™ i3-7102E 2.1 GHz, Dual Core™ Max. Turbo Frequency 3.7 GHz 3.6 GHz 2.9 GHz N.A N.A Chipset Intel® QM175 Intel® QM175 Intel® QM175 Intel® HM175 Intel® HM175 Intel® Smart Cache 8 MB 6 MB 6 MB 3 MB 3 MB Processor Graphics Intel® HD Graphics 630 (GT2) Intel® HD Graphics 630 (GT2) Intel® HD Graphics 630 (GT2) Intel® HD Graphics 630 (GT2) Intel® HD Graphics 630 (GT2) GFX Base/Max. Dynamic Freq. 350 MHz / 1 GHz 350 MHz / 1 GHz 350 MHz / 1 GHz 350 MHz / 950 MHz 350 MHz / 950 MHz Memory (DDR4) 2400 MT/s Dual Channel 2400 MT/s Dual Channel 2400 MT/s Dual Channel 2400 MT/s Dual Channel 2400 MT/s Dual Channel LVDS Yes Yes Yes Yes Yes DP++ (DP/HDMI/DVI) Yes Yes Yes Yes Yes Processor TDP (cTDP) 45 W (35 W) 45 W (35 W) 25 W (N.A) 35 W (N.A) 25 W (N.A) Part-No. 045955 (ECC) 045956 (ECC) Processor Intel® Xeon® E3-1505MV6 3.0 GHz Quad Core™ Intel® Xeon® E3-1505LV6 2.2 GHz Quad Core™ Max. Turbo Frequency 4.0 GHz 3.0 GHz Chipset Intel® CM238 Intel® CM238 Intel® Smart Cache 8 MB 8 MB Processor Graphics Intel® HD Graphics P630 (GT2) Intel® HD Graphics P630 (GT2) GFX Base/Max. Dynamic Freq. 350 MHz / 1.1 GHz 350 MHz / 1 GHz Memory (DDR4) 2400 MT/s Dual Channel (ECC) 2400 MT/s Dual Channel (ECC) LVDS Yes Yes DP++ (DP/HDMI/DVI) Yes Yes Processor TDP (cTDP) 45 W (35 W) 25 W (N.A)

TSKLm16 12/71 2 Specifications 2.1 Feature List Table 3 Feature Summary Form Factor Based on COM Express™ standard pinout Type 6 Rev. 2.1 (Basic size 125 x 95 mm) Processor 7th Generation Intel® Core i7,i5,i3, Celeron and Xeon mobile processors Memory Two memory sockets (located on the top and bottom side of the conga-TS175). Supports - SO-DIMM non-ECC DDR4 modules - Data rates up to 2400 MT/s - Maximum 32 GB capacity (16 GB each) NOTE: Variants that feature the Intel CM238 chipset support ECC memory Chipset Mobile Intel® 100 Series Chipset QM175, HM175 and CM238 PCH Audio High definition audio interface with support for multiple codecs Ethernet Gigabit Ethernet (Intel® i219-LM controller) with AMT 11.6 support Graphics Options Next Generation Intel® HD (610/620). Supports: - API (DirectX 12, OpenGL 4.4, OpenCL 2.1) - Intel® QuickSync & Clear Video Technology HD (hardware accelerated video decode/encode/processing/transcode) - Switchable/Hybrid graphics - Up to 3 independent displays 3x DP++ (DP/HDMI/DVI) 1x LVDS 1x VGA 1x PEG x16 port (Gen 3) Resolutions up to 4K 1x Optional eDP 1.4 (assembly option) NOTE: The conga-TS175 does not natively support TMDS. A DP++ to TMDS converter (e.g. PTN3360D) needs to be implemented. Peripheral Interfaces USB Interfaces: - Up to 8x USB 2.0 - Up to 4x USB 3.0 4x SATA® (6 Gb/s with RAID 0/1/5 support) 8x PCI Express® Gen. 3 lanes *1 2x UART GPIOs LPC I2C (fast mode, multi-master) SMB SPI BIOS AMI Aptio® V UEFI 2.x firmware, 8 or 16 MB serial SPI with congatec Embedded BIOS features Power Management ACPI 5.0 compliant with battery support. Also supports DeepSx and Suspend to RAM (S3) congatec Board Controller Multi-stage watchdog, non-volatile user data storage, manufacturing and board information, board statistics, hardware monitoring, fan control, I²C bus, power loss control Security Optional discrete Trusted Platform Module “TPM 1.2/2.0”; AES Instructions Note Some features are optional.

TSKLm16 13/71 2.2 Supported Operating Systems The conga-TS175 supports the following operating systems. • Microsoft® Windows® 10 • WindRiver® VxWorks® (VX7 or later) • Linux Note 1. The processor supports only 64-bit operating systems. 2. The CSM (Compatibility Support Module) is disabled in the BIOS setup menu by default because we recommend to operate the system in native UEFI mode. 2.3 Mechanical Dimensions • 125.0 mm x 95.0 mm • Height approximately 18 or 21 mm (including heatspreader) depending on the carrier board connector that is used. If the 5 mm (height) carrier board connector is used, then approximate overall height is 18 mm. If the 8mm (height) carrier board connector is used, then approximate overall height is 21 mm. Heatspreader All dimensions in millimeter Module PCB Carrier Board PCB 13.00 4.00 5.00 4.50 2.00±10% 7.00 18.00

TSKLm16 14/71 2.4 Supply Voltage Standard Power • 12V DC ± 5% The dynamic range shall not exceed the static range. 2.4.1 Electrical Characteristics Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for pinout Type 6 (dual connector, 440 pins). Power Rail Module Pin Current Capability (Amps) Nominal Input (Volts) Input Range (Volts) Derated Input (Volts) Max. Input Ripple (10Hz to 20MHz) (mV) Max. Module Input Power (w. derated input) (Watts) Assumed Conversion Efficiency Max. Load Power (Watts) VCC_12V 12 12 11.4-12.6 11.4 +/- 100 137 85% 116 VCC_5V-SBY 2 5 4.75-5.25 4.75 +/- 50 9 VCC_RTC 0.5 3 2.5-3.3 +/- 20 2.4.2 Rise Time The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive. Nominal Static Range Dynamic Range Absolute Minimum Absolute Maximum 12.60V 11.40V 12V 12.10V 11.90V

TSKLm16 15/71 2.5 Power Consumption The power consumption values were measured with the following setup: • Input voltage +12 V • conga-TS175 COM • modified congatec carrier board • conga-TS175 cooling solution • Microsoft Windows 10 (64 bit) Note The CPU was stressed to its maximum workload. Table 4 Measurement Description The power consumption values were recorded during the following system states: System State Description Comment S0: Minimum value Lowest frequency mode (LFM) with minimum core voltage during desktop idle S0: Maximum value Highest frequency mode (HFM/Turbo Boost) The CPU was stressed to its maximum frequency S0: Peak current Highest current spike during the measurement of “S0: Maximum value”. This state shows the peak value during runtime Consider this value when designing the system’s power supply to ensure that sufficient power is supplied during worst case scenarios S3 COM is powered by VCC_5V_SBY S5 COM is powered by VCC_5V_SBY Note 1. The fan and SATA drives were powered externally. 2. All other peripherals except the LCD monitor were disconnected before measurement.

TSKLm16 16/71 Table 5 Power Consumption Values The table below provides additional information about the conga-TS175 power consumption. The values are recorded at various operating mode. Part No. Memory Size H.W Rev. BIOS Rev. OS (64 bit) CPU Current (A) Variant Cores Freq /Max Turbo (GHz) S0: Min S0: Max S0:Peak S3 S5 045950 4 GB B.0 R004 Windows 10 Intel® Core™ i7-7820EQ 4 3.0 / 3.7 0.63 5.93 6.53 0.09 0.06 045951 4 GB B.0 R004 Windows 10 Intel® Core™ i5-7440EQ 4 2.9 / 3.6 0.63 5.66 5.91 0.09 0.06 045952 4 GB B.0 R004 Windows 10 Intel® Core™ i5-7442EQ 4 2.1 / 2.9 0.62 3.03 3.41 0.09 0.06 045953 4 GB B.0 R004 Windows 10 Intel® Core™ i3-7100E 2 2.9 / N.A 0.62 3.41 4.00 0.09 0.06 045954 4 GB B.0 R004 Windows 10 Intel® Core™ i3-7102E 2 2.1 / N.A 0.61 2.36 2.79 0.09 0.06 045955 4 GB B.0 R004 Windows 10 Intel® Xeon® E3-1505MV6 4 3.0 / 4.0 0.61 5.56 6.28 0.09 0.06 045956 4 GB B.0 R004 Windows 10 Intel® Xeon® E3-1505LV6 4 2.2 / 3.0 0.62 3.15 3.49 0.09 0.06 2.6 Supply Voltage Battery Power Table 6 CMOS Battery Power Consumption RTC @ Voltage Current -10oC 3V DC 1.30 µA 20oC 3V DC 1.46 µA 70oC 3V DC 2.00 µA Note 1. Do not use the CMOS battery power consumption values listed above to calculate CMOS battery lifetime. 2. Measure the CMOS battery power consumption of your application in worst case conditions (for example, during high temperature and high battery voltage). 3. Consider the self-discharge of the battery when calculating the lifetime of the CMOS battery. For more information, refer to application note AN9_RTC_Battery_Lifetime.pdf on congatec AG website at www.congatec.com/support/application-notes. 4. We recommend to always have a CMOS battery present when operating the conga-TS175.

TSKLm16 17/71 2.7 Environmental Specifications Temperature Operation: 0° to 60°C Storage: -20° to +80°C Humidity Operation: 10% to 90% Storage: 5% to 95% Caution The above operating temperatures must be strictly adhered to at all times. When using a congatec heatspreader, the maximum operating temperature refers to any measurable spot on the heatspreader’s surface. Humidity specifications are for non-condensing conditions.

TSKLm16 18/71 3 Block Diagram 7th Gen. Intel® Core™ processor CPU Platform VT HT Technology 64 Architecture Turbo Boost 2.0 Technology TXT AES-NI AVX2 SSE 4.2 TSX Hardware Graphics Accelerators Video Codecs APIs Vector Graphics DXVA2 3D 2D MPEG-2 HEVC/H.265 VC1/WMV9 OpenCL 2.1 OpenGL 4.4 DirectX 12 Integrated Intel HD Graphics SATA USB 2.0 LPC Bus PCIe USB 3.0 HDA Multimedia Features ASRC I/O Interfaces DisplayPort 1.2 Display Interface TMDS Mobile Intel® 100 Series PCH-H MGMNT PECI PCIe Gen. 3 Aux Channel *1 PCIe Gen. 3 PECI SM Bus Dual Channel DDR4 eDP PCIe Gen. 3 eDP to LVDS Bridge 2x SO-DIMM (X1/X2) SPI Flash 0 LVDS/eDP TPM XDP LPC SATA 6G USB 2.0 HDA DMI Gen3 UART0/1 DP to VGA congatec System Management Controller Ethernet 10/100/1000 Intel i219LM Ethernet VGA LVDS/eDP COM Express Type 6 A-B Connector LPC Bus SM Bus HDA I/F I2C Bus USB Port 0..7 SATA Port 0 - 3 SER0/1 GPIOs SPI SPI LID#/SLEEP# FAN control PCIe lane 0 - 5 USB 3.0 Port 0 - 3 PCIe lane 6 - 7 (TX BC) congatec custom COM Express Type 6 C-D Connector DP++ (DP/TMDS) DP++ (DP/TMDS) DP++ (DP/TMDS) PEG x16 Note: *1 Supports only TMDS if VGA is enabled

TSKLm16 19/71 4 Cooling Solutions congatec AG offers the following cooling solutions for the conga-TS175 variants. The dimensions of the cooling solutions are shown in the sub-sections. All measurements are in millimeters. Table 7 Cooling Solution Variants Cooling Solution Part No. Description 1 CSA 045930 Active cooling solution with integrated heat pipes and 2.7 mm bore-hole standoffs 045931 Active cooling solution with integrated heat pipes and M2.5 mm threaded standoffs 2 CSP 045932 Passive cooling solution with integrated heat pipes and 2.7 mm bore-hole standoffs 045933 Passive cooling solution with integrated heat pipes and M2.5 mm threaded standoffs 3 HSP 045934 Heatspreader with integrated heat pipes and 2.7 mm bore-hole standoffs 045935 Heatspreader with integrated heat pipes and M2.5 mm threaded standoffs Note 1. We recommend a maximum torque of 0.4 Nm for carrier board mounting screws and 0.5 Nm for module mounting screws. 2. The gap pad material used on congatec heatspreaders may contain silicon oil that can seep out over time depending on the environmental conditions it is subjected to. For more information about this subject, contact your local congatec sales representative and request the gap pad material manufacturer’s specification Caution 1. The congatec heatspreaders/cooling solutions are tested only within the commercial temperature range of 0° to 60°C. Therefore, if your application that features a congatec heatspreader/cooling solution operates outside this temperature range, ensure the correct operating temperature of the module is maintained at all times. This may require additional cooling components for your final application’s thermal solution. 2. For adequate heat dissipation, use the mounting holes on the cooling solution to attach it to the module. Apply thread-locking fluid on the screws if the cooling solution is used in a high shock and/or vibration environment. To prevent the standoff from stripping or cross- threading, use non-threaded carrier board standoffs to mount threaded cooling solutions. 3. For applications that require vertically-mounted cooling solution, use only coolers that secure the thermal stacks with fixing post. Without the fixing post feature, the thermal stacks may move. 4. Do not exceed the recommended maximum torque. Doing so may damage the module or the carrier board, or both.

TSKLm16 20/71 4.1 CSA Dimensions 7,3 ±0,2 F 28 F 7,3 M2.5 x 13 mm threaded standoff for threaded version or ø2.7 x 13 mm non-threaded standoff for borehole version 87 29 95 96.6 21 20 31 14.5 125 58.5 76 79 117 12.5 15 2.7 0.62° 1.24° R0.3 R0.9 2.7

TSKLm16 21/71 4.2 CSP Dimensions 87 14.5 31 117 76 58.5 79 M2.5 x 13 mm threaded standoff for threaded version or ø2.7 x 13 mm non-threaded standoff for borehole version 20 28 95 125 28 15 E E 0.62° 1.24° R0.9 R0.3 2.7 2.7

TSKLm16 22/71 4.3 HSP Dimensions M2.5 x 11 mm threaded standoff for threaded version or ø2.7 x 11 mm non-threaded standoff for borehole version 87 11 95 4 56 41.5 58.5 76 79 117 125

TSKLm16 23/71 4.4 Heatspreader Thermal Imagery The conga-TS175 heatspreader solution features heat pipes. A heat pipe is a simple device that can quickly transfer heat from one point to another. They are often referred to as the “superconductors” of heat as they possess an extra ordinary heat transfer capacity and rate with almost no heat loss. The thermal image below provides a reference to where the heat is being transferred to on the heatspreader surface area. System designers must ensure that the system’s cooling solution is designed to dissipate the heat from the hottest surface spots of the heatspreader.

TSKLm16 24/71 5 Onboard Temperature Sensors The conga-TS175 features two sensors on the top side of the module and two optional DRAM sensors (build-time) on the top and bottom side of the module. Top-Side (CPU Temperature & Board Temperature Sensor) : The CPU temperature sensor (T00) is located in the CPU (U1). This sensor measures the CPU temperature and is defined in CGOS API as CGOS_TEMP_CPU. The board temperature sensor (T01) is located in the congatec Board Controller (U22). This sensor measures the board temperature and is defined in CGOS API as CGOS_TEMP_BOARD. The sensor locations are shown below: CPU Temperature Sensor U8 U22 U1 T00 T01 Board Controller Temp. Sensor Optional DRAM Sensor Location (BOM option)

TSKLm16 25/71 Bottom-Side (Optional DRAM Sensor): The conga-TS175 offers an optional sensor on the bottom side of the module. This sensor measures the temperature of the DRAM module and is defined in CGOS API as CGOS_TEMP_BOTDIMM_ENV. The DRAM sensor location is shown below: Note The optional DRAM sensors are not populated on conga-TS175 standard variants. The sensors are only available as assembly option. Optional DRAM Sensor Location (BOM option)

TSKLm16 26/71 6 Connector Rows The conga-TS175 is connected to the carrier board via two 220-pin connectors (COM Express Type 6 pinout). These connectors are broken down into four rows. The primary connector consists of rows A and B while the secondary connector consists of rows C and D. 6.1 Primary and Secondary Connector Rows The following subsystems can be found on the primary and secondary connector rows. 6.1.1 PCI Express™ The conga-TS175 offers six PCI Express™ lanes on the A–B connector and two lanes on the C–D connector. The lanes support: • up to 8 GT/s (Gen 3) speed • a 8 x1 link configuration • other link configurations (requires a special/customized BIOS firmware) • lane polarity inversion 6.1.2 PCI Express Graphics (PEG) The conga-TS175 offers a PCI Express™ Graphics interface on the C–D connector. The interface supports the following: • a 1 x16 (default), 2 x8 or 1 x8 + 2 x4 link configuration • up to 8 GT/s (Gen 3) speed • optional configuration to support graphics or non-graphic devices or both • a x1, x2, x4 or x8 PCIe device • up to three devices operating simultaneously on the PEG interface • lane reversal

TSKLm16 27/71 The possible configurations are 1 x16 link (default), 2 x8 links or 1 x8 + 2 x4 links as shown in the diagram below: Note The PEG lanes can not be linked together with the PCI Express lanes discussed in section 6.1.1 “PCI Express™”. 6.1.3 Display Interfaces The conga-TS175 supports the following: • up to three DP++ (DP/HDMI/DVI) • single- or dual-channel LVDS • VGA • three independent displays Table 8 shows the supported display combinations and resolutions. PEG LANE 0 Single Link (1x16 Link) Link 1 Link 1 Link 1 Link 2 Link 3 Link 2 Double Links (2x8 Links) Triple Links (1x8 + 2x4 Links) PEG LANE 1 PEG LANE 2 PEG LANE 3 PEG LANE 4 PEG LANE 5 PEG LANE 6 PEG LANE 7 PEG LANE 8 PEG LANE 9 PEG LANE 10 PEG LANE 11 PEG LANE 12 PEG LANE 13 PEG LANE 14 PEG LANE 15

TSKLm16 28/71 Table 8 Maximum Supported Resolutions Display 1 Display 2 Display 3 Interface Max. Resolution Interface Max. Resolution Interface Max. Resolution Option 1 DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp Option 2 DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp LVDS or eDP (BOM Option) 1920x1200 @ 60Hz (dual LVDS mode) 4096x2304 @ 60Hz, 24bpp Option 3 DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp VGA 1920x1200 @ 60Hz Option 4 DP or TMDS 4096x2304 @ 60Hz, 24 bpp/ 4096x2160 @ 30Hz, 24 bpp VGA 1920x1200 @ 60Hz LVDS or eDP (BOM Option) 1920x1200 @ 60Hz (dual LVDS mode) 4096x2304 @ 60Hz, 24bpp Note 1. If VGA interface is enabled in the BIOS menu, the third DDI interface (DDI3) will support only TMDS. 2. To enable VGA, go to Advanced -> Graphics menu and change the Digital Display Interface 3 option. 6.1.3.1 DisplayPort (DP) The conga-TS175 supports the following features: • up to three dual mode DP ports (DP++) • VESA DisplayPort Standard versions 1.2 • up to 4096x2304 resolutions at 60 Hz • audio formats such as linear PCM, Dolby Digital (AC-3), Dolby TrueHD, DTS, DTS-HD Master Audio and up to 8 channels • up to three independent DP displays Note A maximum of two independent DP displays are supported if the VGA interface is enabled.

TSKLm16 29/71 6.1.3.2 LVDS/eDP The conga-TS175 offers an LVDS interface. The interface supports the following: • optional eDP overlay on the A–B connector via a hardware change (assembly option) • single or dual channel LVDS (color depths of 18 bpp or 24 bpp) • integrated flat panel interface with clock frequency up to 112 MHz • VESA and OpenLDI LVDS color mappings • automatic panel detection via Embedded Panel Interface based on VESA EDIDTM 1.3 • resolution up to 1920x1200 in dual LVDS bus mode Note The LVDS/eDP interface supports either LVDS or eDP signals. Both interfaces are not supported simultaneously. 6.1.3.3 VGA The conga-TS175 offers a VGA interface via an eDP to VGA converter, connected to the two upper data lanes of the embedded DisplayPort. Note To enable VGA interface, set the Digital Display Interface 3 to HDMI/DVI from the BIOS menu. 6.1.4 SATA™ The conga-TS175 offers four SATA interfaces (SATA 0-3) on the A–B connector. The interfaces support: • independent DMA operation • data transfer rates up to 6.0 Gb/s • AHCI mode using memory space and RAID mode • Hot-plug detect

TSKLm16 30/71 6.1.5 USB The conga-TS175 offers eight USB 2.0 interfaces on the A–B connector and four SuperSpeed signals on the C–D connector. The xHCI host controller supports: • USB 3.0 specification • SuperSpeed, High-Speed, Full-Speed and Low-Speed USB signaling • data transfers of up to 5 Gb/s • supports USB debug port on all USB 3.0 capable ports Note The xHCI controller supports USB debug port on all USB 3.0 capable ports. 6.1.6 Gigabit Ethernet The conga-TS175 offers a Gigabit Ethernet interface via an onboard Intel® i219-LM Phy. The interface supports full-duplex operation at 10/100/1000 Mb/s and half-duplex operation at 10/100 Mb/s. Note 1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation of Ethernet Phy since it has only three LED outputs—ACT#, LINK100# and LINK1000#. 2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS175 module. 6.1.7 High Definition Audio (HDA) Interface The conga-TS175 provides an interface that supports the connection of HDA audio codecs. 6.1.8 LPC Bus The conga-TS175 offers the LPC (Low Pin Count) bus through the Intel® PCH-LP. For information about the decoded LPC addresses, see section 10.1.1.

TSKLm16 31/71 6.1.9 I²C Bus The I²C bus is implemented through the congatec board controller (Texas Instruments Tiva™ TM4E1231H6ZRB) and accessed through the congatec CGOS driver and API. The controller provides a fast-mode multi-master I²C bus that has the maximum I²C bandwidth. 6.1.10 ExpressCard™ The conga-TS175 supports the implementation of ExpressCards, which requires the dedication of one USB 2.0 port or a x1 PCI Express link for each ExpressCard used. 6.1.11 General Purpose Serial Interface The conga-TS175 offers two UART interfaces via the congatec Board Controller. These interfaces support up to 1 Mb/s and can operate in low- speed, full-speed and high-speed modes. The UART interfaces are routed to the A–B connector. They do not support hardware handshake and flow control. The UART interfaces require congatec device driver to function. 6.1.12 GPIOs The conga-TS175 offers General Purpose Input/Output signals on the A–B connector. The GPIO signals are controlled by the congatec Board controller. 6.1.13 Power Control PWR_OK Power OK from main power supply or carrier board voltage regulator circuitry. A high value indicates that the power is good and the module can start its onboard power sequencing. Carrier board hardware must drive this signal low until all power rails and clocks are stable. Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems. It is a good design practice to delay the PWR_OK signal a little (typically 100ms) after all carrier board power rails are up, to ensure a stable system. A sample screenshot is shown below:

TSKLm16 32/71 Note The module is kept in reset as long as the PWR_OK is driven by carrier board hardware.

TSKLm16 33/71 The conga-TS175 PWR_OK input circuitry is implemented as shown below: The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also makes it possible to use the module on carrier board designs that do not drive the PWR_OK signal. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier board hardware drives the signal low until it is safe to let the module boot-up. When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when the carrier board hardware is ready to boot. The three typical usage scenarios for a carrier board design are: • Connect PWR_OK to the “power good” signal of an ATX type power supply. • Connect PWR_OK to the last voltage regulator in the chain on the carrier board. • Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail. To Module Power Logic PWR_OK R1%47k5S02 TBC847 R1%10kS02 +V12.0_S0 R1%1k00S02 R1%47k5S02 R1%20k0S02

TSKLm16 34/71 With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable. The conga-TS175 supports the controlling of ATX-style power supplies. If you do not use an ATX power supply, do not connect the conga-TS175 pins SUS_S3/PS_ON, 5V_SB, and PWRBTN#. SUS_S3#/PS_ON# The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an ATX-style power supply. To accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and is located on the carrier board. PWRBTN# When using ATX-style power supplies, PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary-contact, active-low debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to 3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this signal from the system may vary as a result of modifications made in BIOS settings or by system software. Standard 12V Power Supply Implementation Guidelines 12 volt input power is the sole operational power source for the conga-TS175. The remaining necessary voltages are generated internally on the module using onboard voltage regulators. A carrier board designer should be aware of the following important information when designing a power supply for a conga-TS175 application: • We noticed that occasionally problems occur when using a 12 V power supply that produces non monotonic voltage when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a malfunction. This problem is rare but has been observed in some mobile power supply applications. To ensure that this problem does not occur, observe the power supply rise waveform with an oscilloscope to determine if the rise is indeed monotonic and does not have any dips. Do this during the power supply qualification phase to ensure that the above mentioned problem does not occur in the application. For more information, see the “Power Supply Design Guide for Desktop Platform Form Factors” document at www.intel.com.

TSKLm16 35/71 6.1.14 Power Management ACPI The conga-TS175 supports Advanced Configuration and Power Interface (ACPI) specification, revision 5.0. It also supports Suspend to RAM (S3). For more information, see section 8.2 “ACPI Suspend Modes and Resume Events”. DEEP Sx The Deep Sx is a lower power state employed to minimize the power consumption while in S3/S4/S5. In the Deep Sx state, the system entry condition determines if the system context is maintained or not. All power is shut off except for minimal logic which supports limited set of wake events for Deep Sx. The Deep Sx on resumption, puts system back into the state it is entered from. In other words, if Deep Sx state was entered from S3 state, then the resume path will place system back into S3.

TSKLm16 36/71 7 Additional Features 7.1 congatec Board Controller (cBC) The conga-TS175 is equipped with Texas Instruments Tiva™ TM4E123GH6ZRBI7R microcontroller. This onboard microcontroller plays an important role for most of the congatec embedded/industrial PC features. It fully isolates some of the embedded features such as system monitoring or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86 processor is in a low power mode. It also ensures that the congatec embedded feature set is fully compatible amongst all congatec modules. The board controller supports the following features: 7.1.1 Board Information The cBC provides a rich data-set of manufacturing and board information such as serial number, EAN number, hardware and firmware revisions, and so on. It also keeps track of dynamically changing data like runtime meter and boot counter. 7.1.2 General Purpose Input/Output The conga-TS175 offers general purpose inputs and outputs for custom system design. These GPIOs are controlled by the cBC. 7.1.3 Watchdog The conga-TS175 is equipped with a multi-stage watchdog solution that is triggered by software. For more information about the Watchdog feature, see the application note AN3_Watchdog.pdf on the congatec AG website at www.congatec.com. Note The conga-TS175 module does not support the watchdog NMI mode. 7.1.4 I2C Bus The conga-TS175 supports I2C bus. Thanks to the I2C host controller in the cBC, the I2C bus is multi-master capable and runs at fast mode.

TSKLm16 37/71 7.1.5 Power Loss Control The cBC has full control of the power-up of the module and therefore can be used to specify the behavior of the system after an AC power loss condition. Supported modes are “Always On”, “Remain Off” and “Last State”. 7.1.6 Fan Control The conga-TS175 has additional signals and functions to further improve system management. One of these signals is an output signal called FAN_PWMOUT that allows system fan control using a PWM (Pulse Width Modulation) output. Additionally, there is an input signal called FAN_TACHOIN that provides the ability to monitor the system’s fan RPMs (revolutions per minute). This signal must receive two pulses per revolution in order to produce an accurate reading. For this reason, a two pulse per revolution fan or similar hardware solution is recommended. Note 1. A four wire fan must be used to generate the correct speed readout. 2. For the correct fan control (FAN_PWMOUT, FAN_TACHIN) implementation, see the COM Express Design Guide. 7.2 OEM BIOS Customization The conga-TS175 is equipped with congatec Embedded BIOS, which is based on American Megatrends Inc. Aptio UEFI firmware. The congatec Embedded BIOS allows system designers to modify the BIOS. For more information about customizing the congatec Embedded BIOS, refer to the congatec System Utility user’s guide CGUTLm1x.pdf on the congatec website at www.congatec.com or contact technical support. The customization features supported are described below: 7.2.1 OEM Default Settings This feature allows system designers to create and store their own BIOS default configuration. Customized BIOS development by congatec for OEM default settings is no longer necessary because customers can easily perform this configuration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_OEM_Default_Map.pdf on the congatec website for details on how to add OEM default settings to the congatec Embedded BIOS.

TSKLm16 38/71 7.2.2 OEM Boot Logo This feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo. Customized BIOS development by congatec for OEM Boot Logo is no longer necessary because customers can easily perform this configuration by themselves using the congatec system utility CGUTIL. See congatec application note AN8_Create_And_Add_Bootlogo.pdf on the congatec website for details on how to add OEM boot logo to the congatec Embedded BIOS. 7.2.3 OEM POST Logo This feature allows system designers to replace the congatec POST logo displayed in the upper left corner of the screen during BIOS POST with their own BIOS POST logo. Use the congatec system utility CGUTIL 1.5.4 or later to replace/add the OEM POST logo. 7.2.4 OEM BIOS Code/Data With the congatec embedded BIOS it is possible for system designers to add their own code to the BIOS POST process. The congatec Embedded BIOS first calls the OEM code before handing over control to the OS loader. Except for custom specific code, this feature can also be used to support, Windows 7, Windows 8 OEM activation (OA3.0), verb tables for HDA codecs, PCI/PCIe OpROMs, bootloaders, rare graphic modes and Super I/O controller initialization. Note The OEM BIOS code of the new UEFI based firmware is only called when the CSM (Compatibility Support Module) is enabled in the BIOS setup menu. Contact congatec technical support for more information on how to add OEM code. 7.2.5 OEM DXE Driver This feature allows designers to add their own UEFI DXE driver to the congatec embedded BIOS. Contact congatec technical support for more information on how to add an OEM DXE driver.

TSKLm16 39/71 7.3 congatec Battery Management Interface To facilitate the development of battery powered mobile systems based on embedded modules, congatec AG defined an interface for the exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according to the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable operating system (for example, charge state of the battery, information about the battery, alarms/events for certain battery states and so on) without the need for additional modifications to the system BIOS. In addtion to the ACPI-Compliant Control Method Battery mentioned above, the latest versions of the conga-TS175 BIOS and board controller firmware also support LTC1760 battery manager from Linear Technology and a battery only solution (no charger). All three battery solutions are supported on the I2C bus and the SMBus. This gives the system designer more flexibility when choosing the appropriate battery sub-system. For more information about this subject visit the congatec website and view the following documents: • congatec Battery Management Interface Specification • Battery System Design Guide • conga-SBM3 User’s Guide 7.4 API Support (CGOS) In order to benefit from the above mentioned non-industry standard feature set, congatec provides an API that allows application software developers to easily integrate all these features into their code. The CGOS API (congatec Operating System Application Programming Interface) is the congatec proprietary API that is available for all commonly used Operating Systems such as Win32, Win64, Win CE, Linux. The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules. All the hardware related code is contained within the congatec embedded BIOS on the module. See section 1.1 of the CGOS API software developers guide, available on the congatec website. 7.5 Security Features The conga-TS175 can be equipped optionally with a “Trusted Platform Module“ (TPM 1.2/2.0). This TPM 1.2/2.0 includes coprocessors to calculate efficient hash and RSA algorithms with key lengths up to 2,048 bits as well as a real random number generator. Security sensitive applications like gaming and e-commerce will benefit also with improved authentication, integrity and confidence levels. 7.6 Suspend to Ram The conga-TS175 supports Suspend to RAM feature.

TSKLm16 40/71 8 conga Tech Notes The conga-TS175 has some technological features that require additional explanation. The following section will give the reader a better understanding of some of these features. 8.1 Intel® Processor Features 8.1.1 Adaptive Thermal Monitor and Catastrophic Thermal Protection Intel® Xeon, Core™ i7/i5/i3 and Celeron® processors have a thermal monitor feature that helps to control the processor temperature. The integrated TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation temperature that the Intel® Thermal Monitor uses to activate the TCC can be slightly modified via TCC Activation Offset in BIOS setup submenu “CPU submenu”. The Adaptive Thermal Monitor controls the processor temperature using two methods: • Adjusting the processor’s operating frequency and core voltage (EIST transitions) • Modulating (start/stop) the processor’s internal clocks at a duty cycle of 25% on and 75% off When activated, the TCC causes both processor core and graphics core to reduce frequency and voltage adaptively. The Adaptive Thermal Monitor will remain active as long as the package temperature remains at its specified limit. Therefore, the Adaptive Thermal Monitor will continue to reduce the package frequency and voltage until the TCC is de-activated. Clock modulation is activated if frequency and voltage adjustments are insufficient. Additional hardware, software drivers, or operating system support is not required. Note 1. For THERMTRIP# to switch off the system automatically, use an ATX style power supply 2. The maximum operating temperature for Intel® Xeon, Core™ i7/i5/i3 and Celeron® processors is 100°C 3. To ensure that the TCC is active for only short periods of time, thus reducing the impact on processor performance to a minimum, it is necessary to have a properly designed thermal solution. The Intel® Xeon, Core™ i7/i5/i3 and Celeron® processor’s respective datasheet can provide you with more information about this subject.

TSKLm16 41/71 8.1.2 Intel® Turbo Boost Technology Intel® Turbo Boost Technology allows processor cores to run faster than the base operating frequency if it’s operating below power, current, and temperature specification limits. Intel® Turbo Boost Technology is activated when the Operating System (OS) requests the highest processor performance state. The maximum frequency of Intel® Turbo Boost Technology is dependent on the number of active cores. The amount of time the processor spends in the Intel Turbo Boost 2 Technology state depends on the workload and operating environment. Any of the following can set the upper limit of Intel® Turbo Boost Technology on a given workload: • Number of active cores • Estimated current consumption • Estimated power consumption • Processor temperature When the processor is operating below these limits and the user’s workload demands additional performance, the processor frequency will dynamically increase by 100 MHz on short and regular intervals until the upper limit is met or the maximum possible upside for the number of active cores is reached. For more information about Intel® Turbo Boost 2 Technology visit the Intel® website. Note Only conga-TS175 variants that feature the Xeon, Core™ i7 and i5 processors support Intel® Turbo Boost 2 Technology. Refer to the power consumption tables in section 2.5 “Power Consumption” for information about the maximum turbo frequency available for each variant of the conga-TS175. 8.1.3 Intel® Virtualization Technology Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. With this technology, multiple, independent operating systems can run simultaneously on a single system. The technology components support virtualization of platforms based on Intel architecture microprocessors and chipsets. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) added hardware support in the processor to improve the virtualization performance and robustness. RTS Real-Time Hypervisor supports Intel VT and is verified on all current congatec x86 hardware. Note congatec supports RTS Hypervisor.

TSKLm16 42/71 8.1.4 Thermal Management ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands put on the CPU by the application. The conga-TS175 supports Critical Trip Point. This cooling policy ensures that the operating system shuts down properly if the temperature in the thermal zone reaches a critical point, in order to prevent damage to the system as a result of high temperatures. Use the “critical trip point” setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system. The Automatic Critical Trip Point BIOS setting shuts down the system 5°C above the maximum specified temperature of the processor. To cool the processor passively, use the Thermal Control Circuit (TCC ) Activation Offset setting in the CPU configuration setup sub-menu. The TCC in the processor is activated at 100°C by default but can be lowered by the Activation Offset - for example, setting 10 activates TCC at 90°C. ACPI OS support is not required. Note Use the setup nodes in the BIOS setup program to establish the appropriate trip points. 8.1.5 Processor Performance Control Intel® processors found on the conga-TS175 run at different voltage/frequency states (performance states), which is referred to as Enhanced Intel® SpeedStep® technology (EIST). Operating systems that support performance control take advantage of microprocessors that use several different performance states in order to efficiently operate the processor when it’s not being fully used. The operating system will determine the necessary performance state that the processor should run at so that the optimal balance between performance and power consumption can be achieved during runtime. The Windows family of operating systems links its processor performance control policy to the power scheme setting. You must ensure that the power scheme setting you choose has the ability to support Enhanced Intel® SpeedStep® technology. The 7th Generation Intel® Core™ processor family supports Intel Speed Shift, a new and energy efficient method for frequency control. This feature is also referred to as Hardware-controlled Performance States (HWP). It is a hardware implementation of the ACPI defined Collaborative Processor Performance Control (CPPC2) and is supported by newer operating systems (Win 8.1 or newer). With this feature enabled, the processor autonomously selects performance states based on workload demand and thermal limits while also considering information provided by the OS e.g., the performance limits and workload history.

TSKLm16 43/71 8.2 ACPI Suspend Modes and Resume Events The conga-TS175 BIOS supports S3 (Suspend to RAM). The BIOS does not support S4 (Suspend to Disk). Table 9 Wake Events The table below lists the events that wake the system from S3. Wake Event Conditions/Remarks Power Button Wakes unconditionally from S3-S5. Onboard LAN Event Device driver must be configured for Wake On LAN support. SMBALERT# Wakes unconditionally from S3-S5. PCI Express WAKE# Wakes unconditionally from S3-S5. WAKE# Wakes unconditionally from S3. PME# Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On PME# to Enabled in the Power setup menu. USB Mouse/Keyboard Event When Standby mode is set to S3, USB hardware must be powered by standby power source. Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu (if setup node is available in BIOS setup program). In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check ‘Allow this device to bring the computer out of standby’. RTC Alarm Activate and configure Resume On RTC Alarm in the Power setup menu. Only available in S5. Watchdog Power Button Event Wakes unconditionally from S3-S5. 8.3 DDR4 Memory The conga-TS175 supports DDR4 memory modules up to 2400 MT/s. The DDR4 memory modules have lower voltage requirements with higher data rate transfer speeds. They operate at a voltage of 1.2V. With this low voltage system memory interface on the processor, the conga-TS175 offers a system optimized for lowest possible power consumption. The reduction in power consumption due to lower voltage subsequently reduces the heat generated. Note Use memory modules with same specifications, same type and model.

TSKLm16 44/71 9 Signal Descriptions and Pinout Tables The following section describes the signals found on COM Express™ Type VI connectors used for congatec AG modules. The pinout of the modules complies with COM Express Type 6 Rev. 2.1. Table 3 describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a COM Express™ module pull-up or pull-down resistor has been used. If the field entry area in this column for the signal is empty, then no pull-up or pull-down resistor has been implemented by congatec. The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level. Note The Signal Description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs implemented by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to the respective chip’s datasheet. Table 10 Signal Tables Terminology Descriptions Term Description PU congatec implemented pull-up resistor PD congatec implemented pull-down resistor I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant I/O 3.3VSB Input 3.3V tolerant active in standby state O 3.3V Output 3.3V signal level O 5V Output 5V signal level OD Open drain output P Power Input/Output DDC Display Data Channel PCIE In compliance with PCI Express Base Specification, Revision 2.0 PEG PCI Express Graphics SATA In compliance with Serial ATA specification Revision 2.6 and 3.0. REF Reference voltage output. May be sourced from a module power plane. PDS Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal module capabilities (pinout type) to the Carrier Board.

TSKLm16 45/71 9.1 Connector Signal Descriptions Table 11 Connector A–B Pinout Pin Row A Pin Row B Pin Row A Pin Row B A1 GND (FIXED) B1 GND (FIXED) A56 PCIE_TX4- B56 PCIE_RX4- A2 GBE0_MDI3- B2 GBE0_ACT# A57 GND B57 GPO2 A3 GBE0_MDI3+ B3 LPC_FRAME# A58 PCIE_TX3+ B58 PCIE_RX3+ A4 GBE0_LINK100# B4 LPC_AD0 A59 PCIE_TX3- B59 PCIE_RX3- A5 GBE0_LINK1000# B5 LPC_AD1 A60 GND (FIXED) B60 GND (FIXED) A6 GBE0_MDI2- B6 LPC_AD2 A61 PCIE_TX2+ B61 PCIE_RX2+ A7 GBE0_MDI2+ B7 LPC_AD3 A62 PCIE_TX2- B62 PCIE_RX2- A8 GBE0_LINK# B8 LPC_DRQ0# A63 GPI1 B63 GPO3 A9 GBE0_MDI1- B9 LPC_DRQ1# A64 PCIE_TX1+ B64 PCIE_RX1+ A10 GBE0_MDI1+ B10 LPC_CLK A65 PCIE_TX1- B65 PCIE_RX1- A11 GND (FIXED) B11 GND (FIXED) A66 GND B66 WAKE0# A12 GBE0_MDI0- B12 PWRBTN# A67 GPI2 B67 WAKE1# A13 GBE0_MDI0+ B13 SMB_CK A68 PCIE_TX0+ B68 PCIE_RX0+ A14 GBE0_CTREF (*) B14 SMB_DAT A69 PCIE_TX0- B69 PCIE_RX0- A15 SUS_S3# B15 SMB_ALERT# A70 GND (FIXED) B70 GND (FIXED) A16 SATA0_TX+ B16 SATA1_TX+ A71 eDP_TX2+/LVDS_A0+ B71 LVDS_B0+ A17 SATA0_TX- B17 SATA1_TX- A72 eDP_TX2-/LVDS_A0- B72 LVDS_B0- A18 SUS_S4# B18 SUS_STAT# A73 eDP_TX1+/LVDS_A1+ B73 LVDS_B1+ A19 SATA0_RX+ B19 SATA1_RX+ A74 eDP_TX1-/LVDS_A1- B74 LVDS_B1- A20 SATA0_RX- B20 SATA1_RX- A75 eDP_TX0+/LVDS_A2+ B75 LVDS_B2+ A21 GND (FIXED) B21 GND (FIXED) A76 eDP_TX0-/LVDS_A2- B76 LVDS_B2- A22 SATA2_TX+ B22 SATA3_TX+ A77 eDP/LVDS_VDD_EN B77 LVDS_B3+ A23 SATA2_TX- B23 SATA3_TX- A78 LVDS_A3+ B78 LVDS_B3- A24 SUS_S5# B24 PWR_OK A79 LVDS_A3- B79 eDP/LVDS_BKLT_EN A25 SATA2_RX+ B25 SATA3_RX+ A80 GND (FIXED) B80 GND (FIXED) A26 SATA2_RX- B26 SATA3_RX- A81 eDP_TX3+/LVDS_A_CK+ B81 LVDS_B_CK+ A27 BATLOW# B27 WDT A82 eDP_TX3-/LVDS_A_CK- B82 LVDS_B_CK- A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 (*) A83 eDP_AUX+/LVDS_I2C_CK B83 eDP/LVDS_BKLT_CTRL A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 A84 eDP_AUX-/LVDS_I2C_DAT B84 VCC_5V_SBY A30 AC/HDA_RST# B30 AC/HDA_SDIN0 A85 GPI3 B85 VCC_5V_SBY A31 GND (FIXED) B31 GND (FIXED) A86 RSVD B86 VCC_5V_SBY A32 AC/HDA_BITCLK B32 SPKR A87 eDP_HPD B87 VCC_5V_SBY A33 AC/HDA_SDOUT B33 I2C_CK A88 PCIE0_CK_REF+ B88 BIOS_DIS1# A34 BIOS_DIS0# B34 I2C_DAT A89 PCIE0_CK_REF- B89 VGA_RED A35 THRMTRIP# B35 THRM# A90 GND (FIXED) B90 GND (FIXED) A36 USB6- B36 USB7- A91 SPI_POWER B91 VGA_GRN

TSKLm16 46/71 Pin Row A Pin Row B Pin Row A Pin Row B A37 USB6+ B37 USB7+ A92 SPI_MISO B92 VGA_BLU A38 USB_6_7_OC# B38 USB_4_5_OC# A93 GPO0 B93 VGA_HSYNC A39 USB4- B39 USB5- A94 SPI_CLK B94 VGA_VSYNC A40 USB4+ B40 USB5+ A95 SPI_MOSI B95 VGA_I2C_CK A41 GND (FIXED) B41 GND (FIXED) A96 TPM_PP B96 VGA_I2C_DAT A42 USB2- B42 USB3- A97 TYPE10# (*) B97 SPI_CS# A43 USB2+ B43 USB3+ A98 SER0_TX B98 RSVD A44 USB_2_3_OC# B44 USB_0_1_OC# A99 SER0_RX B99 RSVD A45 USB0- B45 USB1- A100 GND (FIXED) B100 GND (FIXED) A46 USB0+ B46 USB1+ A101 SER1_TX B101 FAN_PWMOUT A47 VCC_RTC B47 EXCD1_PERST# A102 SER1_RX B102 FAN_TACHIN A48 EXCD0_PERST# B48 EXCD1_CPPE# A103 LID# B103 SLEEP# A49 EXCD0_CPPE# B49 SYS_RESET# A104 VCC_12V B104 VCC_12V A50 LPC_SERIRQ B50 CB_RESET# A105 VCC_12V B105 VCC_12V A51 GND (FIXED) B51 GND (FIXED) A106 VCC_12V B106 VCC_12V A52 PCIE_TX5+ B52 PCIE_RX5+ A107 VCC_12V B107 VCC_12V A53 PCIE_TX5- B53 PCIE_RX5- A108 VCC_12V B108 VCC_12V A54 GPI0 B54 GPO1 A109 VCC_12V B109 VCC_12V A55 PCIE_TX4+ B55 PCIE_RX4+ A110 GND (FIXED) B110 GND (FIXED) Note The signals marked with asterisk symbol (*) are not connected on the conga-TS175.

TSKLm16 47/71 Table 12 Connector C–D Pinout Pin Row C Pin Row D Pin Row C Pin Row D C1 GND (FIXED) D1 GND (FIXED) C56 PEG_RX1- D56 PEG_TX1- C2 GND D2 GND C57 TYPE1# D57 TYPE2# C3 USB_SSRX0- D3 USB_SSTX0- C58 PEG_RX2+ D58 PEG_TX2+ C4 USB_SSRX0+ D4 USB_SSTX0+ C59 PEG_RX2- D59 PEG_TX2- C5 GND D5 GND C60 GND (FIXED) D60 GND (FIXED) C6 USB_SSRX1- D6 USB_SSTX1- C61 PEG_RX3+ D61 PEG_TX3+ C7 USB_SSRX1+ D7 USB_SSTX1+ C62 PEG_RX3- D62 PEG_TX3- C8 GND D8 GND C63 RSVD D63 RSVD C9 USB_SSRX2- D9 USB_SSTX2- C64 RSVD D64 RSVD C10 USB_SSRX2+ D10 USB_SSTX2+ C65 PEG_RX4+ D65 PEG_TX4+ C11 GND (FIXED) D11 GND (FIXED) C66 PEG_RX4- D66 PEG_TX4- C12 USB_SSRX3- D12 USB_SSTX3- C67 RSVD D67 GND C13 USB_SSRX3+ D13 USB_SSTX3+ C68 PEG_RX5+ D68 PEG_TX5+ C14 GND D14 GND C69 PEG_RX5- D69 PEG_TX5- C15 DDI1_PAIR6+ (*) D15 DDI1_CTRLCLK_AUX+ C70 GND (FIXED) D70 GND (FIXED) C16 DDI1_PAIR6- (*) D16 DDI1_CTRLDATA_AUX- C71 PEG_RX6+ D71 PEG_TX6+ C17 RSVD D17 RSVD C72 PEG_RX6- D72 PEG_TX6- C18 RSVD D18 RSVD C73 GND D73 GND C19 PCIE_RX6+ D19 PCIE_TX6+ C74 PEG_RX7+ D74 PEG_TX7+ C20 PCIE_RX6- D20 PCIE_TX6- C75 PEG_RX7- D75 PEG_TX7- C21 GND (FIXED) D21 GND (FIXED) C76 GND D76 GND C22 PCIE_RX7+ D22 PCIE_TX7+ C77 RSVD D77 RSVD C23 PCIE_RX7- D23 PCIE_TX7- C78 PEG_RX8+ D78 PEG_TX8+ C24 DDI1_HPD D24 RSVD C79 PEG_RX8- D79 PEG_TX8- C25 DDI1_PAIR4+ (*) D25 RSVD C80 GND (FIXED) D80 GND (FIXED) C26 DDI1_PAIR4- (*) D26 DDI1_PAIR0+ C81 PEG_RX9+ D81 PEG_TX9+ C27 RSVD D27 DDI1_PAIR0- C82 PEG_RX9- D82 PEG_TX9- C28 RSVD D28 RSVD C83 RSVD D83 RSVD C29 DDI1_PAIR5+ (*) D29 DDI1_PAIR1+ C84 GND D84 GND C30 DDI1_PAIR5- (*) D30 DDI1_PAIR1- C85 PEG_RX10+ D85 PEG_TX10+ C31 GND (FIXED) D31 GND (FIXED) C86 PEG_RX10- D86 PEG_TX10- C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+ C87 GND D87 GND C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2- C88 PEG_RX11+ D88 PEG_TX11+ C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL C89 PEG_RX11- D89 PEG_TX11- C35 RSVD D35 RSVD C90 GND (FIXED) D90 GND (FIXED) C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ C91 PEG_RX12+ D91 PEG_TX12+ C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- C92 PEG_RX12- D92 PEG_TX12- C38 DDI3_DDC_AUX_SEL D38 RSVD C93 GND D93 GND

TSKLm16 48/71 Pin Row C Pin Row D Pin Row C Pin Row D C39 DDI3_PAIR0+ D39 DDI2_PAIR0+ C94 PEG_RX13+ D94 PEG_TX13+ C40 DDI3_PAIR0- D40 DDI2_PAIR0- C95 PEG_RX13- D95 PEG_TX13- C41 GND (FIXED) D41 GND (FIXED) C96 GND D96 GND C42 DDI3_PAIR1+ D42 DDI2_PAIR1+ C97 RVSD D97 RSVD C43 DDI3_PAIR1- D43 DDI2_PAIR1- C98 PEG_RX14+ D98 PEG_TX14+ C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14- D99 PEG_TX14- C45 RSVD D45 RSVD C100 GND (FIXED) D100 GND (FIXED) C46 DDI3_PAIR2+ D46 DDI2_PAIR2+ C101 PEG_RX15+ D101 PEG_TX15+ C47 DDI3_PAIR2- D47 DDI2_PAIR2- C102 PEG_RX15- D102 PEG_TX15- C48 RSVD D48 RSVD C103 GND D103 GND C49 DDI3_PAIR3+ D49 DDI2_PAIR3+ C104 VCC_12V D104 VCC_12V C50 DDI3_PAIR3- D50 DDI2_PAIR3- C105 VCC_12V D105 VCC_12V C51 GND (FIXED) D51 GND (FIXED) C106 VCC_12V D106 VCC_12V C52 PEG_RX0+ D52 PEG_TX0+ C107 VCC_12V D107 VCC_12V C53 PEG_RX0- D53 PEG_TX0- C108 VCC_12V D108 VCC_12V C54 TYPE0# D54 PEG_LANE_RV# C109 VCC_12V D109 VCC_12V C55 PEG_RX1+ D55 PEG_TX1+ C110 GND (FIXED) D110 GND (FIXED) Note The signals marked with an asterisk symbol (*) are not supported on the conga-TS175.

TSKLm16 49/71 Table 13 PCI Express Signal Descriptions (general purpose) Signal Pin # Description I/O PU/PD Comment PCIE_RX0+ PCIE_RX0- B68 B69 PCI Express channel 0, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX0+ PCIE_TX0- A68 A69 PCI Express channel 0, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_RX1+ PCIE_RX1- B64 B65 PCI Express channel 1, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX1+ PCIE_TX1- A64 A65 PCI Express channel 1, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_RX2+ PCIE_RX2- B61 B62 PCI Express channel 2, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX2+ PCIE_TX2- A61 A62 PCI Express channel 2, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_RX3+ PCIE_RX3- B58 B59 PCI Express channel 3, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX3+ PCIE_TX3- A58 A59 PCI Express channel 3, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_RX4+ PCIE_RX4- B55 B56 PCI Express channel 4, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX4+ PCIE_TX4- A55 A56 PCI Express channel 4, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_RX5+ PCIE_RX5- B52 B53 PCI Express channel 5, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX5+ PCIE_TX5- A52 A53 PCI Express channel 5, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_RX6+ PCIE_RX6- C19 C20 PCI Express channel 6, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX6+ PCIE_TX6- D19 D20 PCI Express channel 6, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_RX7+ PCIE_RX7- C22 C23 PCI Express channel 7, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_TX7+ PCIE_TX7- D22 D23 PCI Express channel 7, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 3.0 PCIE_CLK_REF+ PCIE_CLK_REF- A88 A89 PCI Express Reference Clock output for all PCI Express and PCI Express Graphics Lanes. O PCIE A PCI Express Gen2/3 compliant clock buffer chip must be used on the carrier board if the design involves more than one PCI Express device.

TSKLm16 50/71 Table 14 PCI Express Signal Descriptions (x16 Graphics) Signal Pin # Description I/O PU/PD Comment PEG_RX0+ PEG_RX0- PEG_RX1+ PEG_RX1- PEG_RX2+ PEG_RX2- PEG_RX3+ PEG_RX3- PEG_RX4+ PEG_RX4- PEG_RX5+ PEG_RX5- PEG_RX6+ PEG_RX6- PEG_RX7+ PEG_RX7- PEG_RX8+ PEG_RX8- PEG_RX9+ PEG_RX9- PEG_RX10+ PEG_RX10- PEG_RX11+ PEG_RX11- PEG_RX12+ PEG_RX12- PEG_RX13+ PEG_RX13- PEG_RX14+ PEG_RX14- PEG_RX15+ PEG_RX15- C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72 C74 C75 C78 C79 C81 C82 C85 C86 C88 C89 C91 C92 C94 C95 C98 C99 C101 C102 PCI Express Graphics Receive Input differential pairs. Note: Can also be used as PCI Express Receive Input differential pairs 16 through 31 known as PCIE_RX[16-31] + and -. I PCIE

TSKLm16 51/71 Signal Pin # Description I/O PU/PD Comment PEG_TX0+ PEG_TX0- PEG_TX1+ PEG_TX1- PEG_TX2+ PEG_TX2- PEG_TX3+ PEG_TX3- PEG_TX4+ PEG_TX4- PEG_TX5+ PEG_TX5- PEG_TX6+ PEG_TX6- PEG_TX7+ PEG_TX7- PEG_TX8+ PEG_TX8- PEG_TX9+ PEG_TX9- PEG_TX10+ PEG_TX10- PEG_TX11+ PEG_TX11- PEG_TX12+ PEG_TX12- PEG_TX13+ PEG_TX13- PEG_TX14+ PEG_TX14- PEG_TX15+ PEG_TX15- D52 D53 D55 D56 D58 D59 D61 D62 D65 D66 D68 D69 D71 D72 D74 D75 D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs. Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31 known as PCIE_TX[16-31] + and -. O PCIE PEG_LANE_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane order. I PU 10k 3.3V PEG_LAN_RV# is a boot strap signal (see note below) Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”.

TSKLm16 52/71 Table 15 DDI Signal Description Signal Pin # Description I/O PU/PD Comment DDI1_PAIR0+ DDI1_PAIR0- D26 D27 Multiplexed with DP1_LANE0+ and TMDS1_DATA2+. Multiplexed with DP1_LANE0- and TMDS1_DATA2-. O PCIE DDI1_PAIR1+ DDI1_PAIR1- D29 D30 Multiplexed with DP1_LANE1+ and TMDS1_DATA1+. Multiplexed with DP1_LANE1- and TMDS1_DATA1-. O PCIE DDI1_PAIR2+ DDI1_PAIR2- D32 D33 Multiplexed with DP1_LANE2+ and TMDS1_DATA0+. Multiplexed with DP1_LANE2- and TMDS1_DATA0-. O PCIE DDI1_PAIR3+ DDI1_PAIR3- D36 D37 Multiplexed with DP1_LANE3+ and TMDS1_CLK+. Multiplexed with DP1_LANE3- and TMDS1_CLK-. O PCIE DDI1_PAIR4+ DDI1_PAIR4- C25 C26 Multiplexed with SDVO1_INT+. Multiplexed with SDVO1_INT-. Not supported DDI1_PAIR5+ DDI1_PAIR5- C29 C30 Multiplexed with SDVO1_TVCLKIN+. Multiplexed with SDVO1_TVCLKIN-. Not supported DDI1_PAIR6+ DDI1_PAIR6- C15 C16 Multiplexed with SDVO1_FLDSTALL+. Multiplexed with SDVO1_FLDSTALL-. Not supported DDI1_HPD C24 Multiplexed with DP1_HPD and HDMI1_HPD. I 3.3V PD 1M DDI1_CTRLCLK_AUX+ D15 Multiplexed with DP1_AUX+ and HMDI1_CTRLCLK. DP AUX+ function if DDI1_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high I/O PCIE I/O OD 3.3V PD100k DDI1_CTRLDATA_AUX- D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA. DP AUX- function if DDI1_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high I/O PCIE I/O OD 3.3V PU 100k 3.3V Boot strap signal (see note below). Enable strap is already populated. DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX+ and DDI1_CTRLDATA_AUX-. This pin shall have a IM pull-down to logic ground on the module. If this input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled- high, the AUX pair contains the CTRLCLK and CTRLDATA signals. I 3.3V PD 1M DDI2_PAIR0+ DDI2_PAIR0- D39 D40 Multiplexed with DP2_LANE0+ and TMDS2_DATA2+. Multiplexed with DP2_LANE0- and TMDS2_DATA2-. O PCIE DDI2_PAIR1+ DDI2_PAIR1- D42 D43 Multiplexed with DP2_LANE1+ and TMDS2_DATA1+. Multiplexed with DP2_LANE1- and TMDS2_DATA1-. O PCIE DDI2_PAIR2+ DDI2_PAIR2- D46 D47 Multiplexed with DP2_LANE2+ and TMDS2_DATA0+. Multiplexed with DP2_LANE2- and TMDS2_DATA0-. O PCIE DDI2_PAIR3+ DDI2_PAIR3- D49 D50 Multiplexed with DP2_LANE3+ and TMDS2_CLK+. Multiplexed with DP2_LANE3- and TMDS2_CLK-. O PCIE DDI2_HPD D44 Multiplexed with DP2_HPD and HDMI2_HPD. I 3.3V PD 1M DDI2_CTRLCLK_AUX+ C32 Multiplexed with DP2_AUX+ and HDMI2_CTRLCLK. DP AUX+ function if DDI2_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLCLK if DDI2_DDC_AUX_SEL is pulled high I/O PCIE I/O OD 3.3V PD 100k DDI2_CTRLDATA_AUX- C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA. DP AUX- function if DDI2_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high. I/O PCIE I/O OD 3.3V PU 100k 3.3V Boot strap signal (see note below). Enable strap is already populated.

TSKLm16 53/71 Signal Pin # Description I/O PU/PD Comment DDI2_DDC_AUX_SEL C34 Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-. This pin shall have a IM pull-down to logic ground on the module. If this input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled- high, the AUX pair contains the CTRLCLK and CTRLDATA signals I 3.3V DDI3_PAIR0+ DDI3_PAIR0- C39 C40 Multiplexed with DP3_LANE0+ and TMDS3_DATA2+. Multiplexed with DP3_LANE0- and TMDS3_DATA2-. O PCIE DDI3_PAIR1+ DDI3_PAIR1- C42 C43 Multiplexed with DP3_LANE1+ and TMDS3_DATA1+. Multiplexed with DP3_LANE1- and TMDS3_DATA1-. O PCIE DDI3_PAIR2+ DDI3_PAIR2- C46 C47 Multiplexed with DP3_LANE2+ and TMDS3_DATA0+. Multiplexed with DP3_LANE2- and TMDS3_DATA0-. O PCIE DDI3_PAIR3+ DDI3_PAIR3- C49 C50 Multiplexed with DP3_LANE3+ and TMDS3_CLK+. Multiplexed with DP3_LANE3- and TMDS3_CLK-. O PCIE DDI3_HPD C44 Multiplexed with DP3_HPD and HDMI3_HPD. I 3.3V PD 1M DDI3_CTRLCLK_AUX+ C36 Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK. DP AUX+ function if DDI3_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high I/O PCIE I/O OD 3.3V PD 100k DDI3_CTRLDATA_AUX- C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA. DP AUX- function if DDI3_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high. I/O PCIE I/O OD 3.3V PU 100k 3.3V DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-. This pin shall have a IM pull-down to logic ground on the module. If this input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled- high, the AUX pair contains the CTRLCLK and CTRLDATA signals I 3.3V Note 1. Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”. 2. The Digital Display Interface (DDI) signals are multiplexed with TMDS and DisplayPort (DP). The signals for these interfaces are routed to the DDI interface of the COM Express connector.

TSKLm16 54/71 Table 16 TMDS Signal Descriptions Signal Pin # Description I/O PU/PD Comment TMDS1_CLK + TMDS1_CLK - D36 D37 TMDS Clock output differential pair. Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-. O PCIE TMDS1_DATA0+ TMDS1_DATA0- D32 D33 TMDS differential pair. Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-. O PCIE TMDS1_DATA1+ TMDS1_DATA1- D29 D30 TMDS differential pair. Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.. O PCIE TMDS1_DATA2+ TMDS1_DATA2- D26 D27 TMDS differential pair. Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-. O PCIE HDMI1_HPD C24 TMDS Hot-plug detect. Multiplexed with DDI1_HPD. I PCIE PD 1M HDMI1_CTRLCLK D15 TMDS I2C Control Clock Multiplexed with DDI1_CTRLCLK_AUX+ I/O OD 3.3V PD 100k HDMI1_CTRLDATA D16 TMDS I2C Control Data Multiplexed with DDI1_CTRLDATA_AUX- I/O OD 3.3V PU 100k 3.3V Boot strap signal (see note below). Enable strap is already populated TMDS2_CLK + TMDS2_CLK - D49 D50 TMDS Clock output differential pair.. Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-. O PCIE TMDS2_DATA0+ TMDS2_DATA0- D46 D47 TMDS differential pair. Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-. O PCIE TMDS2_DATA1+ TMDS2_DATA1- D42 D43 TMDS differential pair. Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-. O PCIE TMDS2_DATA2+ TMDS2_DATA2- D39 D40 TMDS differential pair. Multiplexed with DDI2_PAIR0+ and DDI2_PAIR0-.. O PCIE HDMI2_HPD D44 TMDS Hot-plug detect. Multiplexed with DDI2_HPD I PCIE PD 1M HDMI2_CTRLCLK C32 TMDS I2C Control Clock Multiplexed with DDI2_CTRLCLK_AUX+ I/O OD 3.3V PD 100k HDM12_CTRLDATA C33 TMDS I2C Control Data Multiplexed with DDI2_CTRLDATA_AUX- I/O OD 3.3V PU 100k 3.3V Boot strap signal (see note below). Enable strap is already populated. TMDS3_CLK + TMDS3_CLK - C49 C50 TMDS TMDS Clock output differential pair.. Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-. O PCIE TMDS3_DATA0+ TMDS3_DATA0- C46 C47 TMDS differential pair. Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-. O PCIE TMDS3_DATA1+ TMDS3_DATA1- C42 C43 TMDS differential pair. Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-.. O PCIE TMDS3_DATA2+ TMDS3_DATA2- C39 C40 TMDS differential pair. Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-. O PCIE HDMI3_HPD C44 TMDS Hot-plug detect. Multiplexed with DDI3_HPD. I PCIE PD 1M HDMI3_CTRLCLK C36 TMDS I2C Control Clock Multiplexed with DDI3_CTRLCLK_AUX+ I/O OD 3.3V PD 100K

TSKLm16 55/71 Signal Pin # Description I/O PU/PD Comment HDMI3_CTRLDATA C37 TMDS I2C Control Data Multiplexed with DDI3_CTRLDATA_AUX- I/O OD 3.3V PU 100k 3.3V HDMI3_CTRLDATA is a boot strap signal (see note below). HDMI enable strap is already populated. Note 1. Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”. 2. The conga-TS175 does not natively support TMDS. A DP++ to TMDS converter (e.g PTN3360D) needs to be implemented. Table 17 DisplayPort (DP) Signal Descriptions Signal Pin # Description I/O PU/PD Comment DP1_LANE3+ DP1_LANE3- D36 D37 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-. O PCIE DP1_LANE2+ DP1_LANE2- D32 D33 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-. O PCIE DP1_LANE1+ DP1_LANE1- D29 D30 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-. O PCIE DP1_LANE0+ DP1_LANE0- D26 D27 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-. O PCIE DP1_HPD C24 Detection of Hot Plug / Unplug and notification of the link layer. Multiplexed with DDI1_HPD. I 3.3V PD 1M DP1_AUX+ D15 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access. I/O PCIE PD 100k DP1_AUX- D16 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access. I/O PCIE PU 100k 3.3V Boot strap signal (see note below) Enable strap is already populated. DP2_LANE3+ DP2_LANE3- D49 D50 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3- O PCIE DP2_LANE2+ DP2_LANE2- D46 D47 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2- O PCIE DP2_LANE1+ DP2_LANE1- D42 D43 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1- O PCIE DP2_LANE0+ DP2_LANE0- D39 D40 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI2_PAIR0+ and DDI1_PAIR0- O PCIE DP2_HPD D44 Detection of Hot Plug / Unplug and notification of the link layer. Multiplexed with DDI2_HPD. I 3.3V PD 1M DP2_AUX+ C32 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access. I/O PCIE PD 100k

TSKLm16 56/71 Signal Pin # Description I/O PU/PD Comment DP2_AUX- C33 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access. I/O PCIE PU 100k 3.3V Boot strap signal (see note below) Enable strap is already populated. DP3_LANE3+ DP3_LANE3- C49 C50 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-. O PCIE DP3_LANE2+ DP3_LANE2- C46 C47 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-. O PCIE DP3_LANE1+ DP3_LANE1- C42 C43 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-. O PCIE DP3_LANE0+ DP3_LANE0- C39 C40 Uni-directional main link for the transport of isochronous streams and secondary data. Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-. O PCIE DP3_HPD C44 Detection of Hot Plug / Unplug and notification of the link layer. Multiplexed with DDI3_HPD. I 3.3V PD 1M DP3_AUX+ C36 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access. I/O PCIE PD 100k DP3_AUX- C37 Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access. I/O PCIE PU 100k 3.3V Boot strap signal (see note below) Enable strap already populated Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”. Table 18 Embedded DisplayPort Signal Descriptions Signal Pin # Description I/O PU/PD Comment eDP_TX3+ eDP_TX3- eDP_TX2+ eDP_TX2- eDP_TX1+ eDP_TX1- eDP_TX0+ eDP_TX0- A81 A82 A71 A72 A73 A74 A75 A76 eDP differential pairs AC coupled off module eDP_VDD_EN A77 eDP power enable O 3.3V PD 10k eDP_BKLT_EN B79 eDP backlight enable O 3.3V PD 10k eDP_BKLT_CTRL B83 eDP backlight brightness control O 3.3V eDP_AUX+ A83 eDP AUX+ AC coupled off module eDP_AUX- A84 eDP AUX- AC coupled off module eDP_HPD A87 Detection of Hot Plug / Unplug and notification of the link layer I 3.3V

TSKLm16 57/71 Table 19 CRT Signal Descriptions Signal Pin # Description I/O PU/PD Comment VGA_RED B89 Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load O Analog PD 150R Optional VGA_GRN B91 Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load O Analog PD 150R Optional VGA_BLU B92 Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load O Analog PD 150R Optional VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V Optional VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V Optional VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify VGA monitor capabilities) I/O OD 5V PU 1k2 3.3V Optional VGA_I2C_DAT B96 DDC data line I/O OD 5V PU 1k2 3.3V Optional Table 20 LVDS Signal Descriptions Signal Pin # Description I/O PU/PD Comment LVDS_A0+ LVDS_A0- LVDS_A1+ LVDS_A1- LVDS_A2+ LVDS_A2- LVDS_A3+ LVDS_A3- A71 A72 A73 A74 A75 A76 A78 A79 LVDS Channel A differential pairs O LVDS LVDS_A_CK+ LVDS_A_CK- A81 A82 LVDS Channel A differential clock O LVDS LVDS_B0+ LVDS_B0- LVDS_B1+ LVDS_B1- LVDS_B2+ LVDS_B2- LVDS_B3+ LVDS_B3- B71 B72 B73 B74 B75 B76 B77 B78 LVDS Channel B differential pairs O LVDS LVDS_B_CK+ LVDS_B_CK- B81 B82 LVDS Channel B differential clock O LVDS LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 10k LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V PD 10k LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V for LVDS support (default) LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V for LVDS support (default)

TSKLm16 58/71 Table 21 Serial ATA Signal Descriptions Signal Pin # Description I/O PU/PD Comment SATA0_RX+ SATA0_RX- A19 A20 Serial ATA channel 0, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0 SATA0_TX+ SATA0_TX- A16 A17 Serial ATA channel 0, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0 SATA1_RX+ SATA1_RX- B19 B20 Serial ATA channel 1, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0 SATA1_TX+ SATA1_TX- B16 B17 Serial ATA channel 1, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0 SATA2_RX+ SATA2_RX- A25 A26 Serial ATA channel 2, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0 SATA2_TX+ SATA2_TX- A22 A23 Serial ATA channel 2, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0 SATA3_RX+ SATA3_RX- B25 B26 Serial ATA channel 3, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 3.0 SATA3_TX+ SATA3_TX- B22 B23 Serial ATA channel 3, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 3.0 (S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low. I/O 3.3v Table 22 USB 2.0 Signal Descriptions Signal Pin # Description I/O PU/PD Comment USB0+ A46 USB Port 0, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB0- A45 USB Port 0, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB1+ B46 USB Port 1, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB1- B45 USB Port 1, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB2+ A43 USB Port 2, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB2- A42 USB Port 2, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB3+ B43 USB Port 3, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB3- B42 USB Port 3, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB4+ A40 USB Port 4, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB4- A39 USB Port 4, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB5+ B40 USB Port 5, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB5- B39 USB Port 5, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB6+ A37 USB Port 6, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB6- A36 USB Port 6, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB7+ B37 USB Port 7, data + or D+ I/O USB 2.0 compliant. Backwards compatible to USB 1.1 USB7- B36 USB Port 7, data - or D- I/O USB 2.0 compliant. Backwards compatible to USB 1.1

TSKLm16 59/71 Signal Pin # Description I/O PU/PD Comment USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. I 3.3VSB PU 10k 3.3VSB Do not pull this line high on the carrier board. USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. . I 3.3VSB PU 10k 3.3VSB Do not pull this line high on the carrier board. USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. I 3.3VSB PU 10k 3.3VSB Do not pull this line high on the carrier board. USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. I 3.3VSB PU 10k 3.3VSB Do not pull this line high on the carrier board. Table 23 USB 3.0 Signal Descriptions Signal Pin # Description I/O PU/PD Comment USB_SSRX0+ C4 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX0- C3 I USB_SSTX0+ D4 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX0- D3 O USB_SSRX1+ C7 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX1- C6 I USB_SSTX1+ D7 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX1- D6 O USB_SSRX2+ C10 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX2- C9 I USB_SSTX2+ D10 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX2- D9 O USB_SSRX3+ C13 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX3- C12 I USB_SSTX3+ D13 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX3- D12 O

TSKLm16 60/71 Table 24 Gigabit Ethernet Signal Descriptions Gigabit Ethernet Pin # Description I/O PU/PD Comment GBE0_MDI0+ GBE0_MDI0- GBE0_MDI1+ GBE0_MDI1- GBE0_MDI2+ GBE0_MDI2- GBE0_MDI3+ GBE0_MDI3- A13 A12 A10 A9 A7 A6 A3 A2 Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mb/sec modes. Some pairs are unused in some modes according to the following: I/O Analog Twisted pair signals for external transformer. 1000 100 10 MDI[0]+/- B1_DA+/- TX+/- TX+/- MDI[1]+/- B1_DB+/- RX+/- RX+/- MDI[2]+/- B1_DC+/- MDI[3]+/- B1_DD+/- GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mb/sec link indicator, active low. O 3.3VSB GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mb/sec link indicator, active low. O 3.3VSB GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the module. In the case in which the reference is shorted to ground, the current shall be limited to 250mA or less. Not connected Note 1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation of Ethernet Phy since it has only three LED outputs—ACT#, LINK100# and LINK1000#. 2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS175 module. Table 25 Intel® High Definition Audio Link Signals Descriptions Signal Pin # Description I/O PU/PD Comment AC/HDA_RST# A30 Intel® High Definition Audio Reset: This signal is the master hardware reset to external codec(s). O 3.3VSB AC’97 codecs are not supported. AC/HDA_SYNC A29 Intel® High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync to the codec(s). It is also used to encode the stream number. O 3.3VSB AC’97 codecs are not supported. AC/HDA_BITCLK A32 Intel® High Definition Audio Bit Clock Output: This signal is a 24.000MHz serial data clock generated by the Intel® High Definition Audio controller. O 3.3VSB AC’97 codecs are not supported. AC/HDA_SDOUT A33 Intel® High Definition Audio Serial Data Out: This signal is the serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel® High Definition Audio. O 3.3VSB AC’97 codecs are not supported. AC/HDA_SDOUT is a boot strap signal (see note below)

TSKLm16 61/71 Signal Pin # Description I/O PU/PD Comment AC/HDA_SDIN[1:0] B29-B30 Intel® High Definition Audio Serial Data In [0]: These signals are serial TDM data inputs from the three codecs. The serial input is single-pumped for a bit rate of 24 Mb/s for Intel® High Definition Audio. I 3.3VSB Pin B28 (HDA_SDIN2) is not connected. Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”. Table 26 ExpressCard Support Pins Signal Descriptions Signal Pin # Description I/O PU/PD Comment EXCD0_CPPE# EXCD1_CPPE# A49 B48 ExpressCard capable card request. I 3.3V PU 10k 3.3VSB EXCD0_PERST# EXCD1_PERST# A48 B47 ExpressCard Reset O 3.3V PU 10k 3.3V Table 27 LPC Signal Descriptions Signal Pin # Description I/O PU/PD Comment LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V LPC_DRQ[0:1]# B8-B9 LPC serial DMA request I 3.3V PU 10k 3.3V LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 10k 3.3V LPC_CLK B10 LPC clock output - 24 MHz nominal O 3.3V Table 28 SPI BIOS Flash Interface Signal Descriptions Signal Pin # Description I/O PU/PD Comment SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Carrier shall pull to SPI_POWER when external SPI is provided but not used. SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB

TSKLm16 62/71 Signal Pin # Description I/O PU/PD Comment SPI_POWER A91 Power source for carrier board SPI BIOS flash. SPI_POWER shall be used to power SPI BIOS flash on the carrier only. + 3.3VSB BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K 3.3VSB Carrier shall be left as no-connect. BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I 3.3VSB PU 10K 3.3VSB Carrier shall be left as no-connect Table 29 Miscellaneous Signal Descriptions Signal Pin # Description I/O PU/PD Comment I2C_CK B33 General purpose I²C port clock output/input I/O 3.3V PU 2K2 3.3VSB I2C_DAT B34 General purpose I²C port data I/O line I/O 3.3V PU 2K2 3.3VSB SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V SPEAKER is a boot strap signal (see note below) WDT B27 Output indicating that a watchdog time-out event has occurred. O 3.3V PD 10K FAN_PWMOUT B101 Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM. O OD 3.3V FAN_TACHIN B102 Fan tachometer input. I OD PU 10K 3.3V Requires a fan with a two pulse output. TPM_PP A96 Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip has an internal pull-down. This signal is used to indicate Physical Presence to the TPM. I 3.3V Trusted Platform Module chip is optional. Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 9.2 “Boot Strap Signals”. Table 30 General Purpose I/O Signal Descriptions Signal Pin # Description I/O PU/PD Comment GPO0 A93 General purpose output pins. Shared with SD_CLK. Output from COM Express, input to SD O 3.3V GPO1 B54 General purpose output pins. Shared with SD_CMD. Output from COM Express, input to SD O 3.3V GPO2 B57 General purpose output pins. Shared with SD_WP. Output from COM Express, input to SD O 3.3V GPO3 B63 General purpose output pins. Shared with SD_CD. Output from COM Express, input to SD O 3.3V

TSKLm16 63/71 Signal Pin # Description I/O PU/PD Comment GPI0 A54 General purpose input pins. Pulled high internally on the module. Shared with SD_DATA0. Bidirectional signal I 3.3V PU 10K 3.3V GPI1 A63 General purpose input pins. Pulled high internally on the module. Shared with SD_DATA1. Bidirectional signal I 3.3V PU 10K 3.3V GPI2 A67 General purpose input pins. Pulled high internally on the module. Shared with SD_DATA2. Bidirectional signal I 3.3V PU 10K 3.3V GPI3 A85 General purpose input pins. Pulled high internally on the module. Shared with SD_DATA3. Bidirectional signal. I 3.3V PU 10K 3.3V Note The conga-TS175 provides GPIO signals on the COM Express connector by default. Table 31 Power and System Management Signal Descriptions Signal Pin # Description I/O PU/PD Comment PWRBTN# B12 Power button to bring system out of S5 (soft off), active on falling edge. Note: For proper detection, assert a pulse width of at least 16 ms. I 3.3VSB PU 10k 3.3VSB SYS_RESET# B49 Reset button input. Active low input. Edge triggered. System will not be held in hardware reset while this input is kept low. Note: For proper detection, assert a pulse width of at least 16 ms. I 3.3VSB PU 10k 3.3VSB CB_RESET# B50 Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software. O 3.3V PD 100k PWR_OK B24 Power OK from main power supply. A high value indicates that the power is good. I 3.3V Set by resistor divider to accept 3.3V. SUS_STAT# B18 Indicates imminent suspend operation; used to notify LPC devices. O 3.3VSB SUS_S3# A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply. O 3.3VSB SUS_S4# A18 Indicates system is in Suspend to Disk state. Active low output. O 3.3VSB Not supported SUS_S5# A24 Indicates system is in Soft Off state. O 3.3VSB WAKE0# B66 PCI Express wake up signal. I 3.3VSB PU 1k 3.3VSB WAKE1# B67 General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or mouse activity. I 3.3VSB PU 10k 3.3VSB BATLOW# A27 Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event. I 3.3VSB PU 8k2 3.3VSB THRM# B35 Input from off-module temp sensor indicating an over-temp situation. I 3.3V PU 10k 3.3V THERMTRIP# A35 Active low output indicating that the CPU has entered thermal shutdown. O 3.3V PU 10k 3.3V SMB_CK B13 System Management Bus bidirectional clock line. I/O 3.3VSB PU 2k2 3.3VSB

TSKLm16 64/71 Signal Pin # Description I/O PU/PD Comment SMB_DAT# B14 System Management Bus bidirectional data line. I/O OD 3.3VSB PU 2k2 3.3VSB SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. I 3.3VSB PU 2k2 3.3VSB LID# A103 Lid button. Used by the ACPI operating system for a LID switch. Note: For proper detection, assert a pulse width of at least 16 ms. I OD 3.3V PU 10k 3.3VSB SLEEP# B103 Sleep button. Used by the ACPI operating system to bring the system to sleep state or to wake it up again. Note: For proper detection, assert a pulse width of at least 16 ms. I OD 3.3V PU 10k 3.3VSB Table 32 General Purpose Serial Interface Signal Descriptions Signal Pin # Description I/O PU/PD Comment SER0_TX A98 General purpose serial port transmitter O 3.3V SER1_TX A101 General purpose serial port transmitter O 3.3V SER0_RX A99 General purpose serial port receiver I 3.3V PU 47k 3.3V SER1_RX A102 General purpose serial port receiver I 3.3V PU 47k 3.3V Table 33 Module Type Definition Signal Description Signal Pin # Description I/O Comment TYPE0# TYPE1# TYPE2# C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X). PDS TYPE[0:2]# signals are available on all modules following the Type 2-6 Pinout standard. The conga-TS175 is based on the COM Express Type 6 pinout therefore the pins 0 and 1 are not connected and pin 2 is connected to GND. TYPE2# TYPE1# TYPE0# X NC NC NC NC GND X NC NC GND GND NC X NC GND NC GND NC Pinout Type 1 Pinout Type 2 Pinout Type 3 (no IDE) Pinout Type 4 (no PCI) Pinout Type 5 (no IDE, no PCI) Pinout Type 6 (no IDE, no PCI) The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.

TSKLm16 65/71 Signal Pin # Description I/O Comment TYPE10# A97 Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev. 1.0/2.0 module is installed. PDS Not connected to indicate “Pinout R2.0”. TYPE10# NC PD 12V Pinout R2.0 Pinout Type 10 pull down to ground with 4.7k resistor Pinout R1.0 This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin is defined as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0 module Types 1-6 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7k resistor. Table 34 Power and GND Signal Descriptions Signal Pin # Description I/O PU/PD Comment VCC_12V A104-A109 B104-B109 C104-C109 D104-D109 Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used. P VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design. P VCC_RTC A47 Real-time clock circuit-power input. Nominally +3.0V. P GND A1, A11, A21, A31, A41, A51, A57, A60, A66, A70, A80, A90, A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110 C1, C2, C5, C8, C11, C14, C21, C31, C41, C51, C60, C70,C73, C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110 Ground - DC power and signal and AC signal return path. All available GND connector pins shall be used and tied to Carrier Board GND plane. P

TSKLm16 66/71 9.2 Boot Strap Signals Table 35 Boot Strap Signal Descriptions Signal Pin # Description of Boot Strap Signal I/O PU/PD Comment AC/HDA_SDOUT A33 High Definition Audio Serial Data Out: This signal is the serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for High Definition Audio. O 3.3VSB PU 1k 3.3VSB Bootstrap signals SPKR B32 Output for audio enunciator, the “speaker” in PC-AT systems O 3.3V PEG_LAN_RV# D54 PCI Express Graphics lane reversal input strap. Pull low on the carier board to reverse lane order. 13.3V PU 10k 3.3V DDI1_CTRLDATA_AUX- DP1_AUX- HDMI_CTRLDATA D16 Multiplexed with DP1_AUX- and HDMI1_CTRLDATA. DP AUX- function if DDI1_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI1_DDC_AUX_SEL is pulled high. I/O PCIE I/O OD 3.3V PU100k 3.3V DDI2_CTRLDATA_AUX- DP2_AUX- HDM2_CTRLDATA C33 Multiplexed with DP2_AUX- and HDMI2_CTRLDATA. DP AUX- function if DDI2_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high. I/O PCIE I/O OD 3.3V PU100k 3.3V DDI3_CTRLDATA_AUX- DP3_AUX- HDM2_CTRLDATA C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA. DP AUX- function if DDI3_DDC_AUX_SEL is no connect. HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high. I/O PCIE I/O OD 3.3V PU 100k 3.3V Caution 1. The signals listed in the table above are used as chipset configuration straps during system reset. In this condition (during reset), they are inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented resistors that are located on the module. 2. No external DC loads or external pull-up or pull-down resistors should change the configuration of the signals listed in the above table. External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/or cause irreparable damage to the module.

TSKLm16 67/71 10 System Resources 10.1 I/O Address Assignment The I/O address assignment of the conga-TS175 module is functionally identical with a standard PC/AT. Note The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not consume I/O resources in that area. 10.1.1 LPC Bus On the conga-TS175 the PCIExpress Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus. Only specified I/O ranges are forwarded to the LPC Bus. In the congatec Embedded BIOS the following I/O address ranges are sent to the LPC Bus: 2Eh – 2Fh 4Eh – 4Fh 60h, 64h A00h – A1Fh E00h - EFFh (always used internally) Parts of these ranges are not available if a Super I/O is used on the carrier board. If a Super I/O is not implemented on the carrier board then these ranges are available for customer use. If you require additional LPC Bus resources other than those mentioned above, or more information about this subject, contact congatec technical support for assistance.

TSKLm16 68/71 10.2 PCI Configuration Space Map Table 36 PCI Configuration Space Map Bus Number (hex) Device Number (hex) Function Number (hex) Description 00h 00h 00h HOST and DRAM Controller 00h 01h 00h PCI Express Graphic Root Port 0 00h 01h 01h PCI Express Graphic Root Port 1 00h 01h 02h PCI Express Graphic Root Port 2 00h 02h 00h Integrated Graphics Device 00h 08h 00h Gaussian Mixture Model Device 00h 14h 00h USB 3.0 xHCI Controller 00h 14h 02h Thermal Subsystem 00h ( Note1) 16h 00h Management Engine (ME) Interface 1 00h ( Note1) 16h 01h Intel ME Interface 2 00h ( Note1) 16h 02h ME IDE Redirection (IDE-R) Interface 00h ( Note1) 16h 03h ME Keyboard and Text (KT) Redirection 00h ( Note1) 16h 04h Intel ME Interface 3 00h 17h 00h SATA Controller 00h 1Ch 00h Not connected (PCI Express Root Port) 00h (Note2) 1Ch 04h PCI Express Root Port 0 00h (Note2) 1Ch 05h PCI Express Root Port 1 00h (Note2) 1Ch 06h PCI Express Root Port 2 00h (Note2) 1Ch 07h PCI Express Root Port 3 00h (Note2) 1Dh 00h PCI Express Root Port 4 00h (Note2) 1Dh 01h PCI Express Root Port 5 00h (Note2) 1Dh 02h PCI Express Root Port 6 00h (Note2) 1Dh 03h PCI Express Root Port 7 00h 1Fh 00h PCI to LPC Bridge 00h 1Fh 02h Power Management Controller 00h 1Fh 03h Intel® High Definition Audio (Intel® HD Audio) 00h 1Fh 04h SMBus Controller 00h 1Fh 06h GbE Controller 01h (Note3) 00h 00h PEG Port 0 02h (Note3) 00h 00h PEG Port 1

TSKLm16 69/71 03h (Note3) 00h 00h PEG Port 2 04h (Note3) 00h 00h PCI Express Port 0 05h (Note3) 00h 00h PCI Express Port 1 06h (Note3) 00h 00h PCI Express Port 2 07h (Note3) 00h 00h PCI Express Port 3 08h (Note3) 00h 00h PCI Express Port 4 09h (Note3) 00h 00h PCI Express Port 5 0Ah (Note3) 00h 00h PCI Express Port 6 0Bh (Note3) 00h 00h PCI Express Port 7 Note 1. In the standard configuration, the Intel Management Engine (ME) related devices are partly present or not present at all. 2. The PCI Express Ports are visible only if a device is attached to the PCI Express Slot on the carrier board. 3. The table represents a case when a single function PCI/PCIe device is connected to all possible slots on the carrier board. The given bus numbers will change based on actual hardware configuration. 4. Internal PCI devices not connected to the conga-TS175 are not listed. 10.3 I2C There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions. 10.4 SM Bus System Management (SM) bus signals are connected to the Intel® chipset. The SM bus is not intended to be used by off-board non-system management devices. For more information about this subject, contact congatec technical support.

TSKLm16 70/71 11 BIOS Setup Description The BIOS setup description of the conga-TS175 can be viewed without having access to the module. However, access to the restricted area of the congatec website is required in order to download the necessary tool (CgMlfViewer) and Menu Layout File (MLF). The MLF contains the BIOS setup description of a particular BIOS revision. The MLF can be viewed with the CgMlfViewer tool. This tool offers a search function to quickly check for supported BIOS features. It also shows where each feature can be found in the BIOS setup menu. For more information, read the application note “AN42 - BIOS Setup Description” available at www.congatec.com. Note If you do not have access to the restricted area of the congatec website, contact your local congatec sales representative. 11.1 Navigating the BIOS Setup Menu The BIOS setup menu shows the features and options supported in the congatec BIOS. To access and navigate the BIOS setup menu, press the or key during POST. The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options and the possible impacts when changing the selected option in the left frame. 11.2 BIOS Versions The BIOS displays the BIOS project name and the revision code during POST, and on the main setup screen. The initial production BIOS for conga-TS175 is identified as BHKLR1xx or BQKLR1xx, where: • R is the identifier for a BIOS ROM file, • 1 is the feature number and • xx is the major and minor revision number. The BHKL binary size is 16 MB and the BQKL binary size is 8 MB.

TSKLm16 71/71 11.3 Updating the BIOS BIOS updates are recommeded to correct platform issues or enhance the feature set of the module. The conga-TS175 features a congatec/AMI AptioEFI firmware on an onboard flash ROM chip. You can update the firmware with the congatec System Utility. The utility has five versions— UEFI shell, DOS based command line1, Win32 command line, Win32 GUI, and Linux version. For more information about “Updating the BIOS” refer to the user’s guide for the congatec System Utility “CGUTLm1x.pdf” on the congatec website at www.congatec.com. Note 1. Deprecated Caution The DOS command line tool is not officially supported by congatec and therefore not recommended for critical tasks such as firmware updates. We recommend to use only the UEFI shell for critical updates. 11.4 Recovering from External Flash The following congatec documents describe how to recover a congatec module from external flash. You can find these documents on the congatec website: • AN1_BIOS_Update.pdf • AN5_BIOS_Update_And_Write_Protection.pdf • AN7_External_BIOS_Update.pdf 11.5 Supported Flash Devices The conga-TS175 supports the following flash devices: • Winbond W25Q128JVSIQ (16 MB) • Winbond W25Q64JVSSIQ (8 MB) The flash devices listed above can be used on the carrier board to support external BIOS. For more information about external BIOS support, refer to the Application Note “AN7_External_BIOS_Update.pdf” on the congatec website at http://www.congatec.com.