Oki ML63326 Operation & User’s Manual

SECOND EDITION ISSUE DATE: Sep. 1999 PEUL63326-02 ¡ Preliminary

technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan E2Y0002-29-62

Refer to the "nX-4/250 Core Instruction Manual" for details of the 4-bit CPU core nX-4/250 which is built in the ML63326. The manuals related to the ML63326 are shown below. • nX-4/250 Core Instruction Manual: Describes the base architecture and instruction set of nX-4/250 core. • SASM63K User's Manual: Describes the structured assembler operation and assembler language specifica- tion. • Dr. 63326 User's Manual: Describes the hardware of the emulator. • DT63K Debugger User's Manual: Describes the debugger commands. This document is subject to change without notice.

xxh, xxH Represents a hexadecimal number. xxb Represents a binary number. n Unit word, W 1 word = 16 bits byte, B 1 byte = 2 nibbles = 8 bits nibble, N 1 nibble = 4 bits mega-, M 106 kilo-, K 210 = 1024 kilo-, k 103 = 1000 milli-, m 10-3 micro-, m 10-6 nano-, n 10-9 second, s (lower case) second KB 1 KB = 1 kilobyte = 1024 bytes MB 1 MB = 1 megabyte = 220 bytes = 1,048,576 bytes n Symbol Note: Gives more information about mistakable items. n Terminology “H” level Indicates high side voltage signal levels VIH and VOH as specified by the electrical characteristics. “L” level Indicates low side voltage signal levels VIL and VOL as specified by the electrical characteristics. n Register description Invalid bit : When read, a value of “1” is always obtained. Write operations are invalid. R/W attribute : “R” indicates data can be read and “W” indicates data can be written. ! Bit name Invalid bit Address R/W attribute Register name PBF — PB1MOD PB0MOD bit 3 bit 2 bit 1 bit 0 PBMOD0 (032H) (R/W)

Table of Contents Chapter 1 Overview 1.1 Overview ........................................................................................................ 1-1 1.2 Features ......................................................................................................... 1-1 1.3 Function List .................................................................................................. 1-5 1.4 Block Diagram................................................................................................ 1-6 1.5 Pin Configuration ........................................................................................... 1-7 1.6 Pin Descriptions ............................................................................................. 1-11 1.6.1 Descriptions of the Basic Pin Functions ............................................. 1-11 1.6.2 Descriptions of the Secondary Pin Functions ..................................... 1-16 1.6.3 Unused Pin Processing ...................................................................... 1-18 1.7 Basic Timing .................................................................................................. 1-19 1.7.1 Basic Timing of CPU Operation.......................................................... 1-19 1.7.2 Port I/O Basic Timing .......................................................................... 1-19 1.7.3 Interrupt Basic Timing......................................................................... 1-21 Chapter 2 CPU and Memory Spaces 2.1 Overview ........................................................................................................ 2-1 2.2 Registers........................................................................................................ 2-1 2.2.1 Accumulator (A) .................................................................................. 2-1 2.2.2 Flag Register ...................................................................................... 2-1 2.2.2.1 Carry Flag (C) ....................................................................... 2-1 2.2.2.2 Zero Flag (Z)......................................................................... 2-2 2.2.2.3 G Flag (G)............................................................................. 2-2 2.2.3 Master Interrupt Enable Flag (MIE) .................................................... 2-2 2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR), HL Register (HL), XY Register (XY) ................................................... 2-3 2.2.5 Program Counter (PC)........................................................................ 2-4 2.2.6 RA Registers (RA3, RA2, RA1, RA0) ................................................. 2-4 2.2.7 Stack Pointer (SP) and Call Stack ...................................................... 2-5 2.2.8 Register Stack Pointer (RSP) and Register Stack.............................. 2-6 2.3 Memory Spaces ............................................................................................. 2-7 2.3.1 Program Memory Space..................................................................... 2-7 2.3.2 Data Memory Space ........................................................................... 2-8 2.3.3 Memory Space for Voice Synthesis and Character Data ................... 2-9 2.3.4 External Memory Space ..................................................................... 2-10

Chapter 3 CPU Control Functions 3.1 Overview ........................................................................................................ 3-1 3.2 System Reset Mode (RST) ............................................................................ 3-2 3.2.1 Transfer to and State of System Reset Mode .................................... 3-2 3.3 Halt Mode ...................................................................................................... 3-3 3.3.1 Transfer to and State of Halt Mode .................................................... 3-3 3.3.2 Halt Mode Release ............................................................................. 3-4 3.3.2.1 Release of Halt Mode by Interrupt ........................................ 3-4 3.3.2.2 Release of Halt Mode by RESET Pin ................................... 3-4 3.3.3 Melody Data Interrupt and Halt Mode Release .................................. 3-5 3.3.4 Note Concerning HALT Instruction ..................................................... 3-5 Chapter 4 Interrupt (INT326) 4.1 Overview ........................................................................................................ 4-1 4.2 Interrupt Registers ......................................................................................... 4-3 4.3 Interrupt Sequence ........................................................................................ 4-10 4.3.1 Interrupt Processing ........................................................................... 4-10 4.3.2 Return from an Interrupt Routine ........................................................ 4-11 4.3.3 Interrupt Hold Instructions .................................................................. 4-11 Chapter 5 Clock Generator Circuit (OSC) 5.1 Overview ........................................................................................................ 5-1 5.2 Clock Generator Circuit Configuration ........................................................... 5-1 5.3 Low-Speed Clock Generator Circuit .............................................................. 5-2 5.4 High-Speed Clock Generator Circuit ............................................................. 5-4 5.5 System Clock Control .................................................................................... 5-6 5.6 Frequency Control Register (FCON) ............................................................. 5-7 5.7 System Clock Select Timing .......................................................................... 5-8 Chapter 6 Time Base Counter (TBC) 6.1 Overview ........................................................................................................ 6-1 6.2 Time Base Counter Configuration ................................................................. 6-1 6.3 Time Base Counter Registers ........................................................................ 6-2 6.4 Time Base Counter Operation ....................................................................... 6-3

Chapter 7 Timers (TIMER) 7.1 Overview ........................................................................................................ 7-1 7.2 Timer Configuration ....................................................................................... 7-1 7.3 Timer Registers.............................................................................................. 7-3 7.4 Timer Operation ............................................................................................. 7-14 7.4.1 Timer Clock ........................................................................................ 7-14 7.4.2 Timer Data Registers .......................................................................... 7-14 7.4.3 Timer Counter Registers .................................................................... 7-14 7.4.4 Timer Interrupt Requests and Overflow Flags .................................... 7-15 7.4.5 Auto-Reload Mode Operation ............................................................. 7-16 7.4.6 Capture Mode Operation .................................................................... 7-18 7.4.7 Frequency Measurement Mode Operation ......................................... 7-21 Chapter 8 100 Hz Timer Counter (100HzTC) 8.1 Overview ........................................................................................................ 8-1 8.2 100 Hz Timer Counter Configuration ............................................................. 8-1 8.3 100 Hz Timer Counter Registers ................................................................... 8-2 8.4 100 Hz Timer Counter Operation ................................................................... 8-3 Chapter 9 Watchdog Timer (WDT) 9.1 Overview ........................................................................................................ 9-1 9.2 Watchdog Timer Configuration ...................................................................... 9-1 9.3 Watchdog Timer Control Register (WDTCON) .............................................. 9-2 9.4 Watchdog Timer Operation............................................................................ 9-2

Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 10.1 Overview ........................................................................................................ 10-1 10.2 Ports List ........................................................................................................ 10-1 10.3 Port 0 (P0.0–P0.3) ......................................................................................... 10-2 10.3.1 Port 0 Configuration.......................................................................... 10-2 10.3.2 Port 0 Registers ................................................................................ 10-2 10.3.3 Port 0 External Interrupt Functions (External Interrupt 5) ................. 10-5 10.4 Ports 4–7 (P4.0–P4.3, P5.0–P5.3, P6.0–P6.3, P7.0–P7.3) ........................... 10-7 10.4.1 Port 4–7 Configuration...................................................................... 10-7 10.4.2 Port 4–7 Registers ............................................................................ 10-8 10.5 Port 8, Port 9, Port A (P8.0, P8.1, P9.0–P9.3, PA.0–PA.3) ........................... 10-15 10.5.1 Port 8, Port 9, Port A Configuration .................................................. 10-15 10.5.2 Port 8, Port 9, Port A Registers ........................................................ 10-16 10.6 Port B (PB.0–PB.3) ........................................................................................ 10-24 10.6.1 Port B Configuration ......................................................................... 10-24 10.6.2 Port B Registers ............................................................................... 10-25 10.6.3 Port B External Interrupt Function (External Interrupt 0) .................. 10-29 10.7 Port E (PE.0–PE.3) ........................................................................................ 10-30 10.7.1 Port E Configuration ......................................................................... 10-30 10.7.2 Port E Registers ............................................................................... 10-31 10.7.3 Port E.3 External Interrupt Function (External Interrupt 2) ............... 10-34 10.8 Port F (PF.0–PF.3)......................................................................................... 10-35 10.8.1 Port F Configuration ......................................................................... 10-35 10.8.2 Port F Registers................................................................................ 10-36 10.8.3 Port F External Interrupt Function (External Interrupt 3) .................. 10-40 Chapter 11 External Memory Transfer Function (EXTMEM) 11.1 Overview ........................................................................................................ 11-1 11.2 Connection with the External Memory ........................................................... 11-2 11.3 External Memory Address Space .................................................................. 11-3 11.4 Setting of Secondary Port Functions ............................................................. 11-4 11.5 Distinction between ROM Area inside the Chip and Memory Area External to the Chip ..................................................................................................... 11-4 11.6 Reading from External Memory ..................................................................... 11-5 11.7 Reading from the Voice ROM inside the Chip ............................................... 11-6 11.8 Writing to External Memory ........................................................................... 11-7 Chapter 12 Melody Driver (MELODY63K) 12.1 Overview ........................................................................................................ 12-1 12.2 Melody Driver Configuration .......................................................................... 12-1 12.3 Melody Driver Registers ................................................................................ 12-2 12.4 Melody Circuit Operation ............................................................................... 12-4 12.4.1 Tempo Data ...................................................................................... 12-5 12.4.2 Melody Data ..................................................................................... 12-6 12.4.3 Melody Circuit Application Example ................................................. 12-9 12.5 Buzzer Circuit Operation................................................................................ 12-10 12.6 Melody/Buzzer Output Selector Circuit .......................................................... 12-12 12.7 Differences with Voice Synthesis Section Melody/Buzzer Output ................. 12-13

13.1 Overview ........................................................................................................ 13-1 13.2 Voice Synthesis Section Configuration .......................................................... 13-1 13.3 Registers Related to the Voice Synthesis Section ......................................... 13-3 13.4 Voice ROM..................................................................................................... 13-8 13.4.1 Voice ROM Configuration ................................................................. 13-8 13.4.2 Creation of Voice ROM Store Data .................................................. 13-9 13.5 Voice Synthesis Section Clock Input Frequency ........................................... 13-10 13.6 Operation of the Voice Synthesis Section...................................................... 13-11 13.6.1 Description of Pins Related to Voice Synthesis ................................ 13-11 13.6.2 Phrase Address and Stop Code ....................................................... 13-12 13.7 Voice .............................................................................................................. 13-13 13.7.1 Voice Reproduction Method ............................................................. 13-13 13.7.1.1 4-Bit ADPCM Method ....................................................... 13-13 13.7.1.2 8-Bit Straight PCM Method ............................................... 13-13 13.7.1.3 8-Bit Nonlinear PCM ......................................................... 13-13 13.7.2 Forcible Stopping of Voice Output .................................................... 13-13 13.7.3 Voice Output Procedure ................................................................... 13-14 13.8 Voice Output Duration.................................................................................... 13-17 13.9 Melody ........................................................................................................... 13-18 13.9.1 Tempo Data ...................................................................................... 13-18 13.9.2 Melody Data ..................................................................................... 13-20 13.9.3 Melody Circuit Application Example ................................................. 13-24 13.9.4 Melody Output Procedure ................................................................. 13-25 13.10 Buzzer ............................................................................................................ 13-27 13.10.1 Buzzer Output Procedure ................................................................. 13-28 13.11 Example of Connections Made for Extending the Voice Data Area .............. 13-29 13.12 Example of Connections Made When Using a Piezoelectric Speaker........... 13-30 Chapter 14 Shift Register (SFT) 14.1 Overview ........................................................................................................ 14-1 14.2 Shift Register Configuration ........................................................................... 14-1 14.3 Shift Registers................................................................................................ 14-2 14.4 Shift Register Operation ................................................................................ 14-4 14.5 Shift Register Application Example................................................................ 14-6 Chapter 15 LCD Driver (LCD) 15.1 Overview ........................................................................................................ 15-1 15.2 LCD Driver Configuration ............................................................................... 15-1 15.3 LCD Driver Registers ..................................................................................... 15-2 15.4 LCD Driver Operation .................................................................................... 15-5 15.5 Bias Generator (BIAS) ................................................................................... 15-6 15.6 LCD Driver Output Waveform ........................................................................ 15-9 - v -

Chapter 16 Battery Low Detect Circuit (BLD) 16.1 Overview ........................................................................................................ 16-1 16.2 Battery Low Detect Circuit Configuration ....................................................... 16-1 16.3 Judgment Voltage .......................................................................................... 16-2 16.4 Battery Low Detect Circuit Register ............................................................... 16-2 16.5 Battery Low Detect Circuit Operation ............................................................ 16-3 Chapter 17 Power Supply Circuit (POWER) 17.1 Overview ........................................................................................................ 17-1 17.2 Power Supply Circuit Configuration ............................................................... 17-1 17.3 Power Supply Circuit Operation ..................................................................... 17-2 Appendixes Appendix A List of Special Function Registers ............................................Appendix-1 Appendix B Package Dimensions ................................................................Appendix-13 Appendix C Input/Output Circuit Configuration ............................................Appendix-14 Appendix D Peripheral Circuit Examples .....................................................Appendix-16 Appendix E Electrical Characteristics ......................................................... Appendix-21 Appendix F Instruction List ..........................................................................Appendix-35 Appendix G Mask Option .............................................................................Appendix-59

3 Chapter 3 CPU Control Functions 4 Chapter 4 Interrupt (INT326) 5 Chapter 5 Clock Generator Circuit (OSC) 6 Chapter 6 Time Base Counter (TBC) 7 Chapter 7 Timers (TIMER) 8 Chapter 8 100 Hz Timer Counter (100HzTC) 9 Chapter 9 Watchdog Timer (WDT) 10 Chapter 10 Ports (INPUT, OUTPUT, I/O PORT) 14 Chapter 14 Shift Register (SFT) 15 Chapter 15 LCD Driver (LCD) 17 Chapter 17 Power Supply Circuit (POWER) Appendixes 11 Chapter 11 External Memory Transfer Function (EXTMEM) 12 Chapter 12 Melody Driver (MELODY63K) 13 Chapter 13 Voice Synthesis 16 Chapter 16 Battery Low Detect Circuit (BLD)

Chapter 1 Overview 1 Chapter 1 Overview 1.1 Overview The ML63326 is a 4-bit microcontroller with built-in voice synthesis section and 1024- segment dot matrix LCD driver. The ML63326 is ideal for applications such as game machines, toys, and clocks, that have LCD displays and synthesized voice outputs. The ML63326 is a mask ROM product belonging to the M633xx series of the OLMS-63K family with Oki's original nX-4/250 CPU core. The ML63326 contains a 24K-word program memory, a 1536-nibble data memory, one 4-bit input port, four 4-bit output ports, five 4-bit and one 2-bit I/O ports, a shift register, an LCD driver capable of driving a maximum of 1024 segments, and a voice synthesis section. The voice synthesis section has a 12-bit D/A converter and a low-pass filter. 1.2 Features The ML63326 has the following features. a. Extensive instruction set • 439 instructions Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations, bit operations, ROM table reference, external memory transfer, stack operations, flag operations, jump, conditional branch, call/return, control b. Wide variety of addressing modes • Indirect addressing mode for 4 types of data memory with current bank register, extra bank register, HL register and XY register • Data memory bank internal direct addressing mode c. Processing speed • 2 clocks per machine cycle, with most instructions executed in 1 machine cycle • Minimum instruction execution time: 61 ms (@ 32.768 kHz system clock) 0.976 ms (@ 2.048 MHz system clock) d. Clock generation circuit • Low-speed clock: Crystal oscillation or RC oscillation selected with mask option (30 kHz to 80 kHz) • High-speed clock: Crystal oscillation (4.096 MHz max.) or RC oscillation (2.048 MHz max.) selected with software (During the crystal oscillation mode, the device operates outputting the 1/2 frequency waveform of the source oscillation clock.) e. Program memory space • 24K words • The basic instruction length is 16 bits per word. f. Data memory space • 1536 nibbles g. External data memory space • 64 Kbytes (expandable by using I/O port)

Chapter 1 Overview h. Stack level Call stack level Register stack level 16 16 i. Ports • Input ports: Selectable as input with pull-up resistor, input with pull-down resistor or high impedance input. Output ports: Selectable as P-channel open drain output/N-channel open drain output/CMOS output/high-impedance output. • I/O ports: Selectable as input with pull-up resistor, input with pull-down resistor or high impedance input. Selectable as p-channel open drain output, n-channel open drain output, high impedance output or CMOS output. • Can be interfaced to external devices having different power supplies. • Number of ports: Input port Output ports I/O ports 1 port ¥ 4 bits 4 ports ¥ 4 bits 5 ports ¥ 4 bits 1 port ¥ 2 bits j. Voice synthesis section • Algorithm: 4-bit ADPCM method/non-linear 8-bit PCM method/ straight 8-bit PCM method • Voice synthesis data area Internal ROM: 1-Mbit mask ROM (128 Kbytes) Stores voice data and character data, etc. External ROM: 4-Mbit ROM (512 Kbytes max.) • Sampling frequencies With a source oscillator of 4.096 MHz: 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, and 16.0 kHz • Built-in 12-bit D/A converter • Built-in low-pass filter • Built-in melody circuit (MELODY) • Voice output duration voice output duration = voice ROM capacity/bit rate = voice ROM capacity/(sampling frequency × bit length) When algorithm = 4-bit ADPCM method, voice ROM capacity = 512 Kbits, and sampling frequency = 4.0 kHz, then the voice output duration = approx. 32.8 sec.

Chapter 1 Overview 1 o. Timers, counters • 8-bit timer: 4 channels Selectable as auto-reload mode, capture mode, clock frequency measurement mode • Watchdog timer: 1 channel • 100 Hz timer: 1 channel 1/100 sec. measurement possible • 15-bit TBC: 1 channel 1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz,128 Hz signals can be read p. Shift register • Shift clock: System clock ¥1 or ¥1/2, Timer 1 overflow, external clock • Data length: 8 bits q. Interrupt factors External factors Internal factors 4 13 Judgment voltage (V) Remarks LD0 LD1 — Undefined 0 0 2.00 ±0.10 Ta = 25°C 1 0 2.20 ±0.10 Ta = 25°C 0 1 2.40 ±0.10 Ta = 25°C 1 1 k. Melody output (MELODY63K) • Melody frequency: 529 Hz to 2979 Hz • Tone length: 63 varieties • Tempo: 15 varieties • Melody data: Stored in program memory • Buzzer driver signal output: 4 kHz l. LCD driver • Number of segments: 1024 segments max. (64 seg. ¥ 16 com.) • 1/1 to 1/16 duty • 1/4 or 1/5 bias (internal regulator) • Selectable as all-ON mode, all-OFF mode, power down mode, and normal display mode • Adjustable contrast (16 levels @ VDD = 2.4 V or more) m. System reset function • System reset by RESET pin • System reset by power-on detection • System reset by detection that low-speed clock has stopped oscillation n. Battery check • Function that detects battery low voltage • Selection of judgment voltage by software (LD1 and LD0 bit settings of BLDCON)

Chapter 1 Overview r. Shipping products Package Product • Chip (159 pads) ML63326-xxx • 176-pin flat package (176LQFP) ML63326-xxxTC LQFP176-P-2424-0.50-BK xxx indicates the ROM code number. s. Operating temperature • –20 to +70°C t. Power supply voltage • 2.0 to 5.5 V (30 kHz to 2.048 MHz operating frequency: internal clock)

Chapter 1 Overview 1 1.3 Function List Table 1-1 shows a list of the ML63326 functions. The solid black circles within the chart indicate that the product has the particular function. Table 1-1 Function List Function Symbol ML63326 Reference page ROM (¥ 16 bits) ROM 24576 Æ2-7 RAM (¥ 4 bits) RAM 1536 Æ2-8 STACK RAM STACK 16 levels Æ2-5 16 levels Æ2-6 System reset generation circuit RST l Æ3-2 Interrupt INT326 l Æ4-1 Clock generator circuit OSC l Æ5-1 Time base counter TBC l Æ6-1 Timers TIMER l Æ7-1 100 Hz timer counter 100HzTC l Æ8-1 Watchdog timer WDT l Æ9-1 Input port INPUT PORT 1 port ¥ 4 bits — P0 l Æ10-2 I/O port I/O PORT 5 ports ¥ 4 bits — P9 l Æ10-15 PA l PB l Æ10-24 PE l Æ10-30 Melody driver MELODY63K l Æ12-1 Shift register SFT l Æ14-1 LCD driver LCD 16 lines Æ15-1 64 lines Display register (¥ 4 bits) DSPR 256 Æ15-4 Bias generator BIAS l Æ15-6 Battery low detect circuit BLD l Æ16-1 Power supply circuit POWER l Æ17-1 Call Register Port 0 Port 9 Port A Port B Port E COM SEG 1 port ¥ 2 bits P8 l Port 8 Voice synthesis VOICE SYNTHESIS l Æ13-1 External memory transfer EXTMEM l Æ11-1 Output port OUTPUT PORT 4 ports ¥ 4 bits — P4 l Æ10-7 Port 4 P5 l Port 5 P6 l Port 6 P7 l Port 7 PF l Æ10-35 Port F

Chapter 1 Overview 1.4 Block Diagram Figure 1-1 is the block diagram of the ML63326. Asterisks (*) indicate the secondary function of each port. Signal names enclosed by chain lines ( ) indicate interface signals of the VDDI power supply system. XT0 OSCL RAM 1536 ¥ 4 bits RESET RST VDDI TIMER 8 bits ¥ 4 SCLK* 4 INT SFT TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* 1 INT I/O PORT P9.0–P9.3 3 INT VDDH CB1 CB2 DATA BUS TBC 4 INT BLD INT 100HzTC 1 DOUBLER VSS 1 INT INPUT PORT P0.0–P0.3 LCD & DSPR COM1–16 SEG0–63 TST1 TST TST2 INT WDT 1 VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDL BIAS INT326 ROM 24K ¥ 16bits BUS CON- TROL MIE CBR EBR L C G Z ALU RA A IR INSTRUCTION DECODER nX-4/250 PC H Y X TIMING CON- TROL SP RSP STACK CAL.S : 16-levels REG.S : 16-levels EXTMEM D0–D7* A0–A15* RD* WR* OUTPUT PORT PA.0–PA.3 PB.0–PB.3 PE.0–PE.3 P4.0–P4.3 P5.0–P5.3 P6.0–P6.3 P7.0–P7.3 P8.0, P8.1 PF.0–PF.3 SOUT* SIN* MELODY63K INT 1 VTEST OSCH XT1 OSC0 OSC1 BUSYB VOICE INTERFACE INT 1 ENVOICE Address Controller 17-bit Multiplexer 17-bit Address Counter PCM Synthesizer ADPCM Synthesizer 1-Mbit ROM Phrase Address Latch MELODY Multiplexer 12-bit DAC AMP2 SP(+) SPEN SP(–) SPIN AMP1 DACOUT AOUT Multiplexer AVDD VREF MD MDB The voice synthesis section VDD Figure 1-1 ML63326 Block Diagram

Chapter 1 Overview 1 1.5 Pin Configuration The ML63326 pin configuration, chip pin configuration, and pad coordinates are shown in Figures 1-2, 1-3, and Table 1-2, respectively. NC (not connected) indicates an unused pin that is left unconnected (open). Figure 1-2 ML63326 176-Pin LQFP Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 (NC) (NC) (NC) (NC) SEG22 SEG23 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 38 39 40 41 SEG58 SEG59 SEG60 SEG61 42 43 44 SEG62 SEG63 (NC) OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS COM16 COM15 COM14 COM13 COM12 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 (NC) (NC) (NC) PE.3 PF.0 PF.1 PF.2 PF.3 VDDI SPEN ENVOICE BUSYB VTEST TST2 TST1 XT0 XT1 RESET COM11 COM10 COM9 (NC) (NC) MD MDB AVSS VSS P0.0 P0.1 P0.2 P0.3 P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 P6.1 P6.2 PA.0 PA.1 PA.2 PA.3 PB.0 PB.1 95 94 93 92 PB.2 PB.3 PE.0 PE.1 91 90 89 PE.2 (NC) (NC) SEG24 SEG25 SEG26 SEG27 SEG28 (NC) (NC) P6.3 P7.0 P7.1 P7.2 P7.3 P8.0 P8.1 P9.0 P9.1 P9.2 P9.3 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 VREF AVDD VDD COM1 COM2 COM3 COM4 COM5 COM6 COM7 (NC) (NC) (NC) DACOUT SP(–) SP(+) SPIN AOUT

Chapter 1 Overview • Chip size : 5.824 mm ¥ 6.370 mm • Chip thickness : 350 mm (280 mm: available as required) • Coordinate origin : center of chip • Pad hole size : 100 mm ¥ 100 mm • Pad size : 110 mm ¥ 110 mm • Minimum pad pitch : 140 mm ! Note: The chip substrate voltage is VSS. Figure 1-3 ML63326 Chip Pin Configuration (Top View) 50 SEG33 SEG21 38 Y X 81 COM9 MD 159 MDB 158 AVSS 157 VSS 156 P0.0 155 P0.1 154 P0.2 153 P0.3 152 P4.0 151 P4.1 150 P4.2 149 SEG20 37 82 COM10 SEG19 36 83 COM11 SEG18 35 84 COM12 SEG17 34 85 COM13 SEG16 33 86 COM14 SEG15 32 87 COM15 SEG14 31 88 COM16 SEG13 30 89 VSS SEG12 29 90 VDD1 SEG11 28 91 VDD2 SEG10 27 92 VDD3 SEG9 26 93 VDD4 SEG8 25 94 VDD5 SEG7 24 95 C1 SEG6 23 96 C2 SEG5 22 97 VDDH SEG4 21 98 CB1 SEG3 20 99 CB2 SEG2 19 100 VDD SEG1 18 101 VDDL SEG0 17 102 OSC1 COM8 16 103 OSC0 COM7 15 104 RESET COM6 14 105 XT1 COM5 13 106 XT0 COM4 12 107 TST1 COM3 11 108 TST2 COM2 10 109 VTEST COM1 9 110 BUSYB 111 ENVOICE 112 SPEN 113 VDDI 114 PF.3 115 PF.2 116 PF.1 117 PF.0 118 PE.3 VDD 8 AVDD 7 VREF 6 AOUT 5 SPIN 4 SP(+) 3 SP(–) 2 DACOUT 1 51 SEG34 P4.3 148 52 SEG35 P5.0 147 53 SEG36 P5.1 146 54 SEG37 P5.2 145 55 SEG38 P5.3 144 56 SEG39 P6.0 143 57 SEG40 P6.1 142 58 SEG41 P6.2 141 59 SEG42 P6.3 140 60 SEG43 P7.0 139 61 SEG44 39 SEG22 40 SEG23 41 SEG24 42 SEG25 43 SEG26 44 SEG27 45 SEG28 46 SEG29 47 SEG30 48 SEG31 49 SEG32 P7.1 138 62 SEG45 P7.2 137 63 SEG46 P7.3 136 64 SEG47 P8.0 135 65 SEG48 P8.1 134 66 SEG49 P9.0 133 67 SEG50 P9.1 132 68 SEG51 P9.2 131 69 SEG52 P9.3 130 70 SEG53 PA.0 129 71 SEG54 PA.1 128 72 SEG55 PA.2 127 73 SEG56 PA.3 126 74 SEG57 PB.0 125 75 SEG58 PB.1 124 76 SEG59 PB.2 123 77 SEG60 78 SEG61 79 SEG62 80 SEG63 PB.3 122 PE.0 121 PE.1 120 PE.2 119 ML63326

Chapter 1 Overview 1 Table 1-2 ML63326 Pad Coordinates Pad No. Pad No. Pad name Pad name X (mm) X (mm) Y (mm) Y (mm) Center of chip: x = 0, y = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DACOUT SP(–) SP(+) SPIN AOUT VREF AVDD VDD COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 –2582 –2442 –2302 –2162 –2022 –1882 –1742 –1592 –1447 –1306 –1166 –1026 –886 –746 –606 –466 –326 –186 –46 94 234 374 514 655 795 935 1075 1215 1355 1495 1635 1775 1915 2055 2195 2335 2476 2616 2766 2766 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –3039 –2897 –2757 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 2766 –2617 –2476 –2336 –2196 –2056 –1916 –1776 –1636 –1496 –1356 –1216 –1076 –936 –796 –656 –515 –375 –235 –95 45 185 325 465 605 745 885 1025 1165 1306 1446 1586 1726 1866 2006 2146 2286 2426 2566 2706 2846

Chapter 1 Overview Table 1-2 ML63326 Pad Coordinates (continued) Pad No. Pad No. Pad name Pad name X (mm) X (mm) Y (mm) Y (mm) Center of chip: x = 0, y = 0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDH CB1 CB2 VDD VDDL OSC1 OSC0 RESET XT1 XT0 TST1 TST2 VTEST BUSYB ENVOICE SPEN VDDI PF.3 PF.2 PF.1 PF.0 PE.3 PE.2 PE.1 2609 2469 2329 2189 2048 1908 1768 1628 1488 1348 1208 1068 928 788 648 508 368 227 87 –53 –193 –333 –473 –613 –753 –893 –1033 –1173 –1313 –1453 –1593 –1734 –1874 –2014 –2154 –2294 –2434 –2574 –2766 –2766 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 2772 2632 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 PE.0 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P8.1 P8.0 P7.3 P7.2 P7.1 P7.0 P6.3 P6.2 P6.1 P6.0 P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P0.3 P0.2 P0.1 P0.0 VSS AVSS MDB MD –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 –2766 2492 2352 2212 2072 1932 1792 1652 1512 1372 1231 1091 951 811 671 531 391 251 111 –29 –169 –309 –449 –590 –730 –870 –1010 –1150 –1290 –1430 –1570 –1710 –1850 –1990 –2130 –2270 –2411 –2551 –2691 –2831

Chapter 1 Overview 1 1.6 Pin Descriptions 1.6.1 Descriptions of the Basic Pin Functions The basic functions of the ML63326 pins are listed in Table 1-3. Use of a slash ("/") in a pin name indicates that the pin has a secondary function. Refer to section 1.6.2, "Descriptions of the Secondary Pin Functions." In the I/O column, "—" indicates a power supply pin, "I" indicates an input pin, "O" indicates an output pin, and "I/O" indicates an input/output pin. Table 1-3 Pin Description (Basic Functions) ClassificationPin name I/O VDD — VSS — VDD1 VDD2 VDD3 — VDD4 Power Supply VDD5 C1 C2 — VDDI — VDDL — VDDH — CB1 — CB2 XT0 I Oscillator XT1 O OSC0 I OSC1 O Function Postive power supply pin Negative power supply pin Power supply pins for LCD bias (internally generated): Connect capacitors (0.1 mF) between these pins and VSS. Capacitor connection pins for LCD bias generation: Connect a capacitor (0.1 mF) between C1 and C2. Positive power supply pin for external interface (Power supply for input, output and I/O ports) Positive power supply pin for internal logic (internally generated): Connect a capacitor (0.1 mF) between pin and VSS. Power supply pin for the high-speed clock generator circuit: Connect a capacitor (1.0 mF) between pin and VSS. Capacitor connection pins for VDDH generation: Connect a capacitor (1.0 mF) between CB1 and CB2. Low-speed clock oscillation pins: Crystal oscillation or RC oscillation is selected by the mask option. If crystal oscillation is selected, connect a crystal between XT0 and XT1, and connect capacitor (CG) between XT0 and VSS. If RC oscillation is selected, connect external oscillation resistor (ROSL) between XT0 and XT1. High-speed clock oscillation pins: Connect a crystal and capacitors (CL0, CL1) or external oscillation resistor (ROSH) to these pins. TST1 I Input pins for testing: Pull-down resistors are built-in. Test TST2 8, 100 89, 156 92 96 113 101 97 99 106 105 103 102 107 108 67, 143 56, 128 59 63 80 68 64 66 73 72 70 69 74 75 90 91 57 58 95 62 93 94 60 61 98 65 VREF 6 141 AVDD 7 142 AVSS 157 129 — Pin for volume adjustment — — Positive power supply pin for analog circuits Negative power supply pin for analog circuits VTEST 109 76 RESET I Reset input pin: Setting this pin to a "H" level causes internal circuitry settings and values to be initialized. Next, if this pin is set to a "L" level, the execution of instructions will begin from address 0000H. A pull-down resistor is built-in. Reset 104 71 Pad No. Pin No.

Chapter 1 Overview Table 1-4 Pin Description (Basic Functions) (continued) ClassificationPin name I/O P0.0/INT5 I Function 4-bit input port: Each bit can be selected as the following. • Input with pull-up resistor • Input with pull-down resistor • High-impedance input P0.1/INT5 P0.2/INT5 P0.3/INT5 155 154 153 152 DACOUT Voice output pin (12-bit DAC output) 1 O 136 AOUT Voice output pin (amplifier output using DACOUT as input) 5 O 140 SPIN Amplifier input pin for driving a piezoelectric speaker 4 I 139 SP(–) Output pin for driving a piezoelectric speaker (negative side) 2 O 137 SP(+) Output pin for driving a piezoelectric speaker (positive side) 3 O 138 SPEN Enable signal of the amplifier for driving a piezoelectric speaker 112 I 79 BUSYB Voice synthesis section output monitor pin 110 O 77 ENVOICE Voice synthesis section enable monitor pin 111 O 78 Voice 127 126 125 124 4-bit output port: Each bit can be selected as the following. • P-channel open drain output • N-channel open drain output • CMOS output • High-impedance output P4.0/A0 151 123 P4.1/A1 150 122 P4.2/A2 149 121 P4.3/A3 148 120 O P5.0/A4 147 119 P5.1/A5 146 118 P5.2/A6 145 117 P5.3/A7 144 116 O P6.0/A8 143 115 P6.1/A9 142 114 P6.2/A10 141 113 P6.3/A11 140 112 O P7.0/A12 139 111 P7.1/A13 138 110 P7.2/A14 137 109 P7.3/A15 136 108 O MD O Melody output pin (positive phase) Melody MDB O Melody output pin (reversed phase) 159 158 131 130 Port P8.0/RD 135 107 P8.1/WR 134 106 I/O 2-bit I/O port: During the input mode, each bit can be selected as the following. • Input with pull-up resistor • Input with pull-down resistor • High-impedance input During the output mode, each bit can be selected as the following. • P-channel open drain output • N-channel open drain output • CMOS output • High-impedance output Pad No. Pin No.

Chapter 1 Overview 1 Table 1-3 Pin Description (Basic Functions) (continued) P9.0 I/O 4-bit I/O port: During the input mode, each bit can be selected as the following. • Input with pull-up resistor • Input with pull-down resistor • High-impedance input During the output mode, each bit can be selected as the following. • P-channel open drain output • N-channel open drain output • CMOS output • High-impedance output 4-bit I/O port: During the input mode, each bit can be selected as the following. • Input with pull-up resistor • Input with pull-down resistor • High-impedance input During the output mode, each bit can be selected as the following. • P-channel open drain output • N-channel open drain output • CMOS output • High-impedance output 4-bit I/O port: During the input mode, each bit can be selected as the following. • Input with pull-up resistor • Input with pull-down resistor • High-impedance input During the output mode, each bit can be selected as the following. • P-channel open drain output • N-channel open drain output • CMOS output • High-impedance output P9.1 P9.2 P9.3 PA.0 I/O PA.1 PA.2 PA.3 PB.0/INT0/ TM0CAP/ TM0OVF/ I/O PB.1/INT0/ TM1CAP/ TM1OVF PB.2/INT0/ T02CK PB.3/INT0/ T13CK 97 96 95 94 133 132 131 130 129 128 127 126 125 124 123 122 ClassificationPin name I/O Function Port 105 104 103 102 101 100 99 98 4-bit I/O port: During the input mode, each bit can be selected as the following. • Input with pull-up resistor • Input with pull-down resistor • High-impedance input During the output mode, each bit can be selected as the following. • P-channel open drain output • N-channel open drain output • CMOS output • High-impedance output PE.0/SIN I/O PE.1/SOUT PE.2/SCLK PE.3/INT2 93 92 91 85 121 120 119 118 PF.0/INT3 117 84 PF.1/INT3 116 83 PF.2/INT3 115 82 PF.3/INT3 114 81 I/O Pad No. Pin No.

Chapter 1 Overview Table 1-3 Pin Description (Basic Functions) (continued) ClassificationPin name I/O Function LCD common signal output pins (COM1 to COM16) LCD segment signal output pins (SEG0 to SEG26) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 LCD O O 9 144 10 145 11 146 12 147 13 148 14 149 15 150 16 151 81 48 82 49 83 50 84 51 85 52 86 53 87 54 88 55 17 152 18 153 19 154 20 155 21 156 22 157 23 158 24 159 25 160 26 161 27 162 28 163 29 164 30 165 SEG26 SEG25 42 5 43 6 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 31 166 32 167 33 168 34 169 35 170 36 171 37 172 38 173 39 2 40 3 41 4 Pad No. Pin No.

Chapter 1 Overview 1 ClassificationPin name I/O Function LCD O SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 44 7 45 8 46 9 47 10 48 11 49 12 50 13 51 14 52 15 53 16 54 17 55 18 56 19 57 20 58 21 59 22 60 23 61 24 62 25 63 26 64 27 65 28 66 29 67 30 68 31 69 32 70 33 71 34 Pad No. Pin No. LCD segment signal output pins (SEG27 to SEG63) SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 72 35 73 36 74 37 75 38 76 39 77 40 78 41 79 42 80 43 Table 1-3 Pin Description (Basic Functions) (continued)

Chapter 1 Overview 1.6.2 Descriptions of the Secondary Pin Functions The secondary functions of the ML63326 pins are listed in Table 1-4. Table 1-4 Pin Description (Secondary Functions) ClassificationPin name I/O PB.0/INT0 External interrupt I Function External interrupt 0 input pins: Changes in the input signal level cause interrupts to be generated. Interrupts can be enabled or disabled for each bit by the port B interrupt enable register (PBIE). PB.1/INT0 PB.2/INT0 PB.3/INT0 PE.3/INT2 I External interrupt 2 input pin: Changes in the input signal level cause interrupts to be generated. P0.0/INT5 I External interrupt 5 input pins: Changes in the input signal level cause interrupts to be generated. Interrupts can be enabled or disabled for each bit by the port 0 interrupt enable register (P0IE). P0.1/INT5 P0.2/INT5 P0.3/INT5 PB.0/ TM0CAP Capture I Timer 0 capture trigger input pin PB.1/ TM1CAP I Timer 1 capture trigger input pin PB.0/ TM0OVF Timer O Timer 0 overflow flag output pin PB.1/ TM1OVF O Timer 1 overflow flag output pin PB.2/ T02CK I Timer 0, timer 2 external clock input pin PB.3/ T13CK I Timer 1, timer 3 external clock input pin PE.0/SIN Shift register I Shift register receive data input pin PE.1/SOUT O Shift register transmit data output pin PE.2/SCLK I/O Shift register clock input/output pin: This pin should be configured as the clock output when this device is used as the master processor, or as the clock input when used as a slave. 97 96 95 94 85 97 96 97 96 95 94 93 92 91 125 124 123 122 118 155 154 153 152 125 124 125 124 123 122 121 120 119 Pad No. PF.0/INT3 I External interrupt 3 input pins: Changes in the input signal level cause interrupts to be generated. Interrupts can be enabled or disabled for each bit by the port F interrupt enable register (PFIE). PF.1/INT3 PF.2/INT3 PF.3/INT3 117 116 115 114 84 83 82 81 127 126 125 124 Pin No.

Chapter 1 Overview 1 Table 1-4 Pin Description (Secondary Functions) (continued) ClassificationPin name I/O P4.0/A0 External memory O Function P4, P5, P6, P7 secondary functions: Address bus signals for external memory access. P4.1/A1 P4.2/A2 P4.3/A3 P6.2/A10 P6.3/A11 P7.0/A12 P7.1/A13 123 122 121 120 151 150 149 148 141 140 139 138 Pad No. P5.2/A6 P5.3/A7 P6.0/A8 P6.1/A9 145 144 143 142 117 116 115 114 113 112 111 110 P5.0/A4 119 147 P5.1/A5 118 146 P7.2/A14 137 109 P7.3/A15 136 108 P9.0/D0 133 105 P9.1/D1 132 104 P9.2/D2 131 103 P9.3/D3 130 102 PA.0/D4 129 101 PA.1/D5 128 100 PA.2/D6 127 99 PA.3/D7 126 98 I/O P9, PA secondary functions: Data bus signals for external memory access. P8.0 secondary function: Read signal (negative logic) for external memory access. P8.0/RD 135 107 P8.1 secondary function: Write signal (negative logic) for external memory access. P8.1/WR 134 106 O O Pin No.

Chapter 1 Overview ! Notes: 1. If a pin set as a high impedance input is left unconnected, the supply current may become excessive. Therefore, it is recommended that unused input ports and input/output ports be set as inputs with either a pull-down or pull-up resistor. 2. When test pins TST1 and TST2 are left unconnected, malfunction may result if there is a large amount of external noise. Therefore, it is recommended to permanently connect TST1 and TST2 to VSS. 3. Connect a capacitor (0.1 mF) between the VDD2 pin and the VSS pin when the LCD drivers are not used. 1.6.3 Unused Pin Processing Table 1-5 lists the handling of unused pins. Table 1-5 Unused Pin Handling Pin Recommended pin handling OSC0, OSC1 Open CB1, CB2 Open TST1, TST2, VTEST Open or VSS P0.0–P0.3 Open P9.0–P9.3 Open PA.0–PA.3 Open PB.0–PB.3 Open PE.0–PE.3 Open MD, MDB Open COM1–COM16 Open SEG0–SEG63 Open C1, C2 Open VDD1, VDD3, VDD4, VDD5 Open P4.0–P4.3 Open PF.0–PF3 Open VREF Open VDDH Open P5.0–P5.3 Open P6.0–P6.3 Open P7.0–P7.3 Open P8.0, P8.1 Open DACOUT, AOUT Open SPIN VSS SPEN Open SP(–), SP(+) Open AVDD VDD AVSS VSS BUSYB, ENVOICE Open

Chapter 1 Overview 1 1.7 Basic Timing 1.7.1 Basic Timing of CPU Operation The system clock (CLK) uses the low-speed oscillation clock using the XT0 and XT1 pins or the high-speed oscillation clock using the OSC0 and OSC1 pins (1/2 frequency waveform when a crystal oscillator is used, no frequency division when an RC oscillator is used).The system clock signal is in phase with the signal from the XT1 pin or the OSC1 pin. As shown in Figure 1-4, a single machine cycle is composed of two states, S1 and S2. One state is the interval from a falling edge of CLK to the falling edge of the next CLK. Instructions are processed in machine cycle units and each instruction is executed in 1 to 3 machine cycles. Instructions are classified according to the number of machine cycles: 1 machine cycle instructions (M1), 2 machine cycle instructions (M1 + M2), and 3 machine cycle instructions (M1 + M2 + M3). Most instructions are executed in 1 machine cycle. 1.7.2 Port I/O Basic Timing Figure 1-5 shows the basic I/O timing. During the execution of an instruction that outputs data to a port, setting data (data A) is output at the rising edge of the clock in the S2 state during the machine cycle of that instruction. During the execution of an instruction that inputs data from a port, data at the input pin (data B) is captured internally while the clock is at a "H" level in the S1 state during the machine cycle of that instruction. That data is transferred to the accumulator at the start of the next machine cycle. Figure 1-4 Clock Configuration of Each Machine Cycle CLK M1 M1 M2 M1 M2 M3 S1 S2 S1 S2 S2 S1 S2 S1 S2 S1 S2 S1 (2 clocks) (4 clocks) (6 clocks) 1 machine cycle 2 machine cycles 3 machine cycles

Chapter 1 Overview Figure 1-6 Input Data Example Figure 1-5 Port I/O Basic Timing ! Note: Regarding input signals "0" will be captured in the internal register if a "L" level is input to the input pin even once (q of Figure 1-6) during the data capture interval. "1" will be captured in the internal register only if a "H" level is maintained (w of Figure 1-6) throughout the data capture interval. Therefore, if noise occurs in the input data, implement noise reduction measures with the program and peripheral devices. MOV obj,(data A) Output instruction Input instruction CLK Instruction (example) S1 S2 S1 S2 Output pin Input pin (data B) Accumulator (data B) (data A) MOV A,obj Input instruction Output instruction CLK Capture signal S1 S2 S1 S2 Input pin w q Data bus Accumulator "0" "1"

Chapter 1 Overview 1 1.7.3 Interrupt Basic Timing Figure 1-7 shows the basic interrupt timing. As shown in the figure, when an interrupt factor is generated, the interrupt factor is sampled at the falling edge of CLK and an interrupt request (IRQ) is set at the first half of S1. When an interrupt condition is established and the CPU receives an interrupt, the interrupt routine will start beginning from the next machine cycle. Figure 1-7 Interrupt Basic Timing M1 M2 CLK Interrupt factor S1 S2 S1 S2 S1 S2 IRQ Process Main routine PC 1st interrupt address Interrupt routine

Chapter 2 CPU and Memory Spaces 2 Chapter 2 CPU and Memory Spaces 2.1 Overview The ML63326 is equipped with an Oki’s original CPU core nX-4/250. The instruction set of the nX-4/250 core consists of 439 types of instructions. The memory space consists of a 16-bit wide program memory space, a 4-bit wide data memory space, and an 8-bit wide memory space for storing voice synthesis and character data. Further, it is possible to add an 8-bit wide memory space for voice synthesis and for storing character data. A stack for saving the program counter during a subroutine call or interrupt (call stack) and a stack for saving registers during a PUSH instruction (register stack) are provided separately from the memory space. The program memory space is used for program data, ROM table data and melody note data. In the data memory space, special function registers (SFRs) are located in BANK 0, the LCD display register (DSPR) in BANK 1, and data RAM in BANKS 2 to 7. 2.2 Registers The nX-4/250 core processes data mainly with the accumulator and register set. The register set is a programming model consisting of the HL and XY registers that store data memory addresses, the current bank register (CBR), the extra bank register (EBR), the RA register that stores program memory addresses, registers that control program flow, and registers that control flags and memory. 2.2.1 Accumulator (A) The accumulator (A) is the central register for various arithmetic operations. At system reset, the accumulator is initialized to "0". When an interrupt occurs, a "PUSH HL" instruction can be used if necessary to save the accumulator on the register stack. The accumulator can be restored with a "POP HL" instruction. 3 2 1 0 Accumulator A G C Z Flag register 2.2.2 Flag Register The flag register consists of 3 flags: the carry flag (C), the zero flag (Z) and the G flag (G). When an interrupt occurs, a "PUSH HL" instruction can be used if necessary to save the flag register on the register stack. The flag register can be restored with a "POP HL" instruction. 2.2.2.1 Carry Flag (C) The carry flag (C) is a 1-bit flag that is loaded with a carry during addition or a borrow during subtraction. At system reset, the carry flag is initialized to "0".

Chapter 2 CPU and Memory Spaces 2.2.2.2 Zero Flag (Z) The zero flag (Z) is a 1-bit flag that is set to "1" when the contents of the accumulator (A) are loaded with "0H". The zero flag is set to "0" when the contents of the accumulator (A) are loaded with a value other than "0H". However, the XCH instruction does not change the zero flag. At system reset, the zero flag is initialized to "0". 2.2.2.3 G Flag (G) The G flag (G) changes to "1" when the HL, XY or RA registers overflow as the result of execution of a post-increment register indirect addressing instruction or as the result of an increment instruction for the HL, XY or RA registers. At system reset, the G flag is initialized to "0". 2.2.3 Master Interrupt Enable Flag (MIE) MIE (bit 0 of MIEF) is a flag that disables or enables all interrupts except for the watchdog timer interrupt. MIEF is a 4-bit register in which bit 0 is the master interrupt enable flag (MIE). If MIE is "0", all interrupts are disabled. If MIE is "1", all interrupts are enabled (with the exception of the watchdog timer). When any interrupt is received, MIE is cleared to "0". MIE is set to "1" by execution of a return from interrupt instruction (RTI instruction). If multi-level interrupt processing is to be performed, execute a RTI instruction (MIE¨"1") during the interrupt processing routines. At system reset, MIE is initialized to "0". MIEF only supports data reference (R) of data memory through addressing instructions. ! Note: When setting MIE, use "EI" instructions (MIE¨"1") and "DI" instructions (MIE¨"0"). — — — MIE MIEF (0FFH) Master Interrupt Enable Flag 0: Interrupts disabled (initial value) 1: Interrupts enabled bit 3 bit 2 bit 1 bit 0 (R)

Chapter 2 CPU and Memory Spaces 2 2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR), HL Register (HL), XY Register (XY) The CBR, EBR, HL, and XY registers are used for indirect addressing of data memory. The CBR and EBR registers indicate the data memory bank. The HL and XY registers indicate addresses in the bank. CBR is also used in combination with 8-bit data in the instruction code for direct addressing within the current bank. Figure 2-1 shows the various register combinations. CBR CBR EBR EBR CBR H L X Y H L X Y Instruction code 8-bit data + + + + A11–A8 A7–A4 A3–A0 + Figure 2-1 Various Register Combinations A11 to A0 in Figure 2-1 indicate data memory addresses (4K nibbles max.). At system reset, the CBR, EBR, HL, and XY registers are initialized to "0". When an interrupt occurs, a "PUSH HL" or "PUSH XY" instruction can be used if necessary to save the CBR, EBR, HL, and XY registers on the register stack. These registers can be restored with a "POP HL" or "POP XY" instruction. The CBR, EBR, HL, and XY registers are assigned to special function register (SFR) addresses 0F9H to 0FEH. e3 e2 e1 e0 EBR bit 3 bit 2 bit 1 bit 0 c3 c2 c1 c0 CBR bit 3 bit 2 bit 1 bit 0 H bit 3 bit 2 bit 1 bit 0 L bit 3 bit 2 bit 1 bit 0 h3 h2 h1 h0 l3 l2 l1 l0 X bit 3 bit 2 bit 1 bit 0 Y bit 3 bit 2 bit 1 bit 0 x3 x2 x1 x0 y3 y2 y1 y0 (0FDH) (R/W) (0FCH) (R/W) (0FBH) (R/W) (0FAH) (R/W) (0F9H) (R/W) (0FEH) (R/W)

Chapter 2 CPU and Memory Spaces 2.2.5 Program Counter (PC) The program counter (PC) is a counter with 16 valid bits that specifies the program memory space. 2.2.6 RA Registers (RA3, RA2, RA1, RA0) The RA registers are used for indirect program memory addressing (ROM table reference instructions). Figure 2-2 shows the address configuration of the RA registers. At system reset, RA3 to RA0 are initialized to "0". ! Note: When executing a ROM table reference instruction that uses RA registers, do not use addresses located in the SFR area to transfer ROM table data to RA registers, otherwise indirect addressing of program memory will not operate properly. RA3 RA2 RA1 RA0 A15–A12 A11–A8 A7–A4 A3–A0 Figure 2-2 Address Configuration of RA3 to RA0 Registers Within the A15 to A0 of Figure 2-2, A14 to A0 indicate program memory addresses (32K words max.). RA3 to RA0 are assigned to special function register (SFR) addresses 0F2H to 0F5H. a15 a14 a13 a12 RA3 bit 3 bit 2 bit 1 bit 0 a11 a10 a9 a8 RA2 bit 3 bit 2 bit 1 bit 0 RA1 bit 3 bit 2 bit 1 bit 0 RA0 bit 3 bit 2 bit 1 bit 0 a7 a6 a5 a4 a3 a2 a1 a0 (0F5H) (R/W) (0F4H) (R/W) (0F3H) (R/W) (0F2H) (R/W)

Chapter 2 CPU and Memory Spaces 2 2.2.7 Stack Pointer (SP) and Call Stack The stack pointer (SP) is a pointer that indicates the call stack address where the program counter is saved when a subroutine call or interrupt occurs. The SP is a 4-bit up/down counter that is incremented during stack saves and is decremented during stack restores. The call stack has 16 levels from address 0H to address 0FH. Because the hardware requires 1 level of the call stack during program execution, only 15 levels can be used for stack saves. The contents of the call stack cannot be read or written by the program. Figure 2-3 shows the relation between SP and the call stack. 3 2 1 0 SP Stack pointer Call stack 0FH 16 levels 0H 15 bits Figure 2-3 Relation Between SP and Call Stack SP is assigned to special function register (SFR) address 0F7H. SP3 SP2 SP1 SP0 SP (0F7H) (R) bit 3 bit 2 bit 1 bit 0 At system reset, SP is initialized to "0" and points to address "0H" of the call stack. SP is a read-only register and writes are invalid.

Chapter 2 CPU and Memory Spaces 2.2.8 Register Stack Pointer (RSP) and Register Stack The register stack pointer (RSP) is a pointer that indicates the register stack address for saving various registers. RSP is a 4-bit up/down counter that is incremented during stack saves (execution of PUSH instructions) and is decremented during stack restores (execution of POP instructions). The register stack has 16 levels from address 0H to address 0FH. The contents of the register stack cannot be read or written by the program. Figure 2-4 shows the relation between RSP and the register stack. 2 1 0 RSP Register stack pointer Register stack 0FH 16 levels 0H 16 bits 3 Figure 2-4 Relation Between RSP and Register Stack The various registers shown in Figure 2-5 are saved onto and restored from the register stack by PUSH and POP instructions. At system reset, RSP is initialized to "0" and points to address "0H" of the register stack. rsp3 rsp2 rsp1 rsp0 RSP (0F6H) bit 3 bit 2 bit 1 bit 0 (R/W) L H A Z C G — 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register stack "PUSH HL" and "POP HL" instruction execution Y X CBR EBR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register stack "PUSH XY" and "POP XY" instruction execution Figure 2-5 Register Save/Restore by Execution of PUSH/POP Instructions RSP is assigned to special function register (SFR) address 0F6H.

Chapter 2 CPU and Memory Spaces 2 2.3 Memory Spaces 2.3.1 Program Memory Space The program memory space is the read-only memory that stores program data. The program memory space has a data length of 16 bits and extends from address 0000H to address 5FFFH in the ML63326. In addition to program data, the program memory can also store ROM table data and the melody data. Figure 2-6 shows the configuration of the program memory space. Program data or ROM table data or Melody data 40 words 24,544 words Interrupt area 0000H 0010H 0037H 5FFFH 32 words 5FDFH Test data area Figure 2-6 Program Memory Space Configuration After system reset, instruction execution begins at address 0000H. The interrupt area from address 0010H to address 0037H contains starting addresses of the interrupt processing routines that are executed when interrupts are generated. (Refer to Chapter 4, "Interrupt.") ROM table data is transferred to data memory by ROM table reference instructions. The melody data defines the tone, tone length, and end tone used in the melody circuit (MELODY63K) of the ML63326. After an MSA instruction specifies the starting address, the melody data is automatically transferred to the melody circuit when a melody data interrupt occurs. (Refer to Chapter 12, "Melody Driver.") Because the test data area contains program data for testing, it cannot be used as a program data area.

Chapter 2 CPU and Memory Spaces 2.3.2 Data Memory Space The data memory space contains data RAM and special function registers (SFRs). The data memory consists of 8 banks. One bank unit is 256 nibbles. BANK 0 is allocated as a SFR area, BANK 1 as the LCD display register, and BANK 2 and the following BANKS are data RAM. Figure 2-7 shows the configuration of the data memory space. BANK5 BANK2 BANK1 BANK0 7FFH 300H 2FFH 200H 1FFH 100H 0FFH 000H Data RAM area (1536 nibbles) Display register (256 nibbles) SFR area (256 nibbles) BANK3 400H 3FFH 500H 4FFH BANK4 600H 5FFH 700H 6FFH BANK6 BANK7 Figure 2-7 Data Memory Space Configuration

Chapter 2 CPU and Memory Spaces 2 2.3.3 Memory Space for Voice Synthesis and Character Data The memory space for voice synthesis and character data is configured by a mask ROM that stores the voice data necessary for the built-in voice synthesis function and the character data used for the LCD display. Figure 2-8 Memory Space Configuration 1FFFFH 0000H 131,072 bytes 8 bits

Chapter 2 CPU and Memory Spaces 2.3.4 External Memory Space The external memory space is one for storing the voice data necessary for the built-in voice synthesis function and the character data used for the LCD display, and is accessed via a port. The external memory space configuration is shown in Figure 2-9. Figure 2-9 External Memory Space Configuration 7FFFFH 0000H 524,288 bytes 8 bits

Chapter 3 CPU Control Functions 3 Chapter 3 CPU Control Functions 3.1 Overview Operating states, including system reset, are classified as follows. • Normal operation mode • System reset mode • Halt mode Figure 3-1 shows the CPU operating state transition diagram. Figure 3-1 Operating State Transition Diagram The normal operation mode is the state in which the CPU executes instructions sequentially. The system reset mode begins when a reset input causes the CPU to begin system reset processing where registers and pins are initialized. The CPU remains in this state until instruction execution begins. After system reset processing, instruction execution begins from address 0000H. The halt mode is the state in which the CPU is halted (instruction execution suspended) but internal peripheral functions continue to operate. During the halt mode, the PC is not incremented. Even upon entering the halt mode, port and peripheral functions will not change. Transfer to the halt mode is accomplished by executing a "HALT" instruction. Normal operation mode Halt mode System reset mode RESET = "H" RESET = "H" RESET = "L" Power on detect Low-speed clock oscillation halt detect HALT instruction execution Interrupt generated

Chapter 3 CPU Control Functions 3.2 System Reset Mode (RST) 3.2.1 Transfer to and State of System Reset Mode The following three factors cause a transfer to the system reset mode. • Setting the RESET pin to a "H" level (for 1 ms or more) • Detection of power on • Detection that low-speed clock oscillation is halted The following operations are performed in the system reset mode. (1) CPU is initialized. (2) Backup flag changes to "1" and backup circuit changes to ON state. (3) Bias reference voltage supply (VR) is energized. (4) All LCD driver outputs are turned OFF and the outputs change to the VSS level. (5) All special function registers (SFRs) are initialized. However, data RAM and display registers are not initialized. After system reset processing, instruction execution begins from address 0000H. Figures 3-2 and 3-3 show the system reset generator circuit and signals when a system reset is generated. Figure 3-3 Signals When System Reset is Generated ! Note: • System reset takes priority over all other processing and terminates all processing up to that point in time. Therefore, the contents of RAM and display registers, which are not initialized, cannot be guaranteed after a system reset. • When performing transfer to the system reset mode by setting the RESET pin to a "H" level, set the RESET pulse width to 1 ms or more. Figure 3-2 System Reset Generator Circuit RESET Power ON detect Low-speed clock oscillation halt detect R Q RESET0 (Time base counter reset) RESETS (System reset) 4 Hz S VSS Sampling circuit 2 kHz RESET0 Crystal oscillation output RESETS 32.768 kHz 125 ms CPU start

Chapter 3 CPU Control Functions 3 3.3 Halt Mode 3.3.1 Transfer to and State of Halt Mode Transfer to the halt mode is performed by the software when a HALT instruction is executed. When a HALT instruction is executed, the CPU enters the HALT mode at the S2 state of the HALT instruction. Oscillation and time base counter operation continue while in the halt mode. If an interrupt request occurs at the same time as execution of a HALT instruction, interrupt processing has priority and the HALT instruction will not be executed. After the HALT instruction performs the equivalent operation of a NOP instruction, the interrupt routine is entered. When an RTI instruction is used to complete the interrupt routine, the main routine is resumed beginning from the instruction immediately following the HALT instruction. Figure 3-4 shows the timing when a HALT instruction and interrupt request occur simultane- ously. S1 S2 S1 S2 S1 S2 S2 S1 S2 S1 S2 S1 S2 S1 S2 HALT HALT instruction execution RTI instruction execution HLT (halt flag) Interrupt request INT PC flow in main routine : HALT instruction address : Starting address of interrupt routine : RTI instruction address (equivalent to NOP) Interrupt routine Main routine System clock n n+1 n+2 (INT) (RTI) n (INT) (RTI) Figure 3-4 Timing of Simultaneous HALT Instruction and Interrupt Request ! Note: While an interrupt request is generated, execution of a HALT instruction will not transfer operation to the halt mode.

Chapter 3 CPU Control Functions 3.3.2 Halt Mode Release The following two methods are available to release the halt mode. • Release by interrupt generation (transfer to normal operation mode) • Release by RESET pin (transfer to system reset mode) 3.3.2.1 Release of Halt Mode by Interrupt If the halt mode is to be released by an interrupt, the enable flag of the interrupt used for release must be set to "1" prior to entering the halt mode. When the halt mode is released by an interrupt, operation transfers to the normal operation mode. Figure 3-5 shows the timing of transferring to the halt mode by execution of a HALT instruction and of releasing the halt mode by an interrupt. When the halt mode is released by an interrupt request, the first instruction immediately following the HALT instruction is executed and then the interrupt routine is entered. When an RTI instruction is used to complete the interrupt routine, the main routine is resumed beginning from the second instruction after the HALT instruction. Figure 3-5 Timing of Transfer to Halt Mode and Release of Halt Mode by Interrupt ! Note: If the halt mode is to be released, set individual interrupt enable flags to "1". If an individual interrupt enable flag is "0", the corresponding interrupt request signal cannot reset the HLT flag, regardless of whether the master interrupt enable flag (MIE) is "0" or "1". 3.3.2.2 Release of Halt Mode by RESET Pin If a high-level is input to the RESET pin, the CPU is released from the halt mode and transfers to the system reset mode. S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 HALT HLT (halt flag) Interrupt request INT PC flow in main routine : HALT instruction address : Starting address of interrupt routine : RTI instruction address HALT instruction execution Halt mode RTI instruction execution Main routine Interrupt routine System clock n (RTI) n+2 n+1 (INT) n (INT) (RTI) Execution of instruction immediately after HALT instruction

Chapter 3 CPU Control Functions 3 3.3.3 Melody Data Interrupt and Halt Mode Release The halt mode is not released by a melody data interrupt. The melody data interrupt is different from a conventional interrupt in that the melody data interrupt is a hardware processing interrupt used for transfer of melody data to the melody circuit. It is not dependent on the program. When this interrupt is generated, the instruction immediately after the HALT instruction is executed, then the melody data is transferred to the melody circuit, and the HALT instruction is executed again. This sequence is indicated in Figure 3-6. S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S2 S2 S2 HALT HALT instruction execution n HLT (halt flag) Melody data request PC flow in main routine : HALT instruction address : Melody data address Halt mode Halt mode HALT Melody data transfer HALT instruction execution (melody) Execution of instruction immediately after HALT instruction n System Clock n+1 n+1 n (melody) Figure 3-6 Melody Data Request Interrupt Operation 3.3.4 Note Concerning HALT Instruction As described above, the instruction immediately after the HALT instruction may be executed any number of times. For this reason, always place an NOP instruction immediately after the HALT instruction. (Example) • • • HALT NOP • • •

Chapter 4 Interrupt (INT326) 4 Chapter 4 Interrupt (INT326) 4.1 Overview The ML63326 supports 17 interrupt factors: 4 external interrupts and 13 internal interrupts. With the exception of the watchdog timer interrupt, interrupt enable/disable is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE0 to IE4). Watchdog timer interrupt is a non-maskable interrupt. When interrupt conditions are met, the interrupt routine is executed from the interrupt start address. Table 4-1 indicates a list of interrupt factors, and Figure 4-1 shows the interrupt control equivalent circuit. Table 4-1 List of Interrupt Factors Priority Interrupt factor Symbol Interrupt start address 1 Watchdog timer interrupt WDTINT 0010H 2 Melody end interrupt MDINT 0012H 3 External interrupt 0 (PB 4-bit OR input) XI0INT 0014H 5 External interrupt 2 (PE.3) XI2INT 0018H 7 8 9 Timer 0 interrupt TM0INT 0020H 10 Timer 1 interrupt TM1INT 0022H 11 Timer 2 interrupt TM2INT 0024H 12 Timer 3 interrupt TM3INT 0026H 13 Shift register interrupt SFTINT 002CH 14 15 T10 Hz interrupt T10HzINT 002EH 16 32 Hz interrupt 32HzINT 0030H 16 Hz interrupt 16HzINT 0032H 4 Hz interrupt 4HzINT 0034H 2 Hz interrupt 2HzINT 0036H 17 External interrupt 5 (P0 4-bit OR input) XI5INT 001EH 4 Voice synthesis interrupt VOINT 0016H 6 External interrupt 3 (PF 4-bit OR input) XI3INT 001AH If multiple interrupts are detected simultaneously, the lowest interrupt start address is given priority. For details on interrupt operation, refer to Chapter 6 (Time Base Counter), Chapter 7 (Timers), Chapter 8 (100 Hz Timer Counter), Chapter 9 (Watchdog Timer), Chapter 10 (Ports), Chapter 12 (Melody Driver), Chapter 13 (Voice Synthesis), and Chapter 14 (Shift Register).

Chapter 4 Interrupt (INT326) Interrupt request signals Interrupt request registers Interrupt enable registers IRQ0.0 QWDT IRQ0.2 QXI0 IRQ0.1 QMD IE0.1 EMD IE0.2 EXI0 IRQ0 IE0 MIE Interrupt vector address Priority encoder WDTINT MDINT XI0INT IRQ1.0 QXI2 IRQ1 XI2INT IE1.0 EXI2 IE1 IRQ2.0 QTM0 IRQ2.2 QTM2 IRQ2.1 QTM1 IRQ2.3 QTM3 IRQ2 TM0INT TM1INT TM2INT TM3INT IE2.0 ETM0 IE2.1 ETM1 IE2.2 ETM2 IE2.3 ETM3 IE2 IRQ3.2 QSFT IRQ3.3 Q10Hz IRQ3 SFTINT T10HzINT IE3.2 ESFT IE3.3 E10Hz IE3 IRQ4.0 Q32Hz IRQ4.2 Q4Hz IRQ4.1 Q16Hz IRQ4.3 Q2Hz IRQ4 32HzINT 16HzINT 4HzINT 2HzINT IE4.0 E32Hz IE4.1 E16Hz IE4.2 E4Hz IE4.3 E2Hz IE4 Interrupt request Master interrupt enable flag IRQ1.3 QXI5 XI5INT IE1.3 EXI5 IRQ0.3 QVI VOINT IRQ1.1 QXI3 XI3INT IE1.1 EXI3 IE0.3 EVI Figure 4-1 ML63326 Interrupt Control Equivalent Circuit

Chapter 4 Interrupt (INT326) 4 4.2 Interrupt Registers The following three types of registers are used to control interrupts. (1) Master interrupt enable register (MIEF) (2) Interrupt enable registers (IE0 to IE4) (3) Interrupt request registers (IRQ0 to IRQ4) These registers are described below. (1) Master interrupt enable register (MIEF) MIEF is a 4-bit register in which bit 0 is the master interrupt enable flag (MIE). MIE (bit 0 of MIEF) is a flag that disables or enables all interrupts except for the watchdog timer interrupt. If MIE is "0", all interrupts are disabled. If MIE is "1", all interrupts are enabled (with the exception of the watchdog timer). When any interrupt is received, MIE is cleared to "0". MIE is set to "1" by execution of a return from interrupt instruction (RTI instruction). If multi-level interrupt processing is to be performed, execute a RTI instruction (MIE¨"1") during the interrupt processing routines. At system reset, MIE is initialized to "0". MIEF only supports data reference (R) of data memory through addressing instructions. — — — MIE MIEF Master Interrupt Enable Flag 0: Interrupts disabled (initial value) 1: Interrupts enabled bit 3 bit 2 bit 1 bit 0 (0FFH) (R) ! Note: When setting MIE, use "EI" instructions (MIE¨"1") and "DI" instructions (MIE¨"0").

Chapter 4 Interrupt (INT326) (2) Interrupt enable registers (IE0 to IE4) IE0, IE1, IE2, IE3, and IE4 are registers that consist of 4 bits each. A logical AND of the corresponding bits of an interrupt enable register (IE0 to IE4) and an interrupt request register (IRQ0 to IRQ4) determines whether or not each interrupt request is issued to the CPU. The watchdog timer interrupt is non-maskable, and is therefore not dependent upon the interrupt enable registers (IE0 to IE4) and the master interrupt enable register (MIEF). If multiple interrupts request the CPU at the same time, as shown in Table 5-1, the interrupts are accepted in order of highest priority and low priority interrupts are placed on hold. When an interrupt is received, the master interrupt enable flag (MIE) is cleared to "0". The corresponding bits in the interrupt enable registers (IE0 to IE4) do not change. At system reset, each bit of IE0 through IE4 is initialized to "0". EVI EXI0 EMD — External interrupt 0 enable flag 0: Disable (initial value) 1: Enable bit 3 bit 2 bit 1 bit 0 IE0 (050H) (R/W) Melody end interrupt enable flag 0: Disable (initial value) 1: Enable EXI5 — EXI3 EXI2 External interrupt 5 enable flag 0: Disable (initial value) 1: Enable bit 3 bit 2 bit 1 bit 0 IE1 (051H) (R/W) External interrupt 2 enable flag 0: Disable (initial value) 1: Enable External interrupt 3 enable flag 0: Disable (initial value) 1: Enable Voice synthesis interrupt enable flag 0: Disable (initial value) 1: Enable

Chapter 4 Interrupt (INT326) 4 E10Hz ESFT — — 10 Hz interrupt enable flag 0: Disable (initial value) 1: Enable bit 3 bit 2 bit 1 bit 0 IE3 (053H) (R/W) Shift register interrupt enable flag 0: Disable (initial value) 1: Enable E2Hz E4Hz E16Hz E32Hz 2 Hz interrupt enable flag 0: Disable (initial value) 1: Enable bit 3 bit 2 bit 1 bit 0 4 Hz interrupt enable flag 0: Disable (initial value) 1: Enable 16 Hz interrupt enable flag 0: Disable (initial value) 1: Enable 32 Hz interrupt enable flag 0: Disable (initial value) 1: Enable IE4 (054H) (R/W) ETM3 ETM2 ETM1 ETM0 Timer 3 interrupt enable flag 0: Disable (initial value) 1: Enable bit 3 bit 2 bit 1 bit 0 Timer 2 interrupt enable flag 0: Disable (initial value) 1: Enable Timer 1 interrupt enable flag 0: Disable (initial value) 1: Enable Timer 0 interrupt enable flag 0: Disable (initial value) 1: Enable IE2 (052H) (R/W)

Chapter 4 Interrupt (INT326) (3) Interrupt request registers (IRQ0 to IRQ4) IRQ0, IRQ1, IRQ2, IRQ3 and IRQ4 are registers that consist of 4 bits each. When an interrupt request is generated, the corresponding bit of the interrupt request register is set to "1" in the first half of the S1 state of the next instruction. So that the CPU can receive interrupt requests, set the master interrupt enable flag (MIE) to "1" and set the appropriate flag of the corresponding interrupt enable register (IE0 to IE4) to "1". The watchdog timer interrupt is non-maskable and does not depend upon the interrupt enable register or the master interrupt enable register (MIEF). Setting the appropriate bits of an interrupt request register to "1" allows software interrupts to be generated. When an interrupt request is received, the corresponding bits of IRQ0 to IRQ4 are cleared to "0". At system reset, each bit of IRQ0 through IRQ4 is initialized to "0". bit 3: QVI (reQuest Voice synthesis Interrupt) This is the interrupt request signal from the voice synthesis section. An interrupt request is generated when the setting of one voice phrase is completed and the setting of the next voice phrase is enabled by the voice synthesis section. bit 2: QXI0 (reQuest eXternal Interrupt 0) The external interrupt 0 request flag. The external interrupt 0 is assigned as the secondary function of each bit of port B (PB.0 to PB.3). External interrupt 0 requests are generated by a 4-bit ORed input. QVI QXI0 QMD QWDT bit 3 bit 2 bit 1 bit 0 External interrupt 0 request flag 0: No request (initial value) 1: Request Melody end interrupt request flag 0: No request (initial value) 1: Request Watchdog timer interrupt request flag 0: No request (initial value) 1: Request IRQ0 (055H) (R/W) Voice synthesis interrupt request flag 0: No request (initial value) 1: Request

Chapter 4 Interrupt (INT326) 4 OXI5 — QXI3 OXI2 External interrupt 5 request flag 0: No request (initial value) 1: Request bit 3 bit 2 bit 1 bit 0 IRQ1 (056H) (R/W) External interrupt 2 request flag 0: No request (initial value) 1: Request External interrupt 3 request flag 0: No request (initial value) 1: Request bit 3: QXI5 (reQuest eXternal Interrupt 5) External interrupt 5 request flag. The external interrupt 5 is assigned as a secondary function to each bit (P0.0 to 0.3) of port 0. An external interrupt 5 request is generated through the 4-bit ORed input. bit 1: QXI3 (reQuest eXternal Interrupt 3) External interrupt 3 request flag. The external interrupt 3 is assigned as a secondary function to each bit (PF.0 to PF.3) of port F. An external interrupt 3 request is generated through the 4-bit ORed input. bit 0: QXI2 (reQuest eXternal Interrupt 2) External interrupt 2 request flag. The external interrupt 2 is assigned as a secondary function of port E.3 (PE.3). Generation of the external interrupt 2 is triggered by the falling edge of the 128 Hz or 4 kHz output of the time base counter. bit 1: QMD (reQuest Melody Driver) Melody end interrupt request flag. Melody end interrupts are generated when the melody driver outputs the end note data (END bit = "1"). bit 0: QWDT (reQuest WatchDog Timer) Watchdog timer interrupt request flag. When the watchdog timer is started and then overflow occurs, an interrupt is requested. The watchdog timer interrupt is non-maskable and does not depend upon the interrupt enable registers or the master interrupt enable register (MIE).

Chapter 4 Interrupt (INT326) Q10Hz QSFT — — 10 Hz interrupt request flag 0: No request (initial value) 1: Request bit 3 bit 2 bit 1 bit 0 IRQ3 (058H) (R/W) Shift register interrupt request flag 0: No request (initial value) 1: Request bit 3: Q10Hz (reQuest 10 Hz) 10 Hz interrupt request flag. A 10 Hz interrupt request is generated whenever the 10 Hz carry generated by the 100 Hz timer counter is output. bit 2: QSFT (reQuest ShiFT register) Shift register interrupt request flag. A shift register interrupt is generated when the 8-bit data transfer for the shift register is completed. QTM3 QTM2 QTM1 QTM0 Timer 3 interrupt request flag 0: No request (initial value) 1: Request bit 3 bit 2 bit 1 bit 0 Timer 2 interrupt request flag 0: No request (initial value) 1: Request Timer 1 interrupt request flag 0: No request (initial value) 1: Request Timer 0 interrupt request flag 0: No request (initial value) 1: Request IRQ2 (057H) (R/W) bit 3: QTM3 (reQuest TiMer 3) Timer 3 interrupt request flag. A timer 3 interrupt request is generated whenever timer 3 overflows. bit 2: QTM2 (reQuest TiMer 2) Timer 2 interrupt request flag. A timer 2 interrupt request is generated whenever timer 2 overflows. bit 1: QTM1 (reQuest TiMer 1) Timer 1 interrupt request flag. A timer 1 interrupt request is generated whenever timer 1 overflows. bit 0: QTM0 (reQuest TiMer 0) Timer 0 interrupt request flag. A timer 0 interrupt request is generated whenever timer 0 overflows.

Chapter 4 Interrupt (INT326) 4 Q2Hz Q4Hz Q16Hz Q32Hz 2 Hz interrupt request flag 0: No request (initial value) 1: Request bit 3 bit 2 bit 1 bit 0 4 Hz interrupt request flag 0: No request (initial value) 1: Request 16 Hz interrupt request flag 0: No request (initial value) 1: Request 32 Hz interrupt request flag 0: No request (initial value) 1: Request IRQ4 (059H) (R/W) bit 3: Q2Hz (reQuest 2 Hz) 2 Hz interrupt request flag. A 2 Hz interrupt request is generated at every falling edge of the 2 Hz output of the time base counter. bit 2: Q4Hz (reQuest 4 Hz) 4 Hz interrupt request flag. A 4 Hz interrupt request is generated at every falling edge of the 4 Hz output of the time base counter. bit1: Q16Hz (reQuest 16 Hz) 16 Hz interrupt request flag. A 16 Hz interrupt request is generated at every falling edge of the 16 Hz output of the time base counter. bit 0: Q32Hz (reQuest 32 Hz) 32 Hz interrupt request flag. A 32 Hz interrupt request is generated at every falling edge of the 32 Hz output of the time base counter.

Chapter 4 Interrupt (INT326) 4.3 Interrupt Sequence 4.3.1 Interrupt Processing While MIE is "1", operation transfers to interrupt processing when individual interrupt factors are generated. The watchdog timer interrupt is non-maskable and regardless of the MIE flag status, operation will shift to interrupt processing when the watchdog timer interrupt factor is generated. The following processes are performed when an interrupt is generated. (1) MIE and the corresponding interrupt request flag are cleared to "0". (2) The program counter (PC) is saved on the call stack. (3) The call stack pointer (SP) is incremented by 1. (SP¨SP+1) (4) The starting address of the interrupt routine is loaded into the program counter (PC). Interrupt processing is performed in 0 machine cycles. Figure 4-2 shows the stack contents after an interrupt is generated. PC11–PC8 PC7–PC4 PC3–PC0 0H 1H 2H 3H 4H 0FH SP position before interrupt SP position after interrupt 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC13– PC12 Figure 4-2 Call Stack Contents after Interrupt Generation

Chapter 4 Interrupt (INT326) 4 4.3.2 Return from an Interrupt Routine Return from a watchdog timer interrupt routine is performed with an "RTNMI" instruction. Return from all other interrupt routines is performed with an "RTI" instruction. Execution of "RTI" and "RTNMI" instructions both require 1 machine cycle. When returning from an interrupt routine, the CPU performs the following processes. (1) The call stack pointer (SP) is decremented by 1. (SP¨SP–1) (2) MIE is set to "1" (when an "RTNMI" instruction is used, MIE is restored to its state prior to the interrupt). (3) 1 is added to the call stack contents and that value is loaded into the program counter (PC). ! Notes: • While the MIE flag is "0" (interrupt disabled state), if a watchdog timer interrupt is processed and an "RTI" instruction is executed, the MIE flag will be set to "1" and interrupts enabled. • Use "RTNMI" instructions to return from watchdog timer interrupts only. Use "RTI" instructions for normal interrupts. 4.3.3 Interrupt Hold Instructions Interrupt requests are not received during execution of the following instructions. These instructions are processed with priority, and interrupt processing is delayed until completion of the instruction. • ROM table reference instructions • External memory transfer instruction • Stack operation instructions • Jump instructions • Conditional branch instructions • Call/return instructions • "EI" (set MIE flag) instructions, "DI" (clear MIE flag) instructions and "MSA cadr15" (start melody output) instructions within control instructions ! Note: If the above instructions are used consecutively, even if an interrupt is generated, that interrupt may be put on hold for a considerable amount of time before the interrupt routine begins.

Chapter 5 Clock Generator Circuit (OSC) 5 Chapter 5 Clock Generator Circuit (OSC) 5.1 Overview The clock generator circuit (OSC) consists of a low-speed clock generator circuit, a high- speed clock generator circuit and a clock controller unit. The clock generator circuit generates the system clock (CLK), time base clock (TBCCLK) and the high-speed clock (HSCLK). The following modes can be selected for the low-speed clock generator circuit and the high- speed clock generator circuit. • Low-speed clock generator circuit: crystal oscillation mode or RC oscillation mode (mask option selection) • High-speed clock generator circuit: crystal oscillation mode or RC oscillation mode (software selection) The system clock is the basic operation clock for the CPU. The time base clock is the basic operation clock for the time base counter. Depending on the contents of the frequency control register (FCON), the system clock frequency is switched to either the output of the low-speed clock generator circuit (TBCCLK) or the output of the high-speed clock generator circuit (HSCLK). The frequency control register (FCON) also controls modes of the high-speed clock generator circuit. 5.2 Clock Generator Circuit Configuration Figure 5-1 shows a block diagram of the clock generator circuit. Figure 5-1 Clock Generator Circuit Configuration OSC1 External circuit OSC0 Oscillation enable High-speed clock generator circuit RC/crystal oscillation select High-speed clock output VDDH XT0 External circuit XT1 Low-speed clock generator circuit Low-speed clock output VDD2 TBCCLK HSCLK Time base clock (TBCCLK) System clock (CLK) High-speed clock (HSCLK) MPX Clock select control FCON 3 3 FCON WRITE Data bus

Chapter 5 Clock Generator Circuit (OSC) 5.3 Low-Speed Clock Generator Circuit The low-speed clock generator circuit has two modes that are selected by the mask option, the RC oscillation mode and crystal oscillation mode. The oscillation frequency is 30 to 80 kHz. For the RC oscillation mode, attach an external resistor, ROSL, as shown in Figure 5-2(a). For the crystal oscillation mode, attach an external crystal unit and capacitor, CG, as shown in Figure 5-2(b). Inside the IC Low-speed clock output (a) External Circuit for RC Oscillation Mode XT0 XT1 ROSL VDD2 CXT VSS Inside the IC Low-speed clock output (b) External Circuit for Crystal Oscillation Mode XT0 XT1 Crystal VDD2 Rf CG VSS VSS CD Figure 5-2 External Circuits for Low-Speed Clock Oscillation ! Note: For convenience, the descriptions of this manual assume that a 32.768 kHz crystal unit is used in the low-speed clock generator circuit. For the method of specifying mask options for the low-speed clock generator circuit, see "Appendix G: Mask Option."

Chapter 5 Clock Generator Circuit (OSC) 5 Table 5-1 lists typical values of oscillation frequency when the low-speed side RC oscillation mode is selected. Table 5-2 shows an example external component to be attached when the low-speed side crystal oscillation mode is selected. Table 5-1 Typical Oscillation Frequencies for the Low-Speed Side RC Oscillation Mode (Typ.) Table 5-2 Example External Component for the Low-Speed Side Crystal Oscillation Mode ROSL 1.5 MW 700 kW 400 kW fROSL 32 kHz ±30% 60 kHz ±30% 80 kHz ±30% CG 12 pF fXT 32.768 kHz

Chapter 5 Clock Generator Circuit (OSC) 5.4 High-Speed Clock Generator Circuit The high-speed clock generator circuit has two modes, the RC oscillation mode and crystal oscillation mode. Oscillation modes are set by OSCSEL (bit 2 of FCON). • OSCSEL = "0" : RC oscillation mode • OSCSEL = "1" : crystal oscillation mode During the RC oscillation mode, the source oscillation clock is output as the high-speed clock. The maximum frequency in this case is 2.048 MHz. During the crystal oscillation mode, the half frequency waveform of the source oscillations is output as the high-speed clock. The maximum frequency of the source oscillations in this case is 4.096 MHz. If the high-speed clock is not to be used, leave the OSC0 and OSC1 pins open (unconnected). For the RC oscillation mode, attach an external resistor, ROSH, as shown in Figure 5-3(a). For the crystal oscillation mode, attach an external crystal unit and capacitors as shown in Figure 5-3(b). (a) External Circuit for RC Oscillation Mode OSC1 OSC0 (b) External Circuit for Crystal Oscillation Mode VDDH VDDH ROSH High-speed clock output High-speed clock output Oscillation enable VSS CL1 CL0 VDDH VDDH Oscillation enable Crystal OSC1 OSC0 Q D Q Figure 5-3 External Circuits for High-Speed Clock Oscillation

Chapter 5 Clock Generator Circuit (OSC) 5 Table 5-3 lists typical values of oscillation frequency when the high-speed side RC oscillation mode is selected. Table 5-4 lists example external components to be attached when the high- speed side crystal oscillation mode is selected. Table 5-3 Typical Oscillation Frequencies for the High-Speed Side RC Oscillation Mode (Typ.) *: Manufactured by Daishinku Corp. ROSH VDDH* fROSH 3.6 V 1.9 MHz ±30% 39 kW 4.2 V 2.1 MHz ±30% 4.8 V 2.2 MHz ±30% 3.6 V 1.6 MHz ±30% 47 kW 4.2 V 1.7 MHz ±30% 4.8 V 1.8 MHz ±30% CL0 CL1 8 pF 8 pF Crystal unit AT-49 (4.096 MHz)* ! Note: *: The power supply voltage VDDH of the high-speed clock generator circuit is a voltage obtained by doubling the voltage VDD2 used in the LCD bias generator section. Take care because VDD2 can be varied from 1.8 V to 2.4 V using the display contrast register (DSPCNT). For details, see Chapter 15, "LCD Driver" and Chapter 17, "Power Supply Circuit." Table 5-4 Example External Components for the High-Speed Side Crystal Oscillation Mode

Chapter 5 Clock Generator Circuit (OSC) 5.5 System Clock Control The system clock is the basic operation clock of the CPU. The clock can be selected as follows with the CPUCLK (bit 0 of FCON) setting. • CPUCLK = "0" (initial value) The output of the low-speed clock generator circuit (TBCCLK) is the system clock. • CPUCLK = "1" The output of the high-speed clock generator circuit (HSCLK) is the system clock. When HSCLK is selected as the system clock, the high-speed clock must be in the oscillating state (ENOSC = "1"). The low-speed generator circuit will continue to oscillate even when the high-speed generator circuit is selected. To reduce the total power consumption in applications that use the high-speed clock generator circuit, the following clock controls are generally implemented in software. • During normal operation, the output of the low-speed clock generator circuit (CPUCLK = "0") should be the system clock. • Only when high-speed operation is necessary should the high-speed clock oscillate (ENOSC = "1") and output of the high-speed clock generator circuit (CPUCLK = "1") should be selected. For details of the system clock select timing, refer to section 5.7, "System Clock Select Timing."

Chapter 5 Clock Generator Circuit (OSC) 5 5.6 Frequency Control Register (FCON) FCON is a special function register (SFR) that selects the system clock. — OSCSEL ENOSC CPUCLK RC oscillation/ceramic oscillation mode select 0: RC oscillation mode (initial value) 1: Crystal oscillation mode High-speed clock oscillation start/stop select 0: Oscillation stop (initial value) 1: Oscillation start System clock select 0: Low-speed clock oscillation output (initial value) 1: High-speed clock oscillation output FCON (062H) (R/W) bit 3 bit 2 bit 1 bit 0 bit 2: OSCSEL This bit selects the RC oscillation mode or the crystal oscillation mode of the high- speed clock generator circuit. At system reset, this bit is cleared to "0", selecting the RC oscillation mode. bit 1: ENOSC This bit starts and stops oscillation of the high-speed clock generator circuit. At system reset, this bit is cleared to "0", stopping oscillation of the high-speed clock generator circuit. bit 0: CPUCLK This bit selects the system clock, the basic operation clock of the CPU. At system reset, this bit is cleared to "0", selecting output of the low-speed clock generator circuit (TBCCLK).

Chapter 5 Clock Generator Circuit (OSC) 5.7 System Clock Select Timing After system reset, the system clock is TBCCLK. When high-speed operation is necessary, switch the system clock to HSCLK. A flowchart of system clock operation is shown below. TBCCLK (Low-speed clock generator circuit output) System clock status HSCLK (High-speed clock generator circuit output) After system reset, the low- speed clock generator output is the system clock. OSCSEL (bit 2 of FCON) setting (1) High-speed clock oscillation mode select OSCSEL = "0" : RC oscillation mode (initial value) OSCSEL = "1" : Crystal oscillation mode ENOSC (bit 1 of FCON) = "0" (2) High-speed clock oscillation stop ENOSC = "0" : Stop high-speed clock oscillation (initial value) ENOSC = "1" : Start high-speed clock oscillation Software processing Software processing ENOSC (bit 1 of FCON) = "1" (2) High-speed clock oscillation start ENOSC = "0" : Stop high-speed clock oscillation (initial value) ENOSC = "1" : Start high-speed clock oscillation Wait: When RC oscillation mode selected: 5 ms or more When crystal oscillation mode selected: 10 ms or more CPUCLK (bit 0 of FCON) = "1" (3) High-speed clock oscillation output select CPUCLK = "0" : Low-speed clock oscillation output (initial value) CPUCLK = "1" : High-speed clock oscillation output CPUCLK (bit 0 of FCON) = "0" (1) Low-speed clock oscillation output select CPUCLK = "0" : Low-speed clock oscillation output (initial value) CPUCLK = "1" : High-speed clock oscillation output

Chapter 5 Clock Generator Circuit (OSC) 5 When ENOSC (bit 1 of FCON) is set to "1", the voltage doubler circuit that doubles VDD2 starts operating and outputs the power supply voltage (VDDH) for high speed oscillation. The oscillations are started in the mode set by OSCSEL. At the same time, the internal logic power supply voltage (VDDL) switches from the constant voltage circuit output level (approx. 1.7 V) to the VDDH level. Next, if CPUCLK is set to "1", the system clock switches from crystal oscillation output (TBCCLK) to high-speed clock output (HSCLK). Figure 5-4 shows the system clock select timing and status of the power supply voltage for high-speed oscillation (VDDH) and the internal logic power supply voltage (VDDL). ENOSC CPUCLK System clock TWAIT High-speed clock Low-speed clock 0.5 to 2.0 high-speed clocks 0.5 to 1.0 low-speed clocks Internal logic power supply voltage (VDDL) VDD VSS = 0 V Approx. 1.7 V (typ.) Low-speed clock OSC1 Power supply voltage for high-speed oscillation (VDDH) 2 ¥ VDD2 VSS = 0 V Figure 5-4 System Clock Select Timing In the crystal oscillation mode, 10 ms are required from the time when ENOSC is set to "1" until the high-speed clock generator circuit enters the oscillating state. Therefore, in this mode, when switching CPUCLK to a high-speed setting, wait for an interval of at least TWAIT = 10 ms after the rising edge of ENOSC. In the CR oscillation mode, oscillation begins soon after setting ENOSC to "1". However, it takes about 5 ms for the power supply voltage for high-speed oscillation (VDDH) to stabilize. Therefore, when switching CPUCLK to a high-speed setting, wait for an interval of at least TWAIT = 5 ms after the rising edge of ENOSC. When switching from the high-speed mode to the low-speed mode, set the CPUCLK bit to "0", and sometime after the next instruction, set the ENOSC bit to "0". For details regarding the power supply for high-speed oscillation and the constant voltage circuit for the internal logic power supply, refer to Chapter 17, "Power Supply Circuit."

Chapter 6 Time Base Counter (TBC) 6 Chapter 6 Time Base Counter (TBC) 6.1 Overview The time base counter (TBC) is a 15-bit internal counter, which generates the clock supplied to internal peripheral functions. The TBC clock is a time base clock (TBCCLK). TBC outputs are used for functions such as time base interrupts and various other circuits. TBC8–11 and TBC12–15 can be read/reset by software. The TBC generates an interrupt request at the falling edge of 32 Hz/16 Hz/4 Hz/2 Hz output. The TBC is initialized to 0000H at system reset. 6.2 Time Base Counter Configuration The configuration of the time base counter (TBC) is shown in Figure 6-1. b3 b2 b1 b0 b3 b2 b1 b0 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 256 Hz 512 Hz 1 kHz 2 kHz 4 kHz 8 kHz 16 kHz (1 Hz) (2 Hz) (4 Hz) (8 Hz) (16 Hz) (32 Hz) (64 Hz) (128 Hz) (256 Hz) (512 Hz) (1 kHz) (2 kHz) (4 kHz) (8 kHz) (16 kHz) TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC11 TBC10 TBC9 TBC8 TBC15 TBC14 TBC13 TBC12 R R R TBCR0 READ TBCR1 READ TBCR1 WRITE TBCR0 WRITE RESET0 Data bus TBCCLK (32.768 kHz) 2HzINT 4HzINT 16HzINT 32HzINT (1/32768TBC) (1/16384TBC) (1/8192TBC) (1/4096TBC) (1/2048TBC) (1/1024TBC) (1/512TBC) (1/256TBC) (1/128TBC) (1/64TBC) (1/32TBC) (1/16TBC) (1/8TBC) (1/4TBC) (1/2TBC) Figure 6-1 Time Base Counter (TBC) Configuration (when a 32.768 kHz crystal is used for low-speed clock oscillation)

Chapter 6 Time Base Counter (TBC) 6.3 Time Base Counter Registers Time base counter register 0 (TBCR0), time base counter register 1 (TBCR1) These 4-bit special function registers (SFRs) are used to read the 1 to 8 Hz and 16 to 128 Hz outputs of the time base counter. A write operation to TBCR0 sets both the 1 to 8 Hz and 16 to 128 Hz outputs to "0", and a write operation to TBCR1 sets the 1 to 8 Hz output to "0". 16 Hz 32 Hz 64 Hz 128 Hz TBCR0 (060H) (R/W) bit 3 bit 2 bit 1 bit 0 1 Hz 2 Hz 4 Hz 8 Hz TBCR1 (061H) (R/W) bit 3 bit 2 bit 1 bit 0

Chapter 6 Time Base Counter (TBC) 6 6.4 Time Base Counter Operation After system reset the time base counter (TBC) begins to count up from 0000H. The count is incremented at the falling edge of the TBCCLK. TBC 32 Hz/16 Hz/4 Hz/2 Hz outputs are used as time base interrupts. At each output falling edge, four bits of interrupt request register 4 (IRQ4) are set to "1", namely bit 3 (Q32Hz), bit 2 (Q16Hz), bit 1 (Q4Hz) and bit 0 (Q2Hz), requesting an interrupt to the CPU. TBC outputs are also used as clocks for various circuits. TBC 1 to 8 Hz output and 16 to 128 Hz output can be read through the time base counter register 0/1 (TBCR0/TBCR1). A write operation to TBCR1 sets the 1 to 8 Hz output counter to "0", and a write operation to TBCR0 sets both the 1 to 8 Hz and 16 to 128 Hz output counters to "0". The write data in these write operations has no significance. For example, the "MOV TBCR0, A" instruction can be used to write, but is not dependent on accumulator content in any way. When write is executed to TBCR0 and TBCR1 and the 1 to 8 Hz and 16 to 128 Hz counters reset, interrupt requests are generated if 32 Hz/16 Hz/4 Hz/2 Hz outputs have been set to "1". To disable these interrupts, first set the master interrupt enable flag (MIE) or interrupt enable register 4 (IE4) to "0", execute the write operation to TBCR 0/1, and set the interrupt request flag 4 (IRQ4) to "0". Figure 6-2 shows interrupt generation timing and time base counter output reset timing by writing "1" to TBCR0 and TBCR1.

Chapter 6 Time Base Counter (TBC) Figure 6-2 Interrupt Timing and Reset Timing by Writing "1" to TBCR0, TBCR1 Write TBCR0 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz Write TBCR1 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz 1 second +0 –1/16 1 second +0 –1/256 Shows interrupt timing

Chapter 7 Timers (TIMER) 7 Chapter 7 Timers (TIMER) 7.1 Overview The ML63326 has four internal 8-bit timers (0 to 3). Timers 0 and 1, or timers 2 and 3, can be used in tandem as a 16-bit timer. Timers 0 and 1 have three operation modes: auto-reload mode, capture mode and frequency measurement mode. Timers 2 and 3 have two modes: auto-reload and frequency measure- ment. Timer clock may be set to the time base clock (TBCCLK: 32.768 kHz), the high-speed clock (HSCLK), or an external clock. When using the timers as a 16-bit timer, the overflow signals of timers 0 and 2 are used as the clocks for timers 1 and 3, respectively. In addition to pulse generation and time measurement, timers can also be used. Figure 7-1 Timer 0 Configuration 7.2 Timer Configuration Figures 7-1 through 7-4 show the configuration of timers 0 to 3. Control circuit Frequency measurement control circuit Capture control circuit TM0CL TM0CH TM0DL TM0DH 8 8 Capture Reload 4 4 4 4 D Q D Q Q R TM0CK TM0 overflow TM0INT PB.0/TM0OVF Data bus TBCCLK HSCLK PB.2/T02CK 64 Hz 437C PB.0/TM0CAP TM0CAP TM0CK RESETS OV 16 kHz 8 kHz 4 kHz 2 kHz 1 kHz 512 Hz 256 Hz 128 Hz 64 Hz 437C 16-bit timer (Timer 0 overflow signal is used as clock for timer 1) Clock TBCCLK / HSCLK / External clock (T02CK, T13CK) Auto-reload mode Capture mode (Timer 2 overflow signal is used as clock for timer 3) — 8-bit timer Timer 0 Timer 2 Timer 1 Timer 3 — Frequency measurement mode

Chapter 7 Timers (TIMER) Control circuit Capture control circuit TM1CL TM1CH TM1DL TM1DH 8 8 Capture Reload 4 4 4 4 D Q Q R D Q TM1CK TM1INT PB.1/TM1OVF Data bus TBCCLK HSCLK PB.3/T13CK PB.1/TM1CAP TM1CAP TM1CK RESETS TM0 overflow OV TM1 overflow Figure 7-2 Timer 1 Configuration Control circuit Frequency measurement control circuit TM2CL TM2CH TM2DL TM2DH 8 Reload 4 4 4 4 D Q D Q Q R TM2CK TM2 overflow TM2INT TM2OVF Data bus TBCCLK HSCLK PB.2/T02CLK 64 Hz 437C TM2CK RESETS OV Figure 7-3 Timer 2 Configuration Control circuit TM3CL TM3CH TM3DL TM3DH 8 Reload 4 4 4 4 D Q Q R D Q TM3CK TM3INT TM3OVF Data bus TBCCLK HSCLK PB.3/T13CK TM3CK RESETS TM2 overflow OV Figure 7-4 Timer 3 Configuration

Chapter 7 Timers (TIMER) 7 7.3 Timer Registers The following four registers are used for timer control. (1) Timer data registers (TM0DL, TM0DH, TM1DL, TM1DH, TM2DL, TM2DH, TM3DL, TM3DH) (2) Timer counter registers (TM0CL, TM0CH, TM1CL, TM1CH, TM2CL, TM2CH, TM3CL, TM3CH) (3) Timer control registers (TM0CON0, TM0CON1, TM1CON0, TM1CON1, TM2CON0, TM2CON1, TM3CON0, TM3CON1) (4) Timer status registers (TM0STAT, TM1STAT, TM2STAT, TM3STAT) Each register is described below. (1) Timer data registers (TM0DL, TM0DH, TM1DL, TM1DH, TM2DL, TM2DH, TM3DL, TM3DH) • During the auto-reload mode, timer data registers store the reload values. • During the capture mode, timer data registers store the capture data. Writing to a timer data register causes the contents of the timer counter register to be transferred to the timer data register. • At system reset, all valid bits are cleared to "0". • Note regarding register values: Writing to the timer counter register causes the same value to also be written to the timer data register. However, when writing to the timer data register, the same value is not written to the timer counter register. Timer 0 Registers T0D3 T0D2 T0D1 T0D0 (068H) (R/W) TM0DL (Timer 0 lower) bit 3 bit 2 bit 1 bit 0 T0D7 T0D6 T0D5 T0D4 (069H) (R/W) TM0DH (Timer 0 upper) bit 3 bit 2 bit 1 bit 0 Timer 1 Registers T1D3 T1D2 T1D1 T1D0 (06AH) (R/W) TM1DL (Timer 1 lower) bit 3 bit 2 bit 1 bit 0 T1D7 T1D6 T1D5 T1D4 (06BH) (R/W) TM1DH (Timer 1 upper) bit 3 bit 2 bit 1 bit 0

Chapter 7 Timers (TIMER) Timer 2 Registers T2D3 T2D2 T2D1 T2D0 (076H) (R/W) TM2DL (Timer 2 lower) bit 3 bit 2 bit 1 bit 0 T2D7 T2D6 T2D5 T2D4 (077H) (R/W) TM2DH (Timer 2 upper) bit 3 bit 2 bit 1 bit 0 Timer 3 Registers T3D3 T3D2 T3D1 T3D0 (078H) (R/W) TM3DL (Timer 3 lower) bit 3 bit 2 bit 1 bit 0 T3D7 T3D6 T3D5 T3D4 (079H) (R/W) TM3DH (Timer 3 upper) bit 3 bit 2 bit 1 bit 0 (2) Timer counter registers (TM0CL, TM0CH, TM1CL, TM1CH, TM2CL, TM2CH, TM3CL, TM3CH) • 8-bit binary counter operation • At system reset, all valid bits are cleared to "0". • Note regarding register values: Writing to the timer counter register causes the same value to also be written to the timer data register. However, when writing to the timer data register, the same value is not written to the timer counter register. Timer 0 Registers T0C3 T0C2 T0C1 T0C0 (06CH) (R/W) TM0CL (Timer 0 lower) bit 3 bit 2 bit 1 bit 0 T0C7 T0C6 T0C5 T0C4 (06DH) (R/W) TM0CH (Timer 0 upper) bit 3 bit 2 bit 1 bit 0

Chapter 7 Timers (TIMER) 7 Timer 1 Registers T1C3 T1C2 T1C1 T1C0 (06EH) (R/W) TM1CL (Timer 1 lower) bit 3 bit 2 bit 1 bit 0 T1C7 T1C6 T1C5 T1C4 (06FH) (R/W) TM1CH (Timer 1 upper) bit 3 bit 2 bit 1 bit 0 Timer 2 Registers T2C3 T2C2 T2C1 T2C0 (07AH) (R/W) TM2CL (Timer 2 lower) bit 3 bit 2 bit 1 bit 0 T2C7 T2C6 T2C5 T2C4 (07BH) (R/W) TM2CH (Timer 2 upper) bit 3 bit 2 bit 1 bit 0 Timer 3 Registers T3C3 T3C2 T3C1 T3C0 (07CH) (R/W) TM3CL (Timer 3 lower) bit 3 bit 2 bit 1 bit 0 T3C7 T3C6 T3C5 T3C4 (07DH) (R/W) TM3CH (Timer 3 upper) bit 3 bit 2 bit 1 bit 0

Chapter 7 Timers (TIMER) (3) Timer control registers (TM0CON0, TM0CON1, TM1CON0, TM1CON1, TM2CON0, TM2CON1, TM3CON0, TM3CON1) • Timer control registers select the operation mode and clock for each timer. • At system reset, all valid bits are cleared to "0". • Note regarding register values: Writing to the timer counter register causes the same value to also be written to the timer data register. However, when writing to the timer data register, the same value is not written to the timer counter register. Timer 0 Registers To use timer 1 in combination as a 16-bit timer, set timer 1 control registers TM1CON0 and TM1CON1. — FMEAS0 TM0ECAP TM0RUN TM0CON0 (070H) (R/W) bit 3 bit 2 bit 1 bit 0 Timer 0 mode select bit 2 0 0 0 0 1 1 1 1 bit 1 0 0 1 1 0 0 1 1 bit 0 0 1 0 1 0 1 0 1 : Auto-reload mode stop (initial value) : Auto-reload mode operation : Capture mode stop : Capture mode operation : Frequency measurement mode operation : Not used : Not used : Not used bit 2, 1, 0: FMEAS0, TM0ECAP, TM0RUN These bits select the timer 0 operation mode. The timer 0 operation mode can be selected as auto-reload mode, capture mode, or frequency measurement mode.

Chapter 7 Timers (TIMER) 7 — — TM0CL1 TM0CL0 TM0CON1 (071H) (R/W) bit 3 bit 2 bit 1 bit 0 Timer 0 clock select bit 1 0 0 1 1 bit 0 0 1 0 1 : TBCCLK (initial value) : HSCLK (high-speed clock) : External clock : Not used bit 1, 0: TM0CL1, TM0CL0 These bits select the timer 0 clock. The timer 0 clock can be selected as TBCCLK (low-speed clock), HSCLK (high- speed clock), or external clock (T02CK: secondary function of PB.2). ! Note: If HSCLK is used as the clock, after ENOSC (bit 1 of FCON) is set to "1", wait for the following time interval before starting timer operation. • Wait at least 10 ms when using crystal oscillation. • Wait at least 5 ms when using RC oscillation.

Chapter 7 Timers (TIMER) Timer 1 Registers — — TM1ECAP TM1RUN TM1CON0 (072H) (R/W) bit 3 bit 2 bit 1 bit 0 Timer 1 mode select bit 1 0 0 1 1 bit 0 0 1 0 1 : Auto-reload mode stop or 16-bit timer mode (initial value) : Auto-reload mode operation : Capture mode stop : Capture mode operation bit 1, 0: TM1ECAP, TM1RUN These bits select the timer 1 operation mode. The timer 1 operation mode can be selected as auto-reload mode, capture mode, or 16-bit timer mode. — — TM1CL1 TM1CL0 TM1CON1 (073H) (R/W) bit 3 bit 2 bit 1 bit 0 Timer 1 clock select bit 1 0 0 1 1 bit 0 0 1 0 1 : TBCCLK (initial value) : HSCLK : External clock : Timer 0 overflow (16-bit timer mode) bit 1, 0: TM1CL1, TM1CL0 These bits select the timer 1 clock. The timer 1 clock can be selected as TBCCLK (low-speed clock), HSCLK (high- speed clock), external clock (T13CK: secondary function of PB.2), or the timer 0 overflow flag. When using as a 16-bit timer, select timer 0 overflow for the clock. ! Note: If HSCLK is used as the clock, after ENOSC (bit 1 of FCON) is set to "1", wait for the following time interval before starting timer operation. • Wait at least 10 ms when using crystal oscillation. • Wait at least 5 ms when using RC oscillation.

Chapter 7 Timers (TIMER) 7 Timer 2 Registers To use timer 3 in combination as a 16-bit timer, set timer 3 control registers TM3CON0 and TM3CON1. — FMEAS2 — TM2RUN TM2CON0 (07EH) (R/W) bit 3 bit 2 bit 1 bit 0 Timer 2 mode select bit 2 0 0 1 1 bit 0 0 1 0 1 : Auto-reload mode stop (initial value) : Auto-reload mode operation : Frequency measurement mode operation : Not used bit 2, 0: FMEAS2, TM2RUN These bits select the timer 2 operation mode. The timer 2 operation mode can be selected as auto-reload mode or frequency measurement mode. — — TM2CL1 TM2CL0 TM2CON1 (07FH) (R/W) bit 3 bit 2 bit 1 bit 0 Timer 2 clock select bit 1 0 0 1 1 bit 0 0 1 0 1 : TBCCLK (initial value) : HSCLK : External clock : Not used bit 1, 0: TM2CL1, TM2CL0 These bits select the timer 2 clock. The timer 2 clock can be selected as TBCCLK (low-speed clock), HSCLK (high- speed clock), or external clock (T02CK: secondary function of PB.2). ! Note: If HSCLK is used as the clock, after ENOSC (bit 1 of FCON) is set to "1", wait for the following time interval before starting timer operation. • Wait at least 10 ms when using crystal oscillation. • Wait at least 5 ms when using RC oscillation.