Cypress Semiconductor CY7C1231H Specification Sheet
Text of the manual
2-Mbit (128K x 18) Flow-Through SRAM
with NoBL™ Architecture
CY7C1231H
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 001-00207 Rev. *B
Revised April 26, 2006
Features
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatib
Document #: 001-00207 Rev. *B
Page 2 of 12
Selection Guide
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
225
mA
Maximum CMOS Standby Current
40
mA
Pin Configuration
100-pin TQFP Pinout
A
A
A
A
A1
A0
NC/288M
NC/144M
VSS
VDD
NC(36M)
A
A
A
A
A
NC/4M
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
D
Document #: 001-00207 Rev. *B
Page 3 of 12
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of
the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:B]
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct write
Document #: 001-00207 Rev. *B
Page 4 of 12
Functional Overview
The CY7C1231H is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input
Document #: 001-00207 Rev. *B
Page 5 of 12
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A1, A0
A1, A0
A1, A0
A1, A0
00
01
10
11
01
00
11
