Zenith SM-Z-89 Service Manual

SAINT JOSEPH, MICHIGAN 49085 585-7 Copyright © 1982 Zenith Data Systems All Rights Reserved Printed in the United States of America

This Z-89/90 Computer System Service Manual contains service information for the following six Zenith Data Systems products: 1. The Z-89/90 Computers. 2. The Z-89-37 Double-Density Disk Controller. 3. The H-88-1 Single-Density Disk Controller. 4. The H-17-1 Floppy Disk Drive. 5. The H-17-4 Floppy Disk Drive. 6. The WH-88-16 Memory Expansion. T

SAINT JOSEPH, MICHIGAN 49085 I I 585-7 Copyright © 1982 Zenith Data Systems All Rights Reserved Printed in the United Statee of America

SPECIFICATIONS 1-1 CPU Boards Z-89/90 , , 1-2 SETUP AND TESTING 2-1 Power Line Considerations ,......... 2-1 Cabinet Removal , 2-2 ZDS SYSTEM CONFIGURATION , . .. 3-1 Terminal Logic Circuit Board 3-1 CPU Logic Circuit Board 3-4 Serial Interface 3-20 Memory Map 3-22 I/O Port Usage 3-22 OPERATION " 4-1 Command Summary 4-1 Keyboard Operation. . . . . . . . . . . . . . . . . . . . . .. 4-3 Normal Modes and Keys ., 4-5 CIRCUIT DESCRIPTION 5-1 Power Supply Circuit B~~~d'::::::::::::::: 5-2 Video Deflection Circuit Board 5-3 Video Driver Circuit Board ::::::::::::: 5-6 Terminal Logic Circuit Board 5-6 CPU Logic Circuit Board 5-15 Serial Interface I/O Circuit Board 5-21 Block Diagrams fold-outs SERVICE , 6-1 CRT Adjustment 6-2 Switch Configurations 6-4 CPU Logic Circuit Board 6-6 Rotational Speed Test 6-22 Memory Testing .. , , 6-23 Troubleshooting Charts 6-25 CIRCUIT BOARD X-RAY VIEWS 7-1 SEMICONDUCTOR IDENTIFICATION CHARTS 8-1 Component Number Index , 8-1 Part Number Index 8-4 REPLACEMENT PARTS LIST 9-1 Power Supply 9-1 Video Deflection Circuit Board 9-1 Video Driver Circuit Board 9-3 Terminal Logic Circuit Board 9-3 CPU Logic Circuit Board 9-4 Chassis Parts 9-5 Serial Interface I/O Circuit Board. . . . . . . . . .. 9-6 SCHEMATIC DIAGRAMS fold-in

Processor . Clock . Memory . DISPLAY CRT . Display Format . Display Size . Character Size . Character Type . Keyboard . Cursor . Cursor Controls . Cursor Addressing . Tab . Refresh Rate . Edit Functions . Erase Functions . Bell . Video . Z-80. 2.048 MHz. 48K bytes user RAM (expandable to 64K), Z-89 series 64K bytes user RAM, Z-90 series 8K System for ROM and RAM. 8K reserved. 12" diagonal - green phosphor. 24 lines of 80 characters (with access to 25th line). 6.5" high x 8.5" wide. 0.2" high x 0.1" wide (approximate). 5 x 7 dot matrix (upper case); 5 x 9 dot matrix (lower case with descenders); 8 x 10 dot matrix (graphics). 84 keys (60 alphanumeric, 12 function/control) plus a 12-key numeric/control pad. Blinking, nondestructive, underline, block, or dis- abled (DIP switch selectable). Up, down, left, right, home, CR, LF, back space, tab, and cursor off. Relative and direct. Standard 8-column tab. 60 Hz at 60 HZ/50 Hz at 50 Hz line frequency. Insert and delete character or line. Erase page, erase to end of line, and erase to end of page. Audible alarm on receipt of ASCII BEL. Normal and reverse by character.

Each channel provides serial data and primary RS- 232C handshake. RS-232C. RS-232C compatible. 5,6,7, or 8 bits. Even, odd, stick, or none. 1, 1-1/2 or 2. All standard rates to 57,600 baud. 115/230 volts at 90 watts max. 13" high x 17" wide x 20" deep (3:3 x 43.2 x 50.8 em). 46 lbs. (20.7 kg). 10° to 35° Celsius. 0° to 50° Celsius. CPU BOARDS Z·89/90 The CPU boards for the Z-89 (HE 181-3396) and the Z-90 (HE 181-3615) are basically the same, with the following exceptions: Z-89 Z-90 IC U516 HE 444-41 HE 444-83 IC U518 HE 444-62 HE 444-84 IC U549 HE 443-904 See note 1. IC U557 HE 443-912 See note 2. IC U558 HE 443-754 HE 100-1817 NOTE 1: The memory chip is left out to receive the cable from the 16K Memory Expansion Board. NOTE 2: U557 is left open to receive the interface cable from the Z-89-37 Controller Board. The Z-90 CPU board has the JJ505 jumper plug removed. Cable (HE 134-1159) is connected from JJ505 to Pin 14 of P508, to enable the 4K ROM at U518. JJ501 must be jumpered for correct memory size (48K or 64K). These boards may be interchanged ifthe above modifications are made. The Z-90 CPU board may be used as a direct replacement if the proper IC's are inserted at U549, U557, and U558. U516 and U518 do not have to be changed. Zenith Data Systems reserves the right to discontinue products and to change specifications at any time without incurring any obligation to incorporate new features in products previously sold.

POWER LINE CONSIDERATIONS If you need to change the position of the 115/230 switch (located on the bottom of the Computer), be sure you change rear panel fuse F1 to the proper value as follows: For 115 VAC, use a 1.5-ampere, 125-volt, slow- blow fuse. For 230 VAC, use a I-ampere, 250-volt, slow- blow fuse. The plug on the power cord is for standard 115 VAC outlets. For 230 VAC operation in the U.S.A., cut off and replace in a manner such that your power connec- tion conforms with section 210-21 (b) ofthe National Electric Code, which reads, in part: "Receptacles connected to circuits having dif- ferent voltages, frequencies, or types of current (AC or DC) on the same premises shall be of such design that attachment plugs used on such cir- cuits are not interchangeable." When you install the new plug, make sure it is con- nected according to your local electrical code. Units with three-wire line cords must always have the green wire connected to chassis ground. Be sure the NORM/LOW switch (on the bottom of the Computer) is set in its proper position to match your line voltage as follows: NORM range - 110 V to 130 V rms or 220 V to 260 V rms. LOWrange-100 Vto 120 Vrms or 200 Vto 240 V rms. NOTE: Ifyou do not know the value ofthe line voltage in your area, set the NORM/LOW switch to NORM.

• Refer to the inset drawing on Figure 2-1, insert the blade of a small screwdriver into the notch in the latch plate, and then, as you lift upward on the front, slide the latch plate toward the front ofthe Computer about 1/4". • Likewise, open the latch plate on the other side of the cabinet top. • WARNING: When the line cord is con- nected to an AC outlet, hazardous voltages can be present inside your Computer. See Figure 2-1. • Carefully tilt the cabinet top back. • Unplug the fan. • When the top is tilted straight up, carefully lift the hinges out of the rear panel. Simply reverse this procedure to close and lock the cabinet top back on the Computer. WARNING: Boxed-In areas show ~ hazardous voltage locations. ~~~ TI LT BACK Figure 2-1

This section of the Manual shows you the normal switch and jumper positions. Check them to be sure they are in their proper positions, or set them (as explained) for the operation that is desired. The Computer communicates with the peripherals at RS-232C signal levels. 25-pin "D" connectors on the rear panel conform to RS-232C standards and mate with most equipment that conforms to this standard. Refer to the following sections that pertain to your Computer. TERMINAL LOGIC CIRCUIT BOARD Carefully tilt back the cabinet top. See Figure 2-1. Be sure the POWER switch is off. Then remove the screws that hold the terminal logic circuit board (the rear circuit board). Remove the two screws that hold the top of the CPU logic circuit board. Disconnect the cables, as necessary, and lift the circuit boards up out of the Computer. SWITCH S402 (Secondary power-up configura- tion) Push all of the switches on S402 up (0) as shown in Figure 3-1 on Page 3-2. If you ever want to change these switch positions, they are defined as follows: SWITCH SECTION DESCRIPTION 0 o = underscore cursor; 1 = block cursor 1 o = key click; 1 = no key click 2 o = discard past end of line; 1 = wrap around 3 o = no auto LF on CR; 1 = auto LF on CR 4 o = no auto CR on LF; 1 = auto CR on LF 5 o = ZDS mode; 1 = ANSI mode 6 o = keypad normal; 1 = keypad shifted 7 o = 60 Hz refresh; 1 = 50 Hz refresh

tion) Refer to Figure 3-1 for the following steps. This switch (located on the terminal logic circuit board) sets the following power-up and reset modes: SWITCH SECTION DESCRIPTION 0-3 Baud Rate 4 Parity Enable 5 Odd/Even Parity 6 Normal/Stick Parity 7 Half/Full Duplex The particular configuration that you select is ini- tialized when you power-up the Computer or when you perform a Computer Reset. Figure 3-1 shows the location of switch S401. Remember that, as you look at switch S401 from the front of the Computer, you select the one (1) positions of the switch by pushing the switches down, and you select the zero (0) posi- tions by pushing the switches up. Set switch S401 for: MODE SWITCH SECTION 0 1 2 3 4 5 6 7 -- 9600 Baud 0 0 1 1 No Parity 0 Odd Parity 0 Normal Parity 0 Full Duplex 1 L--_ When no parity is selected, you can set the even and normal parity switch sections to either position since they will be ignored. Each function of switch S401 is explained in the fol- lowing text. "", r®l ==[JI==@==T m, ~ ,- Figure 3·1 o 5402 ~n~~e~~~~~ 1 10 12 34_.? .6_ 7 (ON). .'; :<---------.', ........J ";"..; ;', ; ,.. : ,'" • ! ~_ •. - •.•_. - _... ._.__. . .-l •....•.. , _ .•... .. __•..•._-_. 5401 o '.. < .•:_ 1aa~~~8B~ ~!u:/_: 1 0' 234567 .----- --- - -.- (ON)- ------- ! .: •

9600. If you use your Computer as a terminal, you can reset the baud rate as explained below. Odd/Even Parity If section 4 = 1, then section 5 of switch S401 selects odd or even parity. Normal/Stick Parity ZDS Software supports full duplex operation. Set sec- tion 7 to 1 for full duplex operation. Section 7 of switch S401 selects either full or half duplex communications between the Computer and the terminal sections. If section 4 = 1, then section 6 of switch S401 sets the ACE to transmit and receive either stick or normal parity. You can select any of 12 different baud rates (110- 9600). To do this, place sections 0, 1, 2, and 3 of switch S401 to the proper positions as shown below. The baud rate will be initialized (or updated) upon Reset or during power-up. BAUD SWITCH SECTION RATE 0 1 2 3 N/A 0 0 0 0 110 1 0 0 0 150 0 1 0 0 300 1 1 0 0 600 0 0 1 0 1200 1 0 1 0 1800 0 1 1 0 2000 1 1 1 0 2400 0 0 0 1 3600 1 0 0 1 4800 0 1 0 1 7200 1 1 0 1 9600 0 0 1 1 19200* 1 0 1 1 Down (1) Up (0) Down (1) Up (0) Half/Full Duplex Down (1) Up (0) Even Parity Odd Parity Stick Parity Normal Full Duplex Half Duplex Parity You can program the ACE (Asynchronous Communi" cation Element) to either generate or eliminate the parity bit. Section 4 of switch S401 selects the parity bit. Replace the circuit boards and reconnect their cables. Down (1) Up (0) Parity No Parity ZDS Software does not check parity. *Not currently supported (may drop characters)

Switch SW501 The functions that switch SWSOl selects are deter- mined by integrated circuit U518. See Figure 3-2. 5-1/4/1 HARD-SECTORED FLOPPY USAGE When you use a 5-1/4/1 hard-sectored floppy disk, integrated circuits part numbers HE 444-40, HE 444- 62, or HE 444-84 must be installed at U518. Set SW501 switch sections as directed in the next two steps. Then proceed directly to "Programming Jum- pers." See Figure 3-2. Set SW501 section 5 to "i." Set the remaining seven SWSOl sections to "0." L...---tU- uuuuuu Figure 3-2 CPU board. I I

When you use an 8" floppy disk (Z-47), integrated circuit part numbers HE 444-62 or HE 444-84 must be installed at U518. • When you boot up from a 5-1/4" hard- sectored floppy disk to enable your 8" floppy disk, set SW501 switch sections as directed in the next two steps. Then proceed directly to "Programming Jumpers." See Figure 3-2. Set SW501 switch sections 2 and 5 to "1." Set the remaining six SW501 sections to "0." • When you boot up from the left-hand 8" floppy disk drive, set SW501 switch sec- tions as directed in the next two steps. Then proceed directly to "Programming Jumpers." Set SW501 switch sections 2, 4, and 5 to "1." Set the remaining five SW501 switch sections to "0." 8" FLOPPY DISK (Z-67) USAGE There are four ways of installing the Interface Board. How you install yours depends on what equipment you already have. If you have: 1. A Z-89-37 Double-Density Controller, you must install your Interface Board as shown in Figure 3-3 on Page 3-6. Switch SW501 on the CPU Board must be set as shown in inset drawing #1. The jumpers on the Interface Board must be set as shown in inset drawing #2. 2. An H-88-1 Disk Controller, you must install your Z-89-67 Interface Board as shown in Figure 3-4 on Page 3-7. Set switch SW501 as shown in inset drawing #1, and the jumpers as shown in inset drawing #2. 3. A Z-89-47 Interface Board, you must install your Z-89-67 Interface Board as shown in Figure 3-5 on Page 3-8. Set switch SW501 as shown in inset drawing #1, and the jumpers as shown in inset drawing #2. 4. None ofthe Above, install your Interface Board as shown in Figure 3-6 on Page 3-9. Set switch SW501 as shown in inset drawing #1, and the jumpers as shown in inset drawing #2. You may set the DIP switches on the Interface Board in any position when you are using Zenith software.

___--I N S ET #2---.....z::-.... .... ~ ~ • JUMPERS ON Z-89-67 BOARD • • • • DO NOT MOVE D7E~; IiDd1IUDD' '----\.i-- JUMPER THESE WHEN US ING P506 AND P512 n ~~ ~ ~~ o n O S l) ~to~ 0-89-37 SERIAL '-89-67 HERE BOAR D HERE HERE Figure 3-3

~ .......---INSET #2---__~ JUMPERS ON Z-89-67 BOARD SWITCH SW501 • • • • • DO NOT MOVE D~ THESE JUMPERS :/~D liD dDooo' -----\.7·-..... JUMPER THESE WHEN US ING P504 AND P510 H-88-1 J- HERE -,i c:- t- SERIAL BOA RD HERE I i~ (J-! Z-89-67 HERE r- ~ rCi- 1 rL, I' I u Ll lSI I LJ Figure 3-4

• • • • • DO NOT MOVE D7[~: liD ClDooo . '----~.i,-.... JUMPER THESE WHEN US ING P506 AND P512 I I n T §L~ I Z-89-67 HERE SERIAL BOARD HERE lJ ~ nrBl- ULJ HERE I~ (d- I IU [cue i-L" i~ II Figure 3·5 I I

SWITCH SW501 • • • • • DO NOT MOVE D~ THE SE JUMPER S :J~D' • • • IiDcmUOO' '----\.i-.... JUMPER THESE WHEN US ING P506 AND P512 Z -89-67=:1- HERE)-l I I ----@~ HERE -I--l-II I :~ -c- iV-I I 0 '" I CL ~J ~J:- I I ~~I , ' I I LI Figure 3·6 I I

Z-89·47 For a system to operate properly with the Z-89-37 ,the Z-89-47 I/O board should be installed at plugs P506 and P512. However, before the Z-89-47 will operate properly when plugged into plugs P506 and P512. a resistor must be added to the Z-89-47 circuit board. To make the modification use a 4700 n. 1/4-watt resistor. HE-6-472 (yellow-violet-red), slide a length of sleeving over the resistor and solder the resistor between pins 1 and 12 of plug P2 on the foil side (not the component side) of the Z-89-47 circuit board. Refer to Figure 3-7. Set the 170/174 programming plug to 174. Install the Z-89-47 board at plugs P506 and P512. NOTE: If you ever move this board to another set of plugs, be sure to remove the 4700 n resistor that you just installed. H-88-l FLOPPY DISK 110 CIRCUIT BOARD • • • · . '.' · . .. Figure 3-7

following information. Use the following information for any special configurations that you may want. Programming modules: We recommend that you do not use both 48 and 96 TPI drives in the same system, since the precompensation will be wrong for at least one of the drives. This can result in reduced data reliability. When precompensa- tion is selected, it is factory pre-set to 300 nanoseconds. J1 & J2 13 Select port 170 or 174. (Both jumpers must be at 170, or both jumpers must be at 174. 170 is normal.) 1 = No precompensation; 0 = pre- compensation. (1 position is normal.) Use "0" if any of your drives are 48 TPI Wangco Model 82 (HE 150-71) drives. Otherwise, use "1." J4 - J7 Selects which drive is connected to plug P3. (Drive numbers are deter- mined by how the drive program- ming modules are cut. See Figure 3-8.) J4 = DS1 J5 = DS2 J6 = DS3 J7 = DS4 (presently not supported)

Refer to the following chart and Figure 3-9, and select the configuration that fits your situation. Configura- tion E is normally used for transferring data and pro- grams from hard-sectored disks to soft-sectored disks. DRIVE ~ After you select the configuration you want, refer to Figure 3-10 on Page 3-14 to program any 48 TPI (H-17-1) drives, or Figure 3-11 on Page 3-15 to program any 96 TPI drives. [Figure 3-12 on Page 3-16 shows single-sided drives (H-17-1) programmed for connection to an H-88-1 Controller.] You can do this programming by physically interchanging preprogrammed drives, interchanging the programming modules, cutting the programming modules (if presently uncut); or by replacing the programming module with a properly set dip switch. DRIVE DRIVE r=J~ 1 2 ~ ~ u w Figure 3-9 TYPES OF DRIVES: FLOPPY DISK • 48 TPI (H-17-1) CONTROLLER BOARD(S) • 96 TPI (H-17-4) Drive 0 Drive 1 Drive 2 A H-88-1 48 TPI (H-17-1) only. DS3 DS2 DS1 Intornal drive present B H-88-1 48 TPI (H-17-1) No drive installed DS3 DS2 Internal drive absent C 2-89-37 Either* DS1 (2-89-37 DS2 DS3 Internal drive present jumper installed at J4) 0 2-89-37 Either* No drive installed DS1 DS2 Internal drive absent (2-89-37 jumper installed at J7) E H-88-1 it< 2-89-37 Either* DS3 IDrive 0 is OS1 (Drive 0 connected DS2 (Drive connected Internal drive present 48 TPI (H-17-1) to 2-89-37) 2-89-37) drive connected to H-88-1. 2-89-37 jumper installed at J6.] * All drives connected to the 2-89-37 should be of the same type, either 48 TPI (H-17-1) or 96 TPI (H-17-4).

t I PROGRAMM I NG MODULE HAROWARE UNIT ONE (052) II~I .,.,... ............ -I CUT "1r:P~R~O~GR:-:A~M~M:-:-I :7':NG::-l ,[-=:J MODULE [ I ~In, , ,,, ..,..,..,., ......... ~==t HARDWARE UNIT TWO (053) Figure 3·10 Single-sided drives (H-17-1) programmed for 2-89-37 Controller. I II ·u

MODULE f,·,·,·'·'·'·1. ~ bl-1-'-'-~ ~ S '-1-1-1-1-1-1-1 COMPUTER------------------------13-15 Hardware Unit Zero (081) Hardware Unit One (082) l s n '-1-1-1-1-1-1-1 ~ n PROGRAMM ING MODULE PROGRAMM I NG MOD ULE n Hardware Unit Two (083) Figure 3-11 Double-sided drives (H-17-4) programmed for Z-89-37 Controller. i I

) '---- HARDWARE UNIT ONE HARDWARE UNIT TWO Figure 3-12 Single-sided drives (H-17-1) programmedfor H-88-1 Controller.

When IC part number HE 444-62 is installed at U518, the following table describes the functions of each SW501 switch section. SWITCH SECTIONS SETTING* DESCRIPTION 1 and 0 00 Port 174/177Q (7CH-7FH) has a 5-1/4/1 hard-sectored floppy disk (normal). 01 Port 174/177Q has a Z-47, 8/1 floppy disk. 10 Undefined. 11 Undefined. 3 and 2 00 Port 170/173Q (78H-7BH) is not in use (normal with Z-47, 8/1 floppy disk). 01 Port 170/173Q has a 8/1 floppy disk (normal with Z-47). 10 Undefined. 11 Undefined. 4 0 Boots from device at port 174/177Q (7CH-7FH) (5-1/4/1 hard- sectored floppy disk). 1 Boots from device at port 170/173Q (78H-7BH) (Z-47, 8/1 floppy disk). 5 0 Performs memory test upon power-up or SHIFT-RESET. 1 Does not perform memory test (normal). 6 0 Sets console to 9600 baud (normal). 1 Sets console to 19200 baud (not currently supported). 7 0 Normal boot (normal). 1 Auto boot on power-up or SHIFT-RESET (not recommended). * Right-hand value is for switch section 0 or 2, depending on respective Switch Section column.

When IC part number HE 444-84 is installed at U518, set the sections of SW501 as described in "Definition of SW501 with MTR-89," except for sections 0,1,2, and 3, which are defined as follows: 7BH) is Z-37 soft-sectored disk. 47, 8" floppy disk. 67. 8" hard disk. -7FH) is 5-1/4" hard-sectored floppy disk. 47, 8" floppy disk. 67, 8" hard disk. SWITCH SECTIONS SETTING* DESCRIPTION 00 Port 174/177Q (7CH 01 Port 174/177Q is Z- 1 and 0 10 Port 174/177Q is Z- 11 Undefined. 00 Port 170/173Q (78H- 01 Port 170/173Q is Z- 3 and 2 10 Port 170/173Q is Z- 11 Undefined. .- u * Right-hand value is for switch section 0 or 2, depending on respective Switch Section column.

The memory decode ROM is located at U517 on the CPU board. Two ROMs have been used. Part number HE 444-42 was originally used. This ROM precluded the use of more than 48K of memory or CP1M. It has been superseded in all production units by HE 444- 66, which allows the ROM based 48K mode, the ROM based 56K mode, and an all RAM 64K mode. All users should upgrade to this part regardless of configura- tion. There are no negative consequences connected with this upgrade. Associated with this ROM are three or four jumpers, JJ501 thru JJ504. Older CPU boards have all four jumpers; they should be set as follows: When using the Old ROM (HE 444-42) When using the New ROM (HE 444-66) . JJ501 JJ502 JJ503 JJ504 16K 0 0 ** o (or B) 32K 1 0 ** o (or B) 48K 0 1 ** o (or B) 64K* 1 1 ** o (or B) Newer CPU boards (which only have three jumpers, JJ501 through JJ503) are supplied with the new de- code ROM (HE 444-66) already installed and the jumper wire incorporated directly into the PC board foil. These boards should not be used with the old ROM (HE 444-42). These jumpers should be set as follows: JJ501 JJ502 JJ503 JJ504 16K 0 0 0 o (or B) JJ501 JJ502 JJ503 32K 1 0 0 o (or B) 48K 0 1 0 o (or B) 16K 0 0 o (or B) 32K 1 0 o (or B) 48K 0 1 o (or B) 64K* 1 1 o (or B) These are four jumper wires associated with the code ROM and the secondary address decoder. These are either JJ505, JJ506, JJ507 and JJ508 (on older units) or JJ504, JJ505, JJ506 and JJ507 (on newer units). These should be set as follows: Older Units: Newer Units: MTR-88, MTR-89 MTR-90 JJ505 JJ504 o JJ506 JJ505 o JJ507 JJ506 o JJ508 JJ507 1 (or B) 1 (or B) * Requires the WH-88-16 accessory PC board. * * A jumper is required between the center pin of JJ503 and pin 17 of P509, or P4 of WH-88-16 (which connects topin 17 of P509). This jumper may have been soldered on the back of the CPU board during manufacture (for Z·89-FA and some other models), or it may be ordered as part number HE 134-1120 and installed by the user. Neither tools nor soldering are required.

FLOPPY DISK The single-density floppy disk interface circuit board is installed at P506 and P512 on the CPU circuit board. SERIAL INTERf'ACE Refer to Figure 3-13 on Page 3-21 and set all three programming jumpers to OFF if this has not already been done. NOTE: These jumpers determine the interrupt prior- ity of the ports. When a jumper is in the "OFF" posi- tion, no interrupt exists for that port. When you install the jumper at 3, 4, or 5, an RST 3, an RST 4, oranRST 5 (respectively) instruction is executed when the inter- rupt for that port occurs. The first port on the circuit board is located at address 340/3470 (OEOH-OE7H) and is normally used as the line printer port. However, it is not restricted only to that use, as it is a standard RS-232C interface with a "DCE" connector. The second port on the circuit board is located at address 320/3270 (ODOH-OD7H) and is a general pur- pose port. It is a standard RS-232C interface with a "DCE" connector. The third port on the circuit board is located at address 330/3370 (OD8H-ODFH) and is a general purpose port. It is a standard RS-232C interface with a "DTE" connector, suitable for use with a MODEM.

o -- -c:J- -e::r - 0-[}- • - -[J-o • • 341".~lP II ~f -~~' 32.~DC[ II ~OFF ,~~ m~~H o o -~. o .. 321 - • Figure 3·13 S . I ena interface board.

8K 48K 1------------- 112 OF US42-U549 U542-U549 8K

Do not turn the Computer on or off when a floppy disk is installed in the disk drive with its door closed. Errant power sig- nals can cause the disk head to bounce. If the drive door is closed, the drive head is engaged on the dis- kette and can possibly damage the diskette. If your Computer uses the MTR-89 or the MTR-90 monitor, you will find a couple of differences in the commands. T(est Memory) The MTR-90 uses a shorter command for T(est Mem- ory). By typing T, the RAM memory test is initiated. The test references memory locations in the current radix. Error messages report the address of any bad memory locations. EXAMPLE: Set the current radix to hexadecimal and then check it. H: R(adix) H(exadecimal) H: R(adix) ~ Hexadecimal H: This summary is a list of the commands that the Computer will respond to and the responses that it will make. You may enter commands in either upper or lower case characters. In all cases, pushing the DELETE key prior to pushing the RETURN key (which terminates the command) will cancel the cur- rent command and cause the Computer to respond with the prompt (H:). All byte entries are in octal, and all address entries are in split octal. NOTE: Split octal is two 3-bit bytes as shown in Figure 4-1. You may also use the same command for Test Mem- ory as used for the MTR-89, which is (H: Go 7375 §). R(adix) HIGH ORDER BYTE LOW ORDER BYTE The R(adix) command sets the current working radix for all other commands. 15 14 13 12 11 10 9 8 o 0 I 000 0 0 6 o 4 o 2 o Figure 4·1 Valid arguments to radix are O(ctal) and H(exadeci- mal). The default current radix on power up is octal. Typing R and RETURN with no argument displays the current radix. o 4 o 2 5 3

seconds until the CRT becomes illuminated. 2. Boot: After you see the prompt (H:), enter "B." The Computer will complete the "Boot" message and then wait for a Carriage Return. Insert a diskette in the floppy disk drive and close the door. Now press the RETURN key and the system should begin booting up. If the system seems to stop after a second or two of disk activity, depress the space bar two or three times. (You may be directed to do this by a message on the screen, depending on the firmware installed.) 3. Go to the user routine: (G) or (G ADDR) A. After the prompt, enter "G." The Computer will complete the "Go" message. B. Enter either a Carriage Return or a new address and a Carriage Return. C. If you did not enter a new address above (in Step B), control will be given to the routine at the address specified by the user program counter. However, if you entered a new address and a Carriage Return, control will be given to the address you specified. 4. Set the user Program Counter values: (P) or (P ADDR) 5. After the prompt, enter "P." The Computer will complete the "Program Counter" mes- sage. Now you may enter a new program counter value (in split octal) and terminate it with a Carriage Return. If no new value is entered and you enter a Carriage Return, the current contents of the user Program Counter will be displayed. Again, a new value may be entered and terminated with a Carriage Re- turn, or just entering a Carriage Return will cause a return to the prompt and the current value to be unaltered. Substitute memory: (S) or (S ADDR) After the prompt, enter "S." The Computer will complete the "Substitute" message and wait for an address to be specified (in split octal notation) and ended with a Carriage Re- turn. The address specified will then be dis- played, followed by its contents. At this point, you can change the contents by enter- ing the octal value to be placed into memory. If you do not want a change, or after you have entered the new value, there are three op- tions. A. To view the contents of the next address; enter a SPACE. B. To view the contents of the previous address; enter the minus sign (-). C. To exit the Substitute mode; enter a Carriage Return. u

power ON/OFF switch is located on the right rear corner of the back panel. Whenever you turn on the Computer, allow the tube about 30 seconds to warm up. You should then see a flashing line (cursor) or block cursor (if it was selected) in the upper left-hand corner of the screen. The keyboard allows you to send data to the Computer of the screen. Most of the keys are the same as they are on most typewriters; they type the same alphanumeric characters. A clicking sound tells you that each keystroke has been processed. You cannot damage the Computer by typing on the keys. ~ i0~ 48 6 ~ rum.l DL ~~~ 3 ~g,,,," Figure 4-2

SWITCH UP 0 olIII( COMPUTER PORTION I KEYBOARD .. SC REEN IOFFLINEI 0 OFF LI NE ~------, SW ITCH DOWN COMPUTER PORTION KEYBOARD I~--------~ SCREEN HALF DUPLEX OFF LINE SWITCH UP 0 (COMPUTE R CAN SEND) TO TERMINAL -(-- ~ COMPUTER PORTION KEYBOARD .. Figure 4-3 The screen contains 2000 normal character positions; 25 lines of 80 characters. Only one character can oc- cupya character position at any given time and it will remain there until it is erased or replaced. When the Computer is initially turned on, it clears the screen by placing spaces in all character positions. The cursor is the blinking horizontal line that appears at the home position. It underlines the character posi- tion where the next character will be written. (The block cursor will fill the character position.) As shown in Figure 4-3, you can use the Computer in anyone of three different modes; full duplex, off line, or half duplex. (However, half duplex is not a normal ZDS mode.) When the Computer is on line, the keyboard can transmit anyone of the 12810 ASCII characters to the computer section. However, some of these characters will not be displayed if the Computer sends them back to the Terminal section.

connected from the Computer and the keyboard con- trols the screen directly. This way, you can position the cursor (t, ~ , ~, ~, and HOME), insert or delete characters or lines (IC, DC, IL, and DL), or erase (ERASE), without sending the codes to the Computer - which could otherwise disrupt a program, etc. Another way of controlling the screen without send·· ing code to the Computer is to use the CTRL key. Example: you want to erase the screen, but you do not want to transmit a code to the Computer. Press and hold the CTRL key and then type SHIFT ERASE. This tells the terminal section to erase the screen, but not to send the code to the Computer section. Again, you can use this procedure with the cursor keys (t, ~, ~, ~, and HOME), the Insert Line, Delete Line, Insert Character, and Delete Character keys, and ERASE. Whenever you use the special escape codes to enter and exit the special modes, make sure you enter the lower-case and upper-case letters. For instance, type ESC p (not ESC P) to enter the reverse video mode. The "ASCII Characters" and "Escape Sequences" show the commands and special escape sequences that the terminal section sends and responds to. Your Computer must contain the proper software for it to respond to and generate the codes that use these spe- cial features. Different versions of software may sup- port different features. The Computer has a 128 character input FIFO (first in, first out) buffer for receiving and holding characters until the terminal section can process them. In some cases (such as when the terminal section is operating at 9600 baud in the "insert character" mode), the FIFO can be filled faster than the terminal section can process the characters. In this case, the terminal sec- tion will send X OFF (control S) when the FIFO has received 112 characters. After the terminal section has processed enough characters so that only 96 characters remain in FIFO, it will send X ON (control Q) to the Computer section to indicate that it is ready to accept more characters. When the terminal section sends X OFF, ·this is only an indication that the buffer is nearly full. Characters will not be lost until after the FIFO has received a full 128 characters. At this point more incoming charac- ters will be lost and the bell will sound. NORMAL MODES AND KEYS The following descriptions are for switch S402 set to all zeros. ALPHABETIC KEYS NONALPHABETIC KEYS The Computer has the standard 26 letters of the alphabet. These keys can transmit either lower-case or upper-case codes as well as display them on the screen. You can either hold the SHIFT key down or you can push the CAPS LOCK key to obtain upper-case letters. The nonalphabetic keys are those with double mark- ings. These include the numbers 0 through 9, punctu- ation marks, and special characters. The lower mark- ing is generated when both of the SHIFT keys are released, while the upper marking is generated when either (or both) SHIFT key is held down. The CAPS LOCK key will not shift these keys.

only to the terminal's internal key handling of the listed codes, which can be overridden by the software. RETURN - Moves the cursor to the first character position of the line that it is currently in. If the cursor is already at the first character position, it remains there. RETURN is a nondisplayable character. Nor- mally, there is n~ automatic line feed. LINE FEED - Moves the cursor down one line. LINE FEED is a nondisplayable character. If the cursor is at the bottom line, a LINE FEED causes it to remain there, but all of the data on the screen moves up one line. Data on the top line is lost as it is scrolled up and off the screen. Normally, there is no CR. SPACE BAR - Causes the cursor to move one charac- ter position to the right. A Space is a nondisplayable character. Ifyou type the Space Bar when the cursor is positioned below a displayed character, the character is replaced by a space and the cursor moves one character position to the right. If you type the Space Bar when the cursor is at the right end of a line, the cursor will remain there since neither a carriage re- turn nor a line feed is generated. BACK SPACE - Moves the cursor one space to the left. Ifthe cursor is at the start (left end) ofa line, it will not move when you type a BACK SPACE. ZDS software uses this key to delete the last input charac- ter. DELETE (Rubout) - Transmits the ASCII code 177Q (7FH). It is a nondisplayable character. ZDS software uses this key to cancel the last character that was input. TAB - When typed on the keyboard, it transmits the ASCII code 011Q (09H). When received by the termi- nal, it moves the cursor to the next tab stop (eight character spaces) to the right. The tab stops are fixed at 9,17,25,33,41,49,57,65, and 73 (columns are numbered 1 through 80). If the cursor is at character position 73 through 79, it will only move one charac- ter position to the right each time you type the TAB key. If the cursor is at character position 80, it will not move when you type the TAB key (unless the wraparound feature has been selected). ESC (Escape) - A nondisplayable character that transmits the ASCII code 033Q (lBH). This key is used in combination with other keys to enter and exit special modes. REPEAT - When you hold this key in, along with another key, it will repeat the function of the other key as long as both keys are held down. The repeat rate is approximately 8 characters per second. However, if the baud rate that has been selected is less than the repeat rate, the repeat function will operate at the slower rate. SHIFT - When you use this key in conjunction with another key, the character printed on the upper por- tion of that key will be displayed. When you use the SHIFT keys in conjunction with the alphabetic keys, the upper-case character is displayed. CAPS LOCK - When this latching key is down, the terminal section will transmit the ASCII code for, and display, upper-case (capital) alphabetic letters. It does not shift the keys with the double markings. This is not a shift lock. OFF LINE - When this latching key is down, the terminal section is inhibited from transmitting or re- ceiving data. However, any displayable characters that you type on the keyboard will appear on the screen and any local control codes will be responded to. BREAK - When you type this key, it generates a continuous space at the output of the terminal sec- tion. It is generally used to tell the computer that you wish to interrupt execution. RESET - Allows you to reset the Computer to its preset condition; it exits all escape modes and resets the baud rate to the rate selected by the switches on the logic circuit board. To use this key, you must press only the right-hand SHIFT key and the RESET key at the same time. This two-key combination pre- vents you from inadvertently resetting the Terminal.

when in the Hold Screen Mode, you can type the SCROLL key to instruct the Terminal to display another line of information onto the screen. You can simultaneously press the SHIFT and SCROLL keys to display another 24 lines of information onto the screen. Bell (BEL or CTRL G) - Causes the Terminal to sound an audible tone through an internal speaker. Back Space (BS or CTRL H) - Duplicates the BACK SPACE key. Horizontal Tab (HT or CTRL I) - Duplicates the TAB key. SCROLL (line) SCROLL (page) CONTROL KEY SCROLL SHIFT/SCROLL Line Feed (LF or CTRL J) - Duplicates the LINE FEED key. Carriage Return (CR or CTRL M) - Duplicates the RETURN key. The CTRL key is held down while you push one of the other keys to send the 32 ASCII control codes to the Computer. These are nondisplayable characters. The Terminal responds to only seven of the control characters from the keyboard or from the serial input port. These seven characters are: Escape (ESC or CTRL [ ) - Duplicates the ESC key. Cancel (CTRL Xl - Cancels the current escape sequence.

Schematic, the circuit component numbers (R1, C101, L301, etc.) for resistors, capacitors, coils, tran- sistors, and integrated circuits are in the following groups. 0- 99 Parts mounted on the molded cabinet base or front panel. 100-199 Parts mounted on the power supply cir- cuit board. 200-299 Parts mounted on the v~deo circuit board. 300-399 Parts mounted on the keyboard circuit board. 400-499 Parts mounted on the terminal logic cir- cuit board. 500-599 Parts mounted on the CPU logic circuit board. 600-699 Parts mounted on the serial interface circuit board. 700-799 Parts mounted on the cassette interface circuit board. 800-899 Parts mounted on the hard-sectored floppy disk interface circuit board. 900-999 Parts mounted on the video driver cir- cuit board.

Refer to the Schematic Diagram (part 3 of 3) lfold-in) as you read the power supply circuit description. The primary circuit of the power supply consists of slow-blow fuse Fl, ON/OFF switch SW3, 115/230- volt switch SW1, NORM/LOW line switch SW2, and the primary windings of transformer Tl. Thered secondary windings oftransformer Tl supply AC to diode bridge rectifier DI09-D112. The 65-volt rectified output of the bridge is filtered by capacitor Cl. It is used to power the video circuits. The yellow secondary windings of Tl supply AC to the diode bridge rectifier BRl. The rectified output of the bridge (approximately 9 VDC) is filtered by capacitors CIOl and CI03 and is used on the logic circuit board. The green secondary windings supply center-tapped 30 VAC to diode bridge rectifier DIOI-DI04. The rec- tified output of the bridge (±18 VDC) is filtered by capacitors CI02 and CI04. This output is used on the logic circuit board. INTERCONNECTION AND GROUNDING The three power supplies (+65, +8.5, and ±18) are not interconnected on the power supply circuit board. Instead, they pick up their appropriate grounds at the circuit boards they power. The +65- volt video supply connects to + and ground points on the video circuit board. The external conductive coat- ing of the CRT and the CRT socket arc-ring both con- nect directly to the video circuit board ground. The +8.5-volt and ± 18-volt supplies connect directly to the logic circuit boards with no common grounds until they meet at the terminal logic circuit boards. This grounding method produces two independent operating systems that do not interact with each other except through the signal ground and sync/video in- puts. In the event of a CRT arc, the arc discharge current is confined to the video circuit board and it does not induce transients into the logic circuits. The logic/video system is also floating with respect to the ground wire of the power cord. The protective ground input (pin 1) of the EIA RS-232 connector connects to the power cord ground, along with all the exposed metal surfaces. The signal ground input (pin 7) of the EIA RS-232 connector connects to the terminal logic circuit board ground.

Refer to the Schematic Diagram (part 1 of 3), and the Block Diagram (fold-out from Page 5-15) as you read the video circuit description. POWER SUPPLY The unregulated 65 volts DC from the power supply circuit board enters the video circuit board at plug P202, pins 2 and 3. Assume that the Computer has just been turned on and the output of the +53-volt reg- ulator is at zero volts. The base current of Q201 is supplied through resistors R201, R202, and R203. The collector current of Q201 causes Q202 to turn on and supply current to the base of Q204. As the output voltage at the emitter of Q204 rises, D202 begins to supply current to zener diode D201 through resistor R202. D201 stabilizes at 12.8 volts and provides a reference for the output voltage. The divider formed by resistors R207 and R208 samples the output volt- age as it continues to rise, and applies a fraction of the voltage to the emitter of Q201. When the emitter volt- age of Q201 reaches 12.15 volts (12.8-.65), its collec- tor current is reduced to a value that keeps the output voltage stabilized at +53 volts. The current through R211, supplied to the load by Q204, generates a voltage that is applied through current limiting resistor R209 to the base of Q203. If the current thus developed exceeds about 1.1 am- peres, Q203 turns on and shunts current from the base of Q202, which, in turn, prevents the output current from exceeding 1.1 amperes. D203 and R212 form another zener regulator that supplies 6.2 volts DC to the video driver circuit board and 6 volts DC to the horizontal section through R213. VERTICAL SECTION The vertical portion of the video circuit board con- sists of two sections, a sweep generator and an amplifier. The sweep (or ramp) generator consists of C208, C209, R221, and Q205. Capacitors C208 and C209 charge to +53 volts through resistor R221 to generate the ramp. This ramp voltage is applied to the anode of Q205, a programmable unijunction transistor. The gate of the unijunction is biased at a voltage deter- mined by R215, R216, D204, and R217. When the anode voltage charges to the gate voltage, Q205 con- ducts and dicharges C208 to ground through L201. As the discharge current decreases to zero, the unijunc- tion stops conducting and the capacitors start to charge again through R221. The ramp voltage is applied to the base of Darlington voltage follower Q206. The emitter voltage of Q206 is fed back to the junction of C208 and C209 to linearize the exponential ramp. Resistor R222 and Vert Linear- ity control R223 determine the amount of correction applied to the ramp. The amplitude of the ramp is determined by R218 and the Vert Size control, R219. The free-running frequency of the oscillator is slightly less than 60 Hz, the normal sweep rate. Verti- cal sync pulses, which enter the circuit board at plug P202, pin 6, are coupled through C206 and D204 to the gate of transistor Q205. The negative-going pulse lowers the gate voltage below the anode voltage and Q205 immediately conducts, discharging C208 and C209 before the free-running trip point is reached. This increases the oscillator frequency to 60 Hz (or 50 Hz if you set section 7 of switch S402 to its "1" position). Each succeeding sync pulse keeps the os- cillator synchronized with the vertical sync signal generated by the CRT controller on the logic circuit board.

posed of Q207, Q208, Q209, Q210, Q211, and Q212. Under steady-state conditions, with no ramp signal applied to the base of transistor Q208, the collector currents of Q207 and Q208 are determined by bias string R225, R226, R227, R228 and emitter resistors R229 and R231. The collector current of Q207 is nom- inally 3 milliamperes, and the collector current of Q208 is nominally 2 milliamperes. The difference (1 milliampere) between the two, supplies base current to driver transistor Q209, which drives output transis- tors Q211 and Q212. Diode D205 and resistor R237 bias transistors Q211 and Q212 so that there is enough idle current to eliminate crossover distorsion. Tran- sistor Q210 is a current source that provides base current for Q212 and the bias network, D205 and R23 7. The output voltage at the junction of R239 and R241 is fed back to the bias string through R234 to keep the output stable at about 25 volts. When the ramp signal is applied to the input of the amplifier through C211, the collector current of Q208 is varied as a function of the amplitude of the ramp voltage. The difference between the currents of Q207 and Q208 drives the outputs through Q209. The out- put voltage is fed through C216 to the vertical deflec- tion yoke. Resistor R242, which is in series with the yoke, generates a voltage proportional to the yoke current. This voltage is fed back to the base of Q207 (negative feedback), which changes its collector cur- rent to keep the yoke current directly proportional to the input ramp voltage. HORIZONTAL SECTION The horizontal portion ofthe video circuit board con- sists of three sections: Time delay and pulse shaping. Horizontal deflection. High voltage supplies. The time delay and pulse shaping circuits are triggered by the horizontal sync pulses that come from the logic circuit board. They generate a time delay that provides horizontal centering and a pulse of the proper width to drive the horizontal sweep system. The horizontal deflection system transfers energy from the power supply to the yoke in order to sweep the beam across the face of the CRT. The high voltage supplies generate the anode and grid voltages that operate the CRT. TIME DELAY AND PULSE SHAPING The horizontal sync pulses enter the circuit board at plug P202, pin 1. These pulses are then coupled through R243, C217, and D206 to U201. The trailing edge of each pulse triggers U201, a timer used as a monostable multivibrator, causing the output (pin 3), to go high. The width of the output pulse is deter- mined by C221, R247 and Horizontal Centering con- trol R246. When the output pulse from U201 goes low, it triggers another timer used as a monostable multivibrator, U202. The 20 microsecond output pulse of U202 (pin 3) is determined by C223 and R249. This pulse drives horizontal driver transistor Q213. HORIZONTAL SWEEP AND HIGH VOLTAGE Transistor Q213 and driver transformer 1'201 drive horizontal output transistor Q214, which, in turn, drives the horizontal output transformer (flyback transformer) and the yoke. The positive-going pulse from U202 is coupled through the parallel combina- tion of R2 51 and C224 to the base of Q213. During the time the pulse is high, the collector current of Q213 flows through the primary of1'201. The phasing ofthe transformer is such that the secondary output voltage during this time is negative and keeps Q214 turned off. While Q213 is turned on and current flows through the primary, energy is stored in 1'201. When the output pulse from U202 returns to zero volts, Q213 turns off, its collector current decreases to zero, the secondary voltage of1'201 goes positive, and Q214 starts to conduct. The energy stored in the trans- former is converted to base current and keeps Q214 turned on for the rest of the cycle. The transformer inductance, R254, R255, C226, and L202 control the base current decay and insure the best efficiency of the output transistor.

energy through the deflection components. When Q214 is turned on, current flows from the power sup- ply through the primary of horizontal output trans- former T202 and through the horizontal yoke, L203, L204, and C232 to ground. During this time, the yoke current increases linearly and the beam is deflected to the right of the screen. When it reaches the right edge, driver transistor Q213 turns on and output transistor Q214 turns off. The energy that was stored in the yoke (along with the energy stored in the primary of T202) is transferred to C228 in the form of a half-wave volt- age pulse with an amplitude of 550 volts. During this cycle, the current through the yoke goes to zero and the beam returns to the center of the screen. Capacitor C228 now discharges into the yoke, inducting a current in the opposite direction, deflecting the beam to the left side of the screen. As the voltage across C228 decreases to zero volts, the resonant circuit of C228, the yoke, and the primary of T202 try to oscillate in a negative direction. The energy transferred to the yoke by C228 now provides the sweep current for the first half of the scan and charges C232 via damper diode, D208. Shortly before the beam reaches the center (before the yoke current reaches zero), transistor Q213 is turned off by U202 and Q214 is turned on. For a brief period, both D208 and Q214 are conducting in opposite di- rections. D208 is conducting the yoke current and Q214 is conducting the primary current of T202. Transistor Q214 turns on early to guarantee a smooth transition from negative to positive yoke current. The value of C232 is chosen to provide "S" shaping of the current waveform through the yoke. This com- pensates for stretching at the left and right edges of the screen. Since the deflected beam sweeps a wider area at the edges than it does at the center for a given deflection angle, the current is decreased slightly at the left and right edges. Width coil L203 is in series with the yoke and its reactance can be adjusted to change the total current through the yoke. If its reactance is high, the yoke current is slightly decreased and the scan width is reduced. If its reactance is low, the scan width is increased. Horizontal linearity coil L204 is a nonlinear inductor that provides further linearity correction that cannot be provided by C232 alone. HIGH VOLTAGE SUPPLIES The flyback voltage pulse developed at the collector of Q214 during the horizontal retrace is rectified by D211 and C231 to provide approximately 500 volts DC. This voltage, which is filtered further by R266, C235, C236, and C237 is coupled through R909, on the driver circuit board, to the CRT grid 2 (G2). The same flyback pulse is transformer coupled to the secondary of T202 and rectified by D207 and C229 to generate a -100-volt DC supply. Resistor R265 and Focus control R264 form a voltage divider between the +500-volt and the -100-volt supplies to provide a bias voltage for grid 4 (the focus grid). This voltage is coupled through R267 and R908, on the driver board, to G4 on the CRT. Another voltage divider consisting of D209, R261, and Gl control R262, between the +55-volt and -100-volt supplies, provides a bias for grid 1 of the CRT. The flyback pulse is also coupled to another secon- dary of transformer T202, the high voltage winding. The output pulse from this winding is about + 15,000 volts. It is rectified by Dl (in the anode lead) and filtered by the internal capacitance of the CRT to provide the anode (or accelerator) voltage for the CRT. Occasionally, the voltage stored in the internal capacitance of the CRT arcs over to the other elec- trodes. An arc ring built into the tube socket, and C233 (a capacitor with a parallel spark gap), in con- junction with driver circuit board series resistors R904, R907, R908, and R909, limit the amount of the arc energy on the video circuit board to a safe value. Flyback transformer T202 also has a filament winding that supplies 6.3 volts AC at 450 milliamperes to power the CRT filament.

Refer to the Schematic Diagram (part 1 of 3), and the Block Diagram (fold-out from Page 5-15) as you read the video driver circuit description. The voltages for the CRT, except for the anode supply and deflection voltages, are either generated on or pass through the video driver circuit board. The CRT 6.3 VAC voltage originates on the video circuit board and passes directly through the video driver circuit board to the CRT. The filament voltage is RF- bypassed to ground on the driver board by capacitors C907 and C908. A common ground also is routed from the video board through the driver board, and forms an arc-ground to the cathode and grid circuits of the CRT. The video amplifier is a conventional cascade amplifier. The video signal is routed onto the board from rear panel Brightness control R1 and through resistor R905 to the base of transistor Q902. The base of transistor Q901 is biased by the 6.2-volt supply coming from the video circuit board. The signal at the collector of Q901 is coupled through resistor R904 to the cathode of the CRT. Choke L901, in series with collector load resistor R903, provides high frequency compensation. Grid voltages for the CRT are routed through three, series-connected, current-limiting resistors on the driver board, R907 to grid 1, R908 to grid 4, and R909 to grid 2. TERMINAL LOGIC CIRCUIT BOARD Refer to the Schematic Diagram (part 2 of 3), and the Block Diagram (fold-out from Page 5-15) as you read the terminal logic board circuit description. The terminal logic board consists of seven functional blocks: 1. Power supplies. 2. Keyboard encoder and configuration logic. 3. Processor/CPU. 4. Master block and system logic. 5. Communications. 6. CRT and memory control. 7. Display memory, character generator, and video control logic. The integrated circuits in each block are numbered as follows: U426, U427, U429, U431, U434, U435, U440-U442 U413, U428, U430, U432, U433, U436-U439 U443-U450 U452-U454 U414-U418 U406-U411, U419-U425 Master clock and system logic. Processor, ROM, RAM, processor control logic. Keyboard encoder and configuration logic. Communications and I/O drivers. CRT and memory control. Display memory, character generator, and video control logic. U401-U405 Power supplies.

lated 5-volt supplies. U401 supplies 5 volts DC for the left half ofthe circuit board, while U402 supplies the right half of the circuit board. U403 supplies +12 volts DC, U404 supplies -12 volts DC, and U405 supplies -5.2 volts DC. These integrated circuits are internally protected against short circuits, overloads, and high temperatures. Capacitors C402, C404, C407 , and C411 at the inputs of the regulators stabilize the supplies, while capacitors C403, C405, C408, C412, and C413 improve the transient response of the reg- ulators. C412 serves as the input stability capacitor for U405 and as the output capacitor for U404. MASTER CLOCK AND SYSTEM LOGIC Clock And Scalers The master clock is a 12.288 MHz crystal-controlled oscillator. Crystal Y401, with C419, C421, and U426E form the oscillator. The series combination of C419 and C421 serve as the load capacitance for the crystal. U426E is the gain stage. Resistors R408 and R409 bias U426E into its linear region, while C418 bypasses any AC feedback through the two resistors. The output of the oscillator is buffered by U426D to prevent loading on the output from changing the oscillator frequency. This output is the "dot clock" and it is used by the shift register to shift dot information to the screen. The dot clock also drives divide-by-sixteen counter U427, which generates 1.536 MHz pulses. This is called the character clock. Each pulse corresponds to one character on the screen. U427 is a synchronous presettable counter that is loaded with a binary eight (1000). It counts dot clock pulses until its output reaches binary fifteen (1111). During the fifteenth count, the ripple carry output (pin 15) goes low. This pulse, which is inverted by U426F, puts a logic one on the load input (pin 9). The next positive-going clock cycle reloads a binary eight back into the counter and the cycle repeats. The Qc output (pin 12) generates a 1.536 MHz pulse that serves as the clock for CRT controller U417 (pin 21). It is inverted by U412D. These two signals are referred to on the Schematic as C and C. The OIl (pin 13) output generates a 3.072 MHz signal that drives the clock input (pin 16) of the ACE (U452). The dot clock also drives U429. U429 is a divide-by- six and divide-by-two scaler. The clock drives the B input (pin 1), and the Ov output (pin 8) generates a 2.048 MHz clock signal for CPU (U430). The Ov out- put (pin 8) also drives the A input (pin 14). The OA output (pin 12) in turn drives the input of binary scaler U440. The output of U440 provides a 128 kHz clock (pin 6) for the keyboard encoder, U444 and a 1 kHz signal (pin 14) for the audible bell signal. System Control Logic The system control logic consists of I/O and memory decoding, power-up and manual reset circuits, and the bell and key clock circuits. I/O and memory decoding are accomplished by three-to-eight line decoders U442 and U435, respec- tively. U442 decodes address bits A5, A6, and A7, to generate eight I/O addresses: 1. Keyboard encoder 200 (80H ) 2. Keyboard status 240 (AOH ) 3. CRT controller 140 (60H ) 4. Power-up configuration (primary) 000 (DOH) 5. Power-up configuration (secondary) 040 (20H ) 6. ACE (communications) 100 (40H ) 7. Bell enable 340 (EOH ) 8. Key click enable 300 (COH ) Decoder U442 is enabled only during an I/O read or write operation to eliminate the possibility of false decoding on a refresh address coming from the Z80.

memory addresses: 1. Program ROM 000.000 (00 DOH) 2. Scratchpad RAM 100.000 (40 DOH) 3. Display memory 370.000 (F8 DOH) Whenever the Z80 performs a read or a write opera- tion it will either write to or read from one of these memory or I/O addresses. When the Computer is first turned on, the CPU, CRT controller, ACE, and keyboard control logic are cleared by the master reset signal. U431A, R412, C422, and D401 form the power-up reset circuit. When power is first turned on, C422 has no charge and temporarily holds pin 2 of U431A at logic zero. The output of U431 goes high and is inverted by U431B. The two outputs are the true and the com- plimented reset pulses. As C422 charges through R412, it pulls the input of U431 high, turning off the reset pulses. A manual reset can also be accomplished if you simultaneously press the Reset and right-hand Shift keys on the keyboard. U446E and U446B are con- nected to those keys and they drive the inputs of U431D. The output of U431D (pin 11) is coupled throughR413 topin 1 ofU431A. R413 and C423 form a de-bounce circuit for the Shift and Reset keys. When the output of U431D goes low, the input of U431A is also pulled low. This generates a reset pulse. The CPU, under the control of the ROM program, can cause a bell tone or a key click to sound through the speaker. When the CPU addresses I{O port 340, pin 7 of U442 triggers one-half of monostable U441. Its output goes low for about 200 milliseconds, causing the output of U431C to go high. This logic 1 is NANDed in U434C with the 1000 Hz signal coming from U422. The output of U434C drives speaker SP1. Diode D402 keeps the output of U434C from being driven above 5 volts at turn-off by the inductive reac- tance of the speaker. When the CPU addresses I/O port 300, pin 9 of U442 triggers the other half of U441. Its output (pin 7) goes low for about six milliseconds and turns on the 1000 Hz tone. This short duration causes the tone to sound like a click. PROCESSOR The processor section of the Terminal consists of the Z80 processor, U430, the CPU (central processing unit), ROM (read only memory), RAM (random access memory), and processor control logic. Processor/CPU The heart ofthe terminal logic circuit board is the Z80 CPU. It acts as a scheduling or dispatching service for the data coming into or originating from the Termi- nal. It examines the data it receives and determines what, if anything, it should do with it. If the data comes from the ACE (U452), for example, the Z80 will compare the ASCII word with a set of conditions determined by the ROM program, and then write the word into the appropriate memory or I/O port. If the ASCII word is a bell signal, the CPU addresses I/O port :340, and the bell tone sounds through the speaker. If the word is the letter "B," the CPU per- forms a memory write to the current cursor position in the display memory. If the data from the ACE is a nonvalid character or a string of characters, the CPU simply ignores the data and does nothing. The ROM program that directs the CPU is rather long and complex, but the mechanics of the process are easy to follow. The 2.048 MHz clock signal drives the clock input (pin 6) of the CPU through U426A. This steps the CPU through an internal "Machine" cycle that starts with a fetch instruction. It executes the remainder of its instructions by stepping through a precise set of a few basic instructions. These include memory read, memory write, I/O read, I{O write, and interrupt acknowledge. The basic thing to remember is that the ROM program directs the Z80 to make decisions and move data from place to place within the circuit board. Without the CPU and ROM, the decisions and data movement would have to be ac- complished with hard-wired logic packages.

(32768 bit) ROMs. Its twelve address inputs connec1 to Ao through All of the address bus and its eight data outputs connect to DO through D7 of the data bus. U413A, U413B, and U434D decode the ROM select line coming from memory decoder U435. RAM The random access memory for the Z80 scratchpad consists of U438 and U439, 256 x 4-bit RAMs. This scratchpad RAM provides temporary data storage for the Z80. The address inputs to each IC connect to An through A7 on the address bus. The lower four bits of data (DO-D3) are provided by U438; the upper four bits (D4-D7) are provided by U439. The select signal comes from U435. Processor Control Logic The processor for the Terminal requires some addi- tional circuitry to control the interrupt process, and to provide a wait cycle for keyboard encoder U444, which is slow in responding to a read cycle. U432C is a 2-input NOR gate that monitors the INTRPT output of the ACE (U452) and pin 6 ofU447B (the keyboard INTRPT). When either INTRPT output goes high, the output of U432C goes low and signals the INT input (pin 16) of the Z80 that data is available from the ACE or keyboard. U433, U432A, and U432B form a counter that drives the WAIT input (pin24) oftheZ80. WhenevertheZ80 performs an I/O read at the keyboard encoder, pin 11 of U442 drives the "reset to zero" inputs (pins 12 and 13) of U433. The Ut and OB outputs (pins 9 and 5) of U433 drive the inputs of U432B, a 2-input NOR gate. The output of U432B holds the Z80 WAIT input low whenever the Ut or OB outputs of the counter are high. This generates a total wait of four clock cycles (one wait cycle is automatically inserted by the Z80 on an I/O instruction) to allow the output buffer of U444 to turn on. When the Qc output (pin 4) of counter U433 goes high, it drives the input of U432A high. This forces the output low and turns off the A input (pin 10) ofU433. The Ut and OB outputs now go low and the wait signal is no longer present. The Z80 then finishes up the I/O read cycle (pin 11 of U442 goes high) and the counter is reset to zero and held there until the next keyboard read. U428 provides a nonmaskable-interrupt (NMI) that operates under the control of the ROM program. The NMI routine is used when the program wants to read something into the CRT Controller (or CRTC) during the vertical blanking period. The data input of U428A is driven by A2 of the address bus. The T, or clock, input is driven by the complemented CRT controller I/O select that comes from pin 12 of I/O decoder U442 through U412C, which provides the complement of the signal. When the program wants to write during vertical retrace, it addresses the CRT controller while holding A2 high. The Q output of U428A is clocked high and drives the reset input of U428B high. The vertical sync signal from U417 drives the T input of U428B and clocks the Q output low as soon as the sync signal begins. The NMI input ofthe Z80 goes low and the program immediately jumps to the "update CRTC" routine. Part of that routine will write a zero to the data input of U428A to clear the NMI signal. KEYBOARD ENCODER AND CONFIGURATlON LOGIC Keyboard Encoder The keyboard of the Terminal consists of single-pole, single-throw switches in a matrix that is scanned by keyboard encoder U444. Outputs Xl through X9 go high, in sequence, and drive one of the Yl through YI0 inputs if one of the switches is depressed. The encoder uses the X and Y information to generate a

this code is latched internally when a key is depressed. The encoder generates a data strobe (DS), which comes from pin 13 of U444, for each key closure. DS clocks the T input (pin 3) of U448A and the Q output of U448A goes low. The Q output drives an input of U447B. The output of U447B, an INT signal, is coupled to Z80, pin 16. When the Z80 services the interrupt at I/O port 200, pin 11 of U442 clears U448A (through U447C and U446A) and the INT signal is removed. Pin 36 of U444 is also a binary data output and it is latched in U448B by the I/O read at 80H (200Q). The keyboard interrupt routine also checks the keyboard status in another I/O read operation. The keyboard status check reads the state of the following: 1. Control key. 2. Shift keys. 3. Repeat key. 4. Break key. 5. Off-line key. 6. Caps Lock key. 7. Data Strobe. 8. Data bit latched in U448B. The ROM program uses this information in conjunction with the encoder data to determine the routing of the data within the Terminal. Pin 10 of I/O decoder U442 drives enable inputs (pin 19) of buffers U449 and U450 to put the status information on the bus. The Caps Lock, Break, Off Line, Control, Repeat, and Shift (left) keys are connected directly to the inputs of these buffers. The outputs of U448A and U448B are also connected to the inputs ofthe buffers. The binary data outputs of the keyboard encoder drive the address inputs (AO-A7) of ROM U445. U445 converts the binary data from the keyboard encoder to ASCII data. The data outputs of U445 drive the DO-D7 bits of the data bus. The chip select input (pin 18) of U445 is driven by pin 11 of U442 (the I/O decoder). When the Repeat key is held down, the input of U446D is low and its output is high. This enables the repeat rate oscillator, U447A, R437, C481, and Q402. The repeat frequency, approximately 15 Hz, is deter- mined by R437 and C481. When the Repeat key is released, the output of U446D goes low, forcing the output of U447A high and disabling the repeat func- tion. The two shift keys are NORed together in U447D.lts output drives the shift input (pin 21) of U444. When the Control key is typed, the output ofU446F is forced high, which drives the control input (pin 19) of keyboard encoder U444. Configuration (Power-up) Logic When the system is first turned on, the ROM program must program the ACE (U452) for the baud rate and parity that you selected on switches S401 and S402. The program addresses I/O port ooH (OOOQ). Pin 15 of I/O decoder U442 drives enable inputs of U449 and U450 to put the information selected by the switches on the bus. The program then interprets the data and configures the ACE accordingly. I/O address 20H (040Q) is used in a similar manner. Pin 14 of the I/O decoder U442 enables buffer U443 and puts the data from S402 on the bus. COMMUNICATIONS AND I/O DRIVERS The Terminal talks to the outside world through an Asynchronous Communications Element (ACE) and EIA RS-232C compatible line drivers and receivers. The ACE (U452) converts parallel ASCII data to serial data and drives the communications line through line driver U453. The ACE also converts serial data com- ing from line receiver U454 into parallel ASCII data. The ACE puts this data on the bus when the ROM program requests it.

'1.. Serial Data Out. 5. Clear To Send leTS). NT RPT RCLK BAUDOUT SIN SOUT m m oTR oSR RLS 0 ifl OUT 1 OUT 2 II ·8) DATA RECEIVER RECEIVER BUS BUFFER SH IfT (j 01 BUFFER REGISTER l REGISTER 11 NE L.._ CONTROL RECEIVER 1.1 REGISTER TIMING & CONTROL DIVISOR 1281 LATCHILSI BAUD liS) (261 GENERATOR DIVISOR lATCHIMSI 4 SELECT 15 & CONTROL TRANSMITTER S LOG IC I+- LINE TI MI NG STATUS & CONTROL REGISTER T , 1--0 TRANSMITTER TRANSMITTER ~ HOLDING SH IFT (Il) REGISTER REGISTER MODEM "" I- CONTROL ~ REGISTER ~ MODEM I<- CONTROL MODEM lOG IC .~ 141)) J + SV I+- STATUS 4 POWER { (20) REGISTER SUPPLY J GN 0 INHRRUPT f-o I NTERR UPT " ENABLE CONTROL , REGISTER lOGIC PPlICABlE PINOUT NUMBERS lUDEO WITHIN PARENTHESES. INHRRUPT '10 REGISTER INTERNAL DATA BUS NOH, A ARE INC ASYNCHRONOUS COMMUNICATIONS ELEMENT (ACE) BLOCK DIAGRAM @: Vee ~~ !J RLSD § OSR AD Al ~ CTS AI ACE ~MR ~ DUll CSO CSI !NSI25() ~ DTR m AifI 1l1 R1S M' := om 2 DISTR 44)-952 ~ 'NT'''' DISTR DOS TR ~NC OOSTR DOIS ~AB CSOUT " Al XTAL I ~ A2 XTAl 2 tll ADS ~ csom t:3 DDrs I:iDISTR ~ DISTR D7~ RCtK ..,. SIN C; sam ::: CSO N CSI :;:; CS2 0: BAUDOm v: XTAll ;: XTAl2 =:; DOSTR$ DOSTR~ ""C~1:!:=======:::!T' oo~ ol~ D1~ OJ- 04- 05_ 06- Read/Write (R/W) - Determines whether the controller's internal register file is to be written to or read from. A write is a logic zero. Pin 22. CRT AND D1SPLA Y MEMORY CONTROL 20, Data Terminal Ready tOTR). 8. Received Line Signal Detector In (RLSD). 7. Signal ground. 6. Uata Set Ready (DSRI· 4. Request To Send IRTS). 1. Protective or chassis ground. CRT Conlroller The heart of the video logic system is the CRT controller. This device generates all of the sync and blanking signals and display memory addresses for the video system, The memory control is used to select either the address coming from the CRT controller or the address bus. and to synchronize read and write pulses. The CRT controller. U417. is a fully programmable device that is set up by the ROM program during power-up. Its didirectional data bits (pins 33-26) connect to system data bits 00-D7. Its address or programming inputs come from the following four input pins: The 110 connector on the back panel of the Computer is a standard 2S·pin D-type plug with the data and signal line connected as follows: U454 isa standard EIA line receiver. The serial data in line drives the input of U454A, which converts the EIA voltages toTTL levels and drives the serial input of the ACE. Likewise, the RLSD, DSR, and CRS line signals drive the inputs of U4548, U454D. and U4S4C. respectively. The outputs drive the appropriate control inputs of the ACE. The characteristics of the ACE must be programmed into the internal registers of U452 by the ROM pro- gram through the address and data busses. Bidirec· lional data bils (pins 1-8) of U452 connect to Ihe system data bus. The address inputs (pins 28. 27. and 261 conncct 10 the system address bils AO, A1. and A'1.. When the ROM program addresses 110 port 40H (100Q), pin 13 of 110 decoder U44'1. selects the CS'1. input (pin 14) of the ACE. The Z8D can then read or write data by enabling the data input and data output strobes at pins '1.1 and 18 tDISTR and DOSTRI of U452. 2. Divides a master clock frequency by a pro· grammed divisor to generate II desired baud rale. 3. Programs Ihe data characteristics, parity, slop bits. and character length. 1. COllverts data from parallel to serial and vice versa. When the ACE receives a complete serial word from the E1A interface. it signals the Z80 thai there is data available by pulling the Z80 INT inputlpin 15) low. The Z80 then examines the internal status and data registers of the ACE. reads the data word. and routes it to the proper device within the Computer. I/O Drivers The standard EIA interface communicates by means of a serial stream of voltage levels that correspond to logic ones and zeros. A logic one (or mark) on the data lines is a voltage between -5 and -15 volts. A logic zero on the data lines is a voltage between +5 and +15 volts. On the control lines (DTR. RTS. RLSD. DSR, CTS). a voltage between +5 and +15 volts is considered to be ON. and a voltage between -5 and -15 volts is considered to be OFF. U453 is a standard EIA line driver. A logic one on the input ofU453C drives the serial data outline to an EIA logic one. or "mark," A zero on the input forces the line to an EIA zero, or "space." U4538 and U453D drive control lines DTR IData Terminal Ready) and RTS (Ready to Send) in a similar manner. Refer to the (ACE) Block Diagram (fold-out from this page) as you read this circuit description. U451 is an Asynchronous Communications Element Ihal performs the following functions: ACE/UART o o o

Selects either the address register (RS =0) or one of the data registers (RS~1) of the inter- nal register file. Chip Select (CS) - A zero sets the CRT controller to read or write the internal memory file. Enable (E) - Enables the I/O buffers and clocks data to and from the CRT controller. Data is clocked on the falling edge of the enable signal. The next CPU clock pulse at pin 11 of U4188 clocks the logic one at the data input through to the Q output. This delays the leading edge of the enable pulse until approximately one clock cycle after the leading edge of the CS pulse. When the I/O request at address 140 goes away (returns to logic one), the output of U412C immediately clears U4188. U4188's Q output (pin 9) drives the E input of the CRT controller to zero. The clear input of U418A goes high at the same time, but the Q output remains low until the next CPU clock pulse at U418A's clock (pin 3) clocks the logic one at the data input through to the output, terminating the CS. This delays the trailing edge of the CS pulse until after the trailing edge of the E pulse. • The internal registers are written to or from by means of the address register. The Z80 sets up the pro- grammable registers by first writing a register number into the address register when the register select input is low. It then performs a write operation when the register select input goes high. Each of the CRT controller's registers is programmed at power-up with appropriate data to generate the SYNC, timing, and refresh signals. The memory address outputs (MAO-MAlO) drive the address inputs of the display RAM through multiplexers U414, U415,and U416. The scan row address outputs (RAO-RA3) drive the address inputs of character generator U420. The display enable output (DISPLA Y) is a logic one whenever the CRT controller, U417, is addressing a port of the RAM during the time it should be displayed. This serves as a blanking output whenever it is a logic zero. The cursor output goes to a logic one when the RAM location being addressed is equal to the address stored in the cursor address registers. Controller Read/Write Logic The CS and E inputs of the CRT controller must be selected in a particular sequence to perform read and write operations to and from the controller. The ena- ble input pulse (pin 23) must always be inside the CS pulse. When the I/O request for address 140 appears at pin 12 of U442, the clear input of U418A goes low, and the Q output immediately drives the CS input low. The Q output drives the data input of U4188 to a logic one. At the same time, U412C puts the Clear input of U4188 at a logic one. Display Memory Control The display memory control consists of an address bus multiplexer, a bidirectional bus buffer, and some gates that control the display memory write enable (WE) and chip select (CS) inputs. The address bus multiplexer consists of quad 2-input multiplexers U414, U415, and U416. Their select in- puts are tied together and controlled by memory de- coder U435. When no read or write operations are being performed on the display' memory, the select inputs are at a logic one, and the memory addresses (MAO-MA9) generated by the CRT controller drive the address inputs (AO-A9) of RAMs U408-U411. Memory address MAlO, generated by the CRT con- troller, is used to select either the upper or the lower lK bank of video RAM. When the Z80 addresses the memory, pin 9 of U435 pulls the select input to a logic zero, CRT controller memory addresses MAO-MA9 are disconnected from the display RAM, and address bus bits AO-A9 are connected to the RAM address inputs. The Z80 can then read from or write into the display RAM. 8us buffer U407 isolates the main data bus from the secondary or refresh bus. During the screen refresh period, the data outputs of the display RAM drive the data inputs of the character generator continuously. This would prevent the processor from having access to the bus except during retrace times. However, by isolating the refresh bus from the main bus, the Z80 can have continuous access to the main bus, and the display RAM and character generator can have con- tinuous access to the secondary bus (refresh bus). When the Z80 needs access to the display RAM, it addresses the memory, which enables U407 through pin 9 of U435, and connects the main bus directly to the secondary bus. •

display RAMs. During the screen refresh cycle, pin 11 ofU414 is driven by Al0 and pins 1 and 4 of U412 are logic one. The output of U412A provides the CS for RAMs U408 and U409 and drives input pin 5 of U412B. The output ofU412B is the complement of the CS signal and it drives the CS input of RAMs U410 and U411. During a display RAM read or write cycle, pins 1 and 4 of U412 are driven by the RD + WR signal coming (indirectly) from pin 3 of U434A. This elimi- nates the possibility of a contention problem on the secondary (refresh) bus between the display RAMs and buffer U407. The write (WE) inputs of the RAMs are connected together and they are controlled by U413C. The WE (pin 8 ofU413C) cannot go low unless pin 9 ofU435 is low (memory is selected), the signal is delayed slightly to avoid a timing race with memory selection, and the Z80 WR output is low. DISPLAY MEMORY, CHARACTER GENERATOR, AND VIDEO CONTROL LOGIC This section of the terminal logic circuit board essentially runs by itself (in conjunction with the CRT controller) after being programmed by the Z80. The CRT controller continually provides refresh addresses for the display RAM, while the output of the RAM continually provides data for the character generator and the video shift register. Character Generator Character generator U420 is a 2048 x 8 (16384 bit) read only memory (ROM) that converts the ASCII data stored in the display memory into d.ot information for the video shift register. Address inputs Ao-A3 (pins 5-8) are driven by the.scan row address outputs of the CRT controller (RAO-RA3) to select a particular row of dots within a character space. Address inputs A4-Al0 connect to the secondary data bus through 8-bit latch U419. These inputs use ASCII data to address the dot data stored in the ROM. The data outputs (01-08) of U420 supply video dot data to the parallel inputs of video shift register U421. The inputs of 8-bit latch U419 connect to the secondary data bus. Data bits DO-D6 are latched into U419A-G and drive the character generator. Data bit D7 is the reverse video bit. It is latched in U419H and drives an input of U423A. Video shift register U421 latches parallel dot data from the character generator at inputs A-H and shifts it out of output On in synchronism with the dot clock (the dot clock drives the clock input, pin 7). The shift register is loaded (the dot data is latched) on a positive-going transition of the dot clock while the shift/load input is held lowbythe ripple carry coming from pin 12 of U426F. The dot data atinput H appears immediately at output On. The next leading edge of the dot clock shifts the data that was latched at QG' The next edge of the dot clock will shift the data that was latched in OF, and so on. After the data from Ott is shifted to the On output, the load input goes low, and the next character cycle begins. Video Control Logic The video control logic consists of two sections: a series, or chain, of gates and latches associated with video cursor, and reverse video data; and a chain of gates and latches associated with blanking data. The display enable (blanking) and cursor data from pins 18 and 19 of the CRT controller is coincident with MAO-MAlO, which address the display RAM. The display enable bit is latched in U424F (after passing through AND gate U423C) by the complemented character clock pulse coming from pin 11 of U412D. The cursor bit is latched in U424F. This delays the two signals by one character time. They are delayed for one more character time by being latched in U424E and U424G, respectively. The two character delays are necessary to compensate for the delays in the display RAM/character generator "pipeline." When MAO-MAlO address the RAM, it takes approximately 450 nS for the data to be valid at the outputs. Once it settles down, the next character clock latches it in U419. The data at the output of U419 then addresses character generator U420. The data at the output takes another 450 nS to settle, and it is latched in the shift register by the following clock pulse. (Since the character clock pulses are 650 nS apart, the RAM and character generator outputs have plenty of time to settle.) This two-character delay matches the delays for the cursor and display enable, so that everything is synchronized. The reverse video bit (D7) in the display RAM is latched first in U419, and then in U424H (after passing through AND gate U423A), so that it too arrives coincident with the video, blanking, and

shift register U421 and the cursor data coming from pin 16 of U424G are exclusive-ORed in U425A. This causes the cursor dots to reverse when the cursor happens to be coincident with video information, and keeps the cursor from disappearing when it occupies the same space as a character. The video/cursor information coming from pin 3 of U425A is then exclusive-ORed in U425B with the reverse video data coming from pin 19 of U424H. When pin 19 is logic zero, the video/cursor data passes through U425B just as it is entered. If pin 19 of U424H is logic one, the data is reversed, and the character appears on the screen as black dots on a white background. The reverse video function can be disabled under the control of the ROM program when a logic zero is written into latch U422B via the address bus. Address bit A3 drives the data input of U422D, and its clock input is clocked when the CRT controller is addressed (I/O address 140). If the reverse video is to be ignored, the Q output (pin 9) of U422B puts pin 1 of AND gate U423A at a logic 0 and disables the reverse video bit coming from pin 19 of latch U424H. The video/cursor/reverse data coming from pin 6 of U425B is ANDed in U423D with the display enable data coming from pin 12 of U424E. If the display enable is logic 1, the video data goes to the video circuit board; if it is a logic zero, the video is blanked. When the Z80 performs a read or write operation on the display RAM, it disturbs the pipeline, and the data on the secondary (refresh) bus does not coincide with what should be written on the screen. Consequently, the video is blanked during a read or write. When pin 9 of memory decoder U435 goes low to select the display RAM, it also drives the clear input (pin 1) of U424. The Q output (pin 6) of U424C drives pin 9 of AND gate U423C to a logic zero and disables the display enable. At the same time, the Q output (pin 12) of U424E drives pin 12 of AND gate U423D to a logic zero, blanking the video information coming from the video chain. The screen will blank as long as the RAM is selected. When pin 9 of U435 goes high to deselect the RAM, U424 is no longer held cleared. The logic one at the D input of U424C is clocked through to its Q output on the next character clock pulse, and it is clocked through U424D and U424E on the next two pulses. This three-character delay gives the pipeline time to reload with valid information before the video is ena- bled. The propagation delays through the various gates and latches (U421, U425A, U425B, and U424) from the edge of the character and dot clocks to their various outputs is not always constant, so another delay is used. Latch U422A acts as a mini-pipeline, clocked at the dot rate. The data input to U422A is the composite video/cursor/reverse/blanking data, and its T input is clocked by the dot clock. This 80 nS delay lets all data settle to valid states before it is sent to the video circuit board. The sync and video signals are buffered before they leave the terminal logic circuit board. U406A inverts and buffers the video data. U406C inverts and buffers the vertical sync signal coming from pin 40 of the CRT controller. U406D buffers the horizontal sync signal coming from pin 39 of the CRT controller.

Refer 10 the Schematic Diagram [pari 3 of 3). and the Block Diagram (fold-out from Page 5-21) as you read Ihe CPU logic circuit description. begins to charge. Approximately lS0 mS after the +S V source reaches +S volts. pin 6 of US088 goes low and pin 8 of US010 goes high and terminates the power-up reset operation. 0'- ,.., '01 '"r• I"'" ....." ..... 'I'" ~ .... ~<"""'~ L:.. "..," ,"" ... .." oU' ".. ~ ",. " ..< ,." ~ ,.,r ,." f- -.." :,1- om ,,,. ".." IL""" .", co,'" '--- ..- ".. "" ~ ~ "" '--- '--- ~ '--- '--- .,,, '--- US08A and US080 form an R-S flip-flop which guarantees that a keyboard reset will occur only during the op code fetch portion of an M1 cycle. Therefore. the refresh for dynamic memories will not be disturbed and no information will be lost. As long as the reset and shift keys are held down on the keyboard, pin 3 of US06A is held low and the display electronics are continuously reset. However. the Computer is not reset until the keys are released. This insures that the display will complete its reset function before the Computer resets: thus resulting in a proper indication on the display. The rising edge of the K8RST L signal toggles US06A and causes its Q output (pin S) to go high. This signal is coupled to a SO IJ.S one-shot tUS07 A) by US08A. and is the trigger signal for the one-shot. US07A's output is the reset signal used by the Computer and is coupled to the Computer by Us088 and US010. When power is first applied. capacitor CS07 is dis- charged. As the +S V source becomes active. CS07 Crystal X501, in conjunction with U501A, forms a cryslal oscillator which operates at 12.288 MHz. Capacitors CS01 and C503 provide the load for the crystal, while RSOl and RS02 force US01A 10 operate in its linear mode. CS02 aels as a low-pass filler 10 insure that Ihe crystal will determine Ihe operating frequency of the circuit rather than the delay time of US01A. SYSTEM CLOCK POWER-UP AND RESET U502 operates both as a divide-by-6 scaler. resulting in a 2.048 MHz clock signal. and as a divide-by-two scaler acting on the 2.048 MHz signal to provide U503'5 clock. U503 operates as a divide·by-1024 scaler and provides the 2 mS clock signal. o TERMINAL LOGIC AND VIDEO CIRCUITS BLOCK DIAGRAM o

• The CPU is a Z80 microprocessor which runs at 2.048 MHz. Figure 5-1 shows the timing during an M1 cycle (instruction fetch). Notice that signal Ml occurs prior to the refresh signal during the instruction fetch. AO-AI5 MI CYCLE 11 12 I) 14 1I -'~~~~ ~ II PC I REFRESH ADDR. \ I \ \ I - ----- --.r--l_ ----- ----- ------ _. - ~----- ----- ----- ----- - - h I \.._---- -- JTN ~ , \ I • Figure 5-1 Figure 5-2 shows the timing of a memory read and memory write cycle. MEMORY READ CYCLE MEMORY WRITE CYCLE 1I 12 I) 11 12 I) ~ ~ r---'\ ~~r-""\ - - II MEMORY ADDR. MEMORY ADDR. \ I \ I \ I \ I IN DAIA OUI I-- - ---- T\.-- - - -- - - -- r-Jl:..--"f----- -- - -- -- ~ -- -- -- - --- f----- -- DAIA BUS tOO-on WA 11 AO-AI5 Figure 5-2

IWRITE \ CYCLE I REA D \CYCLE TI T2 TW T3 TI - r---L-r-L-r-L-r---L-r--L II PORT ADDRESS I \ I \ I IN - ----- ----- :J'C.= 10----- ---- - - - --- ---- - - - --- ---- \ I OUT DATA BU::. DATA BUS AO - A7 Figure 5-3 Figure 5-4 occurs only at the end of an instruction cycle that both an Ml and an IORQ are generated. LAS --- T M CY CLE MI OF INSTRUCTION LA ST T TI T2 TW TW T3 ST ATE - ~~~r---L-~r---L-rt- - ___ :.LLL---- ------ ----- 1----- ----- ----- - --- -- ----- ----- ----- ----- ----- I PC IREFRESH \ I \ I '-TIl''' ~~ - ----- ---- ---- ~--------- -T\.------ - ---- - --- ----1----- ----- - -- ---- DATA BUS AQ-AI5 o RD Figure 5-4

plements BMI L to produce BMI H. USlSA OR's the I/O request and memory request signals to produce the latch address signal (LA L). US62A and US62B form a 100 nS delay for the memory request signal; thus DMERQ L is the delayed memory request. This delay occurs only on the leading edge and not the trailing edge of the signal. ADDRESS LATCH USI0 and US11 are transparent latches. Any data at their inputs is transferred to their outputs when LA L is high. When LA L is low, the last data pattern to occur just before the LA L high-to-Iow transition is retained at their outputs. MEMORY MAP DECODER US17 and US16 are PROMs which decode the latched address lines and determine which memory chips are to be enabled. Specifically, US17 determines which of the eight 8K banks is to be enabled, and US16 deter- mines which of the lK pages within bank 0 is to be enabled. However, the address lines are not the only criteria used to determine memory selection. Jumpers JJSOl, JJS02, and JJS03 select various memory configurations. That is, if only 48K of user RAM is installed, then JJSOI is jumpered for "0," JJS02 is jumpered for "1," and JJS03 is jumpered for "B." As a result, RASO L, RASI L, or RAS2 L, will be selected (coincident with the selected address being within banks 1 and 2, 3 and 4, or Sand 6). In addition, NOMEM L will be asserted low whenever bank 7 is accessed. This results in US21 being enabled and all O's being forced onto the data bus (required by some software memory sizing routines). If ,however, 64K of user memory is installed, J]SOl and J]S02 will be jum- pered for "1," and J]S03 is again a "B." Now, when bank 7 is addressed, RAS3 L will be asserted instead of NOMEM 1. Access to 64K of RAM requires setting the CP/M ORG 0 latch in the software to configure bank 0 as RAM. The write enable line (WE L) will be asserted low whenever there is no read (BRD L is high), no refresh (BRSH L is high), memory is selected (DMERQ L is low), and the bank selected contains writeable memory. Thus, since NOMEM L contains no writeable memory, WE L cannot be asserted if NOMEM L is asserted. However, bank 0 contains both writeable and non-writeable memory. Therefore, WE L will be asserted for bank 0 if the first three conditions are met regardless of the fourth condition. It is up to US16 to either enable or not enable the page select lines (MCSOOI L, MCS023 L, MCSOS L, and MCS067 L), depending on whether the memory addressed is writeable or not. Write enable line 0 (WE 0 L) is used with the lK of RAM associated with the floppy disk. It is only asserted when WE L is asserted, MCsOS L is asserted, and FMWEN H is asserted. It is controlled by bit 7 of I/O port 177. Ifthe refresh line (BRFSH L) is asserted low, then WE L is not asserted. In addition, RASO L, RASI L, and RAS2 L will be asserted (consistent with the position of jumpers JJSOl, J]S02, and J]S03) regardless of the bank address. This insures that all applicablt;J dynamic RAM will be refreshed. DYNANIC RAM MULTIPLEXER US13 and US14 multiplex the 14 address lines required for 16K of memory into the 7 lines available on the memory chips. US12A is used to clock the row and column addresses into the memory chips in the proper sequence and at the proper time. A~su~ethat a memory cycle has just begun (DMERQ H IS hIgh). At this time, the row addresses are multiplexed onto the memory address lines (AO-6 L) and the applicable RAS line (RASO-2 L) is asserted low; thus, latching the row address into the memory chips. One half clock cycle later, US12A is toggled. This causes the row addresses to be removed from the memory address lines (AO-6 L) and the column addresses (A7-13) to be multiplexed in. A short delay later (determined by RS14 and CS22), the CAS L line is asserted and the column address is latched into the memory.

(RAS address selected) when either a refresh cycle is initiated (clears U512A) or after the first clock cycle following the memory cycle (DMERQ H is low, causing the Q output of U512A to go low). SYSTEM ROM U518 is the system ROM which resides in the bottom 2 pages of memory (0, 1). An additional 2K of ROM can be added to the system at Pages 2 and 3 by installing jumper JJ507 at "A." Jumpers JJ504, JJ505, and JJ506 are used to switch between the 3-voltage EPROMs and the single voltage ROMs. When the jumpers are installed in their 0 locations, then the 3-voltage EPROMs are used. FLOPPY DISK ROM U520 is the floppy disk ROM which resides in the address map at Pages 6 and 7. It is restricted to a single voltage ROM. However, by moving jumper JJ507 to "B," U519 will serve as the floppy ROM and a 3-voltage EPROM can be installed. It is now no longer possible to use 4K of system ROM. FLOPPY DISK RAM U523 and U525 are used by the floppy disk and reside in Page 5 of bank 0 of the memory map. They are organized as 1K x 4 static RAMs. Provisions are made for an additional 1K of static memory at Page 4. How- ever, it cannot be write protected as the memory at Page 5 can. SYSTEM RAM The system RAM is organized as 16K x 1 dynamic RAMs and resides in banks 1, 2, 3, 4, 5, 6, and 7. U526 through U533 comprise banks 1 and 2, U534 through U541 comprise banks 3 and 4, and U542 through U549 comprise banks 5 and 6. Bank 7 is accessible when the memory expansion board is installed and JJ501 through JJ503 are properly positioned. INTERRUPT LOGIC U557 detects that an interrupt request has occurred. It transmits this information to the processor by the INT L line. The interrupt priority is also determined by U557, and is available on output pins 6,7, and 9. This information is transmitted to the data bus during the interrupt acknowledge cycle by U558. The highest priority is interrupt level 5, while the lowest priority is the 2 mS clock at level 1. In process- ing the interrupt, the CPU is operating in the 8080 mode. Therefore, the data on the data bus at acknow- ledge time is an instruction (U558 encodes the data from priority encoder U557 such that the processor sees a restart instruction). This instruction directs the processor to execute the instruction at ROM address 10 for the 2 mS clock, at address 20 for the single step, at address 30 for the INT 3L, etc. I/O MAP DECODER U550 is a 256 x 8 PROM, and decodes the various I/O ports required by the Computer. I/O F2H (362Q) is the general purpose port and I/O 362L is its enable signal. I/O NMI L is generated by the system whenever accesses to ports oFoH (360Q), OF1H (361Q), oFAH (372Q), oFBH (373Q) occur. Interrupt acknowledge is generated by the Z80 via a simultaneous M1 Land IORQ L. The BM1 L is used to deselect U550 and terminate the interrupt request. This enables the system to run software previously developed for the H-8 Computer. That is, accesses to the H-8 front panel are rerouted to the system console. Since the interrupt acknowledge generates a BIORQ L signal, this could cause an I/O request to I/O 362 or I/O NMI. The effect would be to either cancel the inter- rupt before it could be processed or to generate an NMI request. In either case, the Computer will get lost. Therefore, since the interrupt acknowledge also generates an M1 signal, M1 is used to deselect U550 during the interrupt acknowledge cycle.

The 2 mS clock is controlled by U506B. It is enabled by writing a "1" on data line Dl H at I/O port OF2H (362Q). Once enabled, the next positive transition of the 2 mS clock will trigger U506B and cause its output (pin 8) to go low; thus enabling interrupt level 1. The clock handler must, as part of its routine, disable the clock interrupt (clear U506). Otherwise, another in- terrupt will be generated as soon as an EI instruction is executed. This occurs because U506B is operating as a latch. It will be cleared whenever a write to I/O port OF2H (362Q) occurs. If Dl H is low when this write occurs, then the 2 mS clock will be disabled. If Dl H is high when the write occurs, then U506B will only be cleared and the 2 mS clock will still be ena- bled; thus allowing another interrupt to occur at the end ofthe next 2 mS period. At power-up or keyboard reset, U506B is enabled. Consequently, a 2 'mS clock interrupt will occur immediately after an EI instruc- tion has been executed. The single step is enabled by DO H and I/O port OF2H (362Q). With bit 0 of port OF2H (362Q) low, U555A and U555B are held in their initialized state. When bit o of port OF2H (362Q) is high, the single step is ena- bled. U556A synchronizes the 2.048 MHz clock with the Ml cycle and valid data on the data lines. U515B and U554 decode the EI instruction for U555A. Thus, an EI instruction causes the D input of U555A (pin 2) to be asserted low. U555A is then toggled by U556A: thus, setting the T input ofU555B (pin 11) low. At the end of the next Ml cycle, U555B is toggled, which latches its output (pin 0) low. Another Ml cycle is executed, which now toggles U556's output (pin 8) high. This generates the interrupt at level 2 (restart 2). The software sequence is: 1. Enable single step 2. Wait for keyboard 3. EI instruction 4. RTI instruction 5. Execute single program instruction 6. Interrupt out of program 7. Disable single step 8. Enable single step (steps 7 and 8 are re- quired to reinitialize single step logic) 9. Wait for keyboard 10. Etc. GENERAL PURPOSE PORT The general purpose port is located at I/O address OF2H (362Q), and is comprised of U551, U552, U553B, and switch SW501. A read from this port puts the DIP switch (SW501) status on the data lines. A write to this port controls the single step and 2 mS interrupt logic. In addition, 4 other lines (MEMO H, MEMl H, 100 H, and 101 H) are available. These lines are routed to the accessory connectors on the CPU logic circuit board and are not presently used. BANK SEL H controls the selection of bank 7 on the 16K memory expansion board. CONSOLE SERIAL PORT This port, at I/O locations OEOH-OE7H [350Q-357Q), is used to communicate with the console terminal. U559 and U560 convert the TTL levels from and to the ACE (U561) into standard EIA signals. U515D acts only as an inverter for the reset line, and Ql provides both inversion and the WIRED-OR function for inter- rupt level 3 (restart 3). The clock for the ACE is supplied by logic inside U561, and is crystal controlled by X502. C525 and C526 provide the load for the crystal, and R515 and R516 provide the proper bias for the internal devices. The clock thus generated is routed to the I/O acces- sory connectors (through buffer U564D) for use by the Serial Interface Accessory circuit board.

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into the receptacle, and the proper voltage is present. • Check and verify that all switches and jum- pers are in the correct positions for the equipment being used. • With the Computer on, verify the presence of high voltage by checking the CRT fila- ment. • With the Computer in the OFF LINE mode, type some letters on the upper and lower portion of the screen to verify the proper character generation. • Hard reset the Computer by depressing the right shift key and reset key simultaneously. This will cause the MTR prompt (H:) to ap- pear in the upper left-hand corner of the screen. • Verify the communication in and out of the ACE port on the terminal logic board by placing a jumper wire between pins 3 and 5 on J404 of the terminal logic board. • Hard reset the Computer; the MTR prompt (H:) will appear. • Check Dynamic RAM Test with MTR-90 by typing the letter (T). • Check Dynamic RAM Test with MTR-89 by typing the letter (G) or (g). The Computer will respond with the word Go. • Type 7375 followed by the RETURN key. The Computer will execute the Dynamic RAM Test which takes about ten minutes. If no failures are detected, the CPU, RAM memory, and the decoders are operational. If an error is detected, it will be printed on the screen. Refer to memory testing on Page 6-11. • Hard reset the Computer. Insert a blank disk into the on-board drive. • Check the disk rotational speed by typing the letter (G) or (g). The Computer will respond with Go. Then type 7372, followed by the RETURN key. The output on the CRT will be a number in Base 8 (octal) ranging from 177-201. The optimum reading should be at 200 (octal).

may need to make to properly maintain your Compu- ter. You will have to remove or tilt back the cabinet top in order to reach the controls, coils, and adjust- ments called for in this section. On the terminal logic circuit board set section 2 of switch S402 down to its 1 position. This enables the wraparound. See Figure 6-1. NOTE: When power is turned on, do not touch the flyback transformer, the high voltage lead, or the anode socket at the back of the CRT, as it is possible to receive an electrical shock from these areas. Also, to lessen the chances of an electrical shock while you are making adjustments, keep your other hand away from this unit and all other metallic objects. Plug in the line cord and set the POWER switch to ON. After a short warm-up time, a light raster should ap- pear on the screen. If it does not, adjust Gl control R262 counterclockwise (as viewed from the left side), to cause the raster to appear. If the display is slanted, loosen the yoke clamp screw slightly and slowly turn the yoke to properly line up the raster on the screen. See Figure 6-2 on Page 6-3. Adjust VERT SIZE control R219 (on the video circuit board) so the raster is approximately 6" high. -- ~ ~ It:=~=-===::JJ [~J ~ --::----------flofrll--+t1IIIf------- 1+1 -Itl-~- fi\WIDTH oCr.l2OJ J -r.> 'I .r--~ I :::\.--~ FOCUSl,t R264 "_~J- r- --, , ' I "1';110 --~ I:~ ,, ,&; ~,: l~', HORIZ A t1,\ CENTER ING ~ \9. R246 Figure 6-1 Video deflection circuit board. -c:::..1- ,1, r.~ ::~"" y "" :: '" IT VERT SIZE R219 v

FIgure 6-2 CRT-yoke. Refer to Figure 6-2 and rotate the ring magnets on the back of the yoke to center the display on the screen. Adjust rear panel BRIGHTNESS control R1 until a blinking cursor (underline) appears at the top corner of the screen. Set the OFF LINE and CAPS LOCK keys to their down positions. Hold the "Z" key and the REPEAT key down and fill the screen with characters. Adjust HORIZ CENTERING control R246 to center the display horizontally within the raster. Adjust VERT LINEARITY control R223 so that the top and bottom rows of characters are of uniform size. NOTE: You should make the next adjustment in a darkened room. Turn G1 control R262 clockwise (as viewed from the left) until the raster just disappears. If the display width is not approximately 8-1/2", ad- just WIDTH coil L203 to correct the width size. Adjust BRIGHTNESS control R1 to obtain the brightness that is most suitable to you. Adjust FOCUS control R264 for the best focus. Recheck the display for proper alignment of the screen. If necessary, rotate the yoke a small amount. Then tighten the yoke clamp screw only enough to hold the yoke from turning. Set the POWER switch to OFF and disconnect the line cord. Set section 2 of switch S402 (on the terminal logic circuit board) up to its 0 position. Resecure all parts in your Computer and replace the cabinet top.

For the switch locations refer to Figure 6-3 . ." : , , UU .....,. .. - + ....-..- o 5402 ~n~~a~~~aBJ 1 i01234567 (ON) _ ._--_._--.... _---., ~-;:: :-:-, ',J .. ,..._..•. ~ ..••._....•.i , ..;.-._.~ .,": .- __ __ J . ,"'" _-.-._., . . •......-._-, .•- . ----~------_._-----_.._. __ ... ,~- ~ .. ,- - _.. -.--. ... _'_ .. _,_ .._--_.. _._-_._._--~----_ . •;' : ' . 1- --------- J ! I J L_...: , 0 540 I . Jf][1BBQQ~BB~:,L 101234567 :,-, .--------- - ---(ON)- ------------------, "j! .: - .,..•..._---•........._,-_.. _.. -_.,-_.~ Figure 6-3 Terminal logic board.

1 o = key click; 1 = no key click 2 o = discard past end of line; 1 = wrap around 3 o = no auto LF on CR; 1 = auto LF on CR 4 o = no auto CR on LF; 1 = auto CR on LF 5 o = ZDS mode; 1 = ANSI mode 6 o = keypad normal; 1 = keypad shifted 7 o = 60 Hz refresh; 1 = 50 Hz refresh SWITCHS401 SWITCH SECTION DESCRIPTION 0-3 Baud Rate 4 Parity Enable 5 Odd/Even Parity 6 Normal/Stick Parity 7 Half/Full Duplex MODE SWITCH SECTION 0 1 2 3 4 5 6 7 9600 Baud 0 0 1 1 No Parity 0 Odd Parity 0 Normal Parity 0 Full Duplex 1 BAUD SWITCH SECTION RATE 0 1 2 3 N/A 0 0 0 0 110 1 0 0 0 150 0 1 0 0 300 1 1 0 0 600 0 0 1 0 1200 1 0 1 0 1800 0 1 1 0 2000 1 1 1 0 2400 0 0 0 1 3600 1 0 0 1 4800 0 1 0 1 7200 1 1 0 1 9600 0 0 1 1 19200* 1 0 1 1 *Not currently supported (may drop characters)

Switch SW501 The functions that switch SW501 selects are determined by integrated circuit U518. See Figure 6-4. SW501 switch sections as directed in the next two steps. Then proceed directly to "Programming Jumpers." See Figure 6-4. 5-1/4/1 HARD-SECTORED FLOPPY USAGE When you use a 5-1/4/1 hard-sectored floppy disk, integrated circuit part numbers HE 444-40, HE 444-62, or HE 444-84 must be installed at U518. Set Set SW501 section 5 to "1." Set the remaining seven SW501 sections to "0." ., [ oj [ nODOOOO L--__~J"'T' ~..,..,..,..,.== JJ505 I~ a'jJ506 ~j L..-I_---'L-.-_-' '~J:=Jo4 ~I BJUB~J_J_50_7__--, Figure 6-4 CPU board.

When you use an 8" floppy disk (Z-47), integrated circuit part numbers HE 444-62 or HE 444-84 must be installed at USI8. • When you boot up from a S-I/4" hard-sectored floppy disk to enable your 8" floppy disk, set SWSDI switch sections as directed in the next two steps. Then proceed directly to "Programming Jumpers." See Figure 6-4. Set SWSDI switch sections 2 and S to "1." Set the remaining six SWSDI sections to "D." • When you boot up from the left-hand 8/1 floppy disk drive, set SWSDI switch sections as directed in the next two steps. Then proceed directly to "Programming Jumpers." Set SWSDI switch sections 2, 4, and S to "1." Set the remaining five SWSDI switch sections to "D." 8/1 FLOPPY DISK (Z-67) USAGE There are four ways of installing the Interface Board. How you install yours depends on what equipment you already have. If you have: 1. A Z-89-37 Double-Density Controller, you must install your Interface Board as shown in Figure 6-S on Page 6-8. Switch SWSDI on the CPU Board must be set as shown in inset drawing #1. The jumpers on the Interface Board must be set as shown in inset drawing #2. 2. An 8-88-1 Disk Controller, you must install your Z-89-67 Interface Board as shown in Figure 6-6 on Page 6-9. Set switch SWSDI as shown in inset drawing #1, and the jumpers as shown in inset drawing #2. 3. A Z-89-47 Interface Board, you must install your Z-89-67 Interface Board as shown in Figure 6-7 on Page 6-1D. Set switch SWSDI as shown in inset drawing #1, and the jumpers as shown in inset drawing #2. 4. None ofthe Above, install your Interface Board as shown in Figure 6-8 on Page 6-11. Set switch SWSDI as shown in inset drawing #1, and the jumpers as shown in inset drawing #2. You may set the DIP switches on the Interface Board in any position when you are using Zenith software.

.. .. DO NOT MOVE : a:j.:HE~.J ..UMPER: • ·cto .0 o • ~tiPUOO' --------------~.t-o-._ JUMPER THESE WHEN USING P506 AND P512 • • • • n ~~ ~ ~~ o 0 9- 0 0 ~ ~~ 0'_"-37 SERIAL '-89-67 HERE BOARD ERE HERE - f- Figure 6-5

• • • O • DO NOT MOVE ~THESE JUMPERS :!?,o ~cW000. . 0 _ _ ' ..J ·-----~*t- ..... JUMPER THESE WHEN US (NG P504 AND P5!O ~ --INSET #2 -- __~ , . i I__.J !V I LJ ;-=SI I I Z-89-67 1=1-- H-88-! J HERE SERIAL HERE -I BOARD -e:. HERE ra- n'l.; I LJ t~~~De~~~ I I I ~ I ULJ -e::J- L.J M j 1 18-1 DOWN FOR H-88-! BOOT (H-88-! PR (MARY) I UP FOR Z -67 BOOT IZ-67 PRIMARY) LJ SWITCH SW501 Figure f)·6

°51E~::_ c~~DDD· _:r-~---------- ---.\.1----.. JUMPER THESE WHEN USING P5D6 AND P512 JUMPERS ON Z-89-67 BOARD

~ "'- SWITCH SW501 JUMPERS ON Z-89-67 BOARD • • -. • DO NOT MOVE D~THESE JUMPERS :f~oo liJ;leJpOOO·C o;r-"----" ...J - ...........---------\..1---- JUMPER THESE WHEN USING P506 AND P512 I -- -.!iQ.~-- Z-89-67 HERE LJ HERE) nrBl ~U ~ r~ I LJ U ~ Figure 6-8

Z-89-47 For a system to operate properly with the Z-B9-3 7, the Z-B9-47 I/O Board should be installed at plugs P506 and P512. However, before the Z-B9-47 will operate properly when plugged into plugs P506 and P512, a resistor must be added to the Z-B9-47 circuit board. To make the modification, use a 4700 n,1/4-watt resistor, HE 6-472 (yellow-violet-red), slide a length of sleeving over the resistor, and solder the resistor between pins 1 and 12 of plug P2 on the foil side (not the component side) of the Z-B9-47 circuit board. Refer to Figure 6-9 . Figure 6-9 Set the 170/174 programming plug to 174. Install the Z-B9-47 board at plugs P506 and P512. NOTE: If you ever move this board to another set of plugs, be sure to remove the 4700 n resistor that you just installed. [ H-88-1 FLOPPY DISK 1/0 CiRCUIT 80ARD

following information. Use the following information for any special configurations that you may want. We recommend that you do not use both 48 and 96 TPI drives in the same system, since the precompensation will be wrong for at least one of the drives. This can result in reduced data reliability. When precompensa- tion is selected, it is factory pre-set to 300 nanoseconds. Programming modules: Jl & J2 J3 Select port 170 or 174. (Both jumpers must be at 170, or both jumpers must be at 174. 170 is normal.) 1 = No precompensation; a = pre- compensation. (1 position is normal.) Use "a" if any of your drives are 48 TPI Wangco Model 82 (HE 150-71) drives. Otherwise, use "1." J4 - J7 Selects which drive is connected to plug P3. (Drive numbers are deter- mined by how the drive program- ming modules are cut. See Figure 6-10.) J4 = DSI J5 = DS2 J6 = DS3 J7 = DS4 (presently not supported)

Refer to the following chart and Figure 6-11, and select the configuration that fits your situation. Con- figuration E is normally used for transferring data and programs from hard-sectored disks to soft-sectored disks. DRIVE ~ After you select the configuration you want, refer to Figure 6-12 on Page 6-16 to program any 48 TPI (H-17-1) drives, or Figure 6-13 on Page 6-17 to program any 96 TPI drives. [Figure 6-14 on Page 6-18 shows single-sided drives (H-17-1) programmed for connection to an H-88-1 Controller.] You can do this programming by physically interchanging the programming modules, cutting the programming modules (if presently uncut); or by replacing the programming module with a properly set dip switch. DRIVE DRIVE L r:=J~ 1 2 ~ EEEI u LI Figure 6-11 TYPES OF DRIVES: FLOPPY DISK • 48 TPI (H-17-1) CONTROLLER BOARD(S) • 96 TPI (H-17-4) Drive 0 Drive 1 Drive 2 A H-88-1 48 TPI (H-17-1) only. DS3 DS2 DS1 Internal drive present B H-88-1 48 TPI (H-17-1) No drive installed DS3 DS2 Internal drive absent C Z-89-37 Either* OS1 (Z-89-37 DS2 DS3 Internal drive present jumper installed at J4) 0 Z-89-37 Either* No drive installed DS1 DS2 Internal drive absent (Z-89-37 jumper installed at J7) E H-88-1 ~ Z-89-37 Either* DS3 IDrive 0 is DS1 (Drive 0 connected DS2 (Drive connected Internal drive present 48 TPI (H-17-1) to Z-89-37) Z-89-37) drive connected to H-88·1. Z-89-37 jumper installed at J6.1 * All drives connected to the Z-89-37 should be of the same type, either 48 TPI (H-17-1) or 96 TPI (H-17-4).

L-/_~J PROGRAMM I NG MODULE u HARDWARE UNIT ONE (DS2) <-1__] ~ . [ I l:CJo'~ "".,... ............ ..J CLIT INSET B L ODD AMSsSH ~~X321S ~ PROGRAMM ING MODULE I 3 L~ ... .,..,.., ... ..,-. HARDWARE UNIT TWO (DS3) Figure 6-12 Single-sided drives (H-17-1) programmed for Z-89-37 Controller.

~ S ~.1-1-1-1-1-1-1 k ~1=-1-=1-1=-1-1=:J-J1 r:-~ _ I l;:;:,:T-l-l-'! PROGRAMMING MODULE Hardware Unit One (052) f1-1-1-HHJ~ 6"""'""1 1;:.==::::=:JI ,-1-1-1~ PROGRAMM ING MODULE PROGRAMM ING MOD ULE (1-'.1.'_1_1-~ .... ,-,.,.,-,-,., ~ S n 1-1-1-1-1-1-1-1 ~ Hardware Unit Two (053) L Figure lli·13 Double-sided drives (H-17-4) Z-89-37 C programmed for ontroller.

HARDWARE UNIT ONE HARDWARE UNIT TWO Figure 6-14 Single-sided drives (H-17-1) programmed for H-88-1 Controller.

When IC part number HE 444-Ei2 is installed at U518, the following table describes the functions of each SW501 switch section. (78H-7BH) is not in use (normal with Z-47, 8" has a 8" floppy disk (normal with Z-47). (7CH-7FH) has a 5-1/4" hard-sectored floppy disk has a Z-47, 8" floppy disk. ory test upon power-up or SHIFT-RESET. rm memory test (normal). ) 9600 baud (normal). ) 19200 baud (not currently supported). vice at port 174/177Q (7CH-7FH) (5-1/4" hard- y disk). vice at port 170/173Q (78H-7BH) (Z-47, 8" floppy normal). power-up or SHIFT-RESET (not recommended). SWITCH SETTING* I DESCRIPTION SECTIONS 1 and 0 00 Port 174/177Q (normal). 01 Port 174/177Q 10 Undefined. 11 Undefined. 3 and 2 00 Port 170/173Q floppy disk). 01 Port 170/173Q 10 Undefined. 11 Undefined. 4 0 Boots from de sectored flopp 1 Boots from de disk) 5 0 Performs mem 1 Does not perfo 6 0 Sets console t< 1 Sets console te 7 0 Normal boot ( 1 Auto boot on * Right-hand value is for switch section 0 or 2, depending on respective Switch Section column.

COMPUTER Definition of SW501 with MTR-90 (HE 444-84) When IC part number HE 444-84 is installed at U518, set the sections of SW501 as described in "Definition of SW501 with MTR-89," except for sections 0,1,2, and 3, which are defined as follows: SWITCH SECTIONS SETTING* DESCRIPTION 00 Port 174/1770 (7CH-7FH) is 5-1/4" hard-sectored floppy disk. 01 Port 174/1770 is Z-47, 8" floppy disk. 1 and 0 10 Port 174/1770 is Z-67, 8" hard disk. 11 Undefined. 00 Port 170/1730 (78H-7BH) is Z-37 soft-sectored disk. 01 Port 170/1730 is Z-47, 8" floppy disk. 3 and 2 10 Port 170/1730 is Z-67, 8" hard disk. 11 Undefined. ---- ---_..._--

The memory decode ROM is located at U517 on the CPU board. Two ROMs have been used. Part number HE 444-42 was originally used. This ROM precluded the use of more than 48K of memory or CP/M. It has been superseded in all production units by HE 444- 66, which allows the ROM based 48K mode, the ROM based 56K mode, and an all RAM 64K mode. All users should upgrade to this part regardless of configura- tion. There are no negative consequences connected with this upgrade. Associated with this ROM are three or four jumpers, JJ501 thru JJ504. Older CPU boards have all four jumpers; they should be set as follows: When using the Old ROM (HE 444-42) When using the New ROM (HE 444-66) JJ501 JJ502 JJ503 JJ504 16K 0 0 ** o(or B) 32K 1 0 ** o (or B) 48K 0 1 ** o (or B) 64K* 1 1 ** o (or B) Newer CPU boards (which only have three jumpers, JJ501 through JJ503) are supplied with the new de- code ROM (HE 444-66) already installed and the jumper wire incorporated directly into the PC board foil. These boards should not be used with the old ROM (HE 444-42). These jumpers should be set as follows: JJ501 JJ502 JJ503 JJ501 JJ502 JJ503 JJ504 16K 0 0 o (or B) 16K 0 0 0 o (or B) 32K 1 0 o(or B) 32K 1 0 0 o (or B) 48K 0 1 o (or B) 48K 0 1 0 o (or B) 64K* 1 1 o(or B) I \....,/ These are four jumper wires associated with the code ROM and the secondary address decoder. These are either JJ505, JJ506, JJ507 and JJ508 (on older units) or JJ504, JJ505, JJ506 and JJ507 (on newer units). These should be set as follows: Older Units: Newer Units: MTR-88, MTR-89 MTR-90 JJ505 JJ504 o JJ506 JJ505 o JJ507 JJ506 o JJ508 JJ507 1 (or B) 1 (or B) * Requires the WH-88-16 accessory PC board. * * A jumper is required between the center pin of JJ503 and pin 17 of P509, or P4 of WH-88-16 (which connects to pin 17 of P509). This jumper may have been soldered on the back of the CPU board during manufacture (for Z-89-FA and some other models), or it may be ordered as part number HE 131-1120 and installed by the user. Neither tools nor soldering are required.

This test will check the rotational speed of the floppy disk drive for the Z-89 and Z-90 Computers. After the test starts, it will display the disk drive speed test message and a "speed equals" message as follows: Disk drive rotational speed test Drive speed = The word "Working" will be flashed on and off at the horne position and a drive speed number (in octal), which should be as close to 200 as possible, will update with each flash on the screen. The rotational speed tolerance is one percent. The displayed value should be between 166 and 212 (remember, octal numbers jump from 177 to 200). Do not adjust the speed unless it is out of tolerance. Your drive unit has a control labeled R30 or R7 which is used to vary the drive speed. The location for this control for various drives is shown in Figure 6-15. This adjustment may be extremely sensitive so if an adjustment is necessary, do not turn it far in either direction. Less than one degree of rotation in either direction should bring the drive speed into tolerance. Turn the control clockwise to decreas~ the speed or counterclockwise to increase it. As the drive bearings wear, the speed may change slightly. Fluctuations within the tolerance are normal and may be attributed to variations in temperature and humidity. To begin the test, be sure the OFF LINE key is up (out). Then obtain the "H:" prompt. (Simultaneously push the right-hand SHIFT and RESET keys if necessary.) Type G7372'§. The total entry will be: H: Go 7372'§ and the test will start. Flol1rp 1':_1!;

using diagnostic programs rather than with test equipment. The system monitor has a built-in mem- ory test you can use to locate a faulty bit. This memory test is for the Z-89 and Z-90 Computers. The memory test uses the Z80 registers as its scratch pad and will check all user memory from 040000A on up to the top end of the supplied memory. You can start it either by setting section 5 of SW501 to its zero position and resetting the Computer, or by entering: H: Go 7375 § The Computer will then load OOOQ into each byte of memory, go back and compare each location to zero, increment each location until it again reaches the end of memory, and then repeat the operation. It will do this until every bit pattern from OOOQ to 377Q has been tested in every memory location. It will then go back to zero and start over. Due to the way the program is written, the first value to be displayed is as shown below (48K system): Dynamic RAM test LWA = 337377 Pass = 002 Depending on the amount of RAM installed, the last working address (LWA) will normally indicate one of the following three numbers: Amount of RAM LWA LWA Installed (Offset Octal) (Decimal) 16K 137377 24575 (24K-1) 32K 237377 40959 (40K-1) 48K 337377 57343 (56K-1) The Pass number indicates the data byte that the program is checking for. If the location being checked were not this value, then an error message similar to the following would occur: Dynamic RAM test LWA = 337377 Pass = 002 Error @ 040100 = 006 And the speaker will continuously beep. This indi- cates that the program expected to see a binary 00000010 at address 040100A, but got a binary 00000110 instead. In other words, data bit D2 is stuck to a logic one. You can determine which IC has failed by converting the Pass Number and Error Number from their octal form to binary form. Then locate the mismatch in the numbers as in the following example. Dynamic RAM test LWA = 337377 Pass = 002 Error = 006 D7D6DsD4D3D2D1Do 002 octal = 0 0 0 0 0 0 1 0 binary 006 octal = 0 0 0 0 0 1 1 0 binary Data bit D2is a mismatch. In this case the defective IC is in the top row (48K = top row, 32K = middle row, 16K = bottom row). Since LWA = 337377 is greater than 32K, its location is in the top row. D2 is the defective IC, so the third IC in the top row is defective.

address and faulty bit location to the IC causing the failure. Since the faulty bit was O2 at address 040100A, then U544 should be replaced. (Refer to the table below.] Note that the dynamic RAMs are laid out on the CPU board as shown in the table. Once you become famil- iar with this test, you should be able to locate most memory data failures without having to refer to the Schematic. MTR-89 48K LWA = 337.377 32K LWA = 237.377 16K LWA = 137.377 U549 U548 U547 U546 U545 U544 U543 U542 U541 U540 U539 U538 U537 U536 U535 U534 U533 U532 U531 U530 U529 U528 U527 U526 o. MTR-90 with 16K expansion O2 64K LWA = 337.377 48K LWA = 337.377 32K LWA = 237.377 16K LWA = 137.377 U5 U6 U4 U7 U3 U8 U2 U9 U548 U547 U546 U545 U544 U543 U542 U541 U540 U539 U538 U537 U536 U535 U534 - U533 U532 U531 U530 U529 U528 U527 U526 0 3 0, 0,

causes of several specific malfunctions. If a particular part is mentioned (Fl or example) as a possible cause, check that part and other components connected to that part to see that they are in good working order. WARNING: Measure the anode voltage only with an approved high voltage probe. CAUTION: Never operate the Computer unless the short black ground wire coming from the corner of the video board is connected to the CRT ground. 6-25

CONDITION POSSIBLE CAUSE Nothing happens at turn on. 1. Not plugged in. 2. Fuse Fl blown. 3. Switch SWl wiring. 4. Fuseholder wiring. 5. Capacitor C1. Fuse blows. 1. Check primary wiring. 2. Short circuit on power supply circuit board. 3. Short circuit across transformer secondary. 4. Diodes 0101-0112, and BR1. 5. Capacitors C1, C102·C104. 6. IC's U401-U405. 7. Short between collector of transistor 0204 and video board heat sink. 8. Incorrect fuse. 9. Power transformer n. No output from 5 V supplies, or voltage(s) too high or too low. 1. IC's U401, U402. 2. Diodes 0105·0107. 3. Capacitor C103. No +12 V, or is too high or too low. 1. IC U403. 2. Diodes 0101·0104. 3. Capacitor C102. No -12 V, or is too high or too low. 1. IC U404. 2. Diodes 0101-0104. 3. Capecitor C104. No -5 V, or is too high or too low. 1. IC U405. 2. IC U404 (-12 V source supplies -5 V regulator). 3. Diodes 0101·0104. 4. Capacitor C104. No +53 V, or is too high or too low. 1. Transistors 0201, 0202, 0204. 2. Diodes 0201, 0202. No unregulated voltages (+65, +8.5, + /-16) on power supply 1. Check appropriate secondary of Tl, diode bridges or filter board. capacitor. No anode voltage when other voltages are OK. 1. No sync pulses coming from terminal logic board. 2. Transistors 0213, 0214. 3. Deflection yoke. 4. Coils L203, L204. 5. Capacitors C228, C232. 6. Diode 0208. 7. IC's U201, U202. +500 V supply is too high or too low. 1. Diode 0211. 2. Capacitor C231. -90 V supply is too high or too low. 1. Diode 0207. 2. Resistor R259. 3. Capacitor C229. -6 V supply is too high or too low. 1. Diode 0203. 2. Resistor R212.

1. Brightness control (R1) turned down. 2. Anode voltage incorrect. 3. Grid voltages incorrect (G 1, G2, G4). 4. No cathode drive. 5. Transistors 0901, 0902. 6. No video signal coming from terminal logic board. 7. IC U406. 8. Video circuits on logic board. g,. Diode D901. 10. No sync pulses coming from logic board. 11. Diode D209. Screen all white (raster). 1. Grid voltages. 2. Transistors 0901, 0902. 3. Video circuits on terminal logic board. 4. Anode voltage incorrect. Insufficient brightness. 1. Transistors 0901, 0902. 2. Diode D902. 3. Capacitors C901-C905. 4. Brightness control, R1, Resistors R901-R904, R214, R218, R219, R217. 5. Grid voltages. One bright horizontal line on screen. 1. Vertical amplifier transistors 0207-0212. 2. Diode D205. 3. Deflection yoke (vertical). 4. Vertical sweep generator transistors 0205, 0206. 5. Diode D204. 6. No vertical sync pulses coming from logic board. 7. IC U406. Too much or too little height. 1. Vertical amplifier or sweep generator. 2. Capacitor C213. 3. Resistor R242. 4. Vertical size control R219. 5. Capacitor C211. Too much or too little width. 1. Adjust width coil L203. 2. Capacitors C228, C232. 3. Deflection yoke (horizontal). 4. Coils L203, L204. 5. +53 V supply not correct. 6. Flyback transformer T202. 7. Transistor 0214.

CONDITION POSSIBl.E CAUSE Picture tube filament does not glow. 1. No horizontal sync pulse coming from logic board. 2. Filament winding of T202 (brown wires). 3. Rosistor R257. Horizontal centering does not work. 1. IC U201. 2. Horizontal centering control R246. 3. Capacitor C221. No horizontal sweep, but sync pulses are present at P202-1. 1. Diode D206. 2. IC's U201, U202. 3. Transistors 0213, 0214. 4. Transformer T201. 5. +15 V supply not correct. 6. Capacitor C226. 7. Diode D208. 8. +53 V supply not correct. 9. DElflection yoke. 10. Coils L203, L204.

NOTE: To find the PART NUMBER of a component for the purpose of ordering a replacement part: A. Find the circuit component number (R5, C3, etc.) on the "X-Ray View." B. Locate this same number in the "Circuit Com- ponent Number" column of the "Replacement Parts List." C. Adjacent to the circuit component number, you will find the ZDS PART NUMBER and DESCRIPTION which must be supplied when you order a replacement part.

Part number HE 181-3244. Shown from the component side. Z-89 AND Z-90 VIDEO DRIVER CIRCUIT BOARD Part number HE 181-3387. Shown from the component side.

CIRCUIT BOARD Pari number HE 181·3400. Shown from thecom- ponent side.

CIRCUIT BOARD Parl number HE 181-3383. Shown from the com- pOllen! side. 7-41 COMPUTER

CIRCUIT BOARD 2-89 Pari number I-IE 181-339ti. 2-90 ParI llumber HE 181-3ti15. Shown from the compo- nenl side.

I/O CIRCUIT BOARD Part number HE 181·3369. Shown from the com- ponent side. 7-61---------- COMPUTER

This section is divided into two parts: "Component Number Index" and "Part Number Index." The first section provides a cross-reference between semiconductor Component Numbers and their respecitive Part Numbers. The Component Numbers are listed in numerical order. The second section provides a lead configuration detail (basing diagram) for each semiconductor Part Number. The Part Numbers in the second section are also listed in numerical order. COMPONENT NUMBER INDEX This index shows the Part Number of each semicon- ductor in the Computer. POWER SUPPLY CIRCUIT BOARD CIRCUIT PART COMPONENT NUMBER NUMBER BR1 HE 57.fi7 0101 HE 57-42 0102 HE 57-42 0103 HE 57-42 0104 HE 57-42 0109 HE 57.fi5 0110 HE 57.fi5 0111 HE 57.fi5 0112 HE 57.fi5 U101 HE 442-30 U102 HE 442-30 U103 HE 442-650

Diodes CIRCUIT PART COMPONENT NUMBER NUMBER 0201 HE 56·94 0202 HE 56-56 0203 HE 56-56 0204 HE 56·56 0205 HE 56-73 0206 HE 56·56 0207 HE 57·27 0208 HE 57-614 0209 HE 57·27 0210 HE 57-27 0211 HE 57-64 Transistors CIRCUIT PART COMPONENT NUMBER NUMBER 0201 HE 417-611 0202 HE 417·924 0203 HE 417-674 0204 HE 417·282 0205 HE 417-623 0206 HE 417-685 0207 HE 417-622 0208 HE 417-621 0209 HE 417·926 0210 HE 417·926 0211 HE 417·264 0212 HE 417·263 0213 HE417-195 0214 HE 417·923 Integrated Circuits CIRCUIT PART COMPONENT NUMBER NUMBER U201 HE 442-53 U202 HE 442-53 VIDEO DRIVER CIRCUIT BOARD Diodes CIRCUIT PART COMPONENT NUMBER NUMBER 0901 HE 57-27 0902 HE 56·93 Transistors CIRCUIT PART COMPONENT NUMBER NUMBER 0901 HE 417·834 0902 HE 417-675 TERMINAL LOGIC CIRCUIT BOARD Diodes CIRCUIT PART COMPONENT NUMBER NUMBER 0401 HE 56-56 0402 HE 56-56 Transistors CIRCUIT PART COMPONENT NUMBER NUMBER 0401 HE 417-937 0402 HE 417·937

* Used for MTR-89 ** Used for MTR-90 Integrated Circuits CPU LOGIC CIRCUIT BOARD Integrated Circuits CIRCUIT PART COMPONENT NUMBER NUMBER U401 HE 442-54 U402 HE 442-54 U403 HE 442-663 U404 HE 442-664 U405 HE 442-630 U406 HE 443-891 U407 HE 443-885 U408 HE 443-764 U409 HE 443-764 U410 HE 443-764 U411 HE 443·764 U412 HE 443-728 U413 HE 443-875 U414 HE 443-799 U415 HE 443·799 U416 HE 443-799 U417 HE 443-906 U418 HE 443-730 U419 HE 443-805 U420 HE 444-29 U421 HE 443-892 U422 HE 443-900 U423 HE 443-780 U424 HE 443-805 U425 HE 443-915 U426 HE 443-18 U427 HE 443-757 U428 HE 443-730 U429 HE 443-34 U430 HE 443-881 U431 HE 443-792 U432 HE 443-779 U433 HE 443-733 U~ HE 443-228 U435 HE 443-877 U436 Not used U437 HE 444-46 U438 HE443-721 U439 HE 443-721 U440 HE 443-760 U441 HE 443-727 U442 HE 443-877 U443 HE 443-791 U444 HE443-913 U445 HE 444-37 U446 HE443-18 U447 HE443-792 U448 HE443-792 U449 HE443-791 U450 HE443-791 U451 HE 443-730 U452 HE443-952 U453 HE443-794 U454 HE443-795 Resistor Packs CIRCUIT PART COMPONENT NUMBER NUMBER RP, HE 9-98 RP2 HE 9-98 Diode CIRCUIT PART COMPONENT NUMBER NUMBER 0501 HE 56-56 Transistor CIRCUIT PART COMPONENT NUMBER NUMBER 0501 HE 417-821 SERIAL INTERFACE CIRCUIT BOARD CIRCUIT PART COMPONENT NUMBER NUMBER U601 HE 443-818 U602 HE 443-952 U603 HE 443-874 U604 HE 443-952 U605 HE 443-795 U606 HE 443-794 U607 HE 443-795 U608 HE 443-794 U609 HE 443-795 U610 HE 443-730 Integrated Circuits CIRCUIT PART COMPONENT NUMBER NUMBER U501 HE 443-18 U502 HE 443-34 U503 HE 443-760 U504 HE 443-881 U506 HE 443-730 U507 HE 443-727 U508 HE 443-792 U509 HE 443-824 U510 HE 443-837 U511 HE 443-837 U512 HE 443-730 U513 HE 443-824 U514 HE 443-824 U515 HE 443-779 U516 HE 444-41 or 444-83 U517 HE 444-66 U518 HE 444-62* or 444-84* * U519 Not Used U520 HE 444-19 U521 HE 443-754 U522 Not Used U523 HE 443-764 U524 Not Used U525 HE 443-764 U526-U549 HE 443-904 U550 HE 444-61 U551 HE 443-791 U552 HE 443-805 U553 HE 443-875 U554 HE 443·732 U555 HE 443-730 U556 HE 443-730 U557 HE 443·912 U558 HE 443-754 U559 HE 443-794 U560 HE 443-795 U561 HE 443-952 U562 HE 443·792 U565 HE 442-664 U566 HE 442-665 U567 HE 442-663 U568 HE 442-663 U569 HE 442-665

This index shows a lead configuration detail (basing diagram) of each semiconductor part number. RESISTOR PACK PART MAY BE NUMBER REPLACED DESCRIPTION LEAD CONFIGURATION WITH (TOP VIEW) HE 9·98 DOT 220 kD OR ........... resistor network I ~ DIODES PART MAY BE NUMBER REPLACED DESCRIPTION LEAD CONFIGURATION WITH (TOP VIEW) HE 56·56 1N4149 10 rnA. 75 V HE 56-58 1N709A Zener, 6.2 V, 25 rnA NOTE: HEATH PART NUMBERS HE 56-73 MZ2360 Compensation ARE STAMPEO ON 1ol0ST DIODES. m::> HE 56·93 FD333 225 rnA, 125 V OR ~= Zener, 12.8 V. 12 rnA OR HE 56-94 mi OR HE 57·27 1N2071 51 Reet ===Uii== 1 A, 600 V OR HE 57-42 3A1 51 Rect ~ 3 A. 100 V OR IiJiii HE 57·64 DR5-110 51 Reet OR 1 A. 1000 V G HE 57·65 1N4002 51Rect 1 A, 100V HE 57-614 MR-508 51Rect 3 A, 800 V HE 57-67 10A20 Diode ~ Bridge HE 412-640 Light-emitting ANODE~FlAT Diode 'CATHODE u

,8·5 COMPUTERl--------- _ TRANSISTORS PART MAY BE BASING LEAD CONFIGURATION NUMBER REPLACED DIAGRAM (TOP VIEW) WITH HE 417-195 MJE340 A METALLIC ~A HE 417-282 MJ2841 E ~ 8-C~~ C E HE 417-811 MPSL01 B HE 417-821 MPSA06 B E~ B MPSA56 B HE 417-822 HE 417-823 MPU131 C HE 417-834 MPSU10 D ,~ C GA HE 417-874 2N3906 B G> HE 417-875 2N3904 B E~~D HE 417-885 MPSA65 B Be E~ HE 417-923 BU500 E C B HE 417-924 MJE172 A r E ,,- HE 417-926 MPSU06 0 ~~!6 E HE 417-927 MPSA93 B C ....~-~7 MJE182 A - HE 417-932 HE 417-937 MPS2369 B

a-6IL COMPUTER INTEGRATED CIRCUITS PART NUMBER HE 442-30 MAYBE REPLACED WITH JLA309K LM309 .DESCRIPTION 5-volt Regulator LEAD CONFIGURATION (TOPYIEW) INPUT (I) / ~ ~ /PUT 12) WIDE A _11- e SPAC//~ ~ I @ CASE ~ IC) HE 442·53 555 Timer TRIGGER 2 OUT PUT 3 7 DISCHARGE THRESHOLD CONTROL VOLTAGE HE 442-54 HE 442-616 7805 LM3302N. LM2901, or JLA775 (selected) +5 V Regulator Quad Operational Amplifier VC C u