Quectel UG96 Hardware Design

UMTS/HSPA Module Series Rev. UG96_Hardware_Design_V1.6 Date: 2018-08-13 Status: Released www.quectel.com

UG96 Hardware Design UG96_Hardware_Design 1 / 76 Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: [email protected] Or our local office. For more information, please visit: http://www.quectel.com/support/sales.htm For technical support, or to report documentation errors, please visit: http://www.quectel.com/support/technical.htm Or email to: [email protected] GENERAL NOTES QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO CHANGE WITHOUT PRIOR NOTICE. COPYRIGHT THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL OR DESIGN. Copyright © Quectel Wireless Solutions Co., Ltd. 2018. All rights reserved.

UG96 Hardware Design UG96_Hardware_Design 2 / 76 About the Document History Revision Date Author Description 1.0 2015-02-28 Tony GAO/ Cat WANG Initial 1.1 2015-10-23 Felix YIN 1. Updated PCM interface information in Table 2. 2. Updated Figure 1. 3. Updated PCM application in Chapter 3.13. 4. Updated ESD values in Chapter 5.7. 1.2 2015-12-08 Felix YIN 1. Updated GPRS/EDGE data features-class33 in Table 2. 2. Updated PCM timing in Chapter 3.13. 3. Updated current consumption values in Chapter 5.4. 4. Updated GPRS multi-slot class in Chapter 10. 1.3 2017-05-24 Eden LIU 1. Updated notes of PCM and I2C interfaces in Chapter 3.13. 2. Updated recommended footprint and stencil in Chapter 6. 1.4 2017-12-21 Yeoman CHEN Modified TVS parasitic capacitance which should be less than 15pF for better performance in Chapter 3.11. 1.5 2018-01-12 Yeoman CHEN Modified baking time and temperature of the module in Chapter 7.1. 1.6 2018-08-13 Yeoman CHEN 1. Modified power down current consumption of the module in Chapter 5.4. 2. Updated the reflow soldering thermal profile in Chapter 7.2.

UG96 Hardware Design UG96_Hardware_Design 3 / 76 Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index ................................................................................................................................................... 5 Figure Index ................................................................................................................................................. 6 1 Introduction .......................................................................................................................................... 8 1.1. Safety Information...................................................................................................................... 9 2 Product Concept ................................................................................................................................ 10 2.1. General Description ................................................................................................................. 10 2.2. Key Features ........................................................................................................................... 11 2.3. Functional Diagram ................................................................................................................. 13 2.4. Evaluation Board ..................................................................................................................... 14 3 Application Interfaces ....................................................................................................................... 15 3.1. General Description ................................................................................................................. 15 3.2. Pin Assignment ........................................................................................................................ 16 3.3. Pin Description ......................................................................................................................... 17 3.4. Operating Modes ..................................................................................................................... 22 3.5. Power Saving ........................................................................................................................... 23 3.5.1. Sleep Mode .................................................................................................................... 23 3.5.1.1. UART Application ................................................................................................. 23 3.5.1.2. USB Application with Suspend Function ............................................................. 24 3.5.1.3. USB Application without Suspend Function ........................................................ 25 3.5.2. Minimum Functionality Mode ......................................................................................... 26 3.6. Power Supply ........................................................................................................................... 26 3.6.1. Power Supply Pins ......................................................................................................... 26 3.6.2. Decrease Voltage Drop .................................................................................................. 27 3.6.3. Reference Design for Power Supply .............................................................................. 28 3.6.4. Monitor the Power Supply .............................................................................................. 29 3.7. Turn on and off Scenarios ....................................................................................................... 29 3.7.1. Turn on Module Using the PWRKEY ............................................................................. 29 3.7.2. Turn off Module .............................................................................................................. 30 3.7.2.1. Turn off Module Using AT Command ................................................................... 31 3.7.2.2. Emergency Shutdown .......................................................................................... 31 3.7.2.3. Automatic Shutdown ............................................................................................ 33 3.8. Reset the Module..................................................................................................................... 34 3.9. RTC Interface .......................................................................................................................... 35 3.10. UART Interface ........................................................................................................................ 36 3.11. (U)SIM Interface ...................................................................................................................... 39 3.12. USB Interface .......................................................................................................................... 41 3.13. PCM and I2C Interfaces .......................................................................................................... 43 3.14. Network Status Indication ........................................................................................................ 46

UG96 Hardware Design UG96_Hardware_Design 4 / 76 3.15. STATUS ................................................................................................................................... 47 4 Antenna Interface ............................................................................................................................... 48 4.1. GSM/UMTS Antenna Interface ................................................................................................ 48 4.1.1. Pin Definition .................................................................................................................. 48 4.1.2. Operating Frequency ..................................................................................................... 48 4.1.3. Reference Design of RF Antenna Interface ................................................................... 49 4.1.4. Reference Design of RF Layout..................................................................................... 49 4.2. Antenna Installation ................................................................................................................. 51 4.2.1. Antenna Requirements .................................................................................................. 51 4.2.2. Recommended RF Connector for Antenna Installation ................................................. 52 5 Electrical, Reliability and Radio Characteristics ............................................................................ 54 5.1. Absolute Maximum Ratings ..................................................................................................... 54 5.2. Power Supply Ratings ............................................................................................................. 54 5.3. Operation and Storage Temperatures ..................................................................................... 55 5.4. Current Consumption .............................................................................................................. 55 5.5. RF Output Power ..................................................................................................................... 58 5.6. RF Receiving Sensitivity .......................................................................................................... 59 5.7. Electrostatic Discharge ............................................................................................................ 60 6 Mechanical Dimensions .................................................................................................................... 61 6.1. Mechanical Dimensions of the Module.................................................................................... 61 6.2. Recommended Footprint Design ............................................................................................. 63 6.3. Top and Bottom Views of the Module ...................................................................................... 64 7 Storage, Manufacturing and Packaging .......................................................................................... 65 7.1. Storage..................................................................................................................................... 65 7.2. Manufacturing and Soldering .................................................................................................. 66 7.3. Packaging ................................................................................................................................ 67 8 Appendix A References ..................................................................................................................... 69 9 Appendix B GPRS Coding Schemes ............................................................................................... 73 10 Appendix C GPRS Multi-slot Classes .............................................................................................. 74 11 Appendix D EDGE Modulation and Coding Schemes ................................................................... 76

UG96 Hardware Design UG96_Hardware_Design 5 / 76 Table Index TABLE 1: FREQUENCY BANDS OF UG96 MODULE...................................................................................... 10 TABLE 2: KEY FEATURES OF UG96 MODULE ............................................................................................... 11 TABLE 3: I/O PARAMETERS DEFINITION ....................................................................................................... 17 TABLE 4: PIN DESCRIPTION ........................................................................................................................... 17 TABLE 5: OVERVIEW OF OPERATING MODES ............................................................................................. 22 TABLE 6: VBAT AND GND PINS ....................................................................................................................... 26 TABLE 7: PIN DEFINITION OF PWRKEY ........................................................................................................ 29 TABLE 8: PIN DEFINITION OF PWRDWN_N .................................................................................................. 32 TABLE 9: PIN DEFINITION OF RESET_N ....................................................................................................... 34 TABLE 10: PIN DEFINITION OF MAIN UART INTERFACE ............................................................................. 37 TABLE 11: LOGIC LEVELS OF DIGITAL I/O .................................................................................................... 37 TABLE 12: PIN DEFINITION OF (U)SIM INTERFACE ..................................................................................... 39 TABLE 13: PIN DEFINITION OF USB INTERFACE ......................................................................................... 42 TABLE 14: PIN DEFINITION OF PCM AND I2C INTERFACES ....................................................................... 44 TABLE 15: PIN DEFINITION OF NETLIGHT .................................................................................................... 46 TABLE 16: WORKING STATE OF NETLIGHT .................................................................................................. 46 TABLE 17: PIN DEFINITION OF STATUS ........................................................................................................ 47 TABLE 18: PIN DEFINITION OF RF ANTENNA ............................................................................................... 48 TABLE 19: MODULE OPERATING FREQUENCIES ........................................................................................ 48 TABLE 20: ANTENNA CABLE REQUIREMENTS ............................................................................................. 51 TABLE 21: ANTENNA REQUIREMENTS .......................................................................................................... 52 TABLE 22: ABSOLUTE MAXIMUM RATINGS .................................................................................................. 54 TABLE 23: POWER SUPPLY RATINGS ........................................................................................................... 54 TABLE 24: OPERATION AND STORAGE TEMPERATURES .......................................................................... 55 TABLE 25: CURRENT CONSUMPTION ........................................................................................................... 56 TABLE 26: RF OUTPUT POWER ..................................................................................................................... 59 TABLE 27: CONDUCTED RF RECEIVING SENSITIVITY ................................................................................ 59 TABLE 28: ELECTROSTATIC DISCHARGE CHARACTERISTICS ................................................................. 60 TABLE 29: REEL PACKING .............................................................................................................................. 68 TABLE 30: RELATED DOCUMENTS ................................................................................................................ 69 TABLE 31: TERMS AND ABBREVIATIONS ...................................................................................................... 69 TABLE 32: DESCRIPTION OF DIFFERENT CODING SCHEMES .................................................................. 73 TABLE 33: GPRS MULTI-SLOT CLASSES ...................................................................................................... 74 TABLE 34: EDGE MODULATION AND CODING SCHEMES ........................................................................... 76

UG96 Hardware Design UG96_Hardware_Design 6 / 76 Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 14 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 16 FIGURE 3: SLEEP MODE APPLICATION VIA UART ....................................................................................... 24 FIGURE 4: USB APPLICATION WITH SUSPEND FUNCTION ........................................................................ 25 FIGURE 5: SLEEP MODE APPLICATION WITHOUT SUSPEND FUNCTION ................................................ 25 FIGURE 6: VOLTAGE DROP DURING BURST TRANSMISSION ................................................................... 27 FIGURE 7: STAR STRUCTURE OF THE POWER SUPPLY............................................................................ 28 FIGURE 8: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 28 FIGURE 9: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 29 FIGURE 10: TURN ON THE MODULE USING KEYSTROKE ......................................................................... 30 FIGURE 11: TIMING OF TURNING ON MODULE ........................................................................................... 30 FIGURE 12: TIMING OF TURNING OFF THROUGH AT COMMAND ............................................................. 31 FIGURE 13: TURN OFF THE MODULE USING DRIVING CIRCUIT ............................................................... 32 FIGURE 14: TURN OFF THE MODULE USING KEYSTROKE ........................................................................ 32 FIGURE 15: TIMING OF EMERGENCY SHUTDOWN ..................................................................................... 33 FIGURE 16: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 34 FIGURE 17: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 35 FIGURE 18: TIMING OF RESETTING MODULE ............................................................................................. 35 FIGURE 19: RTC SUPPLY FROM CAPACITOR .............................................................................................. 36 FIGURE 20: REFERENCE CIRCUIT OF LOGIC LEVEL TRANSLATOR ......................................................... 38 FIGURE 21: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 38 FIGURE 22: RS232 LEVEL MATCH CIRCUIT .................................................................................................. 39 FIGURE 23: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR ................................................................................................................................................................... 40 FIGURE 24: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR . 41 FIGURE 25: REFERENCE CIRCUIT OF USB INTERFACE ............................................................................ 42 FIGURE 26: TEST POINTS OF FIRMWARE UPGRADE ................................................................................. 43 FIGURE 27: PCM MASTER MODE TIMING ..................................................................................................... 44 FIGURE 28: REFERENCE CIRCUIT OF PCM MASTER MODE APPLICATION WITH AUDIO CODEC ........ 45 FIGURE 29: REFERENCE CIRCUIT OF PCM SLAVE MODE APPLICATION WITH AUDIO CODEC ............ 45 FIGURE 30: REFERENCE CIRCUIT OF THE NETWORK STATUS INDICATOR ........................................... 46 FIGURE 31: REFERENCE CIRCUIT OF STATUS ........................................................................................... 47 FIGURE 32: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................. 49 FIGURE 33: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ...................................................................... 50 FIGURE 34: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB .................................................. 50 FIGURE 35: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND) .................................................................................................................................................. 50 FIGURE 36: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND) .................................................................................................................................................. 51 FIGURE 37: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ................................................ 52 FIGURE 38: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 53

UG96 Hardware Design UG96_Hardware_Design 7 / 76 FIGURE 39: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) ........................................................... 53 FIGURE 40: MODULE TOP AND SIDE DIMENSIONS ..................................................................................... 61 FIGURE 41: MODULE BOTTOM DIMENSIONS (TOP VIEW) ......................................................................... 62 FIGURE 42: RECOMMENDED FOOTPRINT (TOP VIEW) .............................................................................. 63 FIGURE 43: TOP VIEW OF THE MODULE ...................................................................................................... 64 FIGURE 44: BOTTOM VIEW OF THE MODULE .............................................................................................. 64 FIGURE 45: REFLOW SOLDERING THERMAL PROFILE .............................................................................. 66 FIGURE 46: TAPE DIMENSIONS ..................................................................................................................... 67 FIGURE 47: REEL DIMENSIONS ..................................................................................................................... 68

UG96 Hardware Design UG96_Hardware_Design 8 / 76 1 Introduction This document defines the UG96 module and describes its air interface and hardware interface which are connected with customers’ applications. This document can help customers quickly understand module interface specifications, electrical and mechanical details, as well as other related information of UG96 module. Associated with application note and user guide, customers can use UG96 module to design and set up mobile applications easily.

UG96 Hardware Design UG96_Hardware_Design 9 / 76 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating UG96 module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel and incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for customers’ failure to comply with these precautions. Full attention must be given to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If the device offers an Airplane Mode, then it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on boarding the aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signals and cellular network cannot be guaranteed to connect in all possible conditions (for example, with unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such conditions, please remember using emergency call. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV set, radio, computer or other electric equipment. In locations with potentially explosive atmospheres, obey all posted signs to turn off wireless devices such as your phone or other cellular terminals. Areas with potentially explosive atmospheres include fueling areas, below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains chemicals or particles such as grain, dust or metal powders, etc.

UG96 Hardware Design UG96_Hardware_Design 10 / 76 2 Product Concept 2.1. General Description UG96 module is an embedded 3G wireless communication module, supports GSM/GPRS/EDGE and UMTS/HSDPA/HSUPA networks. It can also provide voice functionality1) for customers’ specific applications. UG96 offers a maximum data rate of 7.2Mbps on downlink and 5.76Mbps on uplink in HSPA mode. GPRS supports the coding schemes CS-1, CS-2, CS-3 and CS-4. EDGE supports CS1-4 and MCS1-9 coding schemes. The following table shows the frequency bands of UG96 module. Table 1: Frequency Bands of UG96 Module Module GSM 850 EGSM 900 DCS 1800 PCS 1900 UMTS 800 UMTS 850 UMTS 900 UMTS 1900 UMTS 2100 UG96 √ √ √ √ √ √ √ √ √ 1) UG96 module includes Data-only and Telematics versions. Data-only version does not support voice function while Telematics version supports it. More details about GPRS/EDGE multi-slot configuration and coding schemes, please refer to Appendix B, C and D. With a compact profile of 26.5mm × 22.5mm × 2.2mm, UG96 can meet almost all requirements for M2M applications such as wireless POS, metering, telematics, security, industry PDA/PC and tablet, etc. UG96 is an SMD type module, which can be embedded in application through its 102 LGA pads. UG96 is integrated with internet service protocols like TCP, UDP and PPP. Extended AT commands have been developed for customers to use these internet service protocols easily. NOTE

UG96 Hardware Design UG96_Hardware_Design 11 / 76 2.2. Key Features The following table describes the detailed features of UG96 module. Table 2: Key Features of UG96 Module Feature Details Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.8V Frequency Bands GSM 4-band: 850/900/1800/1900MHz UMTS 5-band: 800/850/900/1900/2100MHz Transmission Data HSDPA category 8: Max 7.2Mbps HSUPA category 6: Max 5.76Mbps UMTS: Max 384kbps (DL)/Max 384kbps (UL) EDGE: Max 296kbps (DL)/Max 236.8kbps (UL) GPRS: Max 107kbps (DL)/Max 85.6kbps (UL) CSD: 14.4kbps Transmitting Power Class 4 (33dBm±2dB) for GSM850 and EGSM900 Class 1 (30dBm±2dB) for DCS1800 and PCS1900 Class E2 (27dBm±3dB) for GSM850 and EGSM900 8-PSK Class E2 (26dBm±3dB) for DCS1800 and PCS1900 8-PSK Class 3 (24dBm+1.7/-3.7dB) for UMTS 800/850/900/1900/2100 HSPA/UMTS Features Compliant with 3GPP Release 7 WCDMA data rate is corresponded with 3GPP R99/R4 384kbps on downlink and 384kbps on uplink Support both QPSK and 16-QAM modulation GSM/GPRS/EDGE Data Features GPRS: Support GPRS multi-slot class 33 Coding scheme: CS-1, CS-2, CS-3 and CS-4 Maximum of four Rx time slots per frame EDGE: Support EDGE multi-slot class 33 Support GMSK and 8-PSK for different MCS (Modulation and Coding Scheme) Downlink coding schemes: CS 1-4 and MCS 1-9 Uplink coding schemes: CS 1-4 and MCS 1-9 CSD: CSD transmission rates: 14.4kbps non-transparent Support Unstructured Supplementary Services Data (USSD) Internet Protocol Features Support TCP/UDP/PPP/MMS/HTTP/HTTPS/SMTP/SMTPS/FTP/NTP/ NITZ/PING/SSL protocols

UG96 Hardware Design UG96_Hardware_Design 12 / 76 Support the protocols PAP (Password Authentication Protocol) and CHAP (Challenge Handshake Authentication Protocol) usually used for PPP connections SMS Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: (U)SIM card by default (U)SIM Interface Support (U)SIM card: 1.8V, 3.0V PCM Interface Used for audio function with external codec Support 16/32-bit modes with short frame synchronization Support master and slave modes UART Interface Support one UART interface ⚫ 7-wire on UART interface, without DSR ⚫ Support RTS and CTS hardware flow control ⚫ Baud rate: 300bps to 921600bps ⚫ Default autobauding: 4800bps to 115200bps ⚫ Used for data transmission, AT command communication and firmware upgrade ⚫ Multiplexing function USB Interface Compliant with USB 1.1/2.0 specification (slave only), the data transfer rate can reach up to 480Mbps Used for AT command communication, data transmission, software debugging and firmware upgrade Support USB drivers for Windows XP, Windows Vista, Windows 7/8/8.1/10, Linux 2.6/3.x/4.1, Android 4.x/5.x/6.0 AT Commands Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT commands Real Time Clock Supported Network Indication One pin NETLIGHT to indicate network status Antenna Interface GSM/UMTS antenna, 50Ω Physical Characteristics Size: (22.5±0.15)mm × (26.5±0.15)mm × (2.2±0.2)mm Package: LGA Weight: approx. 3.1g Temperature Range Operation temperature range: -35°C ~ +75°C1) Extended temperature range: -40°C ~ +85°C2) Storage temperature range: -40°C ~ +90°C Firmware Upgrade USB interface or UART interface RoHS All hardware components are fully compliant with EU RoHS directive

UG96 Hardware Design UG96_Hardware_Design 13 / 76 1. 1) Within operating temperature range, the module is 3GPP compliant. 2. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to normal operating temperature levels, the module will meet 3GPP specifications again. 2.3. Functional Diagram The following figure shows a block diagram of UG96 and illustrates the major functional parts. ⚫ RF transceiver ⚫ Baseband ⚫ DDR+NAND flash ⚫ Radio frequency ⚫ Peripheral interfaces —UART interface —(U)SIM interface —USB interface —PCM interface —I2C interface —Status indication —Power control interface NOTES

UG96 Hardware Design UG96_Hardware_Design 14 / 76 PWRKEY RESET_N 32KHz PMU Baseband MCP RF_ANT (U)SIM STATUS UART VBAT_BB USB VBAT_RF B1 VDD_EXT VRTC Nand+DDR PWRDWN_N RF Transceiver NETLIGHT 26MHz XO B2/PCS1900 GSM TX LB Duplexer PCM PMU Reset I2C PA ASM B5/B6/GSM850 B8/GSM900 DC/DC B1 B2 B5/B6 B8 PM_H PM_L GSM TX HB DCS1800 Figure 1: Functional Diagram 2.4. Evaluation Board In order to help customers, develop applications conveniently with UG96, Quectel supplies an evaluation board (UMTS<E EVB), RS-232 to USB cable, USB data cable, power adapter, earphone, antenna and other peripherals to control or test the module. For details, please refer to document [2].

UG96 Hardware Design UG96_Hardware_Design 15 / 76 3 Application Interfaces 3.1. General Description UG96 is equipped with 62-pin 1.1mm pitch SMT pads plus 40-pin ground/reserved pads that can be connected to customers’ cellular application platforms. Sub-interfaces included in these pads are described in detail in the following chapters: ⚫ Power supply ⚫ RTC interface ⚫ UART interface ⚫ (U)SIM interface ⚫ USB interface ⚫ PCM and I2C interfaces ⚫ Status indication

UG96 Hardware Design UG96_Hardware_Design 16 / 76 3.2. Pin Assignment The following figure shows the pin assignment of UG96 module. RESERVED PCM_SYNC PCM_CLK PCM_DIN PCM_DOUT RESERVED RESERVED PWRKEY PWRDWN_N RESET_N RESERVED 1 2 3 4 5 6 7 11 12 13 14 15 16 17 18 50 51 52 53 54 55 58 59 60 61 62 USB_DM AP_READY STATUS NETLIGHT RESERVED RESERVED RESERVED CLK_OUT RESERVED RESERVED RESERVED VDD_EXT DTR GND USIM_CLK USIM_DATA USIM_RST USIM_VDD RI DCD CTS TXD RXD VBAT_BB VBAT_BB USIM_GND GND RESERVED 31 30 29 28 27 26 23 22 21 20 19 10 9 USB_DP USB_VBUS RESERVED GND RESERVED RESERVED RTS I2C_SCL I2C_SDA 8 49 48 47 46 45 44 43 40 41 42 39 38 37 36 35 34 33 32 24 57 56 GND GND RF_ANT GND GND RESERVED VBAT_RF VBAT_RF GND GND RESERVED VRTC GND USIM_PRESENCE 63 64 65 66 67 68 83 84 85 86 87 88 98 97 96 95 94 93 78 77 76 75 74 73 91 92 89 90 71 72 69 70 80 79 82 81 100 99 102 101 POWER USB UART (U)SIM OTHERS GND RESERVED PCM ANT 25 Figure 2: Pin Assignment (Top View) 1. Keep all RESERVED and unused pins unconnected. 2. GND pads should be connected to ground in the design. NOTES

UG96 Hardware Design UG96_Hardware_Design 17 / 76 3.3. Pin Description The following tables show the pin definition of UG96 module. Table 3: I/O Parameters Definition Type Description IO Bidirectional DI Digital input DO Digital output PI Power input PO Power output AI Analog input AO Analog output OD Open drain Table 4: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT_BB 32, 33 PI Power supply for module’s baseband part Vmax=4.3V Vmin=3.3V Vnorm=3.8V It must be able to provide sufficient current in a transmitting burst which typically rises to 2.0A. VBAT_RF 52, 53 PI Power supply for module’s RF part Vmax=4.3V Vmin=3.3V Vnorm=3.8V VRTC 51 PI/ PO Power supply for internal RTC circuit Vnorm=1.8V when VBAT≥3.3V VI=1V~1.9V at IINmax=2uA when VBAT is not applied. If unused, keep it open. VDD_EXT 29 PO Provide 1.8V for external circuit Vnorm=1.8V IOmax=20mA Power supply for external GPIO’s pull up circuits.

UG96 Hardware Design UG96_Hardware_Design 18 / 76 If unused, keep it open. GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67~74, 79~82, 89~91, 100~102 Ground Turn On/Off Pin Name Pin No. I/O Description DC Characteristics Comment PWRKEY 15 DI Turn on the module RPU≈200KΩ VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to VRTC internally. Active low. PWRDWN_N 16 DI Turn off the module RPU≈4.7KΩ VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to VRTC internally. Active low. If unused, keep it open. RESET_N 17 DI Reset signal of the module RPU≈200KΩ VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to VRTC internally. Active low. If unused, keep it open. Status Indication Pin Name Pin No. I/O Description DC Characteristics Comment STATUS 20 DO Indicate the module operating status VOHmin=1.3V VOLmax=0.5V 1.8V power domain. If unused, keep it open. NETLIGHT 21 DO Indicate the module network status VOHmin=1.3V VOLmax=0.5V 1.8V power domain. If unused, keep it open. USB Interface Pin Name Pin No. I/O Description DC Characteristics Comment USB_VBUS 8 PI USB detection Vmax=5.25V Vmin=2.5V Vnorm=5.0V USB_DP 9 IO USB differential data Compliant with USB Require differential

UG96 Hardware Design UG96_Hardware_Design 19 / 76 bus (+) 2.0 standard specification. impedance of 90Ω. USB_DM 10 IO USB differential data bus (-) Compliant with USB 2.0 standard specification. Require differential impedance of 90Ω. (U)SIM Interface Pin Name Pin No. I/O Description DC Characteristics Comment USIM_GND 47 Specified ground for (U)SIM card USIM_VDD 43 PO Power supply for (U)SIM card For 1.8V (U)SIM: Vmax=1.85V Vmin=1.75V For 3.0V (U)SIM: Vmax=2.9V Vmin=2.8V Either 1.8V or 3.0V is supported by the module automatically. USIM_DATA 45 IO Data signal of (U)SIM card For 1.8V (U)SIM: VILmax=0.35V VIHmin=1.25V VOLmax=0.25V VOHmin=1.25V For 3.0V (U)SIM: VILmax=0.5V VIHmin=2.05V VOLmax=0.25V VOHmin=2.05V Pull-up to USIM_VDD with 4.7K resistor internally. USIM_CLK 46 DO Clock signal of (U)SIM card For 1.8V (U)SIM: VOLmax=0.25V VOHmin=1.25V For 3.0V (U)SIM: VOLmax=0.25V VOHmin=2.05V USIM_RST 44 DO Reset signal of (U)SIM card For 1.8V (U)SIM: VOLmax=0.25V VOHmin=1.25V For 3.0V (U)SIM: VOLmax=0.3V VOHmin=2.05V

UG96 Hardware Design UG96_Hardware_Design 20 / 76 USIM_ PRESENCE 42 DI (U)SIM card insertion detection VILmax=0.35V VIHmin=1.3V VIHmax=1.85V 1.8V power domain. External pull-up resistor is required. Main UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment RI 39 DO Ring indicator VOLmax=0.25V VOHmin=1.55V 1.8V power domain. If unused, keep it open. DCD 38 DO Data carrier detection VOLmax=0.25V VOHmin=1.55V 1.8V power domain. If unused, keep it open. CTS 36 DO Clear to send VOLmax=0.25V VOHmin=1.55V 1.8V power domain. If unused, keep it open. RTS 37 DI Request to send VILmax=0.35V VIHmin=1.3V VIHmax=1.85V 1.8V power domain. If unused, keep it open. DTR 30 DI Data terminal ready. Sleep mode control. VILmax=0.35V VIHmin=1.3V VIHmax=1.85V 1.8V power domain. If unused, keep it open. TXD 35 DO Transmit data VOLmax=0.25V VOHmin=1.55V 1.8V power domain. If unused, keep it open. RXD 34 DI Receive data VILmax=0.35V VIHmin=1.3V VIHmax=1.85V 1.8V power domain. If unused, keep it open. RF Interface Pin Name Pin No. I/O Description DC Characteristics Comment RF_ANT 60 IO RF antenna 50Ω impedance PCM Interface Pin Name Pin No. I/O Description DC Characteristics Comment PCM_IN 6 DI PCM data input VILmin=-0.3V VILmax=0.35V VIHmin=1.3V VIHmax=1.85V 1.8V power domain. If unused, keep it open. PCM_OUT 7 DO PCM data output VOLmax=0.25V VOHmin=1.55V 1.8V power domain. If unused, keep it open.

UG96 Hardware Design UG96_Hardware_Design 21 / 76 PCM_SYNC 5 DO PCM data frame synchronization signal VOLmax=0.25V VOHmin=1.55V 1.8V power domain. In master mode, it is an output signal. If unused, keep it open. PCM_CLK 4 DO PCM data bit clock VOLmax=0.25V VOHmin=1.55V 1.8V power domain. In master mode, it’s an output signal. If unused, keep it open. I2C Interface Pin Name Pin No. I/O Description DC Characteristics Comment I2C_SCL 40 OD I2C serial clock. Used for external codec 1.8V power domain. External pull-up resistor is required. If unused, keep it open. I2C_SDA 41 OD I2C serial data. Used for external codec 1.8V power domain. External pull-up resistor is required. If unused, keep it open. Other Pins Pin Name Pin No. I/O Description DC Characteristics Comment AP_READY* 19 DI Application processor sleep state detection VILmin=-0.3V VILmax=0.35V VIHmin=1.3V VIHmax=1.85V 1.8V power domain. If unused, keep it open. CLK_OUT 25 DO Clock output Provide a digital clock output for an external audio codec. If unused, keep it open. RESERVED Pins Pin Name Pin No. I/O Description DC Characteristics Comment RESERVED 1, 2, 11~14, 18, 22~24, Reserved Keep these pins unconnected.

UG96 Hardware Design UG96_Hardware_Design 22 / 76 26~28, 49, 56, 57, 63~66, 75~78, 83~88, 92~99 “*” means under development. 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 5: Overview of Operating Modes Mode Details Normal Operation GSM Idle The module has registered on the GSM network and is ready to send and receive data. GSM Talk/Data GSM connection is ongoing. In this mode, the power consumption is decided by the configuration of power control level (PCL), dynamic DTX control and the working RF band. GPRS Idle The module is ready for GPRS data transfer, but no data transfer is going on. In this case, power consumption is decided by network setting and GPRS configuration. GPRS Data There is GPRS data (PPP, TCP or UDP) in transfer. In this mode, power consumption is decided by the PCL, working RF band and GPRS multi-slot configuration. EDGE Idle The module is ready for data transfer in EDGE mode, but no data is currently sent or received. In this case, power consumption is decided by network settings and EDGE configuration. EDGE Data There is EDGE data (PPP, TCP or UDP) in transfer. UMTS Idle The module has registered on the UMTS network and is ready to send and receive data. UMTS Talk/Data UMTS connection is ongoing. In this mode, the power consumption is decided by network setting (e.g. TPC pattern) and NOTE

UG96 Hardware Design UG96_Hardware_Design 23 / 76 data transfer rate. HSPA Idle The module has registered on the HSPA network and is ready to send and receive data. HSPA Data HSPA data transfer is ongoing. In this mode, the power consumption is decided by network setting (e.g. TPC pattern) and data transfer rate. Minimum Functionality Mode AT+CFUN command can set the module entering into a minimum functionality mode without removing the power supply. In this case, both RF function and (U)SIM card will be invalid. Sleep Mode In this mode, the current consumption of the module will be reduced to the minimal level. During this mode, the module can still receive paging message, SMS and voice call from the network normally. Power Down Mode In this mode, the power management unit shuts down the power supply for the baseband part and RF part. Only the power supply for RTC remains. Software is not active. The serial interface is not accessible. Operating voltage (connected to VBAT_RF and VBAT_BB) remains applied. 3.5. Power Saving 3.5.1. Sleep Mode UG96 is able to reduce its current consumption to a minimum value during the sleep mode. The following sub-chapters describe power saving procedures of UG96. 3.5.1.1. UART Application If the host communicates with module via UART interface, the following preconditions must be met to let the module enter into sleep mode. ⚫ Execute AT+QCFG="uart/power",0,0 to set UART into auto on/off mode. ⚫ Execute AT+QSCLK=1 to enable the sleep mode. ⚫ Drive DTR to high level. The following figure shows the connection between the module and the host.

UG96 Hardware Design UG96_Hardware_Design 24 / 76 RXD TXD RI DTR AP_READY TXD RXD EINT GPIO GPIO Module GND GND Host Figure 3: Sleep Mode Application via UART The RI of module is used to wake up the host and AP_READY* will detect the sleep state of host (can be configured to high level or low level detection). Customers should pay attention to the level match shown in dotted line between module and host. Drive DTR pin to low level to wake up the module. In sleep mode for UART application, the UART port is not accessible. “*” means under development. 3.5.1.2. USB Application with Suspend Function If the host communicates with module via USB interface and supports USB suspend function, the following preconditions must be met to let the module enter into sleep mode. ⚫ Execute AT+QCFG="uart/power",0,0 to set UART into auto on/off mode. ⚫ Execute AT+QSCLK=1 to enable the sleep mode. ⚫ The host’s USB bus, which is connected with the module’s USB interface, enters into suspended state. The following figure shows the connection between the module and host. NOTE

UG96 Hardware Design UG96_Hardware_Design 25 / 76 USB_VBUS USB_DP USB_DM VDD USB_DP USB_DM Module GND GND RI EINT Host Figure 4: USB Application with Suspend Function When the host’s USB bus returns to resume state, the module will be woken up. 3.5.1.3. USB Application without Suspend Function If the host communicates with module via USB interface, and does not support USB suspend function, USB_VBUS should be disconnected with an external control circuit to let the module enter into sleep mode. ⚫ Execute AT+QCFG="uart/power",0,0 to set UART into auto on/off mode. ⚫ Execute AT+QSCLK=1 to enable the sleep mode. ⚫ Disconnect USB_VBUS. Supplying power to USB_VBUS will wake up the module. The following figure shows the connection between the module and host. USB_VBUS USB_DP USB_DM VDD USB_DP USB_DM Module Host RI EINT Power Switch GPIO GND GND Figure 5: Sleep Mode Application without Suspend Function

UG96 Hardware Design UG96_Hardware_Design 26 / 76 In sleep mode, the module can still receive paging message, SMS, voice call and TCP/UDP data from the network normally. 3.5.2. Minimum Functionality Mode Minimum functionality mode reduces the functionality of the module to minimum level, thus minimizes the current consumption at the same time. This mode can be set as below: Command AT+CFUN provides the choice of the functionality levels: =0, 1, 4. ⚫ AT+CFUN=0: Minimum functionality, RF part and (U)SIM card will be closed. ⚫ AT+CFUN=1: Full functionality (by default). ⚫ AT+CFUN=4: Disable RF function (airplane mode). All AT commands related to RF function are not accessible. For detailed information about command AT+CFUN, please refer to document [1]. 3.6. Power Supply 3.6.1. Power Supply Pins UG96 provides four VBAT pins for connection with the external power supply. There are two separate voltage domains for VBAT. ⚫ Two VBAT_RF pins for module RF part. ⚫ Two VBAT_BB pins for module baseband part. The following table shows the details of VBAT pins and ground pins. Table 6: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_RF 52, 53 Power supply for module’s RF part. 3.3 3.8 4.3 V VBAT_BB 32, 33 Power supply for module’s baseband part. 3.3 3.8 4.3 V GND 3, 31, 48, 50 54, 55, 58, Ground - - - - NOTES

UG96 Hardware Design UG96_Hardware_Design 27 / 76 59, 61, 62, 67~74, 79~82, 89~91, 100~102 3.6.2. Decrease Voltage Drop The power supply range of the module is 3.3V~4.3V. Please make sure that the input voltage will never drop below 3.3V. If the voltage drops to below 3.3V, the module will be turned off automatically. The following figure shows the voltage drop during burst transmission in 2G network. The voltage drop will be less in 3G and 4G networks. <400mV Current VBAT ≤2.0A Burst Transmission Burst Transmission Min. 3.3V Figure 6: Voltage Drop during Burst Transmission To decrease voltage drop, a bypass capacitor of about 100µF with low ESR (ESR=0.7Ω) should be used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array, and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace should be no less than 1mm, and the width of VBAT_RF trace should be no less than 2mm. In principle, the longer the VBAT trace is, the wider it will be. In addition, in order to get a stable power source, it is suggested that a zener diode whose dissipation power is more than 0.5W should be used. The following figure shows the star structure of the power supply.

UG96 Hardware Design UG96_Hardware_Design 28 / 76 Module VBAT_RF VBAT_BB VBAT C1 100uF C6 100nF C7 33pF C8 10pF + + C2 100nF C5 100uF C3 33pF C4 10pF D1 Figure 7: Star Structure of the Power Supply 3.6.3. Reference Design for Power Supply The power design for the module is very important, as the performance of module largely depends on the power source. The power supply should be able to provide sufficient current up to 2A at least. If the voltage drop between the input and output is not too high, it is suggested that an LDO should be used to supply power for module. If there is a big voltage difference between the input source and the desired output (VBAT), a buck converter is preferred to be used as the power supply. The following figure shows a reference design for +5V input power source. The typical output of the power supply is about 3.8V and the maximum load current is 3A. DC_IN C1 C2 MIC29302WU U1 IN OUT EN GND ADJ 2 4 1 3 5 VBAT 100nF C3 470uF C4 100nF R2 100K 47K R3 470uF 470R 51K R4 R1 1% 1% MCU_POWER _ON/OFF 47K 4.7K R5 R6 Figure 8: Reference Circuit of Power Supply It is suggested that customers should switch off power supply for module in abnormal state, and then switch on power to restart module. NOTE

UG96 Hardware Design UG96_Hardware_Design 29 / 76 3.6.4. Monitor the Power Supply Command AT+CBC can be used to monitor the VBAT_BB voltage value displayed in millivolt. For more details, please refer to document [1]. 3.7. Turn on and off Scenarios 3.7.1. Turn on Module Using the PWRKEY The following table shows the pin definition of PWRKEY. Table 7: Pin Definition of PWRKEY Pin Name Pin No. Description DC Characteristics Comment PWRKEY 15 Turn on the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to VRTC internally with 200KΩ resistor. When UG96 is in power off mode, it can be turned on to normal mode by driving the PWRKEY pin to a low level for at least 100ms. It is recommended to use an open drain/collector driver to control the PWRKEY. After STATUS pin outputting a high level, PWRKEY pin can be released. A simple reference circuit is illustrated in the following figure. Turn on pulse PWRKEY 4.7K 47K ≥100ms Figure 9: Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure.

UG96 Hardware Design UG96_Hardware_Design 30 / 76 PWRKEY S1 Close to S1 TVS Figure 10: Turn on the Module Using Keystroke The turn on scenarios is illustrated as the following figure. VIL≤0.5V VIH ≥1.3V VBAT PWRKEY (Input) ≥100ms OFF BOOTING Module Status RUNNING ≥3.5s RESET_N STATUS >2.3s NOTE Figure 11: Timing of Turning on Module Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms. It is not suggested to pull down PWRKEY pin all the time. 3.7.2. Turn off Module Any of the following methods can be used to turn off the module: ⚫ Normal power down procedure: Turn off the module using command AT+QPOWD. ⚫ Emergency power down procedure: Turn off the module using the PWRDWN_N pin. NOTE

UG96 Hardware Design UG96_Hardware_Design 31 / 76 ⚫ Automatic shutdown: Turn off the module automatically if under-voltage or over-voltage is detected. 3.7.2.1. Turn off Module Using AT Command There are several different ways to turn off the module. It is recommended to turn off the module by command AT+QPOWD. It is a safe way to turn off the module. This command will let the module log off from the network and allow the firmware to save important data before completely disconnecting the power supply. The power down scenario is illustrated as the following figure. VBAT AT+QPOWD Log out from network in 2s~12s RUNNING Power-down procedure OFF Module Status STATUS RXD Figure 12: Timing of Turning off through AT Command During power down procedure, module will log off from network and save important data. After logging off, module sends out “OK”, then sends out “POWERED DOWN” and shuts down the internal power supply. The power on VBAT pins is not allowed to be turned off before the URC “POWERED DOWN” is outputted to avoid data loss. If logging off is not done within 40s, module will shut down internal power supply forcibly. After that moment, module enters into the power down mode, and no other AT commands can be executed except that only the RTC is still active. Please refer to document [1] for details about the command AT+QPOWD. 3.7.2.2. Emergency Shutdown The module can be shut down by the pin PWRDWN_N. It should only be used under emergency situation. The following table shows the pin definition of PWRDWN_N.

UG96 Hardware Design UG96_Hardware_Design 32 / 76 Table 8: Pin Definition of PWRDWN_N Pin Name Pin No. Description DC Characteristics Comment PWRDWN_N 16 Turn off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to VRTC internally with 4.7KΩ resistor. Drive the PWRDWN_N to a low-level voltage for at least 100ms, the module will execute power down procedure after PWRDWN_N is released. It is recommended to use an open drain/collector driver to control the PWRDWN_N. The level of STATUS pin is low after UG96 is turned off. A simple reference circuit is illustrated in the following figure. Turn off pulse PWRDWN_N 4.7K 47K ≥100ms Figure 13: Turn off the Module Using Driving Circuit Another way to control the PWRDWN_N is using a button directly. When pressing the key, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. PWRDWN_N S2 Close to S2 TVS Figure 14: Turn off the Module Using Keystroke

UG96 Hardware Design UG96_Hardware_Design 33 / 76 The emergency shutdown scenario is illustrated as the following figure. VBAT PWRDWN_N ≥100ms RUNNING Power-down procedure OFF STATUS Module Status Figure 15: Timing of Emergency Shutdown PWRDWN_N can only be used when turning off the module by command AT+QPOWD or the RESET_N pin fails. 3.7.2.3. Automatic Shutdown The module will constantly monitor the voltage applied on the VBAT, if the voltage ≤3.5V, the following URC will be presented: +QIND: “vbatt”,-1 If the voltage ≥4.21V, the following URC will be presented: +QIND: “vbatt”,1 The uncritical voltage is 3.3V~4.3V, If the voltage >4.3V or < 3.3V, the module would automatically shut down itself. If the voltage <3.3V, the following URC will be presented: +QIND: “vbatt”,-2 If the voltage >4.3V, the following URC will be presented: +QIND: “vbatt”,2 NOTE

UG96 Hardware Design UG96_Hardware_Design 34 / 76 The value of voltage threshold can be revised by AT command. Please refer to document [1] for details. 3.8. Reset the Module The RESET_N can be used to reset the module. The module can be reset by driving the RESET_N to a low-level voltage for more than 100ms and then releasing. Table 9: Pin Definition of RESET_N Pin Name Pin No. Description DC Characteristics Comment RESET_N 17 Reset signal of the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to VRTC internally with 200KΩ resistor. Active low. The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N. Reset pulse RESET_N 4.7K 47K ≥100ms Figure 16: Reference Circuit of RESET_N by Using Driving Circuit NOTE

UG96 Hardware Design UG96_Hardware_Design 35 / 76 RESET_N S3 Close to S3 TVS Figure 17: Reference Circuit of RESET_N by Using Button The reset scenario is illustrated as the following figure. VBAT RESTARTING Module Status RESET_N RUNNING STATUS RUNNING OFF >5s VIH ≥1.3V >3s VIL≤0.5V ≥100ms Figure 18: Timing of Resetting Module 3.9. RTC Interface The RTC (Real Time Clock) can be powered by an external capacitor through the pin VRTC when the module is powered down and there is no power supply for the VBAT. If the voltage supply at VBAT is disconnected, the RTC can be powered by the capacitor. The capacitance determines the duration of buffering when no voltage is applied to UG96. The capacitor is charged from the internal LDO of UG96 when there is power supply for the VBAT. A serial 1KΩ resistor has been placed on the application inside the module. It limits the input current of the capacitor.

UG96 Hardware Design UG96_Hardware_Design 36 / 76 The following figure shows the reference circuit for VRTC backup. Large Capacitance Capacitor Module RTC Core 1K VRTC C Figure 19: RTC Supply from Capacitor In order to evaluate the capacitance of capacitor according to the backup time, the following parameters should be considered: ⚫ VRTC - The starting voltage of the capacitor. (Volt) ⚫ VRTCMIN - The minimum voltage acceptable for the RTC circuit. (Volt) ⚫ I - The current consumption of the RTC circuitry when VBAT=0. (Ampere) ⚫ B Time - Backup Time. (Second) ⚫ C - The backup capacitance. (Farad) When the power is off and only VRTC is running, the way of calculating the backup capacitor is as follows: C=B Time *I/ (VRTC-VRTCMIN) For example, when the capacitor is 1000uF: ⚫ VRTC=1.8V ⚫ VRTCMIN=1.0V ⚫ I=2uA ⚫ C=1000uF The backup time is about 400s. 3.10. UART Interface The module provides 7-wire UART interface. The UART interface supports 300bps, 1200bps, 2400bps, 4800bps, 9600bps, 19200bps, 38400bps, 57600bps, 115200bps, 230400bps, 460800bps and 921600bps baud rates, and the default is auto-baud rate 4800bps~115200bps. This interface can be used for data transmission, AT command communication and firmware upgrade.

UG96 Hardware Design UG96_Hardware_Design 37 / 76 The module is designed as DCE (Data Communication Equipment). The following table shows the pin definition of UART interface. Table 10: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment DTR 30 DI Data terminal ready. Sleep mode control. 1.8V power domain RXD 34 DI Receive data 1.8V power domain TXD 35 DO Transmit data 1.8V power domain CTS 36 DO Clear to send 1.8V power domain RTS 37 DI Request to send 1.8V power domain DCD 38 DO Data carrier detection 1.8V power domain RI 39 DO Ring indicator 1.8V power domain The logic levels are described in the following table. Table 11: Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.35 V VIH 1.3 1.85 V VOL 0 0.25 V VOH 1.55 1.8 V UG96 provides one 1.8V UART interface. A level translator should be used if customers’ application is equipped with a 3.3V UART interface, and TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design.

UG96 Hardware Design UG96_Hardware_Design 38 / 76 VCCA VCCB OE A1 A2 A3 A4 A5 A6 A7 A8 GND B1 B2 B3 B4 B5 B6 B7 B8 VDD_EXT RI DCD RTS RXD DTR CTS TXD 51K 51K 0.1uF 0.1uF RI_3.3V DCD_3.3V RTS_3.3V RXD_3.3V DTR_3.3V CTS_3.3V TXD_3.3V VDD_3.3V TXS0108EPWR 10K 120K Figure 20: Reference Circuit of Logic Level Translator Please visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below. The circuit design of dotted line section can refer to the design of solid line section. Please pay attention to the direction of connection. The transistor translation circuit supports a maximum data rate of 0.5Mbps. MCU/ARM /TXD /RXD VDD_EXT 4.7K VCC_MCU 4.7K 4.7K VDD_EXT TXD RXD RTS CTS DTR RI /RTS /CTS GND GPIO DCD Module GPIO EINT VDD_EXT 4.7K GND 1nF 1nF Figure 21: Reference Circuit with Transistor Circuit The following figure is an example of connection between UG96 and PC. A voltage level translator and a RS-232 level translator chip must be inserted between module and PC, since the UART interface does not support the RS-232 level, while supports the 1.8V CMOS level only.

UG96 Hardware Design UG96_Hardware_Design 39 / 76 TXS0108EPWR DCD_3.3V RTS_3.3V DTR_3.3V RXD_3.3V RI_3.3V CTS_3.3V TXD_3.3V DCD RTS DTR RXD RI CTS TXD DCD_1.8V RTS_1.8V DTR_1.8V RXD_1.8V RI_1.8V CTS_1.8V TXD_1.8V VCCA Module GND GND VDD_EXT VCCB 3.3V DIN1 ROUT3 ROUT2 ROUT1 DIN4 DIN3 DIN2 DIN5 R1OUTB FORCEON /FORCEOFF /INVALID 3.3V DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 RIN3 RIN2 RIN1 VCC GND OE Translator DB9M PC side DCD RTS DTR TXD RI CTS RXD DSR GND 1 2 3 4 5 6 7 8 9 Figure 22: RS232 Level Match Circuit 1. The module disables the hardware flow control by default. When hardware flow control is required, RTS and CTS should be connected to the host. Command AT+IFC=2,2 is used to enable hardware flow control and AT+IFC=0,0 is used to disable the hardware flow control. For more details, please refer to document [1]. 2. Rising edge on DTR will let the module exit from the data mode by default, and it can be disabled by AT commands. Please refer to document [1] for details. 3. DCD is used as data mode indication. Please refer to document [1] for details. 4. It is suggested that USB_DP, USB_DM and USB_VBUS pins should be set as test points and then be placed on DTE for debugging. 3.11. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards are supported. Table 12: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_PRESENCE 42 DI (U)SIM card insertion detection 1.8V power domain. USIM_VDD 43 PO Power supply for (U)SIM card Either 1.8V or 3.0V is supported by the module NOTES

UG96 Hardware Design UG96_Hardware_Design 40 / 76 automatically. USIM_RST 44 DO Reset signal of (U)SIM card USIM_DATA 45 IO Data signal of (U)SIM card Pull-up to USIM_VDD with 4.7k resistor internally. USIM_CLK 46 DO Clock signal of (U)SIM card USIM_GND 47 Specified ground for (U)SIM card UG96 supports (U)SIM card hot-plug via the USIM_PRESENCE pin. The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector. USIM_VDD USIM_GND/GND USIM_RST USIM_CLK USIM_DATA USIM_PRESENCE 22R 22R 22R VDD_EXT 51K 100nF GND GND ESD 33pF 33pF 33pF VCC RST CLK IO VPP GND GND USIM_VDD 15K Module (U)SIM card connector Figure 23: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_PRESENCE unconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.

UG96 Hardware Design UG96_Hardware_Design 41 / 76 Module USIM_VDD USIM_GND USIM_RST USIM_CLK USIM_DATA 22R 22R 22R 100nF GND ESD 33pF 33pF 33pF VCC RST CLK IO VPP GND GND 15K USIM_VDD (U)SIM card connector Figure 24: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in customer’s applications, please follow the criteria below in (U)SIM circuit design: ⚫ Keep placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200mm as possible. ⚫ Keep (U)SIM card signal away from RF and VBAT traces. ⚫ Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground no less than 0.5mm to maintain the same electric potential. Make sure the decouple capacitor between USIM_VDD and USIM_GND less than 1μF and be placed as close to the (U)SIM card connector as possible. ⚫ To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away with each other and shield them with surrounded ground. ⚫ In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 15pF. The 22Ω resistors should be added in series between the module and the (U)SIM card so as to suppress the EMI spurious transmission and enhance the ESD protection. The 33pF capacitors are used for filtering interference of EGSM900. Please note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. ⚫ The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace and sensitive occasion are applied, and should be placed close to the (U)SIM card connector. 3.12. USB Interface UG96 contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports high speed (480Mbps) and full speed (12Mbps) modes. The USB interface is

UG96 Hardware Design UG96_Hardware_Design 42 / 76 used for AT command communication, data transmission, software debugging and firmware upgrade. The following table shows the pin definition of USB interface. Table 13: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_DP 9 IO USB differential data bus (+) Require differential impedance of 90Ω. USB_DM 10 IO USB differential data bus (-) Require differential impedance of 90Ω. USB_VBUS 8 PI USB detection 2.5V~5.25V. Typically 5.0V. For more details about the USB 2.0 specification, please visit http://www.usb.org/home. The following figure shows a reference circuit of USB interface. Module USB_VBUS USB_DP USB_DM GND USB connector Close to USB connector Differential layout USB_VBUS USB_DP USB_DM GND NM_2pF ESD NM NM Rs Rs Figure 25: Reference Circuit of USB Interface The following principles should be complied with when design the USB interface, so as to meet USB 2.0 specification. ⚫ It is important to route the USB signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90Ω. ⚫ Pay attention to the influence of junction capacitance of ESD protection components on USB data lines. Typically, the capacitance value should be less than 2pF. ⚫ Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. ⚫ Keep the ESD protection components as close to the USB connector as possible.

UG96 Hardware Design UG96_Hardware_Design 43 / 76 ⚫ The RC circuit is suggested to be reserved near USB connector for debugging. The USB interface is recommended to be reserved for firmware upgrade in customers’ design. The following figure shows the recommended test points. Module USB_DM USB_DP VBAT_BB USB_VBUS PWRKEY GND VBAT_RF USB_DM USB_DP VBAT USB_VBUS PWRKEY GND USB Connector Figure 26: Test Points of Firmware Upgrade 1. UG96 module can only be used as a slave device. 2. It is suggested that USB_DP, USB_DM and USB_VBUS pins should be set as test points and be placed on DTE for debugging. 3. USB interface supports software debugging and firmware upgrade by default. 3.13. PCM and I2C Interfaces UG96 provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports the following modes. It also supports one I2C interface. ⚫ Supports 16/32-bit mode with short frame synchronization. The PCM supports 32-bit mode by default. The default command for PCM codec configuration is AT+QDAC=1. Please refer to document [1] for more details. ⚫ Supports master and slave modes. ⚫ Supports audio sample rate 8KHz. The following table shows the pin definition of PCM and I2C interfaces. NOTES

UG96 Hardware Design UG96_Hardware_Design 44 / 76 Table 14: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK 4 DO PCM data bit clock 1.8V power domain PCM_SYNC 5 DO PCM data frame synchronization signal 1.8V power domain PCM_IN 6 DI PCM data input 1.8V power domain PCM_OUT 7 DO PCM data output 1.8V power domain I2C_SCL 40 OD I2C serial clock Require external pull-up resistor. I2C_SDA 41 OD I2C serial data Require external pull-up resistor. CLK_OUT 25 DO Clock output Provide a digital clock output for an external audio codec. If unused, keep it open. In PCM audio format, the MSB of the channel included in the frame (PCM_SYNC) is clocked on the second CLK rising edge after the PCM_SYNC pulse rising edge. The period of the PCM_SYNC signal (frame) lasts for data word bit +1 clock pulses. UG96’s firmware has integrated the configurations on NAU8814 /ALC5616/MAX9860 application with I2C interface. AT+QDAC command is used to configure the external codec chip linked with PCM interface, and refer to document [1] for more details. Data bit is 32 bit and the sampling rate is 8KHz. The following figure shows the timing of the application with ALC5616 codec. PCM_CLK PCM_SYNC PCM_IN/OUT 32 1 0 31 Sampling freq.=8KHz 32-bit data word BCLK=264KHz 33 MSB Figure 27: PCM Master Mode Timing In general, the BitClockFrequency (BCLK) is calculated by the following expression: BitClockFrequency=(DataWordBit+1) × SamplingFrequency

UG96 Hardware Design UG96_Hardware_Design 45 / 76 The following figure shows a reference design of PCM interface with external codec IC. PCM_IN PCM_OUT PCM_SYNC PCM_CLK I2C_SCL I2C_SDA CODEC Module VDD_EXT 1K 1K BCLK LRCLK DACDAT ADCDAT SCL SDA BIAS MICBIAS MIC+ MIC- SPK+ SPK- CLK_OUT MCLK Rs NM Figure 28: Reference Circuit of PCM Master Mode Application with Audio Codec PCM_IN PCM_OUT PCM_SYNC PCM_CLK I2C_SCL I2C_SDA CODEC Module VDD_EXT 1K 1K BCLK LRCLK DACDAT ADCDAT SCL SDA BIAS MICBIAS MIC+ MIC- SPK+ SPK- CLK_OUT MCLK Rs NM Figure 29: Reference Circuit of PCM Slave Mode Application with Audio Codec 1. It is recommended to reserve RC (e.g. R=22Ω, C=22pF) circuit on the PCM lines, especially for PCM_CLK. 2. UG96 module provides a digital clock output (CLK_OUT) for an external audio codec, the CLK_OUT function is disabled by default. When CLK_OUT is required, AT command is used to provide the NOTES

UG96 Hardware Design UG96_Hardware_Design 46 / 76 codec with a 13/26MHz clock generated from the module. Please refer to document [1] for details. If unused, keep it open. 3. A RC (e.g. R=22Ω, C=47pF) circuit is recommended to be reserved on CLK_OUT line. If external audio CODEC is MAX9860, the RC circuit should be mounted; if it is ALC5616, then it is not mounted. 4. There is a need to provide a 2.048M main clock for MCLK pin if the external audio CODEC is NAU8814. 3.14. Network Status Indication The NETLIGHT signal can be used to drive a network status indication LED. The following tables describe the pin definition and logic level changes in different network status. Table 15: Pin Definition of NETLIGHT Pin Name Pin No. I/O Description Comment NETLIGHT 21 DO Indicate the module network status 1.8V power domain Table 16: Working State of NETLIGHT Pin Name Status Description NETLIGHT PWM (200ms High/1800ms Low) Network searching PWM (1800ms High/200ms Low) Idle & Data transfer Always High Voice & CSD calling A reference circuit is shown in the following figure. 4.7K 47K VBAT 2.2K Module NETLIGHT Figure 30: Reference Circuit of the Network Status Indicator

UG96 Hardware Design UG96_Hardware_Design 47 / 76 3.15. STATUS The STATUS pin is used to indicate the operation status of UG96 module. It will output high level when the module is powered on. The following table describes the pin definition of STATUS. Table 17: Pin Definition of STATUS Pin Name Pin No. I/O Description Comment STATUS 20 DO Indicate the module’s operation status 1.8V power domain A reference circuit is shown as following figure. 4.7K 47K VBAT 2.2K Module STATUS Figure 31: Reference Circuit of STATUS

UG96 Hardware Design UG96_Hardware_Design 48 / 76 4 Antenna Interface UG96 includes a GSM/UMTS antenna interface. The RF interface has an impedance of 50Ω. 4.1. GSM/UMTS Antenna Interface 4.1.1. Pin Definition The pin definition of the RF antenna is shown below. Table 18: Pin Definition of RF Antenna Pin Name Pin No. I/O Description Comment GND 58 Ground GND 59 Ground RF_ANT 60 IO RF antenna pad 50Ω impedance GND 61 Ground GND 62 Ground 4.1.2. Operating Frequency Table 19: Module Operating Frequencies Band Receive Transmit Unit GSM850 869~894 824~849 MHz EGSM900 925~960 880~915 MHz DCS1800 1805~1880 1710~1785 MHz PCS1900 1930~1990 1850~1910 MHz

UG96 Hardware Design UG96_Hardware_Design 49 / 76 UMTS2100 2110~2170 1920~1980 MHz UMTS1900 1930~1990 1850~1910 MHz UMTS900 925~960 880~915 MHz UMTS850 869~894 824~849 MHz UMTS800 875~885 830~840 MHz 4.1.3. Reference Design of RF Antenna Interface A reference design of RF antenna interface is recommended as below. A π-type matching circuit should be reserved for better RF performance, and the π-type matching components (R1/C1/C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. RF_ANT R1 0R C1 NM C2 NM Module Figure 32: Reference Circuit of RF Antenna Interface UG96 provides an RF antenna pad for customers’ antenna connection. The RF trace in host PCB connected to the module’s RF antenna pad should be micro-strip line or other types of RF traces, whose characteristic impendence should be close to 50Ω. UG96 comes with grounding pads which are next to the antenna pad in order to give a better grounding. 4.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic impedance control. The following are reference designs of microstrip line or coplanar waveguide line with different PCB structures

UG96 Hardware Design UG96_Hardware_Design 50 / 76 . Figure 33: Microstrip Line Design on a 2-layer PCB Figure 34: Coplanar Waveguide Line Design on a 2-layer PCB Figure 35: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)

UG96 Hardware Design UG96_Hardware_Design 51 / 76 Figure 36: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: ⚫ Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω. ⚫ The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. ⚫ The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. ⚫ There should be clearance area under the signal pin of the antenna connector or solder joint. ⚫ The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W). For more details about RF layout, please refer to document [7]. 4.2. Antenna Installation 4.2.1. Antenna Requirements The following table shows the requirements on GSM/UMTS antenna. Table 20: Antenna Cable Requirements Type Requirements GSM850/EGSM900 UMTS800/850/900 Cable insertion loss <1dB

UG96 Hardware Design UG96_Hardware_Design 52 / 76 DCS1800/PCS1900 UMTS1900/2100 Cable insertion loss <1.5dB Table 21: Antenna Requirements Type Requirements Frequency Range GSM 4-band: 850/900/1800/1900MHz UMTS 5-band: 800/850/900/1900/2100MHz VSWR <2:1 recommended, <3:1 acceptable Gain (dBi) 1 typical Max Input Power (W) 50 Input Impedance (Ω) 50 Polarization Type Vertical 4.2.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connector provided by HIROSE. Figure 37: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.

UG96 Hardware Design UG96_Hardware_Design 53 / 76 Figure 38: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector Figure 39: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.

UG96 Hardware Design UG96_Hardware_Design 54 / 76 5 Electrical, Reliability and Radio Characteristics 5.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 22: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 2 A Voltage at Digital Pins -0.3 2.3 V 5.2. Power Supply Ratings Table 23: Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF The actual input voltages must stay between the minimum and maximum values. 3.3 3.8 4.3 V

UG96 Hardware Design UG96_Hardware_Design 55 / 76 Voltage drop during burst transmission Maximum power control level on GSM900 400 mV IVBAT Peak supply current (during transmission slot) Maximum power control level on GSM900 1.8 2.0 A USB_VBUS USB detection 2.5 5.0 5.25 V 5.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table. Table 24: Operation and Storage Temperatures Parameter Min. Typ. Max. Unit Operation Temperature Range1) -35 +25 +75 ºC Extended Temperature Range2) -40 +85 ºC Storage Temperature Range -40 +90 ºC 1. 1) Within operation temperature range, the module is 3GPP compliant. 2. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 5.4. Current Consumption The values of current consumption are shown below. NOTES

UG96 Hardware Design UG96_Hardware_Design 56 / 76 Table 25: Current Consumption Parameter Description Conditions Min. Typ. Max. Unit IVBAT OFF state supply current Power down 100 uA GSM/GPRS supply current Sleep (USB disconnected) @DRX=2 1.13 mA Sleep (USB disconnected) @DRX=5 1.10 mA Sleep (USB disconnected) @DRX=9 1.00 mA WCDMA supply current Sleep (USB disconnected) @DRX=6 2.52 mA Sleep (USB disconnected) @DRX=7 1.82 mA Sleep (USB disconnected) @DRX=8 1.75 mA Sleep (USB disconnected) @DRX=9 1.76 mA Idle (USB disconnected) @DRX=6 12.4 mA Idle (USB connected) @DRX=6 32.1 mA GPRS data transfer GSM850 1DL/1UL PCL=5 263 mA GSM850 5DL/1UL PCL=5 272 mA GSM850 4DL/2UL PCL=5 460 mA GSM850 3DL/3UL PCL=5 465 mA GSM850 2DL/4UL PCL=5 495 mA EGSM900 1DL/1UL PCL=5 267 mA EGSM900 5DL/1UL PCL=5 276 mA EGSM900 4DL/2UL PCL=5 475 mA EGSM900 3DL/3UL PCL=5 495 mA EGSM900 2DL/4UL PCL=5 525 mA DCS1800 1DL/1UL PCL=0 175 mA DCS1800 5DL/1UL PCL=0 193 mA

UG96 Hardware Design UG96_Hardware_Design 57 / 76 DCS1800 4DL/2UL PCL=0 302 mA DCS1800 3DL/3UL PCL=0 413 mA DCS1800 2DL/4UL PCL=0 523 mA PCS1900 1DL/1UL PCL=0 189 mA PCS1900 5DL/1UL PCL=0 196 mA PCS1900 4DL/2UL PCL=0 310 mA PCS1900 3DL/3UL PCL=0 425 mA PCS1900 2DL/4UL PCL=0 545 mA EDGE data transfer GSM850 1DL/1UL PCL=8 187 mA GSM850 5DL/1UL PCL=8 199 mA GSM850 4DL/2UL PCL=8 308 mA GSM850 3DL/3UL PCL=8 417 mA GSM850 2DL/4UL PCL=8 528 mA EGSM900 1DL/1UL PCL=8 184 mA EGSM900 5DL/1UL PCL=8 205 mA EGSM900 4DL/2UL PCL=8 307 mA EGSM900 3DL/3UL PCL=8 420 mA EGSM900 2DL/4UL PCL=8 525 mA DCS1800 1DL/1UL PCL=2 197 mA DCS1800 5DL/1UL PCL=2 205 mA DCS1800 4DL/2UL PCL=2 312 mA DCS1800 3DL/3UL PCL=2 416 mA DCS1800 2DL/4UL PCL=2 525 mA PCS1900 1DL/1UL PCL=2 200 mA PCS1900 5DL/1UL PCL=2 207 mA

UG96 Hardware Design UG96_Hardware_Design 58 / 76 PCS1900 4DL/2UL PCL=2 316 mA PCS1900 3DL/3UL PCL=2 422 mA PCS1900 2DL/4UL PCL=2 530 mA WCDMA data transfer UMTS2100 HSDPA @max power 573 mA UMTS2100 HSUPA @max power 540 mA UMTS1900 HSDPA @max power 595 mA UMTS1900 HSUPA @max power 567 mA UMTS900 HSDPA @max power 513 mA UMTS900 HSUPA @max power 489 mA UMTS850/800 HSDPA @max power 537 mA UMTS850/800 HSUPA @max power 493 mA GSM voice call GSM850 @PCL=5 238 mA EGSM900 @PCL=5 242 mA DCS1800 @PCL=0 164 mA PCS1900 @PCL=0 176 mA WCDMA voice call UMTS2100 @max power 465 mA UMTS1900 @max power 475 mA UMTS900 @max power 457 mA UMTS850/800 @max power 493 mA 5.5. RF Output Power The following table shows the RF output power of UG96 module.

UG96 Hardware Design UG96_Hardware_Design 59 / 76 Table 26: RF Output Power Frequency Max. Min. GSM850 33dBm±2dB 5dBm±5dB EGSM900 33dBm±2dB 5dBm±5dB DCS1800 30dBm±2dB 0dBm±5dB PCS1900 30dBm±2dB 0dBm±5dB GSM850 (8-PSK) 27dBm±3dB 5dBm±5dB EGSM900 (8-PSK) 27dBm±3dB 5dBm±5dB DCS1800 (8-PSK) 26dBm±3dB 0dBm±5dB PCS1900 (8-PSK) 26dBm±3dB 0dBm±5dB UMTS2100 24dBm+1.7/-3.7dB <-50dBm UMTS1900 24dBm+1.7/-3.7dB <-50dBm UMTS900 24dBm+1.7/-3.7dB <-50dBm UMTS850/800 24dBm+1.7/-3.7dB <-50dBm In GPRS 4 slots TX mode, the maximum output power is reduced by 3.0dB. The design conforms to the GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1. 5.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of UG96 module. Table 27: Conducted RF Receiving Sensitivity Frequency Receive Sensitivity (Typ.) GSM850 -109.6dBm EGSM900 -108.5dBm NOTE

UG96 Hardware Design UG96_Hardware_Design 60 / 76 DCS1800 -110dBm PCS1900 -108dBm UMTS850/800 -110dBm UMTS900 -110dBm UMTS1900 -109.5dBm UMTS2100 -110.5dBm 5.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the module’s electrostatic discharge characteristics. Table 28: Electrostatic Discharge Characteristics It is recommended to add a 100nF capacitor to RESET_N and PWRDWN_N pins respectively to improve ESD performance. Tested Point Contact Discharge Air Discharge VBAT, GND +/-4KV +/-10KV RF_ANT +/-4KV +/-8KV Others +/-0.5KV +/-1KV NOTE

UG96 Hardware Design UG96_Hardware_Design 61 / 76 6 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm). The tolerances for dimensions without tolerance values are ±0.05mm. 6.1. Mechanical Dimensions of the Module Figure 40: Module Top and Side Dimensions

UG96 Hardware Design UG96_Hardware_Design 62 / 76 Figure 41: Module Bottom Dimensions (Top View)

UG96 Hardware Design UG96_Hardware_Design 63 / 76 6.2. Recommended Footprint Design Figure 42: Recommended Footprint (Top View) 1. For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB. 2. All RESERVED pins should be kept open and MUST NOT be connected to ground. NOTES

UG96 Hardware Design UG96_Hardware_Design 64 / 76 6.3. Top and Bottom Views of the Module Figure 43: Top View of the Module Figure 44: Bottom View of the Module These are renderings of UG96 module. For authentic dimension and appearance, please refer to the module that you receive from Quectel. NOTE

UG96 Hardware Design UG96_Hardware_Design 65 / 76 7 Storage, Manufacturing and Packaging 7.1. Storage UG96 is stored in the vacuum-sealed bag. It is rated at MSL 3 and its storage restrictions are shown as below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/<90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be: ⚫ Mounted within 168 hours at the factory conditions of ≤30ºC/<60%RH. ⚫ Stored at <10%RH. 3. Devices require baking before mounting, if any circumstance below occurs. ⚫ When the ambient temperature is 23ºC±5ºC and the humidity indication card shows the humidity is >10% before opening the vacuum-sealed bag. ⚫ Device mounting cannot be finished within 168 hours at factory conditions of ≤30ºC/60%RH. 4. If baking is required, devices may be baked for 8 hours at 120ºC±5ºC. As the plastic package cannot be subjected to high temperature, it should be removed from devices before high temperature (120ºC) baking. If shorter bake times are desired, please refer to IPC/JEDECJ-STD-033 for bake procedure. NOTE

UG96 Hardware Design UG96_Hardware_Design 66 / 76 7.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.18mm~0.20mm. For more details, please refer to document [6]. It is suggested that the peak reflow temperature is 240~245ºC, and the absolute maximum reflow temperature is 245ºC. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Temp. (°C) Reflow Zone Soak Zone 245 200 220 240 C D B A 150 100 Max slope: 1~3°C/sec Cooling down slope: 1~4°C/sec Max slope: 2~3°C/sec Figure 45: Reflow Soldering Thermal Profile 1. During manufacturing and soldering, or any other processes that may contact the module directly, NEVER wipe the module’s shielding can with organic solvents, such as acetone, ethyl alcohol, isopropyl alcohol, trichloroethylene, etc. Otherwise, the shielding can may become rusted. 2. The shielding can for the module is made of Cupro-Nickel base material. It is tested that after 12 hours’ Neutral Salt Spray test, the laser engraved label information on the shielding can is still clearly identifiable and the 2D barcode is still readable, although white rust may be found. NOTES

UG96 Hardware Design UG96_Hardware_Design 67 / 76 7.3. Packaging UG96 is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application. The reel is 330mm in diameter and each reel contains 250 modules. The following figures show the packaging details, measured in mm. Figure 46: Tape Dimensions

UG96 Hardware Design UG96_Hardware_Design 68 / 76 Direction of feed Cover tape 13 100 44.5+0.20 -0.00 48.5 Figure 47: Reel Dimensions Table 29: Reel Packing Model Name MOQ for MP Minimum Package: 250pcs Minimum Package x 4=1000pcs UG96 250pcs Size: 370mm × 350mm × 56mm N.W: 0.78kg G.W: 1.46kg Size: 380mm × 250mm × 365mm N.W: 3.1kg G.W: 6.45kg

UG96 Hardware Design UG96_Hardware_Design 69 / 76 8 Appendix A References Table 30: Related Documents SN Document Name Remark [1] Quectel_WCDMA_UGxx_AT_Commands_Manual UGxx AT commands manual [2] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB user guide [3] Quectel_UG96_Reference_Design UG96 reference design [4] Quectel_UG96&UG95&M95 R2.0_Reference_Design UG96, UG95 and M95 R2.0 compatible reference design [5] Quectel_UG96&UG95&M95 R2.0_Compatible_ Design UG96, UG95 and M95 R2.0 compatibility design specification [6] Quectel_Module_Secondary_SMT_User_Guide Module secondary SMT user guide [7] Quectel_RF_Layout_Application_Note RF layout application note Table 31: Terms and Abbreviations Abbreviation Description AMR Adaptive Multi-rate ARP Antenna Reference Point bps Bits Per Second CHAP Challenge Handshake Authentication Protocol CS Coding Scheme CSD Circuit Switched Data CTS Clear To Send DRX Discontinuous Reception DCE Data Communications Equipment (typically module)

UG96 Hardware Design UG96_Hardware_Design 70 / 76 DTE Data Terminal Equipment (typically computer, external controller) DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate EGSM Extended GSM900 band (includes standard GSM900 band) ESD Electrostatic Discharge FR Full Rate GMSK Gaussian Minimum Shift Keying GPS Global Positioning System GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packet Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access I/O Input/Output IMEI International Mobile Equipment Identity Imax Maximum Load Current Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier Mbps Mbits per second MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol

UG96 Hardware Design UG96_Hardware_Design 71 / 76 PBCCH Packet Broadcast Control Channel PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol PSK Phase Shift Keying PWM Pulse Width Modulation QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized RMS Root Mean Square (value) RTC Real Time Clock Rx Receive SIM Subscriber Identification Module SMS Short Message Service TDMA Time Division Multiple Access TE Terminal Equipment TX Transmitting Direction UART Universal Asynchronous Receiver & Transmitter UMTS Universal Mobile Telecommunications System URC Unsolicited Result Code USIM Universal Subscriber Identity Module USSD Unstructured Supplementary Service Data Vmax Maximum Voltage Value Vnorm Normal Voltage Value

UG96 Hardware Design UG96_Hardware_Design 72 / 76 Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access

UG96 Hardware Design UG96_Hardware_Design 73 / 76 9 Appendix B GPRS Coding Schemes Table 32: Description of Different Coding Schemes Scheme Code Rate USF Pre-coded USF Radio Block excl.USF and BCS BCS Tail Coded Bits Punctured Bits Data Rate Kb/s CS-1 1/2 3 3 181 40 4 456 0 9.05 CS-2 2/3 3 6 268 16 4 588 132 13.4 CS-3 3/4 3 6 312 16 4 676 220 15.6 CS-4 1 3 12 428 16 - 456 - 21.4

UG96 Hardware Design UG96_Hardware_Design 74 / 76 10 Appendix C GPRS Multi-slot Classes Thirty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependant, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots. The active slots determine the total number of slots the GPRS device can use simultaneously for both uplink and downlink communications. The description of different multi-slot classes is shown in the following table. Table 33: GPRS Multi-slot Classes Multislot Class Downlink Slots Uplink Slots Active Slots 1 1 1 2 2 2 1 3 3 2 2 3 4 3 1 4 5 2 2 4 6 3 2 4 7 3 3 4 8 4 1 5 9 3 2 5 10 4 2 5 11 4 3 5 12 4 4 5 13 3 3 NA 14 4 4 NA

UG96 Hardware Design UG96_Hardware_Design 75 / 76 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 6 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6

UG96 Hardware Design UG96_Hardware_Design 76 / 76 11 Appendix D EDGE Modulation and Coding Schemes Table 34: EDGE Modulation and Coding Schemes Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.8kbps 29.6kbps 59.2kbps MCS-4 GMSK C 17.6kbps 35.2kbps 70.4kbps MCS-5 8-PSK B 22.4kbps 44.8kbps 89.6kbps MCS-6 8-PSK A 29.6kbps 59.2kbps 118.4kbps MCS-7 8-PSK B 44.8kbps 89.6kbps 179.2kbps MCS-8 8-PSK A 54.4kbps 108.8kbps 217.6kbps MCS-9 8-PSK A 59.2kbps 118.4kbps 236.8kbps