Cypress Semiconductor CY7C1336H Specification Sheet
Text of the manual
2-Mbit (64K x 32) Flow-Through Sync SRAM
CY7C1336H
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 001-00210 Rev. *A
Revised February 6, 2006
Features
• 64K x 32 common I/O
• 3.3V core power supply
• 3.3V I/O supply
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
Document #: 001-00210 Rev. *A
Page 2 of 15
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.0
ns
Maximum Operating Current
225
205
mA
Maximum Standby Current
40
40
mA
Pin Configuration
100-pin TQFP Pinout
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/9M
A
A
A
A
A
NC/4M
NC
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
Document #: 001-00210 Rev. *A
Page 3 of 15
Pin Definitions
Name
I/O
Description
A0, A1,
A
Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit
counter.
BWA,
BWB
BWC,
BWD
Input
Document #: 001-00210 Rev. *A
Page 4 of 15
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
The CY7C1336H supports secondary cache in systems
utilizing either a linear or interleaved burst sequen
Document #: 001-00210 Rev. *A
Page 5 of 15
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ Active to sleep current
This parameter is sa
