Basler racer Manual 

GRABBER DESIGNERS Document Number: AW001187 Version: 02 Language: 000 (English) Release Date: 1 February 2013 Applies to prototype cameras only. All content is subject to change. DRAFT

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. You are cautioned that any changes or modifications not expressly approved in this manual could void your authority to operate this equipment. The shielded interface cable recommended in this manual must be used with this equipment in order to comply with the limits for a computing device pursuant to Subpart J of Part 15 of FCC Rules. For customers in Canada This apparatus complies with the Class A limits for radio noise emissions set out in Radio Interference Regulations. Pour utilisateurs au Canada Cet appareil est conforme aux normes Classe A pour bruits radioélectriques, spécifiées dans le Règlement sur le brouillage radioélectrique. Life Support Applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Basler customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Basler for any damages resulting from such improper use or sale. Warranty Note Do not open the housing of the camera. The warranty becomes void if the housing is opened. All material in this publication is subject to change without notice and is copyright Basler AG.

Europe: Basler AG An der Strusbek 60 - 62 22926 Ahrensburg Germany Tel.: +49-4102-463-515 Fax.: +49-4102-463-599 [email protected] Americas: Basler, Inc. 855 Springdale Drive, Suite 203 Exton, PA 19341 U.S.A. Tel.: +1-610-280-0171 Fax.: +1-610-280-7608 [email protected] Asia: Basler Asia Pte. Ltd. 8 Boon Lay Way # 03 - 03 Tradehub 21 Singapore 609964 Tel.: +65-6425-0472 Fax.: +65-6425-0473 [email protected] www.baslerweb.com

Basler racer Camera Link i Table of Contents 1 Camera Link Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 SDR Connector Pin Assignments and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Electrical Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Camera Link Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4.1 Serial to Camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4.2 External Line Start Trigger (ExLSTrig) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5 Camera Link Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.1 Serial to Frame Grabber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.2 Pixel Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.3 Line Valid Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5.4 Data Valid Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.5 CL Spare Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.6 Pixel Data Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.6.1 1X Tap Geometry – 8, 10, or 12 Bit Pixel Depth . . . . . . . . . . . . . 14 1.5.6.2 1X2 Tap Geometry – 8, 10, or 12 Bit Pixel Depth . . . . . . . . . . . . 15 1.5.6.3 1X4 Tap Geometry – 8, 10, or 12 Bit Pixel Depth . . . . . . . . . . . . 16 1.5.6.4 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth. . . . . . . . . . . . . . . . 18 1.5.6.5 1X10 Tap Geometry – 8 Bit Pixel Depth . . . . . . . . . . . . . . . . . . . 21 2 Pixel Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 Data Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 Pixel Clock Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 Camera Link Tap Geometries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.1 Factors Influencing the Timing of Pixel Data Transmission . . . . . . . . . . . . . . 26 2.3.1.1 Camera Link Pixel Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.1.2 Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.2 1X Tap Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.3 1X2 Tap Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.4 1X4 Tap Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.5 1X8 Tap Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.6 1X10 Tap Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Basler racer Camera Link 1 1 Camera Link Implementation 1.1 Overview The Basler racer Camera Link camera transmits Camera Link data in a fashion similar to devices that use National Semiconductor DS90CR287 transmitters. For Camera Link receivers on your frame grabber, we recommend that you use the National Semiconductor DS90CR288A or an equivalent. The camera receives the RS-644 camera control input signals and the serial communication input signal defined in the Camera Link specification in a fashion similar to devices that use National Semiconductor DS90LV048A differential line receivers. The serial communication output signal defined in the specification is transmitted in a fashion similar to devices that use a DS90LV047A differential line transmitter. Detailed data sheets for the National Semiconductor components are available at the National Semiconductor web site (www.national.com). The data sheets contain all of the information, including application notes, that you need to implement Camera Link. All camera models have two 26-pin SDR connectors with 0.03" pin spacing as specified in the Camera Link standard. Table 2 on page 3 and Table 3 on page 4 show the pin assignments for the SDR connectors. The "SDR" (Shrunk Delta Ribbon) designation is the naming used by the 3M company. Other companies use different names for this type of connector. For example, Honda uses "HDR" as the connector name. 6-pin Receptacle (Power) LED Indicator with Green and Red LED Fig. 1: Camera Connections of Basler racer Camera Link Cameras 26-pin SDR Connector (Base Camera Link Connection; Power and Data) 26-pin SDR Connector (Medium/Full Camera Link Connection; Data Functional Earth Connection

AW00118702000 2 Basler racer Camera Link All camera models implement the "base", "medium", and "full" configurations as defined in the Camera Link standard. Individual differential line transmitter circuits support the respective Camera Link configurations: Transmitter X supports the base configuration, transmitter Y partly supports the medium configuration and partly the full configuration, and transmitter Z supports full configuration. The determination of whether a camera will operate in the base, medium, or full configuration depends on the camera’s current tap geometry setting as shown Table 1. 1.2 SDR Connector Pin Assignments and Numbering Two 26-pin, 0.03” pin spacing, Shrunk Delta Ribbon (SDR) female connectors are used on the camera. The pin assignments and pin numbering for the base connector are as shown in Table 2 and for the medium/full connector are as shown in Table 3 on page 4. Camera Link Tap Geometry Setting Available Pixel Bit Depths for Mono Cameras Camera Link Configuration Camera Link Connectors Used to Transmit Data Camera Link Transmitters Used to Transmit Data 1X 8 bit, 10 bit, 12 bit Base Base Only X 1X2 8 bit, 10 bit, 12 bit Base Base Only X 1X4 8 bit, 10 bit, 12 bit Medium Base and Medium/Full X and Y 1X8 8 bit, 10 bit Full (Octo) Base and Medium/Full X, Y, and Z 1X10 8 bit Full (Deca) Base and Medium/Full X, Y, and Z Table 1: Camera Link Details at Various Tap Geometry Settings

Basler racer Camera Link 3 Pin Number Signal Name Direction Level Function 1, 26 * Cam Pow. In +12 VDC Camera power, +12 VDC nominal, < 1% ripple. For more details about PoCL power requirements see the Camera Link specifications v. 2.0 and above. 13, 14 ** Power Ret. Return Camera power return (Gnd) 2 X0- Output Camera Link LVDS Data from transmitter circuit X 15 X0+ 3 X1- Output Camera Link LVDS Data from transmitter circuit X 16 X1+ 4 X2- Output Camera Link LVDS Data from transmitter circuit X 17 X2+ 6 X3- Output Camera Link LVDS Data from transmitter circuit X 19 X3+ 5 XClk- Output Camera Link LVDS Pixel clock from transmitter circuit X 18 XClk+ 7 SerTC+ Input RS-644 LVDS Serial communication data receive (SerTC = "serial to camera") 20 SerTC- 8 SerTFG- Output RS-644 LVDS Serial communication data transmit (SerTFG = "serial to frame grabber") 21 SerTFG+ 9 CC1- Input RS-644 LVDS Configurable 22 CC1+ 10 CC2+ Input RS-644 LVDS Configurable 23 CC2- 11 CC3- Input RS-644 LVDS Configurable 24 CC3+ 12 CC4+ Input RS-644 LVDS Configurable 25 CC4- * Pins 1 and 26 are tied together in the camera. ** Pins 13 and 14 are tied together in the camera. Table 2: Pin Assignments and Numbering for the Base Configuration 26-pin SDR Connector 1 26 14 13

AW00118702000 4 Basler racer Camera Link Pin Number Signal Name Direction Level Function 1, 26 * Cam Pow. In not used 13, 14 ** Power Ret. Return Camera power return (Gnd) 2 Y0- Output Camera Link LVDS Data from transmitter circuit Y 15 Y0+ 3 Y1- Output Camera Link LVDS Data from transmitter circuit Y 16 Y1+ 4 Y2- Output Camera Link LVDS Data from transmitter circuit Y 17 Y2+ 6 Y3- Output Camera Link LVDS Data from transmitter circuit Y 19 Y3+ 5 YClk- Output Camera Link LVDS Pixel clock from transmitter circuit Y 18 YClk+ 7 T+ Connected to T- with 100R; not used 20 T- Connected to T+ with 100R; not used 8 Z0- Output Camera Link LVDS Data from transmitter circuit Z 21 Z0+ 9 Z1- Output Camera Link LVDS Data from transmitter circuit Z 22 Z1+ 10 Z2- Output Camera Link LVDS Data from transmitter circuit Z 23 Z2+ 12 Z3- Output Camera Link LVDS Data from transmitter circuit Z 25 Z3+ 11 ZClk- Output Camera Link LVDS Pixel clock from transmitter circuit Z 24 ZClk+ * Pins 1 and 26 are tied together in the camera. ** Pins 13 and 14 are tied together in the camera. Table 3: Pin Assignments and Numbering for the Medium/Full Configuration 26-pin SDR Connector 1 26 14 13

Basler racer Camera Link 5 1.3 Electrical Implementation The schematics in Fig. 2 through Fig. 6 on the following pages illustrate the basics of the racer Camera Link electrical implementation. The basic difference between the schematics is the number of transmitters used and the port assignments for each transmitter. Fig. 2 on page 6 illustrates the implementation when a camera is set for the 1X or 1X2 tap geometry, which will cause it to operate in the base Camera Link configuration. In this situation, only the X transmitter is used. Fig. 3 on page 7 illustrates the implementation when a camera is set for the 1X4 tap geometry, which will cause it to operate in the medium Camera Link configuration. In this situation, the X and Y transmitters are used. Fig. 4 on page 8 illustrates the implementation when a camera is set for the 1X8 geometry, which will cause it to operate in the full Camera Link configuration. In this situation, the X, Y, and Z transmitters are used. This configuration is commonly referred to as an "octo" configuration because eight sets of Camera Link ports are mapped to the transmitters. Fig. 5 on page 9 illustrates the implementation when a camera is set for the 1X10 geometry, which will cause it to operate in the full Camera Link configuration. In this situation, the X, Y, and Z transmitters are used. This configuration is commonly referred to as a "deca" configuration because ten sets of Camera Link ports are mapped to the transmitters.

AW00118702000 6 Basler racer Camera Link Fig. 2: Electrical Implementation - Base Configuration Transmitter Circuit X racer Xclk+ Xclk- 18 5 12 25 24 11 10 23 22 9 Input Input Input 7 20 21 8 SerTC SerTFG 1 26 14 13 18 5 12 25 24 11 10 23 22 9 7 20 21 8 1 26 14 13 SDR Cable DS90CR288A - Receiver X Frame Grabber Xclk+ Xclk- 9 22 CC4+ CC4- CC3+ CC3- CC2+ CC2- CC1+ CC1- 15 2 3 16 17 4 5 18 Output Output Output Output SerTC+ SerTC- SerTFG+ SerTFG- 20 7 6 19 SerTC SerTFG 1 26 14 13 9 22 15 2 3 16 17 4 5 18 20 7 6 19 1 26 14 13 26-pin Female SDR Connector Pair 4+ Pair 4- Pair 11+ Pair 11- Pair 10+ Pair 10- Pair 9+ Pair 9- Pair 8+ Pair 8- Pair 6+ Pair 6- Pair 7+ Pair 7- 26-pin Male SDR Connector RxCLKOut DS90LV047A Tmtr. DS90LV011A Tmtr. DS90LV012A Rcvr. CC3+ CC3- CC2+ CC2- CC1+ CC1- SerTC+ SerTC- SerTFG+ SerTFG- Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 LVAL FVAL DVAL Port A6 Port A7 Port B6 Port B7 Port C6 Port C7 CL Spare Strobe (PClk) Tx0 Tx1 Tx2 Tx3 Tx4 Tx6 Tx7 Tx8 Tx9 Tx12 Tx13 Tx14 Tx15 Tx18 Tx19 Tx20 Tx21 Tx22 Tx24 Tx25 Tx26 Tx27 Tx5 Tx10 Tx11 Tx16 Tx17 Tx23 TxCLKIn 19 6 19 6 X3+ X3- X3+ X3- 8 21 8 21 Pair 5+ Pair 5- 17 4 17 4 X2+ X2- X2+ X2- 10 23 10 23 Pair 3+ Pair 3- 16 3 16 3 X1+ X1- X1+ X1- 11 24 11 24 Pair 2+ Pair 2- X0+ X0- 15 2 12 25 Pair 1+ Pair 1- 15 2 X0+ X0- 12 25 Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 LVAL FVAL DVAL Port A6 Port A7 Port B6 Port B7 Port C6 Port C7 CL Spare Rx0 Rx1 Rx2 Rx3 Rx4 Rx6 Rx7 Rx8 Rx9 Rx12 Rx13 Rx14 Rx15 Rx18 Rx19 Rx20 Rx21 Rx22 Rx24 Rx25 Rx26 Rx27 Rx5 Rx10 Rx11 Rx16 Rx17 Rx23 Strobe (PClk) Gnd +12 VDC PoCL In Gnd +12 VDC PoCL Out Input CC4+ CC4- 6-pin Receptacle Alternative Power In 1 2 3 4 5 6 Not Connected Not Connected Gnd +12 VDC In FPGA

Basler racer Camera Link 7 Fig. 3: Electrical Implementation - Medium Configuration Transmitter Circuit X racer Xclk+ Xclk- 18 5 12 25 24 11 10 23 22 9 Input Input Input 7 20 21 8 SerTC SerTFG 1 26 14 13 18 5 12 25 24 11 10 23 22 9 7 20 21 8 1 26 14 13 SDR Cable DS90CR288A - Receiver X Frame Grabber Xclk+ Xclk- 9 22 CC4+ CC4- CC3+ CC3- CC2+ CC2- CC1+ CC1- 15 2 3 16 17 4 5 18 Output Output Output Output SerTC+ SerTC- SerTFG+ SerTFG- 20 7 6 19 SerTC SerTFG 1 26 14 13 9 22 15 2 3 16 17 4 5 18 20 7 6 19 1 26 14 13 26-pin Female SDR Connector Pair 4+ Pair 4- Pair 11+ Pair 11- Pair 10+ Pair 10- Pair 9+ Pair 9- Pair 8+ Pair 8- Pair 6+ Pair 6- Pair 7+ Pair 7- 26-pin Male SDR Connector RxCLKOut DS90LV047A Tmtr. DS90LV011A Tmtr. DS90LV012A Rcvr. CC3+ CC3- CC2+ CC2- CC1+ CC1- SerTC+ SerTC- SerTFG+ SerTFG- Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 LVAL FVAL DVAL Port A6 Port A7 Port B6 Port B7 Port C6 Port C7 CL Spare Strobe (PClk) Tx0 Tx1 Tx2 Tx3 Tx4 Tx6 Tx7 Tx8 Tx9 Tx12 Tx13 Tx14 Tx15 Tx18 Tx19 Tx20 Tx21 Tx22 Tx24 Tx25 Tx26 Tx27 Tx5 Tx10 Tx11 Tx16 Tx17 Tx23 TxCLKIn 19 6 19 6 X3+ X3- X3+ X3- 8 21 8 21 Pair 5+ Pair 5- 17 4 17 4 X2+ X2- X2+ X2- 10 23 10 23 Pair 3+ Pair 3- 16 3 16 3 X1+ X1- X1+ X1- 11 24 11 24 Pair 2+ Pair 2- X0+ X0- 15 2 12 25 Pair 1+ Pair 1- 15 2 X0+ X0- 12 25 Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 LVAL FVAL DVAL Port A6 Port A7 Port B6 Port B7 Port C6 Port C7 CL Spare Rx0 Rx1 Rx2 Rx3 Rx4 Rx6 Rx7 Rx8 Rx9 Rx12 Rx13 Rx14 Rx15 Rx18 Rx19 Rx20 Rx21 Rx22 Rx24 Rx25 Rx26 Rx27 Rx5 Rx10 Rx11 Rx16 Rx17 Rx23 Strobe (PClk) Transmitter Circuit Y Yclk+ Yclk- SDR Cable DS90CR288A - Receiver Y Yclk+ Yclk- RxCLKOut Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port E0 Port E1 Port E2 Port E3 Port E4 Port E5 Port F0 Port F1 Port F2 Port F3 Port F4 Port F5 LVAL FVAL DVAL Port D6 Port D7 Port E6 Port E7 Port F6 Port F7 Not Used Strobe (PClk) Tx0 Tx1 Tx2 Tx3 Tx4 Tx6 Tx7 Tx8 Tx9 Tx12 Tx13 Tx14 Tx15 Tx18 Tx19 Tx20 Tx21 Tx22 Tx24 Tx25 Tx26 Tx27 Tx5 Tx10 Tx11 Tx16 Tx17 Tx23 TxCLKIn Y3+ Y3- Y3+ Y3- Y2+ Y2- Y2+ Y2- Y1+ Y1- Y1+ Y1- Y0+ Y0- Y0+ Y0- Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port E0 Port E1 Port E2 Port E3 Port E4 Port E5 Port F0 Port F1 Port F2 Port F3 Port F4 Port F5 LVAL FVAL DVAL Port D6 Port D7 Port E6 Port E7 Port F6 Port F7 Not Used Rx0 Rx1 Rx2 Rx3 Rx4 Rx6 Rx7 Rx8 Rx9 Rx12 Rx13 Rx14 Rx15 Rx18 Rx19 Rx20 Rx21 Rx22 Rx24 Rx25 Rx26 Rx27 Rx5 Rx10 Rx11 Rx16 Rx17 Rx23 Strobe (PClk) 18 5 19 6 17 4 16 3 15 2 18 5 9 22 19 6 8 21 Pair 5+ Pair 5- 17 4 10 23 Pair 3+ Pair 3- 16 3 11 24 Pair 2+ Pair 2- 12 25 Pair 1+ Pair 1- 15 2 10 23 11 24 12 25 9 22 8 21 Input CC4+ CC4- 6-pin Receptacle Alternative Power In 1 2 3 4 5 6 Not Connected Not Connected Gnd +12 VDC In FPGA Gnd +12 VDC PoCL In Gnd +12 VDC PoCL Out

AW00118702000 8 Basler racer Camera Link Fig. 4: Electrical Implementation - Full Configuration (Octo) for 8 bit Pixel Formats

Basler racer Camera Link 9 Fig. 5: Electrical Implementation - Full Configuration (Octo) for 10 bit Pixel Formats

AW00118702000 10 Basler racer Camera Link Fig. 6: Electrical Implementation - Full Configuration (Deca)

Basler racer Camera Link 11 1.4 Camera Link Input Signals The input signals that the camera can accept via the Camera Link interface include a Serial to Camera signal and an External Line Start Trigger signal as described below. 1.4.1 Serial to Camera The Serial To Camera (SerTC) input signal is an RS-644 LVDS signal as specified in the Camera Link standard. The signal is input to the camera on pins 7 and 20 of the base SDR connector as specified in the standard and as shown in Fig. 2 on page 6. The camera is equipped for RS-644 serial communication via a serial port integrated into the frame grabber as specified in the Camera Link standard. The RS-644 serial connection in the Camera Link interface is used to issue commands to the camera that change parameter values. The serial link can also be used to query the camera about its current setup. 1.4.2 External Line Start Trigger (ExLSTrig) The camera can be set to accept an External Line Start Trigger (ExLSTrig) input signal to control exposure and readout of the camera’s sensor. When the ExLSTrig signal is applied to the camera via the Camera Link interface, it is an LVDS signal as specified for RS-644. By default, the camera will accept an ExLSTrig signal on the CC1 input in the Camera Link interface (pins 9 and 22 of the MDR connector) as specified in the Camera Link standard. The camera can also be configured to accept the ExLSTrig signal on CC2, CC3 or CC4. When the camera is under the control of an ExLSTrig signal, it can be set to function in two exposure time control modes: timed or trigger width. ExLSTrig can be a periodic or non-periodic function. The frequency of the ExLSTrig signal determines the camera’s line rate in these modes. Note that ExLSTrig is edge sensitive and therefore must toggle. The minimum high time for the ExLSTrig signal is 1 µs and the minimum low time is also 1 µs. The ExLSTrig signal is typically supplied to the camera by the frame grabber board. For details about using a line start trigger with racer cameras, refer to the Basler racer Camera Link User’s Manual (001185xx000).

AW00118702000 12 Basler racer Camera Link 1.5 Camera Link Output Signals 1.5.1 Serial to Frame Grabber The Serial To Camera (SerTFG) input signal is an RS-644 LVDS signal as specified in the Camera Link standard. The signal is output from the camera on pins 8 and 21 of the base SDR connector as specified in the standard and as shown in Fig. 2 on page 6. The camera is equipped for RS-644 serial communication via a serial port integrated into the frame grabber as specified in the Camera Link standard. The RS-644 serial connection in the Camera Link interface is used to issue commands to the camera that change parameter values. The serial link can also be used to query the camera about its current setup. 1.5.2 Pixel Clock The pixel clock is used to time the sampling and transmission of pixel data. The frequency of the pixel clock (pixel clock speed) is selectable. For more detailed information about the pixel clock speed, see Section 2 on page 25. The pixel clock is assigned as defined in the Camera Link standard to the strobe ports (TxClk pins) of the following transmitter circuits:  transmitter circuit X as shown in Table 2 and in Fig. 2, Fig. 3, Fig. 4, Fig. 5, and Fig. 6.  transmitter circuit Y as shown in Table 3 and in Fig. 3, Fig. 4, Fig. 5, and Fig. 6.  transmitter circuit Z as shown in Table 3 and in Fig. 4, Fig. 5, and Fig. 6. 1.5.3 Line Valid Bit As shown for example in Fig. 10 on page 31, the line valid bit indicates that a valid line is being transmitted. Pixel data is only valid when the line valid bit and the data valid bit are both high. (In those cases where the data valid bit is not available (see Section 1.5.4 on page 13), pixel data is valid when the line valid bit is high.) The line valid bit is assigned as defined in the Camera Link standard to the line valid ports of the following transmitter circuits:  transmitter circuit X as shown in Fig. 2, Fig. 3, Fig. 4, Fig. 5, and Fig. 6.  transmitter circuit Y as shown in Fig. 3, Fig. 4, Fig. 5, and Fig. 6.  transmitter circuit Z as shown in Fig. 4, Fig. 5, and Fig. 6.

Basler racer Camera Link 13 1.5.4 Data Valid Bit As shown for example in Fig. 10 on page 31, the data valid bit indicates that valid pixel data is being transmitted. Pixel data is only valid when the line valid bit and the data valid bit are both high. (In those cases where the data valid bit is not available (see below), data is valid when the line valid bit is high.) The data valid bit is assigned as defined in the Camera Link standard to the data valid ports of the following transmitter circuits:  transmitter circuit X as shown in Fig. 2, Fig. 3, and Fig. 4.  transmitter circuit Y as shown in Fig. 3 and Fig. 4.  transmitter circuit Z as shown in Fig. 4. 1.5.5 CL Spare Bit As shown in Fig. 2 on page 6 and in the tables in Section 1.5.6 on page 13, the Camera Link standard defines a CL spare bit. The camera can be configured to apply one of the following output signals to the CL Spare bit:  Line Trigger Wait  Exposure Active 1.5.6 Pixel Data Bits Pixel data bits are transmitted via output ports on transmitter circuits X, Y, and Z. The assignment of pixel data bits to output ports varies depending on the camera’s current Camera Link Tap Geometry setting and also on the bit depth of the pixels being transmitted (bit depth is determined by the current Pixel Format setting). The bit to port assignments for each available combination of tap geometry and pixel format settings are shown in the tables on the following pages. The data valid bit will not be available:  If the camera is set to operate in the 1X8 tap geometry at 10 bit pixel depth.  If the camera is set to operate in the 1X10 tap geometry. The CL Spare bit will not be available  If the camera is set to operate with 1X8 tap geometry at 10 bit pixel depth.  If the camera is set to operate with 1X10 tap geometry.

AW00118702000 14 Basler racer Camera Link 1.5.6.1 1X Tap Geometry – 8, 10, or 12 Bit Pixel Depth Base SDR Connector, Transmitter Circuit X Port Camera Frame Grabber Bit Assignments 1X - 8 Bits 1X - 10 Bits 1X - 12 Bits Port A0 TxIn0 RxOut0 D0 Bit 0 D0 Bit 0 D0 Bit 0 Port A1 TxIn1 RxOut1 D0 Bit 1 D0 Bit 1 D0 Bit 1 Port A2 TxIn2 RxOut2 D0 Bit 2 D0 Bit 2 D0 Bit 2 Port A3 TxIn3 RxOut3 D0 Bit 3 D0 Bit 3 D0 Bit 3 Port A4 TxIn4 RxOut4 D0 Bit 4 D0 Bit 4 D0 Bit 4 Port A5 TxIn6 RxOut6 D0 Bit 5 D0 Bit 5 D0 Bit 5 Port A6 TxIn27 RxOut27 D0 Bit 6 D0 Bit 6 D0 Bit 6 Port A7 TxIn5 RxOut5 D0 Bit 7 (MSB) D0 Bit 7 D0 Bit 7 Port B0 TxIn7 RxOut7 Not Used D0 Bit 8 D0 Bit 8 Port B1 TxIn8 RxOut8 Not Used D0 Bit 9 (MSB) D0 Bit 9 Port B2 TxIn9 RxOut9 Not Used Not Used D0 Bit 10 Port B3 TxIn12 RxOut12 Not Used Not Used D0 Bit 11 (MSB) Port B4 TxIn13 RxOut13 Not Used Not Used Not Used Port B5 TxIn14 RxOut14 Not Used Not Used Not Used Port B6 TxIn10 RxOut10 Not Used Not Used Not Used Port B7 TxIn11 RxOut11 Not Used Not Used Not Used Port C0 TxIn15 RxOut15 Not Used Not Used Not Used Port C1 TxIn18 RxOut18 Not Used Not Used Not Used Port C2 TxIn19 RxOut19 Not Used Not Used Not Used Port C3 TxIn20 RxOut20 Not Used Not Used Not Used Port C4 TxIn21 RxOut21 Not Used Not Used Not Used Port C5 TxIn22 RxOut22 Not Used Not Used Not Used Port C6 TxIn16 RxOut16 Not Used Not Used Not Used Port C7 TxIn17 RxOut17 Not Used Not Used Not Used LVAL TxIn24 RxOut24 Line Valid Line Valid Line Valid FVAL TxIn25 RxOut25 Not Used Not Used Not Used DVAL TxIn26 RxOut26 Data Valid Data Valid Data Valid CL Spare TxIn23 RxOut23 As assigned by user As assigned by user As assigned by user Strobe TxCLKIn RxCLKOut Pixel Clock Pixel Clock Pixel Clock Table 4: Bit Assignments for 1X Tap Geometry – 8, 10, or 12 Bit Pixel Depth (Transmitter Circuit X)

Basler racer Camera Link 15 1.5.6.2 1X2 Tap Geometry – 8, 10, or 12 Bit Pixel Depth Base SDR Connector, Transmitter Circuit X Port Camera Frame Grabber Bit Assignments 1X2- 8 Bits 1X2 - 10 Bits 1X2 - 12 Bits Port A0 TxIn0 RxOut0 D0 Bit 0 D0 Bit 0 D0 Bit 0 Port A1 TxIn1 RxOut1 D0 Bit 1 D0 Bit 1 D0 Bit 1 Port A2 TxIn2 RxOut2 D0 Bit 2 D0 Bit 2 D0 Bit 2 Port A3 TxIn3 RxOut3 D0 Bit 3 D0 Bit 3 D0 Bit 3 Port A4 TxIn4 RxOut4 D0 Bit 4 D0 Bit 4 D0 Bit 4 Port A5 TxIn6 RxOut6 D0 Bit 5 D0 Bit 5 D0 Bit 5 Port A6 TxIn27 RxOut27 D0 Bit 6 D0 Bit 6 D0 Bit 6 Port A7 TxIn5 RxOut5 D0 Bit 7 (MSB) D0 Bit 7 D0 Bit 7 Port B0 TxIn7 RxOut7 D1 Bit 0 D0 Bit 8 D0 Bit 8 Port B1 TxIn8 RxOut8 D1 Bit 1 D0 Bit 9 (MSB) D0 Bit 9 Port B2 TxIn9 RxOut9 D1 Bit 2 Not Used D0 Bit 10 Port B3 TxIn12 RxOut12 D1 Bit 3 Not Used D0 Bit 11 (MSB) Port B4 TxIn13 RxOut13 D1 Bit 4 D1 Bit 8 D1 Bit 8 Port B5 TxIn14 RxOut14 D1 Bit 5 D1 Bit 9 (MSB) D1 Bit 9 Port B6 TxIn10 RxOut10 D1 Bit 6 Not Used D1 Bit 10 Port B7 TxIn11 RxOut11 D1 Bit 7 (MSB) Not Used D1 Bit 11 (MSB) Port C0 TxIn15 RxOut15 Not Used D1 Bit 0 D1 Bit 0 Port C1 TxIn18 RxOut18 Not Used D1 Bit 1 D1 Bit 1 Port C2 TxIn19 RxOut19 Not Used D1 Bit 2 D1 Bit 2 Port C3 TxIn20 RxOut20 Not Used D1 Bit 3 D1 Bit 3 Port C4 TxIn21 RxOut21 Not Used D1 Bit 4 D1 Bit 4 Port C5 TxIn22 RxOut22 Not Used D1 Bit 5 D1 Bit 5 Port C6 TxIn16 RxOut16 Not Used D1 Bit 6 D1 Bit 6 Port C7 TxIn17 RxOut17 Not Used D1 Bit 7 D1 Bit 7 LVAL TxIn24 RxOut24 Line Valid Line Valid Line Valid FVAL TxIn25 RxOut25 Not Used Not Used Not Used DVAL TxIn26 RxOut26 Data Valid Data Valid Data Valid CL Spare TxIn23 RxOut23 As assigned by user As assigned by user As assigned by user Strobe TxCLKIn RxCLKOut Pixel Clock Pixel Clock Pixel Clock Table 5: Bit Assignments for 1X2 Tap Geometry – 8, 10, or 12 Bit Pixel Depth (Transmitter Circuit X)

AW00118702000 16 Basler racer Camera Link 1.5.6.3 1X4 Tap Geometry – 8, 10, or 12 Bit Pixel Depth Base SDR Connector, Transmitter Circuit X Port Camera Frame Grabber Bit Assignments 1X4 - 8 Bits 1X4 - 10 Bits 1X4 - 12 Bits Port A0 TxIn0 RxOut0 D0 Bit 0 D0 Bit 0 D0 Bit 0 Port A1 TxIn1 RxOut1 D0 Bit 1 D0 Bit 1 D0 Bit 1 Port A2 TxIn2 RxOut2 D0 Bit 2 D0 Bit 2 D0 Bit 2 Port A3 TxIn3 RxOut3 D0 Bit 3 D0 Bit 3 D0 Bit 3 Port A4 TxIn4 RxOut4 D0 Bit 4 D0 Bit 4 D0 Bit 4 Port A5 TxIn6 RxOut6 D0 Bit 5 D0 Bit 5 D0 Bit 5 Port A6 TxIn27 RxOut27 D0 Bit 6 D0 Bit 6 D0 Bit 6 Port A7 TxIn5 RxOut5 D0 Bit 7 (MSB) D0 Bit 7 D0 Bit 7 Port B0 TxIn7 RxOut7 D1 Bit 0 D0 Bit 8 D0 Bit 8 Port B1 TxIn8 RxOut8 D1 Bit 1 D0 Bit 9 (MSB) D0 Bit 9 Port B2 TxIn9 RxOut9 D1 Bit 2 Not Used D0 Bit 10 Port B3 TxIn12 RxOut12 D1 Bit 3 Not Used D0 Bit 11 (MSB) Port B4 TxIn13 RxOut13 D1 Bit 4 D1 Bit 8 D1 Bit 8 Port B5 TxIn14 RxOut14 D1 Bit 5 D1 Bit 9 (MSB) D1 Bit 9 Port B6 TxIn10 RxOut10 D1 Bit 6 Not Used D1 Bit 10 Port B7 TxIn11 RxOut11 D1 Bit 7 (MSB) Not Used D1 Bit 11 (MSB) Port C0 TxIn15 RxOut15 D2 Bit 0 D1 Bit 0 D1 Bit 0 Port C1 TxIn18 RxOut18 D2 Bit 1 D1 Bit 1 D1 Bit 1 Port C2 TxIn19 RxOut19 D2 Bit 2 D1 Bit 2 D1 Bit 2 Port C3 TxIn20 RxOut20 D2 Bit 3 D1 Bit 3 D1 Bit 3 Port C4 TxIn21 RxOut21 D2 Bit 4 D1 Bit 4 D1 Bit 4 Port C5 TxIn22 RxOut22 D2 Bit 5 D1 Bit 5 D1 Bit 5 Port C6 TxIn16 RxOut16 D2 Bit 6 D1 Bit 6 D1 Bit 6 Port C7 TxIn17 RxOut17 D2 Bit 7 (MSB) D1 Bit 7 D1 Bit 7 LVAL TxIn24 RxOut24 Line Valid Line Valid Line Valid FVAL TxIn25 RxOut25 Not Used Not Used Not Used DVAL TxIn26 RxOut26 Data Valid Data Valid Data Valid CL Spare TxIn23 RxOut23 As assigned by user As assigned by user As assigned by user Strobe TxInCLK RxOutClk Pixel Clock Pixel Clock Pixel Clock Table 6: Bit Assignments for 1X4 Tap Geometry - 8, 10, or 12 Bit Pixel Depth (Transmitter Circuit X)

Basler racer Camera Link 17 Medium/Full SDR Connector, Transmitter Circuit Y Port Camera Frame Grabber Bit Assignments 1X4 - 8 Bits 1X4 - 10 Bits 1X4 - 12 Bits Port D0 TxIn0 RxOut0 D3 Bit 0 D3 Bit 0 D3 Bit 0 Port D1 TxIn1 RxOut1 D3 Bit 1 D3 Bit 1 D3 Bit 1 Port D2 TxIn2 RxOut2 D3 Bit 2 D3 Bit 2 D3 Bit 2 Port D3 TxIn3 RxOut3 D3 Bit 3 D3 Bit 3 D3 Bit 3 Port D4 TxIn4 RxOut4 D3 Bit 4 D3 Bit 4 D3 Bit 4 Port D5 TxIn6 RxOut6 D3 Bit 5 D3 Bit 5 D3 Bit 5 Port D6 TxIn27 RxOut27 D3 Bit 6 D3 Bit 6 D3 Bit 6 Port D7 TxIn5 RxOut5 D3 Bit 7 (MSB) D3 Bit 7 D3 Bit 7 Port E0 TxIn7 RxOut7 Not Used D2 Bit 0 D2 Bit 0 Port E1 TxIn8 RxOut8 Not Used D2 Bit 1 D2 Bit 1 Port E2 TxIn9 RxOut9 Not Used D2 Bit 2 D2 Bit 2 Port E3 TxIn12 RxOut12 Not Used D2 Bit 3 D2 Bit 3 Port E4 TxIn13 RxOut13 Not Used D2 Bit 4 D2 Bit 4 Port E5 TxIn14 RxOut14 Not Used D2 Bit 5 D2 Bit 5 Port E6 TxIn10 RxOut10 Not Used D2 Bit 6 D2 Bit 6 Port E7 TxIn11 RxOut11 Not Used D2 Bit 7 D2 Bit 7 Port F0 TxIn15 RxOut15 Not Used D2 Bit 8 D2 Bit 8 Port F1 TxIn18 RxOut18 Not Used D2 Bit 9 (MSB) D2 Bit 9 Port F2 TxIn19 RxOut19 Not Used Not Used D2 Bit 10 Port F3 TxIn20 RxOut20 Not Used Not Used D2 Bit 11 (MSB) Port F4 TxIn21 RxOut21 Not Used D3 Bit 8 D3 Bit 8 Port F5 TxIn22 RxOut22 Not Used D3 Bit 9 (MSB) D3 Bit 9 Port F6 TxIn16 RxOut16 Not Used Not Used D3 Bit 10 Port F7 TxIn17 RxOut17 Not Used Not Used D3 Bit 11 (MSB) LVAL TxIn24 RxOut24 Line Valid Line Valid Line Valid FVAL TxIn25 RxOut25 Not Used Not Used Not Used DVAL TxIn26 RxOut26 Data Valid Data Valid Data Valid Not Used TxIn23 RxOut23 Not Used Not Used Not Used Strobe TxInCLK RxOutClk Pixel Clock Pixel Clock Pixel Clock Table 7: Bit Assignments for 1X4 Tap Geometry - 8, 10, or 12 Bit Pixel Depth (Transmitter Circuit Y)

AW00118702000 18 Basler racer Camera Link 1.5.6.4 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth * In 1X8 8 bit mode, this port is DVAL. In 1X8 10 bit mode, DVAL is not present. Instead, this port is I0 and D0 Bit 0 is assigned to it. Base SDR Conn, Transmitter Circuit X Port Camera Frame Grabber Bit Assignments 1X8 - 8 Bits 1X8 - 10 Bits Port A0 TxIn0 RxOut0 D0 Bit 0 D0 Bit 2 Port A1 TxIn1 RxOut1 D0 Bit 1 D0 Bit 3 Port A2 TxIn2 RxOut2 D0 Bit 2 D0 Bit 4 Port A3 TxIn3 RxOut3 D0 Bit 3 D0 Bit 5 Port A4 TxIn4 RxOut4 D0 Bit 4 D0 Bit 6 Port A5 TxIn6 RxOut6 D0 Bit 5 D0 Bit 7 Port A6 TxIn27 RxOut27 D0 Bit 6 D0 Bit 8 Port A7 TxIn5 RxOut5 D0 Bit 7 (MSB) D0 Bit 9 (MSB) Port B0 TxIn7 RxOut7 D1 Bit 0 D1 Bit 2 Port B1 TxIn8 RxOut8 D1 Bit 1 D1 Bit 3 Port B2 TxIn9 RxOut9 D1 Bit 2 D1 Bit 4 Port B3 TxIn12 RxOut12 D1 Bit 3 D1 Bit 5 Port B4 TxIn13 RxOut13 D1 Bit 4 D1 Bit 6 Port B5 TxIn14 RxOut14 D1 Bit 5 D1 Bit 7 Port B6 TxIn10 RxOut10 D1 Bit 6 D1 Bit 8 Port B7 TxIn11 RxOut11 D1 Bit 7 (MSB) D1 Bit 9 (MSB) Port C0 TxIn15 RxOut15 D2 Bit 0 D2 Bit 2 Port C1 TxIn18 RxOut18 D2 Bit 1 D2 Bit 3 Port C2 TxIn19 RxOut19 D2 Bit 2 D2 Bit 4 Port C3 TxIn20 RxOut20 D2 Bit 3 D2 Bit 5 Port C4 TxIn21 RxOut21 D2 Bit 4 D2 Bit 6 Port C5 TxIn22 RxOut22 D2 Bit 5 D2 Bit 7 Port C6 TxIn16 RxOut16 D2 Bit 6 D2 Bit 8 Port C7 TxIn17 RxOut17 D2 Bit 7 (MSB) D2 Bit 9 (MSB) LVAL TxIn24 RxOut24 Line Valid Line Valid FVAL TxIn25 RxOut25 Not Used Not Used DVAL or Port I0 * TxIn26 RxOut26 Not used D0 Bit 0 Port I1 TxIn23 RxOut23 Not Used D0 Bit 1 Strobe TxInCLK RxOutClk Pixel Clock Pixel Clock Table 8: Bit Assignments for 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth (Transmitter Circuit X)

Basler racer Camera Link 19 * In 1X8 8 bit mode, this port is FVAL and is not used. In 1X8 10 bit mode, FVAL is not present. Instead, this port is I2 and D1 Bit 0 is assigned to it. ** In 1X8 8 bit mode, this port is DVAL. In 1X8 10 bit mode, DVAL is not present. Instead, this port is I3 and D1 Bit 1 is assigned to it. Medium/Full SDR Conn, Transmitter Circuit Y Port Camera Frame Grabber Bit Assignments 1X8 - 8 Bits 1X8 - 10 Bits Port D0 TxIn0 RxOut0 D3 Bit 0 D3 Bit 2 Port D1 TxIn1 RxOut1 D3 Bit 1 D3 Bit 3 Port D2 TxIn2 RxOut2 D3 Bit 2 D3 Bit 4 Port D3 TxIn3 RxOut3 D3 Bit 3 D3 Bit 5 Port D4 TxIn4 RxOut4 D3 Bit 4 D3 Bit 6 Port D5 TxIn6 RxOut6 D3 Bit 5 D3 Bit 7 Port D6 TxIn27 RxOut27 D3 Bit 6 D3 Bit 8 Port D7 TxIn5 RxOut5 D3 Bit 7 (MSB) D3 Bit 9 (MSB) Port E0 TxIn7 RxOut7 D4 Bit 0 D4 Bit 2 Port E1 TxIn8 RxOut8 D4 Bit 1 D4 Bit 3 Port E2 TxIn9 RxOut9 D4 Bit 2 D4 Bit 4 Port E3 TxIn12 RxOut12 D4 Bit 3 D4 Bit 5 Port E4 TxIn13 RxOut13 D4 Bit 4 D4 Bit 6 Port E5 TxIn14 RxOut14 D4 Bit 5 D4 Bit 7 Port E6 TxIn10 RxOut10 D4 Bit 6 D4 Bit 8 Port E7 TxIn11 RxOut11 D4 Bit 7 (MSB) D4 Bit 9 (MSB) Port F0 TxIn15 RxOut15 D5 Bit 0 D5 Bit 2 Port F1 TxIn18 RxOut18 D5 Bit 1 D5 Bit 3 Port F2 TxIn19 RxOut19 D5 Bit 2 D5 Bit 4 Port F3 TxIn20 RxOut20 D5 Bit 3 D5 Bit 5 Port F4 TxIn21 RxOut21 D5 Bit 4 D3 Bit 6 Port F5 TxIn22 RxOut22 D5 Bit 5 D3 Bit 7 Port F6 TxIn16 RxOut16 D5 Bit 6 D5 Bit 8 Port F7 TxIn17 RxOut17 D5 Bit 7 (MSB) D5 Bit 9 (MSB) LVAL TxIn24 RxOut24 Line Valid Line Valid FVAL or Port I2 * TxIn25 RxOut25 Not Used D1 Bit 0 DVAL or Port I3 ** TxIn26 RxOut26 Not Used D1 Bit 1 Port I4 TxIn23 RxOut23 Not Used D2 Bit 0 Strobe TxInCLK RxOutClk Pixel Clock Pixel Clock Table 9: Bit Assignments for 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth (Transmitter Circuit Y)

AW00118702000 20 Basler racer Camera Link * In 1X8 8 bit mode, this port is FVAL and is not used. In 1X8 10 bit mode, FVAL is not present. Instead, this port is J5 and D6 Bit 1 is assigned to it. ** In 1X8 8 bit mode, this port is DVAL. In 1X8 10 bit mode, DVAL is not present. Instead, this port is J6 and D7 Bit 0 is assigned to it. Medium/Full SDR Conn, Transmitter Circuit Z Port Camera Frame Grabber Bit Assignments 1X8 - 8 Bits 1X8 - 10 Bits Port G0 TxIn0 RxOut0 D6 Bit 0 D6 Bit 2 Port G1 TxIn1 RxOut1 D6 Bit 1 D6 Bit 3 Port G2 TxIn2 RxOut2 D6 Bit 2 D6 Bit 4 Port G3 TxIn3 RxOut3 D6 Bit 3 D6 Bit 5 Port G4 TxIn4 RxOut4 D6 Bit 4 D6 Bit 6 Port G5 TxIn6 RxOut6 D6 Bit 5 D6 Bit 7 Port G6 TxIn27 RxOut27 D6 Bit 6 D6 Bit 8 Port G7 TxIn5 RxOut5 D6 Bit 7 (MSB) D6 Bit 9 (MSB) Port H0 TxIn7 RxOut7 D7 Bit 0 D7 Bit 2 Port H1 TxIn8 RxOut8 D7 Bit 1 D7 Bit 3 Port H2 TxIn9 RxOut9 D7 Bit 2 D7 Bit 4 Port H3 TxIn12 RxOut12 D7 Bit 3 D7 Bit 5 Port H4 TxIn13 RxOut13 D7 Bit 4 D7 Bit 6 Port H5 TxIn14 RxOut14 D7 Bit 5 D7 Bit 7 Port H6 TxIn10 RxOut10 D7 Bit 6 D7 Bit 8 Port H7 TxIn11 RxOut11 D7 Bit 7 (MSB) D7 Bit 9 (MSB) Port I5 TxIn15 RxOut15 Not Used D2 Bit 1 Port I6 TxIn18 RxOut18 Not Used D3 Bit 0 Port I7 TxIn19 RxOut19 Not Used D3 Bit 1 Port J0 TxIn20 RxOut20 Not Used D4 Bit 0 Port J1 TxIn21 RxOut21 Not Used D4 Bit 1 Port J2 TxIn22 RxOut22 Not Used D5 Bit 0 Port J3 TxIn16 RxOut16 Not Used D5 Bit 1 Port J4 TxIn17 RxOut17 Not Used D6 Bit 0 LVAL TxIn24 RxOut24 Line Valid Line Valid FVAL or Port J5 * TxIn25 RxOut25 Not Used D6 Bit 1 DVAL or Port J6 ** TxIn26 RxOut26 Not Used D7 Bit 0 Port J7 TxIn23 RxOut23 Not Used D7 Bit 1 Strobe TxInCLK RxOutClk Pixel Clock Pixel Clock Table 10: Bit Assignments for 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth (Transmitter Circuit Z)

Basler racer Camera Link 21 1.5.6.5 1X10 Tap Geometry – 8 Bit Pixel Depth Base SDR Connector, Transmitter Circuit X Port Camera Frame Grabber Bit Assignments 1X10 - 8 Bits Port A0 TxIn0 RxOut0 D0 Bit 0 Port A1 TxIn1 RxOut1 D0 Bit 1 Port A2 TxIn2 RxOut2 D0 Bit 2 Port A3 TxIn3 RxOut3 D0 Bit 3 Port A4 TxIn4 RxOut4 D0 Bit 4 Port A5 TxIn5 RxOut5 D0 Bit 5 Port A6 TxIn6 RxOut6 D0 Bit 6 Port A7 TxIn7 RxOut7 D0 Bit 7 (MSB) Port B0 TxIn8 RxOut8 D1 Bit 0 Port B1 TxIn9 RxOut9 D1 Bit 1 Port B2 TxIn10 RxOut10 D1 Bit 2 Port B3 TxIn11 RxOut11 D1 Bit 3 Port B4 TxIn12 RxOut12 D1 Bit 4 Port B5 TxIn13 RxOut13 D1 Bit 5 Port B6 TxIn14 RxOut14 D1 Bit 6 Port B7 TxIn15 RxOut15 D1 Bit 7 (MSB) Port C0 TxIn16 RxOut16 D2 Bit 0 Port C1 TxIn17 RxOut17 D2 Bit 1 Port C2 TxIn18 RxOut18 D2 Bit 2 Port C3 TxIn19 RxOut19 D2 Bit 3 Port C4 TxIn20 RxOut20 D2 Bit 4 Port C5 TxIn21 RxOut21 D2 Bit 5 Port C6 TxIn22 RxOut22 D2 Bit 6 Port C7 TxIn23 RxOut23 D2 Bit 7 (MSB) LVAL TxIn24 RxOut24 Line Valid FVAL TxIn25 RxOut25 Not Used Port D0 TxIn26 RxOut26 D3 Bit 0 Port D1 TxIn27 RxOut27 D3 Bit 1 Strobe TxInCLK RxOutClk Pixel Clock Table 11: Bit Assignments for 1X10 Tap Geometry – 8 Pixel Depth (Transmitter Circuit X)

AW00118702000 22 Basler racer Camera Link Medium/Full SDR Connector, Transmitter Circuit Y Port Camera Frame Grabber Bit Assignments 1X10 - 8 Bits Port D2 TxIn0 RxOut0 D3 Bit 2 Port D3 TxIn1 RxOut1 D3 Bit 3 Port D4 TxIn2 RxOut2 D3 Bit 4 Port D5 TxIn3 RxOut3 D3 Bit 5 Port D6 TxIn4 RxOut4 D3 Bit 6 Port D7 TxIn5 RxOut5 D3 Bit 7 (MSB) Port E0 TxIn6 RxOut6 D4 Bit 0 Port E1 TxIn7 RxOut7 D4 Bit 1 Port E2 TxIn8 RxOut8 D4 Bit 2 PortE3 TxIn9 RxOut9 D4 Bit 3 Port E4 TxIn10 RxOut10 D4 Bit 4 Port E5 TxIn11 RxOut11 D4 Bit 5 Port E6 TxIn12 RxOut12 D4 Bit 6 Port E7 TxIn13 RxOut13 D4 Bit 7 (MSB) Port F0 TxIn14 RxOut14 D5 Bit 0 Port F1 TxIn15 RxOut15 D5 Bit 1 Port F2 TxIn16 RxOut16 D5 Bit 2 Port F3 TxIn17 RxOut17 D5 Bit 3 Port F4 TxIn18 RxOut18 D5 Bit 4 Port F5 TxIn19 RxOut19 D5 Bit 5 Port F6 TxIn20 RxOut20 D5 Bit 6 Port F7 TxIn21 RxOut21 D5 Bit 7 (MSB) Port G0 TxIn22 RxOut22 D6 Bit 0 Port G1 TxIn23 RxOut23 D6 Bit 1 Port G2 TxIn24 RxOut24 D6 Bit 2 Port G3 TxIn25 RxOut25 D6 Bit 3 Port G4 TxIn26 RxOut26 D6 Bit 4 LVAL TxIn27 RxOut27 Line Valid Strobe TxInCLK RxOutClk Pixel Clock Table 12: Bit Assignments for 1X10 Tap Geometry – 8 Pixel Depth (Transmitter Circuit Y)

Basler racer Camera Link 23 Medium/Full SDR Connector, Transmitter Circuit Z Port Camera Frame Grabber Bit Assignments 1X10 - 8 Bits Port G5 TxIn0 RxOut0 D6 Bit 5 Port G6 TxIn1 RxOut1 D6 Bit 6 Port G7 TxIn2 RxOut2 D6 Bit 7 (MSB) Port H0 TxIn3 RxOut3 D7 Bit 0 Port H1 TxIn4 RxOut4 D7 Bit 1 Port H2 TxIn5 RxOut5 D7 Bit 2 Port H3 TxIn6 RxOut6 D7 Bit 3 Port H4 TxIn7 RxOut7 D7 Bit 4 Port H5 TxIn8 RxOut8 D7 Bit 5 Port H6 TxIn9 RxOut9 D7 Bit 6 Port H7 TxIn10 RxOut10 D7 Bit 7 (MSB) Port I0 TxIn11 RxOut11 D8 Bit 0 Port I1 TxIn12 RxOut12 D8 Bit 1 Port I2 TxIn13 RxOut13 D8 Bit 2 Port I3 TxIn14 RxOut14 D8 Bit 3 Port I4 TxIn15 RxOut15 D8 Bit 4 Port I5 TxIn16 RxOut16 D8 Bit 5 Port I6 TxIn17 RxOut17 D8 Bit 6 Port I7 TxIn18 RxOut18 D8 Bit 7 (MSB) Port J0 TxIn19 RxOut19 D9 Bit 0 Port J1 TxIn20 RxOut20 D9 Bit 1 Port J2 TxIn21 RxOut21 D9 Bit 2 Port J3 TxIn22 RxOut22 D9 Bit 3 Port J4 TxIn23 RxOut23 D9 Bit 4 Port J5 TxIn24 RxOut24 D9 Bit 5 Port J6 TxIn25 RxOut25 D9 Bit 6 Port J7 TxIn26 RxOut26 D9 Bit 7 (MSB) LVAL TxIn27 RxOut27 Line Valid Strobe TxInCLK RxOutClk Pixel Clock Table 13: Bit Assignments for 1X10 Tap Geometry – 8 Pixel Depth (Transmitter Circuit Z)

Basler racer Camera Link 25 2 Pixel Data Output 2.1 Data Depth The camera’s Pixel Format parameter setting determines the data depth of the pixels transmitted from the camera. On mono cameras, the pixel format can be set to Mono 8 (8 bit depth), Mono 10 (10 bit depth), or Mono 12 (12 bit depth). When a camera is set for an 8 bit format, 8 bits of image data are transmitted for each pixel. When a camera is set for a 10 bit format, 10 bits of image data are transmitted for each pixel. When a camera is set for a 12 bit format, 12 bits of image data are transmitted for each pixel. 2.2 Pixel Clock Speed The Camera Link pixel clock speed on all racer Camera Link camera models is selectable. The available pixel clock speeds are listed in Table 14. Camera Link Pixel Clock Speed Camera Link Pixel Clock Period (pclk Period) 32.5 MHz 30.769 ns 48 MHz 20.833 ns 65 MHz 15.385 ns 83.5 MHz 11.976 ns Table 14: Pixel Clock Speeds and Periods

AW00118702000 26 Basler racer Camera Link 2.3 Camera Link Tap Geometries All racer Camera Link cameras have a settable Camera Link Tap Geometry parameter. The Camera Link tap geometry setting determines how pixel data will be transmitted via the Camera Link interface. The available Camera Link tap geometries are:  1X  1X2  1X4  1X8  1X10 The sections 2.3.3 through 2.3.6 include descriptions of all available tap geometries. 2.3.1 Factors Influencing the Timing of Pixel Data Transmission 2.3.1.1 Camera Link Pixel Clock The Camera Link pixel clock is used to time pixel data transmission. The camera transmits data on each rising edge of the pixel clock as shown, for example, for the 1X2 tap geometry in Fig. 10 on page 31. The pixel clock frequency depends on the current setting of the camera’s Camera Link Clock Speed parameter. See Table 14 for the available Camera Link pixel clock speeds and the related pixel clock (pclk) periods. 2.3.1.2 Delays In addition to the Camera Link pixel clock, the three delays A, B, and C are involved in timing pixel data transmission. The delays can be calculated using the formulas 1, 2, and 3 given below. See also Fig. 10, Fig. 12, Fig. 14, and Fig. 16):  Delay A takes account, among others, of the time needed for sensor readout and is subject to the Offset X setting for the image AOI.  Delay B takes account of the Width setting for the image AOI and of the number of taps used for pixel data transmission (e.g. two taps in 1X2 tap geometry).  Delay C takes a minimum (Cmin) of seven pixel clock periods and increases as the line acquisition rate is decreased. Delay C varies somewhat due to jitter.

Basler racer Camera Link 27 Formula 1: Formula 2: Formula 3: Example: Assume that the camera is set to 1X2 tap geometry and a pixel clock speed of 65 MHz. Assume also that the Offset X parameter for the image AOI is set to 16 pixels, and that the Width parameter for the image AOI is set to 24 pixels. In this case, the delays would be: Formula 1: Formula 2: Formula 3: A 22.3 µs Image AOI Offset X 8 ---------------------------------------------------- x 0.0095 µs    +  B Image AOI Width Number of Taps --------------------------------------------- x pclk Period  Cmin 7 x pclk Period = A 22.3 µs 16 8 -------- x 0.0095 µs    +  A 22.319 µs  B 24 2 -------- x 0.015385 µs  B 0.18462 µs  Cmin 7 x 0.015385 µs = Cmin 0.107695 µs =

AW00118702000 28 Basler racer Camera Link 2.3.2 1X Tap Geometry The characteristics of the 1X tap geometry are:  On each cycle of the Camera Link pixel clock, the data for one pixel are transmitted via the Camera Link interface. This is commonly referred to as a "one tap" Camera Link configuration.  The camera will begin transmitting data from the sensor line. It will transmit the data for the first pixel in the line on the first Camera Link pixel clock cycle, the next pixel in the line on the second pixel clock cycle, the next pixel in the line on the third clock cycle, and so on until the line is complete.  When transmission for the line is complete, transmission for the next line acquisition will begin after a time interval (see Fig. 8 on page 29) and will proceed in a similar fashion. Data transmission will continue line after line until line acquisition is stopped. When the camera is set for the 1X tap geometry, it uses the base Camera Link configuration. When the camera is set for the 1X tap geometry, the image AOI Width parameter must be set to a number divisible by 8. Transmission according to the 1X tap geometry is shown graphically in Fig. 7 and the timing of pixel data transmission in Fig. 8. Fig. 7: 1X Tap Geometry Tap 1 Step X = 1 X1 X2 XW-1 XW

Basler racer Camera Link 29 Fig. 8: Timing of Pixel Data Transmission for the 1X Tap Configuration End of Exposure Pixel Clock D0 Pixel Data (12, 10, or 8 bits) W-1 W 1 2 1 2 Data Valid W-1 W A Line Valid Line Acquisition N Line Acquisition N+1 C B TIMING DIAGRAMS ARE NOT DRAWN TO SCALE. W = width = the last pixel according to the current image AOI (e.g., the 2048th pixel of the image AOI when the image AOI width is set to 2048).

AW00118702000 30 Basler racer Camera Link 2.3.3 1X2 Tap Geometry The characteristics of the 1X2 tap geometry are:  On each cycle of the Camera Link pixel clock, the data for two pixels are transmitted via the Camera Link interface. This is commonly referred to as a "two tap" Camera Link configuration.  The camera will begin transmitting data from the sensor line. It will transmit the data for the first two pixels in the line on the first Camera Link pixel clock cycle, the next two pixels in the line on the second pixel clock cycle, the next two pixels in the line on the third clock cycle, and so on until the line is complete.  When transmission for the line is complete, transmission for the next line acquisition will begin after a time interval (see Fig. 10 on page 31) and will proceed in a similar fashion. Data transmission will continue line after line until line acquisition is stopped. When the camera is set for the 1X2 tap geometry, it uses the base Camera Link configuration. When the camera is set for the 1X2 tap geometry, the image AOI Width parameter must be set to a number divisible by 8. Transmission according to the 1X2 tap geometry is shown graphically in Fig. 9 and the timing of pixel data transmission in Fig. 10. Fig. 9: 1X2 Tap Geometry Tap 1 Tap 2 Step X = 2 X1 X2 XW-1 XW W = width

Basler racer Camera Link 31 Fig. 10: Timing of Pixel Data Transmission for the 1X2 Tap Configuration Pixel Clock D0 Pixel Data (12, 10, or 8 bits) W-3 W-1 1 3 1 D1 Pixel Data (12, 10, or 8 bits) W-2 W 2 4 2 3 4 Data Valid W-3 W-1 W-2 W Line Valid Line N Line N+1 C B B End of Exposure of Line N+1 A End of Exposure of Line N+2 TIMING DIAGRAMS ARE NOT DRAWN TO SCALE. W = width = the last pixel according to the current image AOI (e.g., the 2048th pixel of the image AOI when the image AOI width is set to 2048).

AW00118702000 32 Basler racer Camera Link 2.3.4 1X4 Tap Geometry The characteristics of the 1X4 tap geometry are:  On each cycle of the Camera Link pixel clock, the data for four pixels are transmitted via the Camera Link interface. This is commonly referred to as a "four tap" Camera Link configuration.  The camera will begin transmitting data from the sensor line. It will transmit the data for the first four pixels in the line on the first Camera Link pixel clock cycle, the next four pixels in the line on the second pixel clock cycle, the next four pixels in the line on the third clock cycle, and so on until the line is complete.  When transmission for the line is complete, transmission for the next line acquisition will begin after a time interval (see Fig. 12 on page 33) and will proceed in a similar fashion. Data transmission will continue line after line until line acquisition is stopped. When the camera is set for the 1X4 tap geometry, it uses the medium Camera Link configuration. When the camera is set for the 1X4 tap geometry, the image AOI Width parameter must be set to a number divisible by 8. Transmission according to the 1X4 tap geometry is shown graphically in Fig. 11 and the timing of pixel data transmission in Fig. 12. Fig. 11: 1X4 Tap Geometry Tap 1 Tap 2 Step X = 4 X1 X2 XW-1 XW W = width Tap 3 Tap 4

Basler racer Camera Link 33 Fig. 12: Timing of Pixel Data Transmission for the 1X4 Tap Configuration Line Valid Line N Line N+1 Pixel Clock D0 Pixel Data (12, 10, or 8 bits) W-7 W-3 1 5 1 D1 Pixel Data (12, 10, or 8 bits) W-6 W-2 2 6 2 5 6 Data Valid W-7 W-3 W-6 D2 Pixel Data (12, 10, or 8 bits) W-5 W-1 3 7 3 7 W-5 D3 Pixel Data (12, 10, or 8 bits) W-4 W 4 8 4 8 W-4 W-2 W-1 W C B B A End of Exposure of Line N+1 End of Exposure of Line N+2 TIMING DIAGRAMS ARE NOT DRAWN TO SCALE. W = width = the last pixel according to the current image AOI (e.g., the 2048th pixel of the image AOI when the image AOI width is set to 2048).

AW00118702000 34 Basler racer Camera Link 2.3.5 1X8 Tap Geometry The characteristics of the 1X8 tap geometry are:  On each cycle of the Camera Link pixel clock, the data for eight pixels are transmitted via the Camera Link interface. This is commonly referred to as an "eight tap" Camera Link configuration (or sometimes "octo tap").  The camera will begin transmitting data from the sensor line. It will transmit the data for the first eight pixels in the line on the first Camera Link pixel clock cycle, the next eight pixels in the line on the second pixel clock cycle, the next eight pixels in the line on the third clock cycle, and so on until the line is complete.  When transmission for the line is complete, transmission for the next line acquisition will begin after a time interval (see Fig. 14 on page 35) and will proceed in a similar fashion. Data transmission will continue line after line until line acquisition is stopped. When the camera is set for the 1X8 tap geometry, it uses the full Camera Link configuration. When the camera is set for the 1X8 tap geometry, the image AOI Width parameter must be set to a number divisible by 8. Transmission according to the 1X8 tap geometry is shown graphically in Fig. 13 and the timing of pixel data transmission in Fig. 14. Fig. 13: 1X8 Tap Geometry Tap 1 Tap 2 Step X = 8 X1 X2 XW-1 XW W = width Tap 3 Tap 4 Tap 5 Tap 6 Tap 7 Tap 8

Basler racer Camera Link 35 Fig. 14: Timing of Pixel Data Transmission for the 1X8 Tap Configuration Line Valid Line N Line N+1 C B Pixel Clock D0 Pixel Data (10 or 8 bits) W-15 W-7 1 9 D1 Pixel Data (10 or 8 bits) W-14 W-6 2 10 Data Valid D2 Pixel Data (10 or 8 bits) W-13 W-5 3 11 D3 Pixel Data (10 or 8 bits) W-12 W-4 4 12 D4 Pixel Data (10 or 8 bits) W-11 W-3 5 13 D5 Pixel Data (10 or 8 bits) W-10 W-2 6 14 D6 Pixel Data (10 or 8 bits) W-9 W-1 7 15 D7 Pixel Data (10 or 8 bits) W-8 W 8 16 * W-15 W-7 1 9 W-14 W-6 2 10 W-13 W-5 3 11 W-12 W-4 4 12 W-11 W-3 5 13 W-10 W-2 6 14 W-9 W-1 7 15 W-8 W 8 16 B A End of Exposure of Line N+1 End of Exposure of Line N+2 * In 1X8 configuration, data valid is only available when the camera is set for an 8 bit pixel format. TIMING DIAGRAMS ARE NOT DRAWN TO SCALE. W = width = the last pixel according to the current image AOI (e.g., the 2048th pixel of the image AOI when the image AOI width is set to 2048).

AW00118702000 36 Basler racer Camera Link 2.3.6 1X10 Tap Geometry The characteristics of the 1X10 tap geometry are:  On each cycle of the Camera Link pixel clock, the data for ten pixels are transmitted via the Camera Link interface. This is commonly referred to as a "ten tap" Camera Link configuration (or sometimes "deca tap").  The camera will begin transmitting data from the sensor line. It will transmit the data for the first ten pixels in the line on the first Camera Link pixel clock cycle, the next ten pixels in the line on the second pixel clock cycle, the next ten pixels in the line on the third clock cycle, and so on until the line is complete.  When transmission for the line is complete, transmission for the next line acquisition will begin after a time interval (see Fig. 15 on page 36) and will proceed in a similar fashion. Data transmission will continue line after line until line acquisition is stopped. When the camera is set for the 1X10 tap geometry, it uses the full Camera Link configuration. When the camera is set for the 1X10 tap geometry, the image AOI Width parameter must be set to a number divisible by 40. Transmission according to the 1X10 tap geometry is shown graphically in Fig. 15 and the timing of pixel data transmission in Fig. 16. Fig. 15: 1X10 Tap Geometry Tap 1 Tap 2 Step X = 10 X1 X2 XW-1 XW W = width Tap 3 Tap 4 Tap 5 Tap 6 Tap 7 Tap 8 Tap 9 Tap 10

Basler racer Camera Link 37 Fig. 16: Timing of Pixel Data Transmission for the 1X10 Tap Configuration Line Valid Line N Line N+1 Pixel Clock D0 Pixel Data (8 bits) W-19 1 11 D1 Pixel Data (8 bits) W-18 2 12 D2 Pixel Data (8 bits) W-17 3 13 D3 Pixel Data (8 bits) W-16 4 D4 Pixel Data (8 bits) W-15 5 15 D5 Pixel Data (8 bits) W-14 6 16 D6 Pixel Data (8 bits) W-13 W-3 7 17 D7 Pixel Data (8 bits) W-12 W-2 8 18 D8 Pixel Data (8 bits) W-11 W-1 9 19 D9 Pixel Data (8 bits) W-10 W 10 20 14 W-9 W-8 W-7 W-6 W-5 W-4 W-19 1 11 W-18 2 12 W-17 3 13 W-16 4 W-15 5 15 W-14 6 16 W-13 W-3 7 17 W-12 W-2 8 18 W-11 W-1 9 19 W-10 W 10 20 14 W-9 W-8 W-7 W-6 W-5 W-4 C B B A End of Exposure of Line N+1 End of Exposure of Line N+2 TIMING DIAGRAMS ARE NOT DRAWN TO SCALE. W = width = the last pixel according to the current image AOI (e.g., the 2040th pixel of the image AOI when the image AOI width is set to 2040). Note: Data Valid is not available in 1X10 configuration.

39 Revision History Doc. ID Number Date Changes AW00118701000 17 Sep 2012 Initial release of this document. Applies to prototype cameras only. AW00118702000 1 Feb 2013 Initial release of this document applying to series-production status. Updated the e-mail addresses for Basler technical support. Added descriptions of the 1X tap geometry throughout the document. Updated the camera’s back view in Fig. 1 on page 1. Modified the specification for camera power in Table 2. Corrected the AOI width increments in Section 2.3 on page 26.