SIGNALCORE SC5309A Hardware Manual

Hardware Manual SC5309A & SC5310A 2.5 GHz RF Downconverter www.signalcore.com

1 General Information ............................................................................................................................... 4 Warranty .......................................................................................................................................... 4 Copyright & Trademarks .................................................................................................................. 4 International Materials Declarations ................................................................................................ 5 CE European Union EMC & Safety Compliance Declaration ............................................................. 5 Warnings Regarding Use of SignalCore Products ............................................................................. 6 2 Physical Description ................................................................................................................................ 7 Unpacking ......................................................................................................................................... 7 Setting Up the Device ....................................................................................................................... 7 Front Interface Indicators and Connectors ...................................................................................... 8 Signal Connections ................................................................................................................ 8 Device LED Indicators .......................................................................................................... 10 Communication and Supply Connection ............................................................................. 10 Mini-USB Connection .......................................................................................................... 11 Reset Button (Pin Hole) ....................................................................................................... 12 3 Functional Description .......................................................................................................................... 13 Overview ........................................................................................................................................ 13 The Signal Chain ............................................................................................................................. 14 The RF Input ........................................................................................................................ 14 The Input Path Switch.......................................................................................................... 15 The RF Path.......................................................................................................................... 15 The First Mixer and IF1 Path ................................................................................................ 15 The Second Mixer and IF2 Path ........................................................................................... 17 The Third mixer and IF3 Path............................................................................................... 17 Signal Chain Configurations ................................................................................................. 17 The LO Module ............................................................................................................................... 19 The Reference Clocks .......................................................................................................... 19 The First Local Oscillator (LO1) ............................................................................................ 20 The Second Local Oscillator (LO2) ....................................................................................... 20 The Third Local Oscillator (LO3) ........................................................................................... 20 The Interface Module ..................................................................................................................... 21 4 Hardware Registers ................................................................................................................. 22

SignalCore, Inc. 2 SC5309A & SC5310A Hardware Manual Configuration Registers .................................................................................................................. 22 Register 0x01 INITIALIZE ...................................................................................................... 23 Register 0x02 SYSTEM_ACTIVE ............................................................................................ 24 Register 0x10 RF_FREQUENCY ............................................................................................ 24 Register 0x11 IF_FREQUENCY .............................................................................................. 24 Register 0x12 RF_AMP ........................................................................................................ 25 Register 0x13 ATTENUATOR ................................................................................................ 25 Register 0x14 SIGNAL_PATH ................................................................................................ 26 Register 0x15 CONFIG_AUTO_GAIN .................................................................................... 26 Register 0x16 STORE_DEFAULT_STATE ............................................................................... 28 Register 0x17 DEVICE_STANDBY ......................................................................................... 28 Register 0x18 REFERENCE_CLOCK ....................................................................................... 28 Register 0x19 REFERENCE_DAC ........................................................................................... 29 Register 0x1A FREQ_PLAN_PARAM ..................................................................................... 29 Register 0x1B SYNTH_MODE (2 Bytes) ................................................................................ 30 Register 0x1C SYNTH_SELF_CAL .......................................................................................... 30 Register 0x1D USER_EEPROM_WRITE ................................................................................. 31 Query Registers .............................................................................................................................. 31 Register 0x20 GET_DEVICE_PARAM .................................................................................... 32 Register 0x21 GET_TEMPERATURE ..................................................................................... 32 Register 0x22 GET_DEVICE_STATUS .................................................................................... 33 Register 0x23 GET_DEVICE_INFO ........................................................................................ 34 Register 0x24 CAL_EEPROM_READ ..................................................................................... 34 Register 0x25 USER_EEPROM_READ ................................................................................... 35 Register 0x26 SERIAL_OUT_BUFFER .................................................................................... 35 Device Parameters Data and Format ................................................................................... 36 Device Information Parameters and Format ....................................................................... 37 5 Communication Interfaces ...................................................................................................................... 1 Communication Data Format ........................................................................................................... 1 USB Interface .................................................................................................................................... 1 Control Transfer .................................................................................................................... 1 Bulk Transfer ......................................................................................................................... 1 SPI Interface ..................................................................................................................................... 2

Reading the SPI Bus ............................................................................................................... 3 RS232 Interface ................................................................................................................................ 4 Writing to the Device Via RS232 ............................................................................................ 4 Reading from the Device Via RS232 ...................................................................................... 5 PXI Express ....................................................................................................................................... 5 Setting Up the PCI to Serial Bridge ........................................................................................ 5 Writing to the Device............................................................................................................. 6 Reading from the Device ....................................................................................................... 6 6 Calibration .............................................................................................................................................. 7 Calibration EEPROM Map ................................................................................................................. 7 Absolute Conversion Gain ................................................................................................................ 8 Gain Through the RF Conversion Path .............................................................................................. 8 Applying Calibration .............................................................................................................. 8 Revision Table.............................................................................................................................................. 10

SignalCore, Inc. 4 SC5309A & SC5310A Hardware Manual 1 General Information Warranty This product is warranted against defects in materials and workmanship for a period of three years from the date of shipment. SignalCore will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor. Before any equipment will be accepted for warranty repair or replacement, a Return Material Authorization (RMA) number must be obtained from a SignalCore customer service representative and clearly marked on the outside of the return package. SignalCore will pay all shipping costs relating to warranty repair or replacement. SignalCore strives to make the information in this document as accurate as possible. The document has been carefully reviewed for technical and typographic accuracy. If technical or typographical errors exist, SignalCore reserves the right to make changes to subsequent editions of this document without prior notice to possessors of this edition. Please contact SignalCore if errors are suspected. In no event shall SignalCore be liable for any damages arising out of or related to this document or the information contained in it. EXCEPT AS SPECIFIED HEREIN, SIGNALCORE, INCORPORATED MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF SIGNALCORE, INCORPORATED SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. SIGNALCORE, INCORPORATED WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of SignalCore, Incorporated will apply regardless of the form of action, whether in contract or tort, including negligence. Any action against SignalCore, Incorporated must be brought within one year after the cause of action accrues. SignalCore, Incorporated shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow SignalCore, Incorporated’s installation, operation, or maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control. Copyright & Trademarks Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of SignalCore, Incorporated. SignalCore, Incorporated respects the intellectual property rights of others, and we ask those who use our products to do the same. Copyright and other intellectual property laws protect our

intellectual property rights of others. “SignalCore”, “signalcore.com”, and the phrase “preserving signal integrity” are registered trademarks of SignalCore, Incorporated. Other product and company names mentioned herein are trademarks or trade names of their respective companies. International Materials Declarations SignalCore, Incorporated uses a fully RoHS compliant manufacturing process for our products. Therefore, SignalCore hereby declares that its products do not contain restricted materials as defined by European Union directive 2002/95/EC (EU RoHS) in any amounts higher than limits stated in the directive. This statement assumes reliable information and data provided by our component suppliers and may not have been independently verified through other means. For products sold into China, we also comply with the “Administrative Measure on the Control of Pollution Caused by Electronic Information Products” (China RoHS). In the current stage of this legislation, the content of six hazardous materials must be explicitly declared. Each of those materials, and the categorical amount present in our products, are shown below: 鉛 Lead (Pb) 汞 Mercury (Hg) 镉 Cadmium (Cd) 六价铬 Hexavalent Chromium (Cr(VI)) 多溴联苯 Polybrominated biphenyls (PBB) 多溴二苯醚 Polybrominated diphenyl ethers (PBDE) ✓ ✓ ✓ ✓ ✓ ✓ A ✓ indicates that the hazardous substance contained in all of the homogeneous materials for this product is below the limit requirement in SJ/T11363-2006. An X indicates that the particular hazardous substance contained in at least one of the homogeneous materials used for this product is above the limit requirement in SJ/T11363-2006. CE European Union EMC & Safety Compliance Declaration The European Conformity (CE) marking is affixed to products with input of 50 - 1,000 Vac or 75 - 1,500 Vdc and/or for products which may cause or be affected by electromagnetic disturbance. The CE marking symbolizes conformity of the product with the applicable requirements. CE compliance is a manufacturer’s self-declaration allowing products to circulate freely within the European Union (EU). SignalCore products meet the essential requirements of Directives 2004/108/EC (EMC) and 2006/95/EC (product safety) and comply with the relevant standards. Standards for Measurement, Control and Laboratory Equipment include EN 61326 and EN 55011 for EMC, and EN 61010-1 for product safety.

SignalCore, Inc. 6 SC5309A & SC5310A Hardware Manual Warnings Regarding Use of SignalCore Products (1) PRODUCTS FOR SALE BY SIGNALCORE, INCORPORATED ARE NOT DESIGNED WITH COMPONENTS NOR TESTED FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN. (2) IN ANY APPLICATION, INCLUDING THE ABOVE, RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS, INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY, COMPUTER HARDWARE MALFUNCTIONS, COMPUTER OPERATING SYSTEM SOFTWARE FITNESS, FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION, INSTALLATION ERRORS, SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS, MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES, TRANSIENT FAILURES OF ELECTRONIC SYSTEMS (HARDWARE AND/OR SOFTWARE), UNANTICIPATED USES OR MISUSES, OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER (ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED “SYSTEM FAILURES”). ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS (INCLUDING THE RISK OF BODILY INJURY AND DEATH) SHOULD NOT BE SOLELY RELIANT UPON ANY ONE COMPONENT DUE TO THE RISK OF SYSTEM FAILURE. TO AVOID DAMAGE, INJURY, OR DEATH, THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES, INCLUDING BUT NOT LIMITED TO BACK-UP OR SHUT DOWN MECHANISMS. BECAUSE EACH END-USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM SIGNALCORE'S TESTING PLATFORMS, AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE SIGNALCORE PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY SIGNALCORE, THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF SIGNALCORE PRODUCTS WHENEVER SIGNALCORE PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION, INCLUDING, WITHOUT LIMITATION, THE APPROPRIATE DESIGN, PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION.

Unpacking All SignalCore products ship in antistatic packaging (bags) to prevent damage from electrostatic discharge (ESD). Under certain conditions, an ESD event can instantly and permanently damage several of the components found in SignalCore products. Therefore, to avoid damage when handling any SignalCore hardware, you must take the following precautions: 1. Ground yourself using a grounding strap or by touching a grounded metal object. 2. Touch the antistatic bag to a grounded metal object before removing the hardware from its packaging. 3. NEVER touch exposed signal pins. Due to the inherent performance degradation caused by ESD protection circuits in the RF path, the device has minimal ESD protection against direct injection of ESD into the RF signal pins. 4. When not in use, store all SignalCore products in their original antistatic bags. Remove the product from its packaging and inspect it for loose components or any signs of damage. Notify SignalCore immediately if the product appears damaged in any way. Setting Up the Device Integration of the SC5309A and SC5310A modules requires attention to maintain effective cooling. Inadequate cooling can cause the temperature inside the RF housing to rise above the maximum for this product, leading to improper performance, reduction of product lifespan, or complete product failure. SignalCore suggests providing moderate airflow across the RF housing. If active cooling is not an option, use thermal interface materials to bond the RF housing to a larger heatsinking surface (i.e. a system enclosure). As each device’s integrated system configuration is unique, detailed cooling options cannot be provided. A cooling plan is sufficient when the SC5309A and SC5310A on-board temperature sensors indicate a rise of no more than 20°C above ambient temperature under normal operating conditions.

SignalCore, Inc. 8 SC5309A & SC5310A Hardware Manual Front Interface Indicators and Connectors The SC5309A is a PXIe-based RF downconverter with all user I/O located on the front face of the module.

module. Signal Connections All signal connections (ports) on the device are female SMA-type. Exercise caution when fastening cables to the signal connections. Over-tightening any connection can cause permanent damage to the device. The condition of your system signal connections can significantly affect measurement accuracy and repeatability. Connections that are improperly mated, dirty, damaged, or worn can degrade measurement performance. Clean out any loose, dry debris from connectors with clean, low- pressure air (available in spray cans from office supply stores). If deeper cleaning is necessary, use lint-free swabs and isopropyl alcohol to gently clean inside the connector barrel and the external threads. Do not mate connectors until the alcohol has completely evaporated. Excess liquid alcohol trapped inside the connector may degrade measurement performance until fully evaporated (this may take several days). Tighten all SMA connections to 8.8 in-lb max (100 N-cm max) RF In This is the RF input port to the device with nominal impedance of 50 . Its maximum input power is +27 dBm. IF2 In This is the input to the second IF stage of the converter. Its nominal input frequency is 1250 MHz. IF Out This is the IF output of the device with nominal impedance of 50 . Ref In This is the 10 MHz refence input to the device, enabling the device to phase lock its internal clocks to an external reference source. This nominally 50  port is AC coupled. Maximum rated input power is +10 dBm.

SignalCore, Inc. 10 SC5309A & SC5310A Hardware Manual Ref Out This is the output reference port of the device, allowing for the export of its internal reference clocks. The reference frequency is selectable between 10 MHz or 100 MHz. Typical power level is 3 dBm. Device LED Indicators These are LED indicator lights for the device, and their functions are listed in Table 1 and Table 2. Table 1. Status LED Indicator LED Color Description Green The device is functioning properly in the state that it is programmed for. Amber Indicates that all functions are on standby mode. Red Indicates that one or more local oscillators are not functioning correctly. Off No supply or supply error. Table 2. Active Indicator LED Color Description Green An external interface port has accessed the device. Red Input supply voltage exceeded. Off No current interface access. Communication and Supply Connection Figure 1. Power and Digital IO Connector Power and communication to the SC5310A is provided through a Molex Milli-GridM 2.00mm pitch, 30 position, male header connector. Its part number is 87833-3020. A suggested receptacle female connector is the crimp terminal type 51110-3051 or ribbon type 87568-3093 from Molex. The pin definitions of this I/O connector are listed in Table 3. Pinouts are different for different SignalCore products with the same connector type. Please ensure that mating connectors and cables are wired correctly before connection. Table 3. Interface connector pin out description PIN # Description 1,3,5,7 12V Supply Rail

17,18 Reserved, pull high to 3.3V or DNC 19 Reset, System reset, logic 0 to reset device 21 Device Active, accessed 22 PLL status 23 RS232 Baud Rate / SPI Mode Select 25 CS Device select for SPI 26 SPI Clock 27 TX/MOSI. TX (DTE) for RS232 or MOSI for SPI 29 RX/MOSE. RX (DTE) for RS232 or MISO for SPI 30 SRDY. This pin is serial ready for SPI Mini-USB Connection This is a mini-USB Type B connector for USB communication with the device using the standard USB 2.0 protocol (full speed) found on most host computers. The pinout of this connector, viewed from the front, is shown in the following table. PIN # USB Function Description 1 VBUS Vcc (+5 Volts) 2 D- Serial Data (neg) 3 D+ Serial Data (pos) 4 ID Not Used 5 GND Device Ground (also tied to connector shell) Figure 2. Proper Removal of Latching-Style Ribbon Cable Connectors

SignalCore, Inc. 12 SC5309A & SC5310A Hardware Manual Reset Button (Pin Hole) Behind this pin hole is the reset button, which is only available on the SC5310A. Using a pin to lightly depress this momentary-action push button switch will cause a hard reset to the device, putting it back to its default settings. All user settings will be lost. System reset capability can also be accessed through the communication header connector.

Overview The SC5310A uses USB as its primary interface with an optional SPI or RS232 interface. The SC5309A is a PXIe version of the product. The downconverter assembly consists of three module parts: • The Signal Conversion Module contains the mixers, filters, signal amplifiers, and attenuators. This module is referred to as the “signal chain”. • The Synthesized Local Oscillator Module contains the 3 synthesized LO signals and the reference signal circuitry. • The Power Conditioning and Digital Control Board contains the supply switchers that generate the needs rails for the RF modules and an onboard MCU that provides both the computation engine and interface between the user and the RF modules. The figure below shows how the modules relate to each other. Figure 3. Simplified Block Representation of the Downconverter Assembly Module The downconverter has a maximum of three conversion stages. The first converted intermediate frequency (IF) stage is called IF1, whose signal is converted from the RF input signal. The second converted stage is called IF2, and the third converted stage is IF3. The converted signals in each stage are derived by mixing their respective input signal with their local oscillator (LO) signal. This mixing process results in many products and the desired product at each IF stage is picked out using band- pass filters. Signals that appear inside the passband of the filter will be passed through, while those that are outside the passband are suppressed. Generally, the farther an unwanted signal is away from the filters the better it is suppressed. Unwanted signals that are close to the passband or inside the passband are called spurious signals (or ‘spurs’ for short). Because of the wide bandwidth of the Signal Conversion Module Synthesized Local Oscillator Module Supply Conditioning and Digital Control/Interface RF Input Ref In Ref Out Digital IO Supply IF Output IF2 Input LO1 Output

SignalCore, Inc. 14 SC5309A & SC5310A Hardware Manual IF filters there are input RF frequency regions as well as IF output regions where the number and level of spurs are higher than typical, making those regions unsuitable for high dynamic range applications. The input tunable range of the downconverter is from ≈100 kHz to 2.5 GHz, while the output tunable IF3 range is from ≈10 MHz to 100 MHz. The RF is tuned using the first local oscillator (LO1) and IF3 is tuned with LO3. IF3 is tunable from 15 MHz to 140 MHz. The frequency accuracy and stability of the device is derived from an onboard Temperature Controlled Crystal Oscillator (TCXO) with accuracy better than 500 ppb. For better accuracy and stability, the downconverter can lock to an external reference of higher precision. The Signal Chain The conversion module contains the mixers, filters, amplifiers, and attenuators used to convert, purify, and maintain the amplitude of the signal, all the way from the input of the device to its output. This cascade of signal conversion and conditioning stages is often referred to as the signal chain, which is shown on the system block drawing in Figure 4. The RF Input All RF connectors are high quality female stainless steel SMA types rated to 18 GHz of operation. The RF port is AC coupled with a 0.1 𝑟���𝐹 broadband capacitor as indicated in Figure 4. The input frequency range at this port is less than 100.0 kHz to greater than 2.5 GHz. The upper limit to which the device tunes to above 2.5 GHz varies slightly from unit to unit depending on the limits of the oscillator circuitry. The usability of the upper out-of-bounds region depends on the roll-off response of the RF elliptic filter and the IF1 mixer. Figure 4. Block diagram of the signal conversion module of the downconverter assembly R I L R I L R I L LO1 3.625-6.125 GHz LO2 3.32 GHz DSA IF3 ATTEN2 This is a lowpass filter with the option for a bandpass IF2_BPF1, BW= Option IF3 MIXER RF PREAMP IF1 BPF CF=3.625 GHz BW=100 MHz IF2 LPF 500 MHz IF2_BPF0, CF=305GHz BW=20 MHZ DSA IF3 ATTEN1 DSA RF ATTEN2 DSA RF ATTEN1 IF1 CF = 3.625 GHz IF2 CF=305Hz BYPASS IF3 CONVERSION PATH RF IN IF OUT User programmable components Fixed components IF3 Freq = ~10-100 MHz RF Freq = 100kHz to 2.5 GHz From LO Module BYPASS CONVERSION PATH ELLIPTIC LPF IF2 MIXER IF1 MIXER Device controlled components LO3 420 MHz – MHz 220 MHz – MHz

Immediately following the capacitor is an RF switch to selectively direct the RF signal down two paths: 1. The default is the conversion path where the RF signal is converted to a final IF. 2. The alternative path is directly to the IF port, bypassing all means of frequency conversion. For lower RF frequency that can be digitized directly by a digitizer at the IF port, this path provides the convenience. Another reason for choosing this path for lower frequencies is that converting low RF to an IF may result in more unwanted spurs at the IF output. When the conversion path is bypassed, the conversion path and the internal LO are disabled by powering down. The RF Path The first device in the RF conversion path is a step attenuator with 1 dB step resolution. This attenuator (RF_ATTEN) is used to control the signal level at the mixer or at the RF preamplifier. If the RF level at the input of these devices is relatively large with respect to their input compression points, the signal would experience greater nonlinear effects, distorting its waveform, and producing large spurious 3rd intermodulation distortion effects. Following RF_ATTEN is a switchable RF amplifier that can be switched into the signal path to improve the device sensitivity, effectively lowering the device noise figure. In other words, the effective input noise level of the device is lowered when this amplifier is enabled. Turning on this amplifier is recommended to improve the signal-to-noise dynamic range (DRSNR) when expected signal levels are lower than -30 dBm. The typical maximum gain of the downconverter without the amplifier enabled is +30 dB. When the amplifier is enabled, its additional +15 dB will boost the typical maximum gain to +45 dB. The attenuator (RF_ATTEN2) following the amplifier switch is used together with RF_ATTEN1 to control the level at the input of the mixer. Unless the input level is very high, and the attenuation range of RF_ATTEN1 is exhausted, RF_ATTEN2 is not commonly used except when the RF amplifier is enabled. RF_ATTEN1 and RF_ATTEN2 provide 60 dB of attenuation range, which is enough to keep the device in the linear mode of operation even for signal levels near the maximum recommended value of +27 dBm. Between RF_ATTEN2 and the mixer is the RF elliptic low pass filter. This filter cuts off just above 2.7 GHz and has better than 75 dB of rejection for frequencies above 3.6 GHz. This suppresses back-travel LO leakages to better than -100 dBm (typically -120 dBm) at the input RF port. Another function of this filter is to provide superior suppression of RF image frequencies. The lack of suppression of these RF images could result in mixing with LO1 and appear as spurious components in the IF. The First Mixer and IF1 Path The first mixer (IF1 mixer) of the downconverter is very critical as it sets the dynamic ranges of the device for both the signal-to-noise and third order IMD (DRIMD) dynamic ranges. The DRSNR and DRIMD are directly related to the mixer input compression point (IP1dB) and to the input third-order

SignalCore, Inc. 16 SC5309A & SC5310A Hardware Manual intercept point (IIP3). The IIP3 of the mixer is typically better than +18 dBm, and its P1dB is better than 5 dBm. In applications that require better signal linearity, it is recommended that the level at the mixer input is kept at -20 dBm or less. Typically, the IMD is better than -75 dBc for two -20 dBm tones at the mixer. Increasing the level at the mixer improves SNR of the IF output signal at the expense of linearity. Another important characteristic of the mixer is the LO-IF isolation and LO-RF isolation. The higher the isolation, the lower the leakage LO signal is at the RF and IF ports. The IF1 mixer is driven with a ≈+20 dBm LO1 signal and the LO-IF isolation is about 45 dB, resulting in a -25 dBm LO1 leakage in the IF1 path. If the RF signal level at the mixer is -20 dBm and the mixer conversion loss is -8 dB, the converted IF1 signal is -28 dBm. For this case, the LO leakage is greater than the converted IF signal. For most of the RF input range, the LO1 leakage is not an issue because the first IF filter (IF1 BPF) will suppress it. Furthermore, when the leakage passes through the IF2 bandpass filters, it will be further suppressed. However, when the downconverter turns to lower frequency, especially when the RF is near the value of the bandwidth of these filters, the LO1 becomes an unwanted spur. The frequency relationship between the three ports of the mixer is given as: 𝐿𝑂 = 𝐼𝐹 + 𝑅𝐹 As RF approaches 0 Hz, LO -> IF, resulting in the LO leakage being inside the passband of the filter. The filters are not able to optimally reject leakages inside their passband or within their filter slope. This LO1 leakage will mix with the converted IF1 signals or with LO2 to produce higher order unwanted in-band spurs that could be large enough to affect the recovery of signal data. These intermodulation spurs are usually not so easy to determine and deal with. Having high linearity components helps maintain these spurs at acceptable levels. The linearity in these modules keeps these types of 3rd order effects at typically less than -60 dBc. In addition, the LO leakage is a known signal that shows up as the DC value when the final IF spectrum is digitized and processed. For lower RF frequencies it is recommended to switch the RF directly to a digitizer at the IF port instead of putting it through the conversion stages. The user should determine whether the application can tolerate LO leakages, what the effects will be, and decide on the most appropriate route to take. The first IF (IF1) frequency is centered typically at 3.675 GHz with a minimum bandwidth of 100 MHz. This center frequency may be adjusted programmatically from 3.675 GHz to ± 50 MHz offset. The default center frequency is set at the factory at the time of calibration to compensate for shifts in the IF1 and IF2 filter responses due to fabrication variations. Another advantage of setting the IF frequency higher is to place it closer to the filter slope region, providing better LO1 leakage suppression. This stage of conversion is an up conversion rather than a down conversion. This broadband architecture simplifies the input RF and IF1 sections to achieve: 1. Superior image rejection without the use of multiple RF bandpass filters. 2. Great RF suppression and isolation in the IF2 passband without multiple IF and LO frequency bands.

demanding phase noise requirements on the LO1 synthesizer. The Second Mixer and IF2 Path The second IF (IF2) is typically centered at 305 MHz and has settable range with 5 MHz steps. The relationship between LO2, IF1, and IF2 is: 𝐿𝑂2 = 𝐼𝐹1 − 𝐼𝐹2 IF1 and IF2 are settable with the condition that LO2 must be tuned in 5 MHz steps and have a range less than ± 50 MHz. The converted IF2 signal out of the mixer is passed through a 500 MHz filter to suppress IF1 and LO2 leakages. The IF2 LPF is not aggressive, so converted LO1 leakages that are close to the IF1 frequency may appear at relatively high values in the IF2 path. After IF2 LPF, the signal passes through the selectable bandpass filters BPF0 and BPF1, whose frequency bandwidths are dependent of the customer option for IF BW. These filters may shape the final BW of the device for low IF frequencies because there are limited filter selections. If there is a need for further signal shaping, an external LPF or BPF will need to be placed after the IF OUT port. This signal will be converted to IF3 via the third IF3 mixer. For low RF signals, BPF1 can optionally be fitted with a narrow 100 kHz BW filter to suppress LO leakages, especially for those frequencies that are less than the BW of BPF0. The Third mixer and IF3 Path The third IF (IF3) is tunable from ±5 MHz to ±100 MHz, as LO3 is tuned from 220 MHz to 420 MHz in 5 MHz steps. The negative value of IF3 indicates that the spectrum is inverted with respect to the RF input spectrum. When spectral inversion is selected, LO3 tunes below IF2 and it tunes above for no spectral inversion. There is an LPF filter in this stage to provide filtering of IF2 and LO3 leakages as well as harmonics of the IF3 signal. Attenuators IF3_ATTEN1 and IF3_ATTEN2 are used to set the output amplitude of IF3. Attenuation should be applied to IF3_ATTEN2 first and any overflow of more than 30 dB is then applied to IF3_ATTEN1. However, if better linearity is needed, apply the first 6 dB to IF3_ATTEN1 and then the rest to IF3_ATTEN2. Signal Chain Configurations Recommended signal chain configurations are provided below for various application scenarios. These are strictly recommendations and not indicative of the downconverter function limitations; users will need to adapt the device to their own applications. Low Input RF If the RF value is on the order of the bandwidth of the narrowest filter, significant LO leakage may appear at the IF output. Placing an external IF filter will provide further suppression of the leakage that appears outside of the passband. If the external digitizer can handle the RF directly, then the RF signal should be switched to the IF port directly, bypassing conversion.

SignalCore, Inc. 18 SC5309A & SC5310A Hardware Manual Converted Signals Selecting the narrower filters in the IF2 stage improves the leakage spurs, and allows for lower frequencies at both IF and RF. For example, IF3 could be set to lower for a narrow BW IF2 filter without the risk of possible increase of in-band spurs arising from LO2-LO3 intermodulation or having significant LO leakages even when the device is tuned for RF as low as 5 MHz. The final IF3 LPF is only a 5th order Chebyshev filter so the rejection slope is not particularly aggressive. This means the harmonic rejection is not as effective for some applications, especially when IF3 is low. It is recommended that an external filter be used to further suppress these harmonics. Dynamic Range Setting There are 2 sets of digital step attenuators to control the conversion gain of the downconverter. The first set consists of RF_ATTEN1 and RF_ATTEN2 and the second set consists of IF3_ATTEN1 and IF3_ATTEN2. All attenuators, except for IF3_ATTEN2, have 30 dB range and 1 dB step. Attenuator IF3_ATTEN2 has 30 dB range and 0.25 dB step. To set the downconverter for better sensitivity or better SNR, the gain should be shifted to the RF input path of the device, before the mixer. The RF pre-amplifier should be enabled if necessary and/or RF attenuation reduced. The IF3 attenuator is then used to adjust the final IF output level. The drawback is that the signal level starts off higher as it enters the first mixer as well as the subsequent components. As a result, the apparent linearity of the device is lower. To set the device for better linearity, the gain should be shifted to the output IF3 path (after the third mixer) and reduced in the RF path. The signal power level at the first mixer should be lower than -20 dB for improved linearity. Since the input signal is low, the relative SNR will be lower. But, as the first mixer and subsequent components experience lower power levels, the apparent linearity of the device is improved. When the device gain is balanced well, the device can achieve SNR better than 130 dBc/Hz while maintaining IMD3 levels close to 80 dBc. These numbers are representative of converters used in large box high end spectrum analyzers. When the device is optimized for best SNR, typical values better than -150 dBc/Hz can be achieved, and when the device is optimized for sensitivity, the input spectral noise floor is typically lower than -160 dBm/Hz. The flexible use of these attenuators allows the downconverter to achieve better than 190 dB of measurement dynamic range.

The local oscillator (LO) module contains three local oscillators, the reference clocks, and the calibration EEPROM as shown in Figure 5. Figure 5. Block diagram of the local oscillator The Reference Clocks The base clock of the downconverter is a 10 MHz Voltage Controlled Temperature Controlled Crystal Oscillator (VCTCXO) with an initial accuracy better than 500 ppb once the device has reached a stable temperature. Its initial accuracy is set at the factory via an on-board 14-bit voltage reference DAC. This DAC is accessible for dynamic accuracy calibration. The other reference is a 100 MHz Voltage Controlled Crystal Oscillator (VCXO) which is phase locked to the base reference whenever an external reference source is not used. When an external reference is selected as the base clock by enabling the device to phase lock to it, the effect only occurs when the presence of this reference is detected. In other words, although the device is programmed to lock externally it will not attempt to do so until the reference signal is detected at the input reference port. Notice, both the reference clocks will attempt to lock to the external source. Having the VCXO lock directly to the external source has the advantage of utilizing the close-in phase noise of the source; it is best to assume that the external source is superior to the internal base. Although the internal VCTCXO is not used when an external reference 100M PLL REF DETECT 10 To Signalchain Module ENABLE LO3 LO2 LO1 TCXO PLL Programmable component REF IN REF OUT Fixed component LO Section Reference Section CAL EEPROM

SignalCore, Inc. 20 SC5309A & SC5310A Hardware Manual is selected, it is important to have it remain powered on to maintain its temperature stability. Like the VCXO, it is also phase locked to the external source. The reference output is derived from the buffered VCXO. When its output is enabled, its frequency can be selected for 10 MHz or 100 MHz. Typically, output power is +3 dBm as its accuracy and stability is that of either the internal VCTCXO or external reference source. The First Local Oscillator (LO1) The first local oscillator (LO1) is a YIG based synthesizer tunable between at least 3.3 GHz and more than 6.2 GHz typically. Its multiple hybrid PLL approach gives it the advantages of having lower phase noise, very low spurs, and a small frequency step of 1 Hz. This signal drives the first mixer of the signal chain. The frequency of LO1 is set indirectly by setting the frequency plan for IF1, IF2, and the RF signal frequency. The Second Local Oscillator (LO2) The second LO (LO2) is normally fixed at 3.32 GHz, by it may be set via the frequency plan to tune between 3.1 GHz and 3.45 GHz in 5 MHz frequency steps. LO2 drives the second mixer of the signal chain. Its frequency is indirectly set using frequency plan IF1 and IF2 values using the following relationship: 𝐿𝑂2 = 𝑟���𝑟���𝑒𝑛��� ∗ 𝑒���𝑙𝑛���𝑛���𝑟 (𝐼𝐹1 − 𝐼𝐹2 𝑟���𝑟���𝑒𝑛��� ) The ability to tune LO2 allows for the optimization of IF combinations to move higher order intermodulation products that may form inside the passband to outside the passband. The Third Local Oscillator (LO3) The third LO (LO3) frequency is set indirectly with IF2 and IF3 frequency values, and the polarity of the IF3 spectrum is set with respect to the RF. IF3 can be set ideally from DC to 100 MHz. When the IF3 spectrum is set to be non-inverted, LO3 tunes from IF2 up to IF2 + 100 MHz, otherwise it tunes from IF2 down to IF2 – 190 MHz. Caution needs to be taken when tuning to the limits because of larger LO leakages and intermodulation products that could form in-band. For example, when the LO3 is set to IF2 - 100 MHz in the inverted case, the IF3 low-pass filters may not sufficiently provide the suppression needed to keep the leakage to an acceptable level at the IF output port. In this case, an external low-pass filter may be needed.

Figure 6 shows the power and control interface block for both the SC5309A and SC5310A. All supply rails are produced on board; their voltages are regulated and actively filtered to keep noise to a minimum. Thus, these downconverters are tolerant to “dirty” external power supplies. +8V, +5V, +3.3V, -5V To LO & SignalChain Modules MCU Switchers and regulators PXI Power PXI Interface Ext.Power +12V USB RS232, SPI PXI-Serial Bridge SC5309A SC5310A Figure 6. Block diagram of the power and interface module.

SignalCore, Inc. 22 SC5309A & SC5310A Hardware Manual 4 Hardware Registers The set of hardware registers of the downconverter may be divided into a configuration set and a query set; the configuration registers are write-only registers to set up the states of the device, while the query registers request the device to prepare and send back data associated with them. The registers are identical for all communication interfaces: PXIe, USB, RS232, and SPI. Data communication to all interfaces are sent in 1 byte wide, that is, data is transferred byte-by-byte. Register data lengths vary in size, and it is important that the correct number of bytes are sent for the corresponding register. Failure to do so may cause communication to lock-up and the device to become unresponsive. Configuration Registers These are write-only registers to configure the device. The registers vary in length to reduce redundant data and improve the communication speed, especially for SPI and RS232 interfaces. Furthermore, it is vitally important that the length of data written to a register is exact because failure to do so will cause the interfaces to misinterpret the incoming data, leaving the device in a stalled state. The total number of bytes is the sum of the register address (1 Byte) and its corresponding data bytes. For example, to set the RF frequency value, eight bytes must be written; the sum of the 1 register byte and 7 data bytes. See the RF_FREQUENCY register of Table 4. The table provides a summary of the configuration registers, and each register is explained in detail. Table 4. Configuration Registers Register Name Reg Add Serial Range Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INITIALIZE 0x01 [7:0] Set to zeros [7:1] Mode SYSTEM_ACTIVE 0x02 [7:0] Set to zeros [7:1] Enable “active” LED RF_FREQUENCY 0x10 [7:0] Frequency Word (Hz) [7:0] [15:8] Frequency Word (Hz) [15:8] [23:16] Frequency Word (Hz) [23:16] [31:24] Frequency Word (Hz) [31:24] [39:32] Frequency Word (Hz) [39:32] [47:40] Frequency Word (Hz) [47:40] [55:48] Set to zeros LO IF_FREQUENCY 0x11 [7:0] Frequency Word (Hz) [7:0] [15:8] Frequency Word (Hz) [15:8] [23:16] Frequency Word (Hz) [23:16] [31:24] Frequency Word (Hz) [31:24] [39:32] Frequency Word (Hz) [39:32] [47:40] Frequency Word (Hz) [47:40] [55:48] Set to zeros RF_AMP 0x12 [7:0] Set to zeros [7:1] Enable ATTENUATOR 0x13 [7:0] 0 Attenuator value [15:8] Set to zeros [15:11] Attenuator Number [23:16] Set to zeros [23:16] SIGNAL_PATH 0x14 [7:0] If3 fil#2 select If3 fil#1 select IF2 filter select 0 Bypass IF3 conv Ext. IF2 select Bypass convert [15:8] Set to zeros [15:10] Rf amp invert

CONFIG_AUTO_GAIN 0x15 [7:0] Set to zeros [7:5] Linear mode Auto ctrl amp Load params Auto Enable [15:8] Sign Absolute RF level (0 - 127) dB [6:0] [23:16] Sign Absolute mixer level (0 - 127) dB [6:0] [31:24] Sign Absolute IF level (0 - 127) dB [6:0] [39:32] Set to zeros STORE_DEFAULT_STATE 0x16 [7:0] Set all to zeros DEVICE_STANDBY 0x17 [7:0] Set to zeros [7:4] Device sections Enable REFERENCE_CLOCK 0x18 [7:0] [7:4] set to zeros PXI 10 enable Clk 100 enable Ref out enable Lock ext REFERENCE_DAC 0x19 [7:0] DAC WORD [7:0] [15:8] 0 0 DAC WORD [13:8] [23:16] Set to zeros FREQ_PLAN_PARAM 0x1A [7:0] Frequency word (Hz) [7:0] [15:8] Frequency word (Hz) [15:8] [23:16] Frequency word (Hz) [23:16] [31:24] Frequency word (Hz) [31:24] [39:32] Frequency word (Hz) [39:32] [47:40] Frequency word (Hz) [47:40] [55:48] Set to zeros [55:52] PARAM [3:0] SYNTH_MODE 0x1B [7:0] Set to zeros [7:2] Loop Gain SYNTH_SELF_CAL 0x1C [7:0] Set all to zeros USER_EEPROM_WRITE 0x1D [7:0] BYTE DATA [7:0] [15:8] ADDRESS [7:0] [23:8] ADDRESS [15:8] Register 0x01 INITIALIZE This register initializes the devices to the default state or reprograms all the device components with the current state parameters. Note, this register does not need to be called in order to program the device. Bytes written 2 Bytes read 1 Bits Type Name Width Description [0] WO Mode 1 0 = Resets the current state 1 = Resets the default to the default or startup state [7:1] WO Unused 7 Set to zeros [7:0] RO Read back byte 8 Read 1 byte back is required for PXIe and RS232

SignalCore, Inc. 24 SC5309A & SC5310A Hardware Manual Register 0x02 SYSTEM_ACTIVE This register turns on or off the active LED indicator on the front connector interface of the device. This register should be called when the device is opened or closed in software. Bytes written 2 Bytes read 1 Bits Type Name Width Description [0] WO Mode 1 0 = Turns off the active LED 1 = Turns on the active LED [7:1] WO Unused 7 Set to zeros [7:0] RO Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x10 RF_FREQUENCY This register tunes the device to the input RF frequency. Bytes written 8 Bytes read 1 Bits Type Name Width Description [47:0] W Frequency word 48 Frequency word in milli-Hz (mHz); mHz used for future compatibility [48] W LO 1 Set to 1 to apply value directly to the first LO. The RF frequency value is unchanged. [55:49] W Unused 7 Set to zeros [7:0] RO Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x11 IF_FREQUENCY This register sets the final IF value. Bytes written 8 Bytes read 1

future compatibility [55:48] W Used 8 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x12 RF_AMP This register enables and disables the RF amplifier. Bytes written 2 Bytes read 1 Bits Type Name Width Description [0] W Frequency word 1 0 = Disables the RF amplifier 1 = Enables the RF amplifier [7:1] W Unused 7 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x13 ATTENUATOR This register sets the value of the device attenuators. Bytes written 4 Bytes read 1 Bits Type Name Width Description [7:0] W Attenuator value 8 In 0.25 dB steps, i.e. LSB = 0.25 dB [10:8] W The target attenuator 3 The attenuator number: 0 = RF Atten #1 1 = RF Atten #2 3 = IF3 Atten #1 4 = IF3 Atten #2 [23:11] W Unused 13 Set to zeros

SignalCore, Inc. 26 SC5309A & SC5310A Hardware Manual Bits Type Name Width Description [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x14 SIGNAL_PATH This register configures how the signal chain is routed. Bytes written 2 Bytes read 1 Bits Type Name Width Description [0] W rfPreAmp 1 0 = Turn off RF amp 1 = Turn on RF amp. This parameter is only valid if autogain is off or autogain auto_ctrl_rf_amp is off. [1] W If2Filter 1 0 = Selects the IF2 filter #0 1 = Selects the IF2 filter #1 (custom option) [2] W invertSpectrum 1 0 = Not spectral inversion 1 = IF3 spectrum inverted w.r.t RF [3] W Bypass_rf_conversion 1 0 = RF is converted to IF 1 = RF is directed to the IF port (used for low frequencies) [7:4] W Not used 4 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x15 CONFIG_AUTO_GAIN This register will configure the device to set the attenuator values and control the RF amplifier to keep the device gain close to the desired gain with changes in RF frequency, as computed from its input parameters such as RF input level, mixer level, and IF out level. Bytes written 6 Bytes read 1

manipulated when RF values are changed 1 = Computes and applies new sets of attenuator and amplifier states to the device as frequency is changed [1] W loadParams 1 0 = Not to load new input parameter such as RF level, etc. Will not load any information from bits [47:2] 1 = Will load bits [31:2] [2] W autoCntrlRfAmp 1 0 = Computation will leave the state of the RF amplifier unchanged 1 = Computation will change the state of the RF amplifier to provide the best device configuration to meet the input parameter requirements [4:3] W linearMode 2 0 = Best signal-to-noise (SNR), least linear 1 = Better SNR, sufficiently linear 2 = Better linearity, sufficient SNR 3 = Best linearity, least SNR [7:5] W Unused 3 Set to zeros [14:8] W rfLevel 7 Set the absolute level of the expected RF input level in dB. [15] W rfLevel Sign bit 1 0 = Positive 1 = Negative [22:16] W mixerLevel 7 Set the absolute level of the expected input mixer level in dB [23] W mixerLevel Sign bit 1 0 = Positive 1 = Negative [30:24] W ifLevel 7 Set the absolute level of the expected output IF3 level in dB [31] W ifLevel Sign bit 1 0 = Positive 1 = Negative [39:32] W Unused 8 Set to zeros

SignalCore, Inc. 28 SC5309A & SC5310A Hardware Manual Bits Type Name Width Description [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x16 STORE_DEFAULT_STATE This register will store all current settings of the device into EEPROM and will become the default startup setting. Bytes written 2 Bytes read 1 Bits Type Name Width Description [7:0] W Unused 8 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x17 DEVICE_STANDBY This register sets either the entire device or sections of the device into standby mode. Placing a section into standby involves powering down its circuitry. This conserves power and eliminates unwanted LO signals when they are not used. Bytes written 2 Bytes read 1 Bits Type Name Width Description [0] W State 1 0 = Active 1 = Standby enabled [7:4] W Unused 4 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x18 REFERENCE_CLOCK This register configures the reference clock behavior. Bytes written 2 Bytes read 1

1 = Enables frequency locking to external 10 MHz reference source [1] W RefOutEnable 1 Reference out port enabled [2] W Clk10Enable 1 0 = 10 MHz output 1 = 100 MHz output [3] W PXI10Enable 1 Only on SC5309A to enable export of the 10 MHz backplane clock [7:2] W Unused 4 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x19 REFERENCE_DAC This register makes adjustments to the 10 MHz TCXO accuracy via DAC to its tuning port. Bytes written 4 Bytes read 1 Bits Type Name Width Description [15:0] W Tuning DAC word 16 DAC WORD [23:16] W Unused 8 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x1A FREQ_PLAN_PARAM This register sets up the frequency plan parameters and stores them as the default values. Bytes written 8 Bytes read 1 Bits Type Name Width Description [47:0] W Data 48 Data for the parameter

SignalCore, Inc. 30 SC5309A & SC5310A Hardware Manual Bits Type Name Width Description [50:48] W Parameter 3 0 = RF frequency 1 = IF1 frequency 2 = IF2 frequency Filt#0 path 3 = IF2 frequency Filt#1 path 4 = IF3 frequency 5 = LO2 pll step size 6 = LO3 pll step size [55:51] W Unused 5 Set to zeros [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x1B SYNTH_MODE (2 Bytes) This register configures the PLL loop gain of the local oscillator synthesizers. It also enables or disables faster tuning of the YIG based oscillator of LO1. Bytes written 2 Bytes read 1 Bits Type Name Width Description [1:0] WO Loop Gain 2 0 = Low loop gain, improves phase noise > 50 kHz 1 = Normal loop gain 2 = High loop gain, improves phase noise < 50 kHz [7:2] WO Unused 5 Set to zeros [7:0] RO Read back byte 8 Read 1 byte back is required for PXIe and RS232 Register 0x1C SYNTH_SELF_CAL This register will start the YIG synthesizer calibration. Note that although the calibration procedure takes about 6-8 seconds to complete, the register returns a byte almost immediately. Bytes written 2 Bytes read 1 Bits Type Name Width Description [7:0] W Unused 8 Set to zeros

8 Read 1 byte back is required for PXIe and RS232 Register 0x1D USER_EEPROM_WRITE This register writes a byte to the onboard EEPROM. Bytes written 4 Bytes read 1 Bits Type Name Width Description [7:0] W Data 8 Byte to be written to the address [23:8] W Address 16 EEPROM address [7:0] R Read back byte 8 Read 1 byte back is required for PXIe and RS232 Query Registers These are request for data registers, in that a request for certain data is made by writing to the specific register first, followed by reading back the requested data. Some registers may require instruction data to specify the type of data to return, while others do not need any. For example, the register GET_DEVICE_PARAM (0x30) returns the RF Frequency, IF1 Frequency, IF3 Frequency, etc.; the data returned depends on the parameter value of the instruction byte. Returned data length is always 8 bytes (64 bits), with the first byte being the most significant (MSB). It is important that all 8 bytes are read to clear the interface buffers. How the different interface buses handle the return data is explained in the Device Information Parameters and Format section. Table 5. Query Registers Register Name Reg Add Serial Range Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GET_DEVICE_PARAM 0x20 [7:0] Parameter GET_TEMPERATURE 0x21 [7:0] Zeros [7:0] GET_DEVICE_STATUS 0x22 [7:0] Zeros [7:0] GET_DEVICE_INFO 0x23 [7:0] Info CAL_EEPROM_READ 0x24 [7:0] EEPROM ADDRESS [7:0] [15:8] EEPROM ADDRESS [15:8] USER_EEPROM_READ 0x25 [7:0] EEPROM ADDRESS [7:0] [15:8] EEPROM ADDRESS [15:8]

SignalCore, Inc. 32 SC5309A & SC5310A Hardware Manual Register Name Reg Add Serial Range Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SERIAL_OUT_BUFFER 0x26 [7:0] Zeros [7:0] [15:8] Zeros [15:8] [23:16] Zeros [23:16] [31:24] Zeros [31:24] [39:32] Zeros [39:32] [47:40] Zeros [47:40] [55:48] Zeros [55:48] Register 0x20 GET_DEVICE_PARAM Write to this register the required device parameter to query from the device. Bytes written 2 Bytes read 8 Bits Type Name Width Description [3:0] W Parameter 1 0: Returns current RF frequency 1: Current IF1 frequency 2: Current IF2 frequency 3: Current IF3 frequency 4: Current LO1 frequency 5: Current LO2 frequency 6: Current LO3 frequency 7: Current attenuator values 8: Current signalchain configuration [7:4] W Unused 4 Set to zeros [63:0] R Read back bytes 64 Returned Data (See Device Parameter Data section for more info) Register 0x21 GET_TEMPERATURE Write to this register to query the device temperature. Bytes written 2 Bytes read 8

[31:0] R Temperature Data 32 These 32 bits of data need to be type casted back to float. i.e. var_float = *(float*)&var_u32 where var_u32 is some unsigned integer that holds the 32 bits of read data. [63:32] R Invalid data 32 Ignore Register 0x22 GET_DEVICE_STATUS Write to this register to query the current operating conditions. Bytes written 2 Bytes read 8 Bits Type Name Width Description [7:0] W Unused 7 Set to zeros [0] R Pll status: LO1 sum 1 The summing PLL of LO1 [1] R Pll status: LO1 crs 1 The coarse tuning PLL of LO1 [2] R Pll status: LO1 fine 1 The fine tuning PLL of LO1 [3] R Pll status: LO2 1 LO2 [4] R Pll Status: LO3 1 LO3 [5] R Pll status: VCXO 1 100 MHz OCXO [6] R Pll status: TCXO 1 TCXO, only valid when lock to external reference is enabled [7] R Pll status: ref_detect 1 Detected a reference signal of sufficient amplitude [8] R Device Accessed 1 When the SET SYS ACTIVE register is accessed [9] R LockExtRef 1 Enable device to lock to external reference [10] R RefOutEnable 1 Reference output enable

SignalCore, Inc. 34 SC5309A & SC5310A Hardware Manual Bits Type Name Width Description [11] R RefOutFreqSelect 1 10MHz(0) or 100MHz(1) selected as output reference frequency [12] R loopGain 2 Pll loop gain: 0 = Low 1 = Normal 2 = High [14] R IF2FilterSelect 1 IF2 filters: 0 = filt#0 1 = filt#1 [16] R Device standby 1 0 = Device off standby 1 = Device in standby mode [17] R rfAmpEnable 1 RF amplifier is enabled [18] R autoRfAmp 1 Auto set the RF preamplifier when autoGainEnable = 1 [19] R autoGainEnable 1 Auto calc of gain enabled (default 0). Software gain calculation used. 1 = Gain can be read back from device (less accurate) [63:20] R Invalid data 29 Ignore Register 0x23 GET_DEVICE_INFO Write to this register to query the device information such as serial number. Bytes written 2 Bytes read 8 Bits Type Name Width Description [3:0] W DeviceInfo 4 0: Product serial number and Interface type 1: Firmware and hardware revision 2: Calibration and manufacture date [7:4] W Unused 4 Ignore [63:0] R Data 64 Information data (see Device Info data) Register 0x24 CAL_EEPROM_READ Write to this register to query 8 bytes of data from the user EEPROM at the starting address.

Bytes read 8 Bits Type Name Width Description [15:0] W Address 16 Starting EEPROM address [23:16] W Unused 8 Zeros [63:0] R Data 64 8 bytes of data, LSB is the byte at the start address Register 0x25 USER_EEPROM_READ Write to this register to query 8 bytes of data from the user EEPROM at the starting address. Bytes written 4 Bytes read 8 Bits Type Name Width Description [15:0] W Address 16 Starting EEPROM address [23:16] W Unused 8 Zeros [63:0] R Data 64 8 bytes of data, LSB is the byte at the start address Register 0x26 SERIAL_OUT_BUFFER Writing to this register only provides the 64 clock edges (Reg + 7 data bytes) to transfer serial data from the device through SPI. Other interfaces do not use this register. Bytes read 8 Bits Type Name Width Description [55:0] W Unused 56 Zeros, just to provide clocking for SPI data from device [63:0] R Data 64 8 bytes of data

SignalCore, Inc. 36 SC5309A & SC5310A Hardware Manual Device Parameters Data and Format The data read back from the GET_DEVICE_PARAM register has a total of 8 bytes, however not all bytes contain valid data. The table below shows the valid data for each of the parameters. Table 6. Device parameter data Device Parameter Name Param num Data type Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 RF FREQ 0 U64 zeros Data IF1 FREQ 1 U64 zeros Data IF2 FREQ 2 U64 zeros Data IF3 FREQ 3 U64 zeros Data LO1 FREQ 4 U64 zeros Data LO2 FREQ 5 U64 zeros Data LO3 FREQ 6 U64 zeros Data ATTEN VALUES 7 8xU8 zeros NA NA NA RF A1 RF A2 IF3 A1 IF3 A2 CHAIN CONFIG 8 2xU16 zeros zeros zeros zeros SC Gain SC Config Frequency parameter values Frequency parameter values are returned in the first 7 bytes with the last byte padded with zeros. The least significant bit (LSB) is 1/1000 Hertz (the data is returned in 1 one thousandth of a Hertz). Divide the data by 1000 to obtain the result in Hertz. Attenuator values Each attenuator value is returned as one byte and the LSB is in 0.25 dB. Divide each byte by 4 to obtain the result in dB. Signal Chain Configuration The signal chain configuration data is in the first 2 bytes, and their data is represented in the following table. Table 7. Signal chain configuration data representation Bit Description [0] RF preamplifier state [1] IF spectral inversion [2] IF2 filter selection [7:3] NA The first order computed gain (device approx.) of the device is returned in bytes 3 and 4. Data bits [14:0] represent the absolute value in 1/100 of a dB, while bit [15] is the sign bit.

Not all the 8 bytes read back contain valid data. The following table shows the valid bytes of data for each of the parameters. Device Parameter Name Param num Data type Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 INTERFACE 0 U32 Intrfce Serial Number REVISIONS 1 F32 Software revision Firmware revision DATES 2 U32 Mfg year Month Day Cal year Month Day Interface Information The first 4 bytes contain the device serial number as an unsigned 32-bit integer. Byte [4] contains the interface as represented in the following table. Table 8. Interface ID Bit Description [0] PXI/PXIe [1] USB [2] SPI [3] RS232 [7:4] Undefined Revision Information The first 4 bytes represent the hardware revision and the last 4 bytes represent the firmware revision of the device. These 4 bytes encompass a 32-bit floating point number so the data needs to be type casted from an unsigned 32-bit value to float value. Date Information The first 4 bytes represent the manufactured date and the last 4 bytes represent the last calibration date. The date format is outlined in the following table. Bit Type Description [0] U8 Day [1] U8 Month [4:3] U16 Year (i.e. 2016)

The SC5309A has a PXI express interface, while the SC5310A has 2 communication interfaces: 1. USB and SPI 2. USB and RS232 This section will examine the communication aspects of the product, focusing on data transfer to and from the device on each interface. Although the registers are identical for all interfaces, there are subtle differences in the implementation of the interfaces to transfer the data. Communication Data Format All data sent and received by all interfaces is sent as buffers of unsigned bytes. For example, to change RF frequency of the device to 2.5 GHz we perform the following: 1. Frequency is sent in 1000th of Hertz, so the data that represents the frequency is 2,500,000,000,000 milli-Hertz. 2. This number can be represented by a 64-bit unsigned long, and in Hexadecimal is 0x 0000 0574 FBDE 6000. Only the least 6 bytes are needed to represent all frequencies allowable for this device. 3. A byte data buffer needs to be 8 bytes for register RF_FREQUENCY (address 0x10), so the byte array buffer to be sent would be: [0x10][0x00][0x05][0x74][0xFB][0xDE][0x60][0x00] The register address byte [0x10] is the first member of the buffer to be sent. USB Interface There are 2 transfer types for the USB interface. • Control transfer • Bulk transfer Control Transfer The USB control transfer parameters are: ENDPOINT_IN 0x80 ENDPOINT_OUT 0x00 TYPE_VENDOR 0x40 RECIP_INTERFACE 0x01 Bulk Transfer The USB bulk transfer parameters are: ENDPOINT_IN 0x83 ENDPOINT_OUT 0x04

SignalCore, Inc. 2 SC5309A & SC5310A Hardware Manual The bulk transfer from the host to the device operates on a loopback with a data buffer of 8 bytes. When a device register is addressed, and upon completion of the register task, such as changing frequency, it will send back 8 bytes, which the host must read to clear the transfer buffers. Unlike the other interface methods, where only the required number of bytes needs to be sent for a given register, 8 bytes are needed for every USB bulk transfer. For example, if a configuration register requires only 4 bytes to be sent, these bytes will be the first of the 8 bytes and the last 4 bytes are zeros. The returned 8 bytes do not carry valid data for a configuration register. However, they do carry valid data for query registers. SPI Interface The SPI interface on the device is implemented using an 8-bit (single Byte) buffer for both the input and output, hence, it needs to be read and cleared by the device before consecutive bytes can be transferred to and from it. The process of clearing the SPI buffer and decisively moving it into the appropriate register takes CPU time, so a time delay is required between consecutive bytes written to or read from the device by the host. The chip-select pin (𝐶𝑅��� ̅̅̅) must be asserted low before data is clocked in or out of the product. Furthermore, pin 𝐶𝑅��� ̅̅̅̅ must be asserted low for the entire duration of a register transfer. Once a full transfer has been received, the device will proceed to process the command and de- assert low the SRDY pin. The status of this pin may be monitored by the host because when it is de- asserted low, the device will ignore any incoming data. The device SPI is ready when the previous command is fully processed and the SRDY pin is re-asserted high. It is important that the host either monitors the SRDY pin or waits for 500 𝜇𝑟��� between register writes. There are 2 SPI modes: 0 and 1. The default mode is 1, where data is clocked in and out of the device on the falling edge of the clock signal. In mode 0, data is clocked in and out on the rising edge. To select mode 0, pin 23 of the interface connector must be pulled low to ground as the device is powered on or as the reset line (pin 19) is toggled low-high. If pin 23 is pulled high or left unconnected, mode 1 is selected. Figure 7. SPI Mode 1 shown. Register writes are accomplished in a single write operation. Register lengths vary depending on the register. They vary in lengths of 2 to 8 bytes, with the first byte sent being the register address followed by the data associated with that register. The (𝐶𝑅��� ̅̅̅) pin must be asserted low for a minimum period of 1 𝜇𝑟��� (𝑅���𝑆, see Figure 8) before data is clocked in, and must remain low for the entire register write. The clock rate may be as high as 5.0 MHz (𝑅���𝐵��� = 0.2 𝜇𝑟���), however, if the external SPI signals do not have sufficient integrity due to trace issues, the rate should be lowered. MSB CS MISO MOSI CLK MSB LSB LSB

As mentioned above, the SPI architecture limits the byte rate since after every byte transfer the input and output SPI buffers need to be cleared and loaded respectively by the device SPI engine. Data is transferred between the input buffer and internal register buffers. The time required to perform this task is indicated by 𝑅���𝐵, which is the time interval between the end of one byte transfer and the beginning of another. The recommended minimum time delay for 𝑅���𝐵 is 1 𝜇𝑟���. The number of bytes transferred depends on the register. It is important that the correct number of bytes is transferred for the associated register, because once the first byte (MSB) containing the device register address is received, the device will wait for the desired number of associated data bytes. The device will hang if an insufficient number of bytes are written to the register. To clear a hung condition, the device will need an external hard reset. The time required to process a command is also dependent on the command itself. Measured times for command completions are typically between 50 𝜇𝑟��� to 300 𝜇𝑟��� after reception. Writing the SPI Bus The SPI transfer size (in bytes) depends on the register being targeted. The first byte sent is the register address and subsequent bytes contain the data associated with the register. As data from the host is being transferred to the device via the MOSI line, data present on its SPI output buffer is simultaneously transferred back, MSB first, via the MISO line. The data returned is invalid for configuration registers. The following figure shows the contents of a single 3-byte SPI command written to the device. The Hardware Registers section provides information on the number of data bytes and their contents for an associated register. There is a minimum of 1 data byte for each register even if the data contents are “zeros”. Figure 9. Example of a 3-byte write Reading the SPI Bus Data is simultaneously read back during an SPI transfer cycle. Requested data from a prior command is available on the device SPI output buffers, and these are transferred back to the user host via the MISO pin. To obtain valid requested data would require querying the SERIAL_OUT_BUFFER, which requires 8 bytes or 64 clock cycles; 1 byte for the device register (0x37) and 7 empty bytes (MOSI) to clock out the returned data (MISO). An example of reading the device RF parameters (IF3 frequency) from the device is shown in the following figure. TS TB TC 8 Bit Command/ Reg. Address Byte N (MSB) Byte N-1 (LSB) CLK DATA CS 23 15 7 0 Register Address Byte 1 Byte 0

SignalCore, Inc. 4 SC5309A & SC5310A Hardware Manual Figure 10. Query example: Write followed by Read to the GET_SERIAL_BUFFER In the figure above, the first transfer cycle is to make the request for IF3 frequency data through the GET_DEVICE_PARAM register. The subsequent cycle is to clock the data that was requested by sending 64 clocks into the GET_SERIAL_BUFFER register. RS232 Interface The RS232 version of the SC5310A has a standard interface buffered by an RS232 transceiver so that it may interface directly with many host devices, such as a desktop computer. The interface connector for RS232 communication is labeled “Digital I/O” on the front of the panel. Refer to Table 3. Interface connector pin out descriptionfor position and pin-out information. The RS232 device communication control set is provided in the following table. Table 9. RS232 Control Setting Baud rate Rate of transmission *Pin 16 of the Digital IO connector selects the rate. By default, if the pin is pulled high or open, the rate is set to 56700 at power up or upon HW reset. When the pin is pulled low or grounded, the rate is set to 115200 upon reset or power up. Data bits The number of bits in the data is fixed at 8. Parity Parity is 0 (zero) Stop bits 1 stop bit Flow control 0 (zero) or none Only 3-wire RS232 is required since hardware flow control is not used. These connections are the Tx, Rx, and Gnd. This interface is common on most host computers and microcontrollers, so user access to host ports is readily provided by the computer OS or microcontroller hardware registers. Writing to the Device Via RS232 It is important that all necessary bytes associated with any one register are fully sent. In other words, if a register requires a total of 6 bytes (address plus data), then all 6 bytes must be sent even though the last byte may be null. The device, upon receiving the first register addressing byte, will wait for all the associated data bytes before acting on the register instruction. Failure to complete the register transmission will cause the device to behave erratically or hang. Information for writing to the configuration registers is provided in Table 4. Configuration Registers. Upon the 0x20 CLK MOSI CS MISO 0x03 Invalid Invalid 0x37 0x00 0x00 0x00 0x00 0x00 Byte 7 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 0x00 Byte 5 Request for IF3 frequency from the GET_DEVICE_PARAM register Clock out the 6 bytes with write to the GET_SERIAL_OUT_BUFFER register (0x26) 0x00 Byte 6

to indicate success. This byte must be read by the host to clear its receive buffer so that reading subsequent registers will not contain corrupted data. Furthermore, reading back this byte will ensure that the device is ready for the next register command. Reading from the Device Via RS232 To query information from the device, the query registers are addressed, and data is returned. Table 5. Query Registers contains the query register information. As with the configuration registers, it is important that all data byte(s) (write) associated with the query registers are sent even if they are null. All queries will return 8 bytes of data (read) with the first received byte being the most significant (MSB). Section 4.2 Query Registers provides the format details of the received data. PXI Express The PXIe interface contains a high-speed PCIe-to-Serial bridge chip. This bridge chip communicates with the onboard microcontroller serially. The interface on the bridge chip resides at offset addresses between 0x00 and 0xFF from BAR0; which is memory mapped. A kernel level driver for the operating system is needed to access this memory address. A simple driver using IO controls should be sufficient to read and write byte data to this block of addresses. Although SignalCore provides the driver and API for these products, information is provided here for users who may need to write drivers for a different operating system or a different driver. An example would be writing the API for the Linux operating system. Setting Up the PCI to Serial Bridge The serial function of the bridge chip must first be initialized before it can communicate with the onboard microcontroller, and hence communication between the microcontroller and the PXIe bus. The initialization can be done at the kernel level mode or at the user level mode, the decision is left to the user. The following table lists the programming order of the bridge register addresses to initialize and setup the serial port function. Step BAR0 Register Address Data (Byte) 1 0x88 0x01 2 0x04 0x00 3 0x03 0x80 4 0x00 0x04 5 0x01 0x00 6 0x03 0x03 7 0x02 0x07

SignalCore, Inc. 6 SC5309A & SC5310A Hardware Manual Writing to the Device Bytes that are written to the device must go through the bridge chip. In this section, we will first look at the write cycle of each byte, and then the write cycle of each device register. Do note the difference between the bridge register addresses and the device register addresses. Single Byte Write The serial transfer buffer register address is located at 0x100 offset from BAR0 of the bridge chip, however, before writing byte data to this register, its status needs to be checked to confirm that it is ready to accept a new buffer set of bytes. The status register is located at 0x05; it must be read and bit 7 must be high to indicate that the transfer register is ready to receive the next byte buffer. Checking the status register of the serial bridge chip is required before every new command write. Device Register Write The process of writing the device registers is the same as writing an RS232 port, so the description of Section 5.4.1 Writing to the Device Via RS232 is applicable. Writing the device registers involves sending byte-by-byte data as described previously. Section 4.1 Configuration Registers provides information on the number of configuration write bytes needed for each device register. The first byte sent is the device register address, followed by the most significant byte of the register’s associated data. When a device register is fully written, that is, all its data has been sent to the device, it will return 1 byte. This returned byte must be read (by the host) to clear the transfer buffer so that later received data are not corrupted. Section 5.5.3.1 Single Byte Read describes how a byte read cycle is performed. Reading from the Device Device data is passed back to the host via the bridge chip byte-by-byte. Details about a single byte read process and an entire register read process are explained in the following subsections. Single Byte Read The serial transfer buffer register address is located at 0x00 offset from BAR0 of the bridge chip. Before valid data can be read from the transfer register, its ready status must first be confirmed. The status register is located at 0x05; it must be read and bit 0 must be high to indicate that valid data is available. Checking the status register for available data is required before every byte read. Device Register Read After a write request to the device is made, 8 bytes of data is available to be read back. Use the single byte read process, as mentioned previously, to read all the bytes. See Section 4.2 for information of the exact number of request write bytes and the number of request read bytes, which is 8. All 8 bytes must be read to fully clear the transfer buffer; the first byte read is the most significant byte.

Table 10 represents the EEPROM map of the device calibration values. All values are stored as little- endian 4-byte floating point numbers. Every point is 4-bytes long. Access to the data is possible through the CAL_EEPROM_READ register, which reads 8 bytes starting at the address pointed to by the register input. Table 10. Calibration EEPROM Map Offset address Points Length (Bytes) Data Type Description 0x00 664 664 U_8 Factory Reserved 0x3F8 1 4 Float_32 Calibration temperature 0x3FC 2 8 Float_32 Temp coeff C1, C2 0x498 21 84 Float_32 IF3_response cal frequencies 5, 10, 15, …,100, in MHz 0x510 21 84 Float_32 IF3 relative gain response to the IF set for absolute RF gain measurement 0x72C 30 120 Float_32 Relative If3_atten#1, 1-30 dB, 1 dB step 0x7A4 30 120 Float_32 Relative If3_atten#2, 1-30 dB, 1 dB step 0x938 1 4 Float_32 Relative IF2 Filt#1 gain 0x93C 1 4 Float_32 Relative spectral inversion gain 0x1A58 35 140 Float_32 RF cal freq, 5, 10, 20,…90, 100, 200,300,… 2500, in MHz 0x1AF8 35 140 Float_32 Absolute RF gain at each cal freq 0x1B98 35 140 Float_32 Relative RF amp gain at each cal freq 0x1C38 30x35 4200 Float_32 RF atten#1, 1-30 dB, 1 dB step for each freq a1_f0, a1_f1,…,a1_fN a2_f0, a2_f1,…,a2_fN a30_f0, a30_f1,…,a30_fN Data is row catenated 0x2EF8 30x35 4200 Float_32 RF atten#2, 1-30 dB, 1 dB step for each freq a1_f0, a1_f1,…,a1_fN a2_f0, a2_f1,…,a2_fN a30_f0, a30_f1,…,a30_fN Data is row catenated

SignalCore, Inc. 8 SC5309A & SC5310A Hardware Manual Absolute Conversion Gain It is difficult to make gain measurements of every configuration setting of the downconverter as there are many combinations of attenuator and frequency settings, not to mention the various operating temperatures. However, the gain of the device can be computed to a reasonable level of accuracy with less data if the assumption is that every component setting is independent from one another. For example, assume the attenuator state of the IF3_ATTEN#1 does not affect the state of IF3_ATTEN#2, so with this independence there are only 2*30 attenuation measurements that need to be made; there is a mutually exclusive relationship. On the other hand, if they are not independent, for every setting of IF_ATTEN#1, 30 measurements are needed for IF3_ATTEN#2, bringing the total number of measurements to 30*30. Gain Through the RF Conversion Path Assuming independency, and to be able to compute the gain of the downconverter at any setting, an absolute reference state of the device must be determined first. Once this reference state is established, compensation can be applied to other relative configured states of the device. The established reference state of the device is as follows: • All attenuators are set to 0 dB. • IF2 Filter setting is 0. • Inverted spectrum set to 0. • RF amplifier disabled, set to 0. • IF frequency is set at user specific setting or defaults to 50 MHz. • RF is tuned to the list frequencies: 5, 10, 20, …, 90, 100, 200, 300, …, 2500 MHz. The gain of the device in this state is measured at each frequency of the list. This set of measurements is the RF absolute gain stored at starting address 0x1B98 of the calibration EEPROM. Measurements taken for deviations from this reference setting are relative. Applying Calibration The amplifier gain, IF filter selections, and attenuator values are relative measurements from the absolute reference values made over various RF frequencies. These relative values are either subtracted (attenuation) or added (gain) to the absolute gain value to determine the gain of the relative configuration. For example, assume the RF_ATTEN#1 is at 20 dB, IF3_ATTEN#1 is at 10 dB, IF2_Filter bank is set to 1, IF3 frequency is set to 15 MHz, and the RF frequency is set to 1.550 GHz. A possible systematic approach would be: 1. Compute the relative RF Atten#1 value by interpolation because there is no measurement value at 1.55 GHz. A simple linear interpolation between the measured 1.5 GHz and 1.6 GHz values should provide a good estimate. A local spline interpolation over 5-6 surrounding points would provide better accuracy. Let us call this value 𝑟𝑒���_𝑎𝑟���𝑟���𝑒𝑛1. 2. The IF3 Atten#1 attenuation value is read directly from memory: the 15th index of the attenuator array ATTEN3#1[15]. Let us call this correct attenuation value 𝑖𝑒���3_𝑎𝑟���𝑟���𝑒𝑛1.

IF response array. Let us call this the 𝑖𝑒���3_𝑟𝑒𝑟���𝑛���𝑛���𝑛𝑟���𝑒. 4. The IF2 filter gain is read directly from memory, which we shall call 𝑖𝑒���2_𝑒���𝑖𝑙𝑟���𝑒𝑟. 5. The absolute gain at the frequency can be determined using interpolation between 2 absolute gain points, which we shall call 𝐹���_𝑎𝑎���𝑟���. 6. The gain for this configuration is calculated using: 𝐹��� = 𝐹���𝑎𝑎���𝑟��� + 𝑖𝑒���2𝑒���𝑖𝑙𝑟���𝑒𝑟 + 𝑖𝑒���3_𝑟𝑒𝑟���𝑛���𝑛���𝑛𝑟���𝑒 − 𝑟𝑒���𝑎𝑟���𝑟���𝑒𝑙���1 − 𝑖𝑒���3𝑎𝑟���𝑟���𝑒𝑙���1 If the current device temperature is different from the calibration temperature, the gain correction due to temperature difference is computed using ∆𝐹���𝑟���𝑒𝑙���𝑙��� = 𝐶1(𝑅��� − 𝑅���0) + 𝐶2(𝑅��� − 𝑅���0)2 . ∆𝐹���𝑟���𝑒𝑙���𝑙��� is the gain correction, 𝐶1 and 𝐶2 are the first and second order temperature gain coefficients respectively, and 𝑅��� and 𝑅���0 are the current temperature and calibration temperature respectively. Adding this correction to the previously calculated gain will compensate the value for temperature deviation. 𝐹��� = 𝐹���𝑎𝑎���𝑟��� + 𝑖𝑒���2𝑒���𝑖𝑙𝑟���𝑒𝑟 + 𝑖𝑒���3𝑟𝑒𝑟���𝑙���𝑙���𝑙���𝑟���𝑒 + ∆𝐹���𝑟���𝑒𝑙���𝑙��� − 𝑟𝑒���𝑎𝑟���𝑟���𝑒𝑙���1 − 𝑖𝑒���3𝑎𝑟���𝑟���𝑒𝑙���1

SignalCore, Inc. 10 SC5309A & SC5310A Hardware Manual Revision Table Revision Revision Date Description 1.0 8/10/18 Initial Release 1.1 2/26/19 Added feature to signal path register 16. Changed figure 6 to reflect latest conversion path implementation. 1.2 4/14/20 Updated tunable IF3 range. 2.0 8/13/20 Updated formatting.