Fujitsu MB86R02 Hardware Manual

MB86R02 ‘Jade-D’ Graphics Controller Hardware Manual Fujitsu Semiconductor Europe GmbH Release 1.64 (amended) (17.09.2013 13:11) This document is subject to changes and corrections without prior warning

Preface Intention and Target Audience of this Document This document describes and gives you detailed insight to the stated Fujitsu semiconductor product. The MB86R02 ‘Jade-D’ device is the successor of Fujitsu’s MB86R01 ‘Jade’ and contains both improvements and many new features. This target audience of this document is engineers developing products which will use the MB86R02 ‘Jade-D’ device. It describes the function and operation of the device. Please read this document carefully. Trademarks APIX is a registered trademark of Inova Semiconductors GmbH, Grafinger Str. 26, 81671 Munich, Germany. ARM is a registered trademark of ARM Limited in UK, USA and Taiwan. ARM is a trademark of ARM Limited in Japan and Korea. ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan. ARM Powered logo is a trademark of ARM Limited in Korea. ARM926EJ-S and ETM9 are trademarks of ARM Limited. System names and the product names which appear in this document are the trademarks of the respective company or organization. Licenses Under the conditions of Philips corporation I2C patent, the license is valid where the device is used in an I2C system which conforms to the I2C standard specification by Philips Corporation. The purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. Any information in this document, including functional descriptions and schematic diagrams, shall not be construed as license of the use or the exercising of any intellectual property rights, such as patent rights or copyright or any other right of FUJITSU or any third party or does FUJITSU warrant non- infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured for general use, including unrestricted ordinary industrial use, general office use, personal use, and household use but are not designed, developed and manufactured for use accompanying fatal risks or dangers that, unless extremely high safety levels are ensured, could have a serious effect to the public and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon systems), or (2) for use requiring extremely high reliability (i.e., submarine or satellite technology). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by the Japanese government will be required for export of those products from Japan. All rights reserved and Copyright © FUJITSU SEMICONDUCTOR EUROPE 2010

Document Change History Version Date Editor Comment V1.64 (amended) 17.09.2013 RvReitzenstein Table ‘Pin Functional Description’ rectified. Amended row are marked with a change bar on the right side. Amended entries are marked bold. V1.64 30.01.2013 von Treuberg Extended section 17.2.1.3 ' Jade-D Restrictions'. Removed reference to Application note on APIX jitter (no longer applies). Added hint on using Demand Mode for DMA/UART transfers. V1.63 30.01.2012 von Treuberg Changed RSDS electrical characteristics. V1.62 07.11.2011 von Treuberg Changed Channel Mapping table (26.6). V1.61 21.09.2011 von Treuberg Corrected pin names in chapters 1, 7, 17: APIX_n_SB > APIXn_SB_ APIX_SB0 > APIX0_SB APIX_SB1 > APIX1_SB APIX_SB5-0 > APIX0_SB APIX1_SB5-0 > APIX1_SB Modified section 5.1.13 (Only ES2 > Not available in ES1) Extended Driving capability 2: list in 34.4.1, 3.3V Standard CMOS I/O. RLD: Changed statement 'little endian' to 'big endian'. Removed 'Uplink' in description of CH0CFG/CH1CFG bits 6:3. The swing setting has an effect regardless of RX/TX usage. Corrected GPIO listings (number of GPIOs effected) with concern to CMPX_MODE_10 descriptions in mulitplex overview and register description. Added an additional note concerning multiplex mode #3 if the pins are unused (check the table for multiplex mode #3). Corrected 9.6.1: address of instruction vector table to 0000_0080H. Corrected IRQ connections diagram in chapter 9. IRQ5 is connected to IRC2. Added information about unused case for TRACEDATA_X pins in pinmultiplex mode #3. Replaced MediaLB Signal Timings chapter. V1.60 29.10.2010 von Treuberg Added new section in Electrical Characteristics: 'Transmitter Serial Data Signal Characteristics' V1.50 25.03.2010 von Treuberg SSCG: Modified modulation peak values (e.g. 3% > 2x 1.56%), added SSCG settings table for recommended value of 20 kHz. CRG: Modified table 5-1 Clock Overview List Electrical Characteristics: Added important requirement for APIX PLL stability (power-on procedure) EXTBUS: 11.6.1 corrected typo in description for NOR flash page access mode. CNT: Corrected reset values of register CAXI_PS and CMUX_MD. EXTBUS: modified diagram in section 11.8 (Word write access to 16 bit width SRAM/NOR Flash) I2S: corrected FIFO size from previously documented 18/36

Words, to the implemented size of 66/132 Words. CCNT: Modified CCID register fields. Electrical Characteristics: changes: (1) Table 34-1 Maximum Ratings (2) Table 34-3 3.3V Standard CMOS I/O Recommended Operating Conditions, added driving capabilities. (3) New section: APIX Characteristics (4) Added RSDS characteristics GDC: 18.6.3.3 Direct Color (24 bits/pixel) – corrected RGBA table (A field is only 1 bit) GDC: Extended all LxEC descriptions for RGBA (e.g. L1EC, L2EC etc.) RLD: byte alignment information added to StrideCfg1 register. Limitations information added to AHBMTransferWidth Setup section. V1.40 19.10.2009 von Treuberg Overview: Unused pins - changed handling of OSC_FILTER, changed handling of XTRST pin. GPIO: re-inserted block diagram (mistakenly removed) IRC: removed IRQs as only required for debugging DMAC: Corrected line to MPX_MODE_1[1:0] = "HL" in section 'Related Pins'. Corrected DMA configuration A register (DMACAx), BC[3:0] and TC[15:0] function descriptions. RLD: added more detail to DestAddress register description Electrical characteristics, almost all tables modified CRG: corrected initial value of CRAM register. TCON: exchanged Figure 22-4 Block diagram of TSIG. SSCG: updated register description UART: changed table 28-2: (external input condition: CLK = 25.0MHz, CRIPM[3:0] = 0001) Addendum (differences ES1/ES2): added note about APIX TX initialization V1.30 24.07.2009 von Treuberg CCNT: Corrected typo in description of register CAXI_PS ADDENDUM: Added note about JTAGSEL polarity DMAC: changed hex value in second diagram of section '15.8.1 DMA start in Single channel' GPIO: corrected base address in table 24-1 DDR2: several small corrections concerning DRIMRx and OCD adjustment CCNT: Added note that only 32 bit access to DDR is poss. when in big endian mode. Extended description of multiplex mode/function selection register CMUX_MD. Corrected ChipID register displayed values. Overview + Addendum: modified MUX tables for better understanding. Added cell types to pin overview. Memory map: changed RHlite to APIX, added SSCG area. Modified Register Access description. I2C: added 'Example of a slave address transmission' GPIO: new block diagram and note about configuration of differential pair configuration in MUX mode 4, function 4 SIG: added limitation for cyclic monitoring mode. SSCG: added base address to register description.