Sharp ER-A440 Service Manual

CAUTION EXTREME CAUTION MUST BE TAKEN WHEN SERVICING THIS MACHINE. EVEN THOUGH THE MODE SWITCH IS IN THE OFF POSITION, VOLTAGE IS STILL SUPPLIED TO THE ENTIRE MACHINE. WHEN WORKING ON THIS MACHINE MAKE SURE THAT THE POWER CORD IS REMOVED FROM THE WALL OUTLET. CHAPTER 1. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 CHAPTER 2. OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CHAPTER 3. SERVICE (SRV) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 CHAPTER 4. HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 CHAPTER 5. TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 CHAPTER 6. DOWN LOAD FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 CHAPTER 7. SERVICE PRECAUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 CHAPTER 8. CIRCUIT DIAGRAM & PWB LAYOUT . . . . . . . . . . . . . . . . . . . 8-1 PARTS GUIDE SHARP CORPORATION CONTENTS This document has been published to be used for after sales service only. The contents are subject to change without notice. Parts marked with " " is important for maintaining the safety of the set. Be sure to replace these parts with specified ones for maintaining the safety and performance of the set.

1. Appearance/Rating 1) Rating Power source AC 120 V ±10% 50/60Hz Power consumption Standby: 11.5 W Maximum: 40 W (max.) Operating temperature 0°C~40°C (32°F~104°F) Operating humidity 10%~90% (RH) Physical dimensions, including the drawer 420(W)  427(D)  292(H)mm 16.5(W)  16.8(D)  11.5(H)in. Weight 28.7 lbs (13 kg) 2. Keyboard 1) Standard keyboard layout Fig. 2-1 2) Key top name WYPL2 WYPL2 WYPL2 WYPL2 RECEIOT # PCPT CL NS 0 00 1 2 3 4 5 6 7 8 9 1 6 11 16 2 7 12 17 3 8 13 18 4 9 14 19 5 10 15 20 CA/AT CHK CH CONV FS SHIFT AUTO 1 AUTO 2 PLU/SUB TAX1 SHIFT TAX2 SHIFT TAX FS TEND SBTL MDSE SBTL JOURNAL CASH PRINT %1 %2 PO VOID # RA RFND @/ FOR Standard Key Top KEY TOP DESCRIPTION 0 to 9,00 Numeric keys • Decimal point key CL Clear key @/FOR Multiplication/split-pricing key 1 to 20 Department 1 to 20 keys ↑ R Receipt Paper Feed key ↑ J Journal Paper Feed key RCPT Receipt print & on/off key # Non-Add Code key AUTO 1, 2 Automatically Entry key 1, 2 CASH # Cashier code entry key NS No Sales key Discount key % 1, 2 % key 1, 2 PO 1, 2 Paid Out key RA Received on Account key VOID Void key PLU/SUB PLU/Subdept code entry key SBTL Subtotal key CH Charge key CA/AT Cash/amount tendered TAX1 SHIFT TAX1 shift key TAX2 SHIFT TAX2 shift key TAX Tax key KEY TOP DESCRIPTION PRINT Validation print key RFND Refund key CONV Currency conversion key CHK Check key MDSE SBTL Merchandise subtotal key FS SHIFT Food stamp shift key FS TEND Food stamp tendered key Optional Key Top KEY TOP DESCRIPTION % 3, 4 % key 3, 4 2, 3, 4 Discount key 2, 3, 4 AUTO 3 ∼ 10 Automatically entry key 3 ∼ 10 CA 2 Cash total 2 key CH 2 ∼ 5 Charge key 2 ∼ 5 CR 3, 4 Credit key 3, 4 21 to 50 Department 21 to 50 key TAX3 SHIFT TAX3 shift key TAX4 SHIFT TAX4 shift key RA2 Received on account key 2 PO2 Paid out key 2 CONV2 ∼ 4 Currency conversion key 2 ∼ 4 CHK2 Check key 2 RFND SALE Refund sales key BIRTH Birthday key 1 to 68 Direct price lookup/Subdepartment keys 1 – 1

Fig. 3-1 * The key can be removed in the REG or OFF position. * In the SRV’ mode, key inputs are prohibited and no display is made. * With the key in the off position power is not supplied to the main PWB. [Functions] • Function for each key position • SRV’: System reset • SRV: Service mode (Service programming) • PGM2: Allows programming of an item that is not changed frequently, in addition to the PGM1 mode program- ming. • PGM1: Allows programming of items frequently changed (e.g. department, PLU pricing, and discount rate setting). • OP, X/Z: Allows X or Z operation by servers or cashiers. • REG: Allows registrations. • MGR: Allows the operations, by authorized person such as a manager (e.g. correction after transaction finished or cancellation of entry limits), which are not permitted to ordinary cashiers. • X1/Z1: Allows reading and resetting of a day’s sales total. • X2/Z2: Allows reading or resetting sales totals in a specified period. • OFF: Switching off the display to prevent key board entries. (The setting turn off the AC power.) 4. Display 1) Layout Operator display Fig. 4-1 7 segment display (LED) No. of positions 10 Color of display Yellow Green Character size 14.2 (H)  8.0 (W) mm Customer display (Pop-up display) Fig. 4-2 7 segment display (LED) No. of positions 7 Color of display Yellow Green Character size 14.2 (H)  8.0 (W) mm Display contents Display Position Description Amount 1-8 Minus sign 4-10 –: Floating Error 10 E PGM Mode 10 P VOID Mode 10 u CA/AT CHK, CR 10 F: Lights up when a registration is finalized by depressing CA/AT, CHK, CR key SUB TOTAL/ short tender 10 o Change 10 C: Light up whenever the change due amount appears in the display. Department 9-10 No zero-suppressed PLU 5-10 No zero-suppressed Repeat 8 Endless count, starting from 2. Decimal point 3-1 TAB Receipt OFF 9 (–) Cashier No. 2-3 –xx–: free code VP compulsory 10 U: Light up when the validation printing is compulsory Sentinel 10 Light up the decimal point 5. Printer (DP-730) 1) Specifications • Part number: DP-730 • No. of stations: 2 • Printing system: Mechanical serial dot • Direction of printing: Bidirectional • Printing capacity: Receipt – 24 characters Journal – 24 characters Validation – 55 characters (one line only) • Character size: 1.36 (W)  2.75 (H) mm at 7  7 dots Print pitch: Column distance Row distance 1.59 mm 5.08 mm • Total number of dots: Receipt – 108 dots/216 positions Journal – 108 dots/216 positions Validation – 248 dots/495 positions • Font: 7  7 dots (including half dot) Space between characters – 1 dot (2 positions) X2/Z2 X1/Z1 MGR REG OP,X/Z PGM1 PGM2 (SRV) (SRV') OP SM MA SRV OFF 1 – 2

0.353 mm (H)  0.353 mm (W) • Journal near end sensor: Service route option • Print speed: Approx. 3.0 lines/sec. • Paper feed speed: Receipt – Approx. 30 lines/sec. Journal – Approx. 30 lines/sec. • Reliability: MCBF – 4 million lines (excluding the print head) Head life – 50 million characters (at 4 dots/1 character/ 1 pin) • Validation form sensor: Not setup 2) Printing area Receipt/journal Fig. 5-1 Validation form Fig. 5-2 3) Paper • Paper roll dimensions: 44.5±0.5mm in width, 83mm in diameter • Paper quality: Journal Bond paper (paper thickness: 0.06 to 0.09mm, paper weight: 52.3 to 64g/m2) Validation form Thickness: 0.07 to 0.14mm Size: 130mm or more (W)  70mm or more (H) 4) Inking • Ink supply system: Ink ribbon • Form: Cartridge/Endless ribbon • Specification: Material – Nylon • Ribbon life: Approx. 6 million characters • Print color: Purple (single color) 5) Logo stamp: None 6) Cutter • Method: Manual 6. Drawer 1) Specification (1) Drawer box and drawer Model name SK-423 Size 420 (W)  427 (L: included lock key)  112 (H: included rubber leg) Color GRAY 368 Material Metal Bell — Release lever Standard equipment; Situated at the bottom Drawer open sensor Standard equipment 2) Money case For "U" version For "A" version Separation from the drawer Allowed Allowed Separation of the coin com- partments from the money case Disallowed Disallowed Bill separator — YES Number of compartments 5B/5C 4B/8C 3) Lock Location of the lock Front Method of locking and unlocking Locking: Insert the drawer lock key into the lock and turn it 90 degrees counterclockwise. Unlocking: Insert the drawer lock key into the lock and turn it 90 degrees clockwise. Key No. SK1-1 87.08 44.5± 0.5 RECEIPT JOURNAL Unit : mm 37.87 44.5± 0.5 3.56 3.56 3.56 37.87 4.2 3.56 70 130 ~ 210 87.08 (PRINT AREA) 20 22 Unit : mm 5B/8C Bill compartments Coin compartments Bill separator 5B/5C For "U" Version For "A" Version 1 – 3

1. System configuration Fig. 1-1 (NOTE1) This symbol shows NEW MODEL COMPUTER LOCAL PURCHASE OPTION RAM ER-03RA ER-A440 MASTER MACHINE CABLE 3.5 inch FDD ER-01/02FD COMMERCIAL PRODUCT ER-04DW REMOTE DRAWER 2 – 1

ER-03RA 512K bytes RAM CHIP 2 REMOTE DRAWER ER-04DW 3 PRESETS LOADER ER-01FD/02FD FD unit 4 KEY TOP KIT ER-11KT7 1 × 1 KYE TOP UNIT ER-12KT7 1 × 2 KYE TOP UNIT ER-22KT7 2 × 2 KYE TOP UNIT ER-11DK7G 1 × 1 DUMMY KYE KIT ER-51DK7G 5 × 1 DUMMY KYE KIT 5 COIN CASE ER-55CC2 for "U" version 6 COIN CASE ER-48CC2 for "A" version 3. Service options No. NAME PARTS CODE PRICE RANK DESCRIPTION 1 SERVICE KEY AF 2 MODE KEY GRIP COVER AL OP key only 3 DRIP-PROOF KEYBOARD COVER BE Include the switch cover 4 JOURNAL NEAR END SENSOR BB 5 TEXT PRESET KEYBOARD COVER BH 4. Service tools No. NAME PARTS CODE PRICE RANK DESCRIPTION 1 RS-232 LOOP BACK CONNECTOR BU 2 KEY TOP REMOVER BB 5. Supplies No. NAME PARTS CODE PRICE RANK DESCRIPTION 1 ROLL PAPER AR 5 roll/pack 2 INK LIBBON AZ 6. Options For installation of the options, refer to the Installation Manual which is issued separately. 2 – 2

MASTER RESET 1. SRV. reset (Program Loop Reset) Used to return the machine back to its operational state after a lock- up has occurred. Procedure • Method 1 1) Unplug the AC cord from the wall outlet. 2) Set the mode switch to (SRV′) position. 3) Plug in the AC cord to the wall outlet. 4) Turn to (SRV) position from (SRV′) position. • Method 2 1) Set the mode switch to PGM2 position. 2) Turn off the AC switch. 3) While holding down JOURNAL FEED key and RECEIPT FEED key, Turn on the AC switch. Note: When disassembling and reassembling always power up us- ing method 1 only. Method 2 will not reset the CKDC8. Note: SRV programming job#926-B must be set to "4" to allow PGM program loop reset. 2. Master reset (All memory clear) There are two possible methods to perform a master reset. • MRS-1 Used to clear all memory contents and return machine back to its initial settings and return keyboard back to default keyboard layout. Procedure 1) Unplug the AC cord from the wall outlet. 2) Set the MODE switch to the (SRV′) position. 3) Plug in the AC cord to the wall outlet. 4) While holding down JOURNAL FEED key, turn to (SRV) position from (SRV′) position. • MRS-2 Used to clear all memory and keyboard contents. This reset returns all programming back to defaults. The keyboard must be entered by hand. This reset is used if an application needs different keyboard layout other than that supplied by a normal MRS-1. Procedure 1) Unplug the AC cord from the wall outlet. 2) Set the MODE switch to the (SRV′) position. 3) Plug in the AC cord to the wall outlet. 4) While holding down JOURNAL FEED key and RECEIPT FEED key, turn to (SRV) position from (SRV′) position. 5) Key position assignment: After the execution of MRS-2, only the RECEIPT FEED and JOURNAL FEED keys can remain effective on key assignment. Any key can be assigned on any key position on the main key- board. [key setup procedure] NOTES: 1: When the 0 key is pressed, the key of the key number on display is disabled. 2: Push the key on the position to be assigned. With this, the key of the key number on display is assigned to that key position. Key number Key name Key number Key name 1 Numeric key "0" 10 Numeric key "9" 2 Numeric key "1" 11 Numeric key "00" 3 Numeric key "2" 12 Numeric key "000" 4 Numeric key "3" 13 Decimal point key 5 Numeric key "4" 14 CL key 6 Numeric key "5" 15 @/FOR key 7 Numeric key "6" 16 SBTL key 8 Numeric key "7" 17 CA/AT key 9 Numeric key "8" MRS-2 executed Key position set Free key Disable Free key setup complete. *2 *1 0 0 3 – 1

1. Hard ware block diagram Fig. 1-1 CPU GATE ARRAY MPCA7 DRAWER STANDARD RAM1 32KBx2 OPTIONAL RAM 512KB ER-03RA:512KB STANDARD ROM 256KB SWITCH KEY BOARD RS232 I/F 1 ports CKDC8 1 LINE 7SEG 7DIG 1 LINE 7SEG 10DIG CUSTOMER DISPLAY OPERATER DISPLAY PRINTER DP-730 RAM2 4 – 1

2-1. CPU (HD6415108-10) 1) Pin configuration HD6415108-10 pin configuration Fig. 2-1 RES NMI VSS P10 P11 P12 P13 P14 P15 P16 P17 D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 STBY MD2 MD1 MD0 VCC RFSH LWR HWR RD AS E VSS XTAL EXTAL VSS TXD2 RXD2 TXD1 RXD1 SCK2 UASKC IRQ1 IRQ0 VCC AVCC AN3 AN2 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 P41 P42 P43 P44 P45 P46 P47 VSS P50 P51 P52 P53 P54 P55 P56 P57/STOP P60 P61 P62 P63 P64 P65 P66 P67 VSS AVSS AN0 AN1 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 78 80 81 82 83 84 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS WAIT BACK BREQ P33 P34 P35 P36 P37 VCC P40 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 X 4 – 2

Fig. 2-2 P47 FTI2 P45 FTI1 P43 P42 P41/TMCI P40 P37 P36 P35 P34 P33 BREQ BACK WAIT P27/A23 P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS MD2 MD1 MD0 RES STBY NMI AS RD HWR LWR RFSH EXTAL XTAL E P17 P16 P15 P14 P13 P12 P11 P10 D7 D6 D5 D4 D3 D2 D1 D0 STOP/P57 P56 FMRS P54 P53 P52 P51 P50 P67 P66 RS/P65 RR/P64 CD/P63 CS/P62 DR/P61 ER/P60 P73 AN2 AN1 AN0 TXD2 RXD2 TXD1 RXD1 SCK2 IRQ2 IRQ1 IRQ0 H8/500 CPU DTC Serial communication interface x 2ch 8bit timer 16bit free running timer x 2ch Refresh controller Wait state controller A/D convertor Interruption controller Clock oscillator Watch dog timer Data bus Port 1 Data bus (Lower) Data bus (Upper) Address bus Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Address bus X 4 – 3

PIN No. SYMBOL SIGNAL NAME IN/ OUT FUNCTION 1 IN RESET INPUT from CKDC WUTH BUFFER 2 IN NON-MASKABLE INTERRUPT INPUT FOR SSP INTERRUPT INPUT 3 VSS VSS GND 4 P10 ERC OUT EVENT READ CANCEL (to CKDC) 5 P11 LDRQ OUT LOAD REQUEST (to CKDC) 6 P12 /SHEN IN SHIFT ENABLE (from CKDC) 7 P13 /FRES OUT FISCAL MEMORY RESET (NU) 8 P14 BUSY IN FISCAL MEMORY BUSY (NU) Pull-up 9 IN FISCAL MEMORY READY (NU) Pull-up 10 IN POP-UP DISPLAY SENSOR (NU) Pull-up 11 P17 IN GND Nu 12 D0 D0 I/O DATA BUS 0 13 D1 D1 I/O DATA BUS 1 14 D2 D2 I/O DATA BUS 2 15 D3 D3 I/O DATA BUS 3 16 D4 D4 I/O DATA BUS 4 17 D5 D5 I/O DATA BUS 5 18 D6 D6 I/O DATA BUS 6 19 D7 D7 I/O DATA BUS 7 20 VSS VSS GND 21 A0 A0 OUT ADDRESS BUS 0 22 A1 A1 OUT ADDRESS BUS 1 23 A2 A2 OUT ADDRESS BUS 2 24 A3 A3 OUT ADDRESS BUS 3 25 A4 A4 OUT ADDRESS BUS 4 26 A5 A5 OUT ADDRESS BUS 5 27 A6 A6 OUT ADDRESS BUS 6 28 A7 A7 OUT ADDRESS BUS 7 29 A8 A8 OUT ADDRESS BUS 8 30 A9 A9 OUT ADDRESS BUS 9 31 A10 A10 OUT ADDRESS BUS 10 32 A11 A11 OUT ADDRESS BUS 11 33 A12 A12 OUT ADDRESS BUS 12 34 A13 A13 OUT ADDRESS BUS 13 35 A14 A14 OUT ADDRESS BUS 14 36 A15 A15 OUT ADDRESS BUS 15 37 VSS VSS GND 38 A16 A16 OUT ADDRESS BUS 16 39 A17 A17 OUT ADDRESS BUS 17 40 A18 A18 OUT ADDRESS BUS 18 41 A19 A19 OUT ADDRESS BUS 19 42 A20 A20 OUT ADDRESS BUS 20 43 A21 A21 OUT ADDRESS BUS 21 44 A22 A22 OUT ADDRESS BUS 22 45 A23 A23 OUT ADDRESS BUS 23 46 VSS VSS GND 47 /WAIT /WAIT IN Wait signal from MPCA 48 OUT Bus control request acknowl edge (Nu) 49 /BREQ /BREQ IN Bus control request (Nu) pull-up 50 P33 DOPS IN Drawer open sencer signal 51 P34 /DR0 OUT Drawer open drive signal 52 P35 /DR1 OUT Option drawer 1 drive signal 53 P36 NU IN (Nu) GND 54 P37 NU IN (Nu) GND 55 VCC VCC +5V 56 P40 /IFV IN Slip printer enable (Nu) pull-up 57 IN Printer (Dp-730) timing signal from MPCA PIN No. SYMBOL SIGNAL NAME IN/ OUT FUNCTION 58 P42 /TOF IN Slip TOF signal (Nu) pull-up 59 P43 /BOF IN Slip BOF signal (Nu) pull-up 60 IN Printer (Dp-730) Reset signal from MPCA 61 P45 /NEJ IN Near END signal jounal 62 IN CKDC interface shift enable signal (NU) GND 63 P47 /NER IN Near END signal receipt 64 VSS VSS GND 65 P50 TRG1 OUT Dot pulse adjust signal 66 P51 /PSTOP OUT Nu 67 P52 /CKDCR2 OUT Nu 68 P53 OPDS IN Nu (GND) 69 P54 FVPON OUT Nu 70 P55 FMRS IN Nu (GND) 71 P56 /SLIPLMP OUT Nu 72 P57 /STOP OUT Nu 73 OUT ER signal for RS232 (Equipment Ready) 74 IN DR signal for RS232 (Data set Ready) 75 IN CS signal for RS232 (Clear to Send) 76 IN CD signal for RS232 (Carrier Detect) 77 OUT RR signal for RS232 (Ready to Receive) (Nu) 78 OUT RS signal for RS232 (Request to Send) 79 IN CI signal for RS232 (Calling Indicator) 80 IN Printer (Dp-730) Home position pulse 81 VSS VSS GND 82 AVSS AVSS IN GND 83 P70 VPJ IN Validation sensor journal (NU) GND 84 P71 VPR IN Validation sensor receipt (NU) GND 85 P72 VPTEST IN +24V test input 86 P73 IN Validation sense signal (Nu) GND 87 AVCC AVCC IN +5V 88 VCC VCC +5V 89 P80 /iRQ0 IN Interrupt signal 0 from MPCA 90 IN Interrupt signal from OPTION PWB 91 P82 /iRQ2 IN Interrupt signal (Nu) pull-up 92 P83 SCK2 OUT CKDC & FMC i/F sync shift clock 93 P84 RXD IN RS232C RECEIVE DATA 94 P85 TXD OUT RS232C SEND DATA 95 IN CKDC, Fiscal memory unit I/F shift input data 96 OUT CKDC, Fiscal memory unit I/F shift output data 97 VSS VSS GND 98 EXTAL EXTAL IN X-TAL (14.7456MHz) 99 XTAL XTAL IN X-TAL (14.7456MHz) 100 VSS VSS GND 101 φ φ OUT System clock (7.3728MHz) 102 E OUT E clock (NU) 103 /AS /AS OUT Address strobe 104 /RD /RD OUT Read 105 /HWR /WR OUT Write 106 /LWR OUT Nu 107 /RFSH /RFSH OUT Refresh cycle (NU) 108 VCC VCC +5V 109 MD0 MD0 IN +5V (MODE 3) 110 MD1 MD1 IN +5V (MODE 3) 111 MD2 MD2 IN GND (MODE 3) 112 /STBY /STBY IN +5V (Nu) 4 – 4

1) Pin configuration GATE ARRAY (LZ9AH39) MPCA7 Fig. 2-3 1 RF 2 JF 3 PCUT 4 FCUT 5 VF 6 STAMP 7 SLF 8 SLRS 9 SLMTD 10 RES 11 TRG 12 TRG 13 POFF 14 INT1 15 HTS1 16 SCK1 17 STH1 18 NU 19 NU 20 VCC 21 GND 22 NU 23 VRESC 24 SLTMG 25 SLRST 26 AS 27 RD 28 WR 29 PHAI 30 SDT7 31 SDT6 32 SDT5 33 GND 34 SDT4 35 SDT3 36 SDT2 37 SDT1 38 D0 39 D1 40 D2 160 NU 159 DOTEN 158 TWAIT 157 NU 156 NU 155 NU 154 NU 153 NU 152 STH2 151 SCK2 150 HTS2 149 SLMTR 148 SLMTS 147 SLMTD 146 RJMTR 145 RAS3 144 NU 143 GND 142 VCC 141 ASKRX 140 NU 139 NU 138 NU 137 RJMTD 136 RJMTS 135 DT5 134 DT6 133 DT7 132 GND 131 DT1 130 DT2 129 DT3 128 DT4 127 RJTMG 126 RJRST 125 RAS1 124 RAS2 123 ROS2 122 ROS1 121 OPTCS 41 D3 42 GND 43 D4 44 D5 45 D6 46 D7 47 SSPRQ 48 RESET 49 INT2 50 INT3 51 RXDI 52 TXDI 53 SCKI 54 IRQ0 55 A0 56 A1 57 A2 58 A3 59 A4 60 A5 61 GND 62 VCC 63 A6 64 A7 65 A8 66 A9 67 A10 68 A11 69 A12 70 A13 71 A14 72 A15 73 A16 74 A17 75 A18 76 A19 77 A20 78 A21 79 A22 80 NU 120 EXINT0 119 EXINT1 118 EXINT2 117 EXINT3 116 WRO 115 RDO 114 RA15 113 RA16 112 GND 111 RA17 110 RA18 109 EXWAIT 108 WAIT 107 NU 106 MCR1 105 NU 104 DAX1 103 RCKX 102 IRRX 101 GND 100 VCC 99 UATX 98 UARX 97 UASCK 96 IRTX 95 RCO 94 NU 93 NU 92 NU 91 NU 90 MA15 89 TEST 88 MD0 87 MD1 86 IPLON 85 INT4 84 PRST 83 PTMG 82 TRGI 81 A23 4 – 5

Fig. 2-4 MTD MTD RJMTR SLMTD SLMTS SLMTR SLMTD TXDI SCKI RXDI HTS1 SCK1 STH1 HTS2 SCK2 STH2 ROS1 ROS2 RAS1 RAS2 RAS3 OPTCS AS RD WR RDO WRO Φ RESET RES VRESC POFF MD0 MD1 WAIT RJRST SLRST *PRST RJTMG SLTMG PTMG INT4 INT1 INT2 INT3 EXINT0 EXINT1 EXINT2 EXINT3 SDT1~7 DT1~9 TEST IRQ0 A23~A0 SSPRQ SLF SLRS VF RF JF FCUT PCUT STAMP TRGI TRG TRG DOTEN IRLON D0~D7 Φ Address decode External CS Internal CS RASEL Image control SSP comparison register BAR. Buffer Read/write control Divider CHS serial select Multiplexer WAIT control CAPS select Print gate Print pulse control Print mode PMD INTO control Printer control port Motor drive * Output selection with CAPS. PRST/PTMG. EXWAIT I/R Control IRTX IRRX RCI ASKRX 4 – 6

Pin No. Signal name In/ Out Function 1 RF Out Receipt side paper feed solenoid 2 JF Out Journal side paper feed solenoid 3 PCUT Out Printer partial cut signal (NU) 4 FCUT Out Printer auto cut signal (NU) 5 VF Out Multi line validation paper feed (NU) 6 STAMP Out Printer stamp signal (NU) 7 SLFS Out Slip printer paper feed singnal (NU) 8 SLRS Out Slip printer release signal (NU) 9 SLMTD Out Slip printer motor drive signal (NU) 10 RES Out Peripheral output reset 11 TRG Out Dot head trigger signal (NU) 12 TRG Out Dot head trigger signal 13 POFF In Power off signal input 14 INT1 In (NU) 15 HTS1 Out 8 bit serial port output (for CKDC8) 16 SCK1 Out Serial port shift clock output (for CKDC8) 17 STH1 In 8 bit serial port input (for CKDC8) 18 RAS VZ — Chip select (NU) 19 — — Nu 20 VCC — +5V 21 GND — GND 22 INTMCR — Interrupt (NU) 23 VRESC Out Turns active when reset and power down is met 24 SLTMG In Slip printer timing signal (NU) 25 SLRST In Slip printer reset signal (NU) 26 AS In Address strobe 27 RD In Read strobe 28 WR In Write strobe 29 φ In (φ) System clock (7.3728 MHz) 30 SDT7 Out Slip printer printhead drive signal (dot7) (NU) 31 SDT6 Out Slip printer printhead drive signal (dot6) (NU) 32 SDT5 Out Slip printer printhead drive signal (dot5) (NU) 33 GND — GND 34 SDT4 Out Slip printer printhead drive signal (dot4) (NU) 35 SDT3 Out Slip printer printhead drive signal (dot3) (NU) 36 SDT2 Out Slip printer printhead drive signal (dot2) (NU) 37 SDT1 Out Slip printer printhead drive signal (dot1) (NU) 38 D0 I/O Data bus 0 39 D1 I/O Data bus 1 40 D2 I/O Data bus 2 41 D3 I/O Data bus 3 42 GND — GND 43 D4 I/O Data bus 4 44 D5 I/O Data bus 5 45 D6 I/O Data bus 6 46 D7 I/O Data bus 7 47 SPRQ Out SSP interrupt request to CPU 48 RESET In MPCA reset 49 SHEN In Shift enable from CKDC8 Pin No. Signal name In/ Out Function 50 INT3 In Interrupt signal (Nu) 51 RXD2 Out 8 bit serial port output to CPU 52 TXD2 In 8 bit serial port input from CPU 53 SCK2 In Serial port shift clock input from CPU. 54 IRQ0 Out Interrupt request to CPU 55 A0 In Address bus 0 56 A1 In Address bus 1 57 A2 In Address bus 2 58 A3 In Address bus 3 59 A4 In Address bus 4 60 A5 In Address bus 5 61 GND — GND 62 VCC — +5V 63 A6 In Address bus 6 64 A7 In Address bus 7 65 A8 In Address bus 8 66 A9 In Address bus 9 67 A10 In Address bus 10 68 A11 In Address bus 11 69 A12 In Address bus 12 70 A13 In Address bus 13 71 A14 In Address bus 14 72 A15 In Address bus 15 73 A16 In Address bus 16 74 A17 In Address bus 17 75 A18 In Address bus 18 76 A19 In Address bus 19 77 A20 In Address bus 20 78 A21 In Address bus 21 79 A22 In Address bus 22 80 LCDC — LCD CS (NU) 81 A23 In Address bus 23 82 TRGI In Dot pulse control/drive signal 83 PTMG Out Printer timing signal 84 PRST Out Printer reset signal 85 RDY In Ready from FMC unit 86 IPLON In To option connector (NU) 87 MD1 In Mode select input (+5V) 88 MD0 In Mode select input (GND) 89 TEST In +5V 90 MA15 — Image address 15 (NU) 91 MA18 — Nu 92 MA19 — Nu 93 RCVRDY1 — Nu 94 RCVRDY2 — Nu 95 RC0 — Remote control encord signal for CPU 96 IRTX — I/R output for LED (NU) 97 UASCK — I/R serial data shift clock (NU) 98 UARX — I/R serial data for CPU (NU) 99 UATX — I/R serial data from CPU (NU) 100 VCC — +5V 101 GND — GND 102 IRRX — I/R input from I/R unit (NU) 103 RCI — I/R input from I/R unit (NU) 104 DAX1 — System clock (7.3728MHz) 4 – 7

109 EXWAIT In External wait control input signal 110 RA18 Out Nu 111 RA17 Out Nu 112 GND — GND 113 RA16 Out Nu 114 RA15 Out Nu 115 RDO Out Expansion RD signal Option 116 WRO Out Expansion WR signal 117 EXINT3 In Expansion interruption signal 3 Option 118 EXINT2 In Expansion interruption signal 2 119 EXINT1 In Expansion interruption signal 1 120 EXINT0 In Expansion interruption signal 0 121 OPTCS Out Chip select base signal for expansion option 122 ROS1 Out ROM 1 chip select signal 123 ROS2 Out ROM 2 chip select signal (NU) 124 RAS2 Out RAM 2 chip select signal 125 RAS1 Out RAM 1 ship select signal 126 RJRST In Printer reset signal 127 RJTMG In Printer timing signal 128 DT4 Out Printer dot signal 4 129 DT3 Out Printer dot signal 3 130 DT2 Out Printer dot signal 2 131 DT1 Out Printer dot signal 1 132 GND — GND 133 DT7 Out Printer dot signal 7 134 DT6 Out Printer dot signal 6 135 DT5 Out Printer dot signal 5 136 MTD Out Printer motor drive signal 137 MTD Out Printer motor drive signal 138 DOT9 Out Printer dot signal 9 (NU) 139 DOT8 Out Printer dot signal 8 (NU) 140 SYNC — Nu (+5V) 141 ASKRX — I/R input from I/R unit (NU) 142 VCC — +5V 143 GND — GND 144 — — Nu 145 RAS3 Out 146 RJMTR In Printer motor lock detection signal (NU) 147 SLMTD In Nu 148 SLMTS In Nu 149 SLMTR In GND 150 HTS2 Out Serial output to FMC unit (NU) 151 SCK2 Out Serial clock to FMC unit (NU) 152 STH2 In Serial input to FMC unit (NU) pull-up 153 — — Nu 154 — — Nu 155 — — Nu 156 — — Nu 157 — — Nu 158 LCDWT — Nu 159 DOTEN Out Dot drive enable signal 160 RASP — Nu 2-3. CKDC8 1) Pin configulation 2) Pin assignment (CKDC8) Pin No. SYMBOL SIGNAL NAME IN/ OUT FUNCTION 1 DP DP OUT DISPLAY SEGMENT Dp 2 A SA OUT DISPLAY SEGMENT a 3 B SB OUT DISPLAY SEGMENT b 4 C SC OUT DISPLAY SEGMENT c 5 D SD OUT DISPLAY SEGMENT d 6 E SE OUT DISPLAY SEGMENT e 7 F SF OUT DISPLAY SEGMENT f 8 G SG OUT DISPLAY SEGMENT g 9 VSS0 GND GND 10 VDD0 VDD VDD 11 KR4 KR4 IN KEY RETURN 4 12 KR10 KR10 IN KEY RETURN (feed clerk MRS sw) 13 KR11 KR11 IN KEY RETURN (MODE sw) 14 KR8 NU IN GND 15 HTS HTS IN 16 STH STH OUT 17 /SCK /SCK IN SHIFT CLOCK 18 ST0 ST0 OUT KEY STROBE 0 19 ST1 ST1 OUT KEY STROBE 1 20 ST2 ST2 OUT KEY STROBE 2 21 ST3 ST3 OUT KEY STROBE 3 22 ST4 ST4 OUT KEY STROBE 4 23 ST5 ST5 OUT KEY STROBE 5 24 VDD1 VDD VDD 25 AXSS GND GND 26 KR9 NU GND 27 KR0 KR0 IN KEY RETURN 0 28 KR1 KR1 IN KEY RETURN 1 29 KR2 KR2 IN KEY RETURN 2 30 KR3 KR3 IN KEY RETURN 3 31 KR5 KR5 IN KEY RETURN 5 32 KR6 KR6 IN KEY RETURN 6 NU NU G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 BUZ /POFF NU ST8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DP SA SB SC SD SE SF SG GND VDD KR4 KR10 KR11 NU HTS STH 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ST7 ST6 /RESETS /SHEN ERC LDRQ GND GND /RES0 VDD GND KR7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 /SCK ST0 ST1 ST2 ST3 ST4 ST5 VDD GND NU KR0 KR1 KR2 KR3 KR5 KR6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CKDC8 4 – 8

34 AVRF GND 35 AVDD VDD 36 /RESET /RES0 IN 37 XT2 32.768 KHz 38 XT1 39 IC GND 40 X2 4.19 M Hz 41 X1 42 VSS1 GND 43 LDRQ LDRQ IN LORD REQUEST 44 ERC ERC IN EVENT READ CANCEL 45 SHEN /SHEN OUT SHIFT ENABLE 46 /RES1 /RESETS OUT SYSTEM TO RESET 47 ST6 ST6 OUT KEY STROBE 6 48 ST7 ST7 OUT KEY STROBE 7 49 ST8 ST8 OUT KEY STROBE 8 50 ST9 NU OUT KEY STROBE 9 51 /POFF /POFF IN POWER OFF 52 BUZ BUZ OUT BUZZER 53 T0 G1 OUT DISPLAY DIGIT 1 54 T1 G2 OUT DISPLAY DIGIT 2 55 T2 G3 OUT DISPLAY DIGIT 3 56 T3 G4 OUT DISPLAY DIGIT 4 57 T4 G5 OUT DISPLAY DIGIT 5 58 T5 G6 OUT DISPLAY DIGIT 6 59 T6 G7 OUT DISPLAY DIGIT 7 60 T7 G8 OUT DISPLAY DIGIT 8 61 T8 G9 OUT DISPLAY DIGIT 9 62 T9 G10 OUT DISPLAY DIGIT 10 63 T10 NU OUT DISPLAY DIGIT 11 64 ID NU OUT DISPLAY SEGMENT 3. Clock generator 1) CPU (HD64151010FX) Fig. 3-1 Basic clock is supplied from a 14.7456MHz ceramic oscillator. The CPU contains an oscillation circuit from which the basic clock is internally driven. If the CPU was not operating properly, the signal does not appear on this line in most cases. 2) CKDC8 oscillation circuit Fig. 3-2 Two oscillators are connected to the CKDC8. The main clock X3 generates 4.19MHz which is used during power on. When power is turned off, the CKDC8 goes into the standby mode and the main clock stops. The sub-clock X2 generates 32.768KHz which is primarily used to update the internal RTC (real time clock). During the standby mode, it keeps oscillating to update the clock and monitoring the power recov- ery. 4. Reset (POFF) circuit Fig. 4-1 In order to prevent memory loss at a time of power off and power supply failure of the ECR, the power supply condition is monitored at all times. When a power failure is met, the CPU suspends the execu- tion of the current program and immediately executes the power-off program to save the data in the CPU registers in the external S-RAM with the signal STOP forced low to prepare for the power-off situation. The signal STOP is supplied to the CKDC8 as signal RESET to reset the devices. CPU (HD64151010FX) 99 98 XTAL EXTAL 14.7456MHz X1 101 PHAI 37 38 33P HD404728A91FS C105 CKDC 8 X2 X3 4.19MHz X2 32.768KHz 2 1 3 41 18P C106 40 X1 XT2 XT1 R164 330K + - /POFF 3 2 1 4 8 B IC3A KIA393F C3 1000P D7 1SS133 C208 1µ 50V + ZD2 MTZ5.1A R14 9.1KG R13 15KG R10 56K R11 2.7K R9 2.7K R12 8.2KG +24V +5V POFF CPU 72 IRQ0 89 RESET (FROM CKDC 8) STOP (TO CKDC 8) MPCA7 13 48 1 IRQ0 54 INT0 4 – 9

The voltage at the (–) pin of the comparator IC3A is always main- tained to 5.1V by means of the zener diode ZD2, while +24V supply voltage is divided through the resistors R12, R13, and R14, and is applied to the (+) pin. When normal +24V is in supply, 6.8V is sup- plied to the (+) pin, therefore, signal POFF is at a high level. When +24V supply voltage decreases due to a power off or any other reason, the voltage at the (+) pin also decreases. When +24V supply voltage drops, the voltage at the (+) pin drops below +5.1V, which causes POFF to go low, thus predicting the power-off situation. The STOP signal from the CPU is converted into the RESETS signal by the CKDC6. The RESETS signal from the CKDC8 is converted into the RESET signal at the gate backed-up by the VRAM power, performing the system reset. 5. Memory control 1) Memory map All range memory map Fig. 5-1 ( 1) “Internal I/O” means the registers in the H8/510. ( 2) “External I/O” means the base system I/O area to be ad- dressed in page 0. ( 3) "Memory image area" means the lower 32KB of ROM area which is projected to 000000H ~ 007FFFH for allowing reset start and other vector addressing, or the lower 32KB of RAM area which is projected to 008000H ~ 00FE7FH for allowing 0 page addressing of work RAM area. ( 4) “Expansion I/O” means expansion I/O device area which isad- dressed to area other than page 0. 0 page memory map Fig. 5-2 • ROM image area: Image is formed in ROM area address C00000H to C07FFFH. This area is identical to IPL ROM area which will beseparately developed. • RAM image area: Image is formed in RAM area address 1F0000H to 1F7E7FH. ( Note) Note: Image can be formed in lower 32KB of RAS2. ROM area memory map Fig. 5-3 RESETS STOP CKDC8 RAS3 4 5 6 IC10B 74HC00S /(RAS3./RESET) /RESET 1 2 3 IC10A 74HC00S VDD C86 1000P C87 1000P R123 10K C88 1000P 9 10 8 14 IC10C 74HC00S 14 14 VDD VDD Internal I/O External I/O Memory image area (*1) (*2) (*3) RAM area (10M byte) ROM area (3M byte) Expansion I/O area (1M byte) 000000H 1C0000H C00000H FFFFFFH 000000H 004000H 008000H 00FFFFH 1FFFFFH ROM image area 32KB RAM image area slightly smaller than32KB NOT USE 00F800H 00FE80H 00FF80H 00FFFFH RAM image area Internal I/O area External I/O area (0 page) 1BFFFFH RAM area C00000H D00000H EFFFFFH ROS3 NOT USE ROS1 (256K Byte) C40000H CA0000H ROS2 (Not used) 4 – 10

Fig. 5-4 Note: RAS2 signal is formed as OR in the image area of 0 page. (lower32KB). I/O area memory map Fig. 5-5 Note 1: MPCCS signal is the base signal for MPCA7 internal reg- isterdecoding, and does not exist as an internal signal. Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC (optionperipheral controller) using the base signal OPTCS for optiondecoding. They does not exist as external sig- nals. 2) Block diagram Fig. 5-6 ROM control Fig. 5-7 IPLON: IPL board detection signal incorporated in the option slot. Note used in the ER-A445P. (Not used) Access is performed with two ROM chip select signals ROS1 and ROS2, which decode 512KB address area respectively to access- max. 4MB ROM. RAM control Fig. 5-8 Access is performed with two RAM chip select signals, RAS2 and RAS3. The control register in MPCA7 allows selection of pageimage memory area. (RAS1 is selected for initializing.) : For 0 page image area, selection between RAS2 and RAS3 can bemade with the control register. The 0 page control registerper- forms initializing at the timing of no stack processimmediately after resetting. 100000H 400000H BFFFFFH NOT USE NOT USE RAS1 (Not use) RAS2 64K Byte RAS3 512K Byte 1C0000H 1F0000H 200000H (MAX 2MB) 280000H (OPTION) 00FF80H 00FFA0H 00FFFFH MPCCS NOT USE NOT USE NOT USE OPCCS1 OPCCS2 00FFC0H 00FFD0H 00FFE0H 00FFF0H (*1) (*2) (*2) 00FFE8H MCR1 (NOT USE) MCR2 (NOT USE) NOT USE CPU MPCA7 ROM1 (STANDARD) RAM1 RAM2 (OPTION) RAM Data bus Address bus ROS1 RAS2 RAS3 Address A23~A14 (IPLON) Address decorder C80000H~CFFFFFH C00000H~C7FFFFH 000000H~007FFFH MPCA7 ROS2 ROS1 Address A23~A14 Address decorder 1C0000H~1DFFFFH 008000H~ 00F7FFH *1 1E0000H~1FFFFFH RAS1 RAS2 RESET D CK Q R DOI S8F Control register MPCA7 RAS3 200000H~3FFFFFH 4 – 11

1) Block diagram This is the circuit employed to do the Special Service Preset(SSP). (Block diagram) Fig. 6-1 (MPCA7 block diagram) Fig. 6-2 As the address detection system, the brake address register compari- son system is employed though the mapping system was employed in the conventional monitor RAM. The address registerlocated in MPCA is always compared with the system address bus to monitor and generate NMI signal at a synchronized timing and togo to NMI exception process. In the exception process routine service routine, the entry address is checked to go to SSP sub routine. Entry to the break address register (BAR) is performed through ad- dress FFFF00H or later decoded in MPCA7. 2) SSP register The break address register (BAR) is accessed through direct address of FFFF00H~FFFFFFH. Entry number is 32 entry. Fig. 6-3 Each BAR is composed of 4 byte address. Bit composition is as follows: Fig. 6-4 is the enable register. The entry registers of the break address are assigned to , , and . Each bit of address corresponds to each bit position, writing to , , and is performed without shifting. The corresponding area is 1MB space of ROS1 and ROS2. CPU MPCA7 A0~23 D0~D7 NMI SSPRQ D0~ D7 A23~ A0 BAR 0 BAR N REGCS Decode Comparator Coincide Coincide SPE (Enable register) SSPRQ (NMI) Control signal ROMCS O N 1 2 3 4 FFFF00 H 1 2 3 4 5 6 7 BAR0 BAR1 BAR2 7 0 1 2 3 4 A19 A18 A17 A16 A15 A8 A7 A2 EN Upper bits Intermediate bits Lower bits Enable register EN (bit7) = 1 Enable = 0 Inhibit Don't care for "-----." < BAR composition > 4 – 12

Access to SSP break address register is performed through the tem- porary register as shown below: Fig. 6-5 Enable flags can be accessed individually. Though enable register can be accessed individually, writing to brake address registers and is performed at the same time as writing to brake address register through the temporary register. Therefore, set and to temporary, then write into at last. Since the temporary register is commonly used by BAR sets, thefol- lowing register setting is performed after completion ofsetting of each break address register. SSP control method Access to the enable register and the brake address register is only possible when writing to them from the CPU. Information on which brake register the SSP brake is detected in is read as binary data by reading address FFFFFFH (*1). Used in an expanded register. Normally is a reserve bit. Whenreading, fixed to 0. If there are 32 break registers, binary expression is made with the above 5 bits, and 0th is “00000B” and 31st is “11111B.” When detected simultaneously by two or more break registers, onewith the smaller BAR number is read as binary data. The brake signals (NMI) and the above detection data (CMP0~4) areheld until the above detection data are read. So read should be- made in the NMI sub routine. (Clear by FFFFFFH read.) 1: FFFFFFH is not fulldecoded. (FFFF00H~FFFFFFH). There- fore,unnecessary read access in parentheses should not be performed. 1 2 3 4 A19 A18 A17 A16 A15 A8 A7 A2 EN WR WR Temporary Temporary bit 7 6 5 4 3 2 1 0 0 0 CMP4 0 CMP3 CMP2 CMP1 CMP0 (FFFFFFH) 7. PRINTER control circuit 1) Block diagram Fig. 7-1 2) General description of the printer controller The DP-730 is used as the R/J printer. The printer mechanical timing control is made by the CPU through MPCA7. 3) Printer motor drive circuit When the MTD is high, the motor rotates. When the MTD is low, the motor stops. CPU Data bus MPCA7 DRIVER PRINTER (DP-730) RECEIVER Address bus MTD MPCA7 M Speed limiter circuit 2.2K R128 +24V C92 DP Normal 555µs (516~590µs) Main PWB side Printer side R127 COM Q7 C227 MTD DP 4 – 13

When an abnormal load is applied to the mechanism, the DP (Dot Pulse) frequency is checked to prevent against the motor burn-out, the timing belt shift, and gear damage. If the following condition is made, the CPU stops the motor rotation. When starting the motor: When the cycle from starting to the 100th pulse of DP is 16ms. (The one pulse cycle of DP is normally 555us.) During constant rotation of the motor: When one pulse of DP is 1100us or more. 4) Printer sensor circuit The printer supplies the RP (Reset Pulse) signal, the HP (Home Position) signal, and the DP (Dot Pulse) signal) to control printing timing and conduction timing of solenoids. It also supplies the VPJ signal to detect the presence of validation paper. These sensor are photo interrupters. RP (RJRST) signal This signal is outputted once for every reciprocating motion of the print head. It indicates the reference position of the HP signal. The rear edge of RP (OFF -- ON) is used as the signal. HP signal The pulse signal is outputted from the slit in the disk installed to the DC motor shaft. It is used as the reference signal for starting counting of the DP signal. It is generated once for twenty DP signals. The rear edge of the HP signal (ON -- OFF) immediately after generation of the RP signal is used as the signal. DP (RJTMG) signal The pulse signal is outputted from the slit in the disk installed to the DC motor shaft. It is used as the control signal for the print solenoid and the paper feed solenoid. The front edge of the output signal (ON -- OFF) is used as the signal. VPJS (VPJ) signal The presence of a validation card is detected by interruption of the photo interrupter LED light by the validation card. 5) Dot solenoid drive circuit The DOT1 ∼ DOT7 (the dot solenoid drive signals from the MPCA7) are pulled up by the VRESE and converted into LOW by the driver IC. A +24V voltage is applied to the solenoid. This operates the dot wire. 6) Paper feed circuit The PFJ0 (the journal paper fed signal from the MPCA7) and the PFR0 (the receipt paper feed signal) are pulled up by the VRESE and converted into LOW level. A +24V voltage is applied to the solenoid. This operates the paper feed solenoid. R207 Q6 C93 +5V R206 R126 HP HP +5V R132 Q8 C91 +5V R131 R130 RJTMG DP +5V C228 +5V RJRST RP +5V VPS VPJS(NU) +5V R129 R133 MPCA7 CPU R1134 NOT USED OFF ON 555µs(TYP.)(516~590µS) #1 #2 #3 #4 +5V GND +5V GND ON ON +5V GND OFF OFF RP HP DP Relation ship among RP/HP/DP 1.5ms or above The first HP after turning OFF/ON RP. 20 cycles of DP (TYP.11.1ms) 50µs above 50µs above Print area * The waveforms are those indicated with arrow in Fig.3-3. VRESC R146 R145 Q9 R149 DOT1 ~DOT4 IC15 DOT1~DOT4 IC16 DOT5~DOT7 DOT5 ~DOT7 MPCA7 +5V +24V R152 R153 R155 VRESC R146 R145 Q9 PFJ0 PFJ0 PFR0 MPCA7 +5V +24V PFR0 Q11 F2 IC16 IC18 R156 R161 4 – 14

sure to check the head impedance and driver breakdown. When fuse F2 is blown: Remove F2, and perform the service resetting. The set the mode switch to a position other than SRV and SRV’ and turn off the power. Install fuse F2 (1A) and turn on the power. If the fuse blows with the above operation, driver 4AC16 may be shorted. Turn off the power. Disconnect the printer cable from the printer. Measure impedance between the printer body connector pin 5 and the following pins: 1, 3, 9, 11, 13, 21, 25 The impdenace must be 10.5Ω ± 10%. If impedance is outside the above range, the dot solenoid is bad. Replace the dot head unit. 8. Drawer drive circuit Fig. 8-1 The drawer is directly supported by the CPU. No action starts when the power supply is not steady as the output stage of the driver is pulled VP by VRESC signal. Drawer open and close is sensed with the microswitch provided in the drawer whose signal is level converted with R74 and R73 and directly read by the CPU. 9. Key, display, time buzzer controls Fig. 9-1 1) Power on sequence During service interruption, the CKDC8 senses POF within 500msec. When service interruption is cancelled by turning on the power, the CKDC8 cancels resetting of the CPU in the command mode. After initializing each port, the CPU reads the start condition (1 byte). Fig. 9-2 After sampling POF High, the CKDC5 performs mode scan and key scan at , then cancels resetting of the CPU. After being cancelled, the CPU initializes each port at and reads the start condition. After being cancelled, the CPU reads the start condition without fail to set the sift mode. If, however, the first starting is made in other than SRV mode after the CKDC8 resets the CPU without request from the CPU, the CKDC8 sets the start condition supposing that starting is made in SRV mode. VCOM 5 VCOM 7 VCOM 17 VCOM 23 DOT3 1 3 9 11 13 21 25 DOT7 DOT5 DOT2 DOT1 DOT4 DOT6 DOT1~DOT7 +24V DR0 DRAW0 52 50 DOSP C97 1000P R144 1K TD62308F R143 4.7K 51 DR1 DRAW1 VRESC CPU +24V Drawer solenoid +24V R42 47K IC18 KR0~7,KR10,KR11 ST0~ST7 ST0~ST7 G1~G10 T0~T9 RES0 RESET VDD RES0 a~g,DP KR0~KR7 KR10,KR11 a~g,DP Key board Display CKDC 8 VCC B BUZZER 2 Driver Driver HTS1 SCK1 RESET INT2 POFF HTS SCK RESET HTS SCK RES1 CPU MPCA7 STH1 STH STH P11 P12 RES LDRQ SHEN LDRQ SHEN P10 ERC ECR P-OFF POFF POF RES1 SHEN LDRQ 1 2 Start condition Next command 4 – 15

When the CPU senses a service interruption, it performs necessary procedures for CPU stop. Then the CPU outputs a reset request to the CKDC5. Reset request Fig. 9-3 When the CPU senses a service interruption or an error, it performs necessary procedure for CPU stop and issues reset request. CPU procedures necessary for reset request All CPU interrupts are made DI. SCK is driven to low. Keep LDRQ at LOW level for 20usec or more and drive it HIGH. Loop to . During looping, access should not be made to external memory. It should be within 140usec from rising of one LDRQ to rising of another. When, however, the CKDC8 senses a service interruption at POF, it stops displaying. Service interruption procedure is performed after receiving reset request from the CPU. If reset request is not sent from the CPU within 100msec the service interruption procedure is started after 110 ±10msec to go into the stand-by mode. Fig. 9-4 3) Key and switch scanning Fig. 9-5 As the strobe signal, 8 bits of ST0 - 8 are used. KR0 - KR7 are used as the key return signal. KR10 is used as the return signal of the paper feed key, cashier key and MRS switch. KR11 is used as the return signal of the mode switch. 4) DISPLAY CONTROL Fig. 9-6 CKDC8 directly drives the LED display unit. 10. Power supply circuit Fig. 10-1 +24V: Printer, solenoid power +5V: VCC (Logic power) VDD: Battery charge, Battery back-uped power, CKDC-8 and RAM Back-up power 20µsec or more SCK LDRQ SHEN DON'T CARE TH 20µsec or more TL TL+TH 140µsec <= RES1 POF RES1 110±10msec 356.25µsec 38µsec KR0~KR7 KR10,KR11 ST0 ST9 CKDC5 G1-G10 SA-SG,DP LED-display (for custmer) LED-display (for operator) Driver Power trans. DC-DC Converter circuit Battery circuit +5V F1 F2 Switching regulator +24V + - ~ ~ VDD 4 – 16

1. General 1) This diagnostic program has been developed for diagnosing ma- chine functions in the field. The program is contained within the ER-A440. The diagnostic program is stored in the external ROM which will be executed by the CPU (H8/510) which requires the following diagnostic operations: a) Proper power supply voltages are mandatory for logic circuits (+5V, VDD, POFF, +12.5V, +24V). b) CPU input/output pins, CPU internal logic, CKDC8, MPCA7, system bus and common ROM/RAM must be working prop- erly. 2. Operational procedure To start the diagnostic program, you must enter the following com- mand. 3-digit test item number → key in the SRV mode. The key assignment must be properly set and the ROM and RAM must be operating properly to go into this mode. This is necessary because the control jumps to the program area in the SRV mode. A master reset must be performed before operating the ECR for the first time. After any option is installed, a program reset is required. When the master reset or program reset is performed, be sure to check the printout on the journal paper. Master reset: Turn power on in the SRV’ mode and change it to the SRV mode with the JF key pressed. Journal print: MASTER RESET *** Program reset: Turn power on in the SRV’ mode and change it to the SRV mode. Journal print: PRG. RESET *** 3. Test command list With the SRV mode and the following test code entry, the test start. CODE DESCRIPTION 100 Display & Buzzer test 101 Key code & Cashier key test 102 R/J printer test 104 Keyboard test 105 Mode switch test 106 Printer sensor test 108 Calendar osckllator test 109 SSP test 110 Drawer open sensor test (For standard drawer) 111 Drawer open sensor test (For remote drawer) 120 Standard RAM test 130 Standard ROM test 150 Printer dot pulse width adjustment 200 Option RAM test 500 RS-232 loop back test 4. Test contents [1] Display & Buzzer test 1) Key operation 2) Functional description Display the following message on the front and the rear display boards. A decimal point shifts from lower number of digit by one digit (per 200m sec.). Next, display the following segments (for approx. 1 sec.). Repeat the above two kinds of displays. Sound a buzzer continuously during test. 3) Check items a) The display must be correctly shown at each position. b) The luminosity of displays must be uniform and even at each position. c) Abnormal buzzer sound is not allowed. 4) Test termination Press any key. The test terminates with the test and message printed [2] Key code & Cashier key test 1) Key operation 2) Functional description Key code, MRS switch state and Cashier code are displayed. 100 CA/AT 1. 2. 3. 4. 5. 6. 7. 8. 9. 0. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 1 0 0 101 CA/AT (Not used) Key code (Not used) 5 – 1

a) Key code HARDWARE CODE" of the following keys will be displayed ever time the keys are pressed. "---" indicates that a key is struck twice and also that input data is not accepted. [KEY POSITION CODE] 4) Test termination Change the mode switch position other than SRV position to termi- nate the test. The test terminates with the test and message printed [3] R/J printer test 1) Key operation 2) Functional description Display the following message. Print the following characters. 3) Check items a) The head of printing position must be exactly aligned for "RE- CEIPT" and "JOURNAL". b) Printed characters must be free of stain and blur. 4) Test termination This check is terminated automatically. [4] Keyboard test 1) Key operation XXXX: Sumcheck data Standard keyboard layout sumcheck data ER-A440 2266 2) Functional description Keyboard test is performed with the sumcheck data of key code. For sumcheck data, data are inputted to the upper upper four digits befor the diagnostics code. The data are compared with the added data which are added until the final key (TL) is pressed. if the data agree with the added data, the end print is made. If not, the error print is made. The su check data is obtained by totalizing all key hardware codes except for the (TL) key and converting the total into a decimal figure. [ALL KEY LAYOUT] [STANDARD KEYBOARD LAYOUT] SUMCHECK DATA = 4A + 0E + 04 + 2B + 17 + ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ = 2266 Display the following message on the front display. Key code 68 67 58 77 78 66 55 56 57 48 38 R J 63 62 61 52 51 40 45 35 46 47 37 74 43 33 42 32 41 31 30 76 75 36 28 27 14 23 24 22 72 21 71 70 15 05 16 18 04 13 03 12 02 11 01 00 26 25 06 08 65 17 07 60 50 20 10 68 67 58 77 78 66 55 56 57 48 38 R J 63 62 61 52 51 40 45 35 46 47 37 74 43 33 42 32 41 31 30 76 75 36 28 27 14 23 24 22 72 21 71 70 15 05 16 18 04 13 03 12 02 11 01 00 26 25 06 08 17 1 0 1 102 CA/AT 1 2 3 4 5 6 7 8 9 0 ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ 3 lines of Z(24 characters) are printed ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ 3 lines of Z(24 characters) are printed XXXX 104 CA/AT 44 43 3A 4D 4E 42 37 38 39 30 26 R J 3F 3E 3D 34 33 28 2D 23 2E 2F 25 4A 2B 21 2A 20 29 1F 1E 4C 4B 24 1C 1B 0E 17 18 16 48 15 47 46 0F 05 10 12 04 0D 03 0C 02 0B 01 00 1A 19 06 08 41 11 07 3C 32 14 0A 44 43 3A 4D 4E 42 37 38 39 30 26 R J 3F 3E 3D 34 33 28 2D 23 2E 2F 25 A4 2B 21 2A 20 29 1F 1E 4C 4B 24 1C 1B 0E 17 18 16 48 15 47 46 0F 05 10 12 04 0D 03 0C 02 0B 01 00 1A 19 06 08 11 1 0 4 5 – 2

a) Check of the display in the test and the content of end print. 4) Test termination This check is terminated automatically. The test terminates with the test and message printed [5] Mode switch test 1) Key operation 2) Functional description Display the following message on the front display. When the Mode Switch is switched over in the following order, a numerical value corresponding to each position of mode switch is displayed at X. 3) Check items a) Check of the display in the test and the content of end print. 4) Test termination The test terminates with the test and message printed [6] Printar sensor test 1) Key operation 2) Functional description State of the paper near end sensor is sensed and displayed. 3) Check items X, Y Description C Paper near end sensor not detected. (Paper is existed) O Paper near end sensor detected. (Paper is not existed) "C" is always display when no sensor is used. 4) Test termination Press any key. The test terminates with the test and message printed [7] Calendar oscillator test 1) Key operation 2) Functional description This program is used to test the calendar oscillator function. Display: "66 – 66" shows the current time. "–" is blinking. (500ms ON and OFF) 3) Check items Time elapsed after master reset must be displayed. 4) Test termination Press any key. The terminates with the test and message printed [8] SSP test 1)Key operation 2) Functional description If an SSP is programmed, its contents are automatically chacked and the result is printed. Display: Normal end Error 1 0 4 1 0 4 E----- 105 CA/AT 1 0 5 X Mode: x : PGM2 OFF OP X/Z SRV 0 PGM1 1 2 9 3 X2/Z2 MGR REG SRV 0 X1/Z1 7 6 5 4 Normal end Error 1 0 5 1 0 5 E----- 106 CA/AT 1 0 6 X-X JOURNAL side RECEIPT side 1 0 6 108 CA/AT 1 0 8 109 CA/AT 1 0 9 5 – 3

Check printing of the termination message. 4) Test termination This check is terminated automatically. The test terminates with the test and message printed In this SSP check, set the data for check in the empty area of SSP entry REG and erase the data for check after completion of check. Therefore SSP setting before check is not cleard. If therefore there is no SSP entry REG remainedfor SSP check, F-print is performed to terminate the program without check. [9] Drawer open sensor test (For standard test) 1) Key operation 2) Functional description State of the drawer open sensor is sensed and displayed. 3) Check items X Description O Drawer open sensor detected. (Drawer opend) C Drawer open sensor not detected. (Drawer closed) a) Check opening of the specified drawer. b) Check the display indication when the drawer is open and closed. 4) Test termination Press any key. The test terminates with the test and message printed [10] Drawer open sensor test (For remote drawer) 1) Key operation 2) Functional description State of the drawer open sensor is sensed and displayed. 3) Check items X Description O Drawer open sensor detected. (Drawer opend) C Drawer open sensor not detected. (Drawer closed) a) Check opening of the specified drawer. b) Check the display indication when the drawer is open and closed. 4) Test termination Press any key. The test terminates with the test and message printed [11] Standard RAM test 1) Key operation 2) Functional description Perform the following check for the standard RAM 128 KByte SRAM. The memory contents should not be changed before and after the check. Perform the following processes for memory address to be checked (1E0000H~1F0000H). PASS1: Save memory data. PASS2: Write data "0000H." PASS3: Read and compare data "0000H," write data "5555H." PASS4: Read and compare data "5555H," write data "AAAAH." PASS5: Read and compare data "AAAAH." PASS6: Restore the memory data. If a compare error occurs in the check sequence PASS1-PASS6, an error print is made. If no error occurs through all address, the check ends normally. The following address check is performed further. Check point address = 1E0000H, 1E0001H 1E0002H, 1E0004H 1E0008H, 1E0010H 1E0020H, 1E0040H 1E0080H, 1E0100H 1E0200H, 1E0400H 1E0800H, 1E1000H 1E2000H, 1E4000H 1E8000H, 1F0000H 3) Check the following items: Check the termination printout. 4) Test termination The test terminates after printing the termination printout. Termination printout: Normal termination 120 Abnormal termination Ex – – – – – 120 X = 01: Data check error 02: Address check error Note: When an error occurs, the error print is performed and the check is terminated. The error occurrence address is shown in hexadecimal at positions shown with . Normal end Error 1 0 9 1 0 9 E----- 1 0 9 F----- SSP table full 110 CA/AT 1 1 0 X 1 1 0 111 CA/AT 1 1 1 X 1 1 1 120 CA/AT 1 0 7-SEGMENT DISPLAY: 2 5 – 4

1) Key operation 2) Functional description Sum check of the standard ROM (C00000H - C7FFFFH) is per- formed. If the lower two digits of SUM is 10H, it is normal. 3) Check the following items: Check the printout after the test. 4) Test termination The test automatically terminates with termination message. Normal termination print 130 ROM1 27020 Error termination print E – – – – 130 ROM1 27020 Note: " " means the ROM version number. The underlined section (10 bytes) of code table is provided in the ROM as a standard and the table content is always printed. The table position is the upper 10 digits of the ROM address. The check sum correction address is the last address -0FH. [13] Printer dot pulse width adjustment 1) Key operation 2) Functional description Adujustment width of TPW at the test point TP1. The pulse width of TPWW canw bwe adjusted using the 200K pot VR1. 3) Check items a) The pulse width of TPW must be adjusted to that at the above test point TP1. 4) Test termination Do the program reset. [14] Option RAM test 1) Key operation JOB #NO. RAM NO. Memory to be checked Address area to be checked 200 Option RAM ER-03RA 200000H ∼ 27FFFFH 2) Content The following check are performed for the optional RAM. The following process is performed for memory addresses to be checked. PASS1: memory data save PASS2: Data "0000H" write PASS3: Data "0000H" read and comparison, data "5555H" write PASS4: Data "5555H" read and comparison, data "AAAAH" write PASS5: Data "AAAAH" read and comparison PASS6: Memory data restore 130 CA/AT 1 0 7-SEGMENT DISPLAY: 3 150 CA/AT TPW=370±3(µs) MAIN PWB GND VR1 TP 200 CA/AT 5 – 5

PASS6, error print (error code E1) is performed. If there is no error found to the end of the last address, the operation is completed normally. Then the following address check is performed. " " shows a valid address, and "" shows an invalid address. In case of an error, error code E2 is printed. Check Address JOB#201(ER-03RA) 200000H 200001H 200002H 200004H 200008H 200010H 200020H 200040H 200080H 200100H 200200H 200400H 200800H 201000H 202000H 204000H 208000H 210000H 220000H 240000H 260000H 3) Check the following items. Check the termination print. 4) Test termination The test terminates after printing the termination printout. Termination print E01--- 200 (data check error) E02--- 200 (address check error) 200 (normal end) : Error address [15] RS-232 loop back test Connect the loop back connector(UKOG-6705RCZZ) to RS232 con- nector. 1) Key operation 2) Functional description Control signal check OUT PUT INPUT /ER /RS /DR /CI /CD /CS OFF OFF OFF OFF OFF OFF OFF ON OFF OFF ON ON ON OFF ON ON OFF OFF ON ON ON ON ON ON Data communication check Perform 256-byte branch loop back test between SD and RD. DATA: $00 - $FF BAUD RATE: 9600 BPS Display: 4) Test termination This check is terminated automatically. The test terminates with the test and message printed XX: Error code E1 ER-DR error E2 ER-CI error E3 RS-CD error E4 RS-CS error E5 SD-RD error (DATA error) E6 SD-RD error (DATA error/Flaming error) 2 0 7-SEGMENT DISPLAY: 0 500 CA/AT 5 0 0 Normal end Error NG RS TEST ER XX RS TEST OK 5 – 6

FUNCTION 1. General RAM data can be transmitted in the following two methods. Save the data before servicing as follows: ECR ←→ ECR • Cable: 9 pin D-SUB – 9 pin D-SUB Fig. 1-1 ECR ←→ ER-02FD • Cable: 9 pin D-SUB – 25 pin D-SUB Fig. 1-2 2. SIO interface specification 1) Operation: Simplex 2) Line configuration: Direct connect 3) Data rate: 19200, 9600, 4800, 2400, 1200, 600, 300BPS (Selected by SRV JOB#903-A) 4) Sync mode: Asynchronous 5) Checking: Vertical parity (odd) 6) Code: 7 bits (ASCII) 7) Bit sequence: LSB first 8) Line level: RS232 level 9) Data forma: FIg. 2-1 3. Location of connector pins ECR-ECR cable Fig. 3-1 ECR ECR ECR ER-02FD P b1 b2 b3 b4 b5 b6 b7 LSB MSB Start bit Parity bit Stop bit SD 3 SD RD CTS RD 2 6 8 3 2 6 8 5 5 SG RTS 7 DCD 1 DTR 4 DSR 7 1 4 ECR CTS SG RTS DCD DTR DSR 9PIN D-SUB 9PIN D-SUB SD : TRANSMITTED DATA RD : RECEIVED DATA DTR: DATA TERMINAL READY DSR: DATA SET READY RTS: REQUEST TO SEND DCD: DATA CARRIER DETECTOR CTS: CLEAR TO SEND ECR 6 – 1

The following service (SRV) modes are available for the serial data transfer of the ECR 1) Data transmit (Source side) X: 0=SSP DATA 2) Data receive (Target) 5. Data format A single byte image of the RAM data to be transmitted is divided into a high order 4 bits and low order 4 bits and converted into ASCII code. Then, the image of the memory is sent in the following format: Memory top address: 0000H ∼ FFFFH Top address of the memory to be transmitted in ASCII number. Page:1F ∼ 27,00 Page of the memory to be transmitted in ASCII number. Sum check End code: Hex 0D NOTE: • In order that contents of RAM memory may not over-ride pages for this job, RAM image is sent in unit of 64 bytes from the address 0000. In other words, 128 bytes are sent at one time on the transmit data format. RAM DATA FORMAT Exhibit: Code table HEX ASCII Character HEX ASCII Character 0 30 0 8 38 8 1 31 1 9 39 9 2 32 2 A 41 A 3 33 3 B 42 B 4 34 4 C 43 C 5 35 5 D 44 D 6 36 6 E 45 E 7 37 7 F 46 F 6. END record End message: Fixed to 30303030. End massage: Fixed to 4646. Sum check End code: CR (0D) SD 2 SD RD CTS RD 3 6 5 3 2 6 8 ER-02FD 7 5 SG RTS 4 DCD 8 DTR 20 DSR 7 1 4 ECR CTS SG RTS DCD DTR DSR 1 FG FRAME GROUND is connected to the shield of the cable. 25PIN D-SUB 9PIN D-SUB SD : TRANSMITTED DATA RD : RECEIVED DATA DTR: DATA TERMINAL READY DSR: DATA SET READY RTS: REQUEST TO SEND DCD: DATA CARRIER DETECTOR CTS: CLEAR TO SEND FG : FRAME GROUND 996 X CA/AT All data X SBTL (Auto baud rate setting: ECR to ECR only) (Baud rate setting: #903-A) 998 X CA/AT (Auto baud rate setting: ECR to ECR only) (Baud rate setting: #903-A) SBTL 1 2 3 4 Data (128bytes) BD 7E 83 FC 03 B6 42 44 37 45 38 33 46 43 30 33 42 36 30 3 4 30 30 30 1 2 6 – 2

1) To prepare an ECR to receive data from another ECR or the ER-02FD, the memory size of the receiving unit must the same as or greater than the sending unit. 2) Master reset the receiving ECR. 3) Connect loader cable between ECRs. 4) Set the receiving ECR ready to receive. 5) Start the sending ECR. X: 0 = SSP 6) Transmission status. Description of error status 1: Application error (Command error) 2: Application error (Parity error) 3: Application error (Check sum error) 4: Application error (Data size error) 5: Hard ware error 6: Power off error 7: Time out error 11: Application error (Transmit data size error) 12: Application error (Block sequence error) 7) Service reset the receiving ECR. 8. Saving/Loading of data to/From the FD unit Configuration 1) Turn off the power switch of the ER-02FD, and set the DIP switches of the FD unit as follows: ER-02FD (The ER-01FD functions of the ER-02FD are used.) 2) Connect the cable. Saving data 1) Turn on the power switch and insert a floppy disk which has been formatted. 2) Start the SEND JOB on the ECR side as follows: X: 0 = SSP 3) Data transmission is started and the green lamp on the ER-02FD blinks. Loading data 1) Turn on the power switch and insert the floppy disk which stores the data. 2) Start the RECEIVE JOB on the ECR side as follows: 3) Press the SEND key on the FD unit. 4) Data transmission is started and the Green lamp on the ER-02FD blinks. 5) Service reset the ECR. 998 X (Auto baud rate setting: ECR to ECR only) CA/AT SBTL (Baud rate setting: #903-A) 996 X All data X (Auto baud rate setting: ECR to ECR only) CA/AT SBTL (Baud rate setting: #903-A) OFF ON OFF OFF OFF ON X ON OFF OFF OFF ON DS-1 1 2 3 4 5 6 7 8 1 2 3 4 DS-2 Data rate 4 6 Rate [bps] OFF OFF 19200 ON OFF 9600 OFF ON 4800 ON ON 2400 Disk format CCP/M: OFF PC-DOS: ON 996 X All data X CA/AT 998 X CA/AT 6 – 3

1. Error code table When the following error codes are displayed, press the key and take a proper action according to the table below. Error code Error status Action E01 Registration error Make a correct key entry. E02 Misoperation error Make a correct key entry. E03 Undefined code is entered. Enter a correct code, or declare it by the programming. E04 Paper empty Replace a journal paper roll with a new one. E05 Secret code error Enter a correct secret code. E07 Memory is full. Expand the file within a capacity of memory. E11 Compulsory depression of the i key for direct finalization Press the i key and continue the operation. E12 Compulsory tendering Make a tendering operation. E26 File type error Create files correctly. E27 Power-off E31 Compulsory non-add code entry Enter a non-add code. E32 No entry of your cashier code Make a cashier code entry. E33 The current cashier code should not be changed. Change a cashier after finalizing the transaction. E34 Overflow limitation error Make a registration within a limit of entry. E35 The open price entry is inhibited. Make a preset price entry. E36 The preset price entry is inhibited. Make an open price entry. E37 The direct finalization is inhibited. Make a tendering operation. E39 Power-off during validation printing Print a validation again. E67 Registration buffer is full. E76 The drawer is still opened. Close the drawer. E86 Communication error E87 Data format error E88 Time-out error E94 Age verification error The dept./PLU is protected by the age limitation. 2. Conditions for soldering circuit parts To solder the following parts manually, follow the conditions described below. PARTS NAME PARTS CODE LOCATION CONDITIONS FOR SOLDERING Front LED (HDSP5621) Front LED PWB: FND1-5 315°C/2 sec. Pop-up LED (HDSP-F501#S02) Pop-up LED PWB: FND1-10 315°C/2 sec. 7 – 1

Q2 C4153 HEAT SINK 5 6 1 2 3 4 IC2 KA34063A 1 2 CN1 PS CN F1 FUSE FROM PS PWB +24V GND C2 220P R7 1KF 100U/50V C1 0.1uF 50V VBT 16V C206 330uF/16V C207 330uF/16V C120 0.1uF/50V 2 1 CN2 BTCN BT1 BATTERY R216 150 +5V R9 2.7K +24V D7 1SS353 R12 8.2KG R13 15KG R11 2.7K R10 56K +24V +24V +5V +5V +24V TP VR1 200K D5 1SS353 1 2 D6 E102 5 6 7 8 4 IC3B KIA393F R18 130KF R17 2K R16 62K R15 3.3K TRG 3-8D Q3 KRC106S PE 3-4D C4 10000P ZD3 UDZ4.3B 3 2 1 8 4 IC3A KIA393F C208 1u/50V R14 9.1KG ZD2 UDZ5.1B /P0FF 3-8C C3 1000P 1/10 CHAPTER 8. CIRCUIT DIAGRAM & PWB LAYOUT 1. MAIN PWB CIRCUIT DIAGRAM 8 – 1

RA1(R19~R26) 10K C5~C12 +5V +5V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 10K X8 A[0..23] 3-8B 1 2 3 4 5 6 7 8 9 RA2(R27~R34) 10K R43~R50 +5V 10K X8 ERC LDRQ /FRES BUSY R52 33 R53 33 R54 33 R55 33 R56 33 R57 33 R58 33 R59 33 8-4B 8-4B 4-4C R35~R42 PDS 4-4C 8-2B /SHEN 8-8B /RDY VPJ +5V FIL1 100P 1 3 2 X1 14.7456MHz +5V +5V +5V +5V 7-4B R63 4.7KX4 R64 R65 R66 R69 4.7K +24V TXD2 RXD2 /IRQ0 /IRQ1 PHAI +5V +5V RXD TXD R67 10KF R70 1K R71 1K 3-8B 6-2C 3-8B 10-8C 10-8C 3-8B 3-8C R68 1.2KF SCK2 C44 150P /STOP +5V /ERS /CSS /CDS /RSS /RI /DRS HP C40 330P R62 10K 7-1A 3-4A 8-7B 7-4D /PRST +5V /NER TRGI R60 10K R61 10K +5V /WAIT +5V 330PX8 R51 10K C13~C20 A12 A13 A14 A15 330PX8 330PX8 A16 A17 A18 A19 A20 A21 A22 A23 3-4B C29~C36 C21~C28 +5V 10K 330P 1000P 100 R79 R80 R81 C45 C46 C47 R82 R83 R84 C48 C49 C50 7-4A 7-7A 7-7A DOPS /DR0 /DR1 C37 100P /PTMG /NEJ C38 330p C39 330p 3-4A 7-1B 3-4A 2/10 8 – 2

C212 0.33U/50V +24 1 2 3 IC6 KIA7812 Q4 KTA1664 VR2 5K R112 820 C74 0.1u/50V C213 10u/50V R113 1.2K R114 3.3K R111 68 /FRES FSD FRD FSCK BUSY R118 56K R119 56K R120 56K R121 56K 2-5C 3-1D 3-1D 3-1D 2-5C 2-5C /RDY 3-3A VCH GND 1 VPP 2 VCH 3 FRES 4 FSD 5 FRD 6 FSCK 7 BUSY 8 RDY 9 VCON 10 VPF 11 CN3 FMC CN +5V JP1 Q5 A1036 R115 3.9K R117 10K Q36 KRC106S 4/10 Not moun ted 8 – 4

A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 A[0..18] N.C 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 D0 13 D1 14 D2 15 GND 16 VCC 32 A15 31 CS2 30 WE 29 A13 28 A8 27 A9 26 A11 25 OE 24 A10 23 CS 22 D7 21 D6 20 D5 19 D4 18 D3 17 IC14 RAM DIP A15 A13 A8 A9 A11 A10 /WR /RD /(RAS3./RESET) A17 VDD /WR /RD 2-1D 2-1D 5-6B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 CN4 EFT CN D3 D4 D5 D6 D7 VDD C90 100P D0 D1 D2 D[0..7] C89 0.1uF C218 10uF/16V 6/10 NOT MOUNTED 8 – 6

Q8 C2412K R132 5.6K R131 2.7K C91 1000P 3-1C +5V COM 1K Q9 A1036 R145 5.6K R146 1K +24V DOT1 DOT2 DOT3 DOT4 DOT5 DOT6 DOT7 PFJ0 COM IC15 IC16 R149 R150 R151 R152 R153 R154 R155 R156 3-3C 3-3C 3-3C 3-3C 3-8D +5V VRESC /DOT1 /DOT2 /DOT3 /DOT4 /DOT5 /DOT6 /DOT7 /PFJ0 R130 3.3K R133 10K 3-7C /MTD Q7 C2412K R128 27K R127 22K 3-3C C92 M0.22UF M(+) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CN5 PR CN C227 M0.1U D8 1SR154-400 C231 100PF +5V +5V NEJ NES0 GND 2 1 CN8 NEJ CN C94 1000P 2-2A +5V R210 10K R138 1K R139 1K R140 1K R211 0ohm R212 0ohm +5V VPJ Q10 C2412K R135 10K R137 3.3K 2-3C BD14 R136 5.6K C96 0 OHM +24V +24V RJRST(RP) MTD /DOT8 /DOT9 /VPF /AUTO R134 5.6K C229 103 C228 M103 3-1C 3-3C MTD C98 0.1U/50V 1 2 3 CN7 DR CN +24V DOT8 DOT9 /ACUT0 /VPF0 IC17 Q12 C2412K Q13 C2412K R157 R158 R147 22K R159 R148 22K R160 3-7D 3-7D 3-3C 3-3C /STAMP0 /DR0 /DR1 PFR0 Q11 C2412K 1 8 3 6 14 11 4 5 16 9 2 7 10 15 12 13 IC18 TD62308F R161 3-8D 2-6A 2-6A 3-8D DS /DRAW0 +24V DS /DRAW1 +24V /STAMP /PFR0 /DRAW0 /DRAW1 C121 0.1U C122 0.1U 1 2 3 CN6 DR CN DOPS DS R142 47K R143 4.7K R144 1K C97 1000P 2-6A NER NES1 GND 2 1 CN9 NER CN C95 1000P 2-2A +5V R141 1K R213 10k R214 0ohm R215 0ohm 7/10 3-3C 3-3C 3-3C NOT USED Not moun ted 8 – 7

POP UP LED PWB ERC LDRQ HTS STH ST[0..9] 3-8C 3-8C 2-5C 2-5C 9-8C 9-8C 9-8D TO TO CN10-A CN10-B KR11 KR10 KR0 BD2 BD3 BD4 C103 330P C104 330P R164 330 9-8B R208 10K R209 10K /RES0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 /RESETS DP C99 330P C100 2200P C220 10U/16V 9-8C 3-8B 2-5C 5-8A /SHEN SA SB SC SD SE SF SG KR4 /SCK VDD BD1 C101 0.1U C221 10U/16V 3-8C 9-8B SA..DP C102 330P 1 0 7 1 1 6 1 2 5 DP SG SF SE E' F' G' DP' NU IC20 KID65003P C107 1000P C108 C109 C110 Q35 KRC106S 1 3 4 1 4 3 1 5 2 1 6 1 SD SC SB SA A' B' C' D' A'..DP' C111 C112 C113 C114 1000PX7 8/10 8 – 8

ST[0..9] KR10 8-4B 2 3 4 5 6 1 /RES0 KR11 R199 47K 8-4B 8-8B 8-4B ST0 ST1 ST2 ST3 CL1 CL2 CL3 CL4 GND /RES0 ST0 ST1 ST2 KR11 P-ON V0 SW1 CN12 CLERK CN D22 D23 D24 (NU) (NU) 1 2 3 4 5 D25 1SS353X4 2 3 4 5 6 7 8 9 10 11 ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 ST8 U? KEY74 ST5 KR10 CL1 CL2 CL3 CL4 D13 DD14 DD15 DD16 DD17 DD18 DD19 DD20 D21 1SS353X11 K R 1 K R 2 K R 3 K R 4 K R 5 K R 6 K R 7 K R 1 0 2 3 4 5 6 7 8 9 KEY CN K R 0 1 CN15 KEY CN R190~R198 47KX9 C234~C242 330PX9 MRS SW ST4 ST5 ST6 ST7 ST3 D28 1SS353 ST6 KR10 OFF ON KR[0..7] 7 8 9 10 11 MODE SW CN 8-5C 8-8C 8-7A 9/10 Not used 8 – 9

1/1 CN1 POP CN(NORMAL) FND1 G1' G2' G1'..G8' FND3 FND2 G3' G4' G5' G6' G7' FND4 G8' G' DP' R7 27 R8 27 C' D' E' F' R2 27 R3 27 R4 27 R5 27 R6 27 A' B' R1 27 A'..DP' 8 – 13

1/1 DIG7' DIG5' DIG6' DIG2' DIG3' DIG4' DIG1' CN1 POP UP CN FND1 FND3 FND2 FND4 DP' R10 27 F' G' R12 27 R14 27 D' E' R16 27 R18 27 B' C' R20 27 R22 27 R24 27 A' 8 – 15

7. PS PWB POWER UNIT 1 2 CN1 PS CN 4 1 2 3 BD1 CP301 R1 18K C2 4700UF/50V F1 T2.5AL 250V 3.15A 125V C1 M0.033u 1 5 7 3 4 2 IC1 LM2574HVN R2 10 6,8PIN:NC R3 22KF R4 1.2KF D2 PS156R C3 22UF/50v +24V GND 2 1 TO MAIN PWB C4 2200uF/50V 1/1 Not used 8 – 17

All rights reserved. Printed in Japan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without prior written permission of the publisher. SHARP CORPORATION Information Systems Group Quality & Reliability Control Center Yamatokoriyama, Nara 639-1103, Japan 1998 March Printed in Japan