Intel IXF1104 Datasheet

Media Access Controller Datasheet The Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller (hereafter referred to as the IXF1104 MAC) supports IEEE 802.3* 10/100/1000 Mbps applications. The IXF1104 MAC supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or ASIC, and concurrently supports copper and fiber physical layer devices (PHYs). The copper PHY interface supports the standard and reduced pin-count Gigabit Media Independent Interface (GMII and RGMII) for high-port-count applications. For fiber applications the integrated Serializer/Deserializer (SerDes) on each port supports direct connection to optical modules to reduce PCB area requirements and system cost. Product Features Applications Four Independent Ethernet MAC Ports for Copper or Fiber Physical layer connectivity. — IEEE 802.3 compliant — Independent Enable/Disable of any port Copper Mode: — RGMII for 10/100/1000 Mbps links — GMII for 1000 Mbps full-duplex links — IEEE 802.3 MDIO interface Fiber Mode: — Integrated SerDes interface for direct connection to 1000BASE-X optical modules — IEEE 802.3 auto-negotiation or forced mode — Supports SFP MSA-compatible transceivers SPI3 interface supports data transfers up to 4 Gbps in both modes: — 32-bit Multi-PHY mode (133 MHz) — 4 x 8-bit Single-PHY mode (125 MHz) IEEE 802.3-compliant Flow Control —Loss-less up to 9.6 KB packets and 5 km links — Jumbo frame support for 9.6 KB packets Internal per-channel FIFOs: 32 KB Rx, 10 KB Tx Flexible 32/16/8-bit CPU interface Programmable Packet handling — Filter broadcast, multicast, unicast, VLAN and errored packets — Automatically pad undersized Tx packets — Remove CRC from Rx packets Performance Monitoring and Diagnostics — RMON Statistics — CRC calculation and error detection — Detection of length error, runt, or overly large packets — Counters for dropped and errored packets — Loopback modes — JTAG boundary scan .18 μ CMOS process technology — 1.8 V core, 2.5 V RGMII, GMII, OMI, and 3.3 V SPI3 and CPU Operating Temperature Ranges: — Copper Mode: -40°C to +85°C — Fiber Mode: 0°C to +70°C Package Options: — 552-ball Ceramic BGA (standard) —552-ball Ceramic BGA (RoHS-compliant) — 552-ball Plastic FC-BGA (contact your Intel Sales Representative) Load Balancing Systems MultiService Switches Web Caching Appliances Intelligent Backplane Interfaces Edge Routers Redundant Line Cards Base Station Controllers and Transceivers Serving GPRS Support Nodes (SGSN) Gateway GPRS Support Nodes (GGSN) Packet Data Serving Nodes (PDSN) DSL Access Multiplexers (DSLAM) Cable Modem Termination Systems (CMTS) Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005

Revision Number: 009 Revision Date: 27-Oct-2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The IXF1104 MAC Media Access Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2005, Intel Corporation

Revision Number: 009 Revision Date: 27-Oct-2005 Contents 1.0 Introduction..................................................................................................................................20 1.1 What You Will Find in This Document ................................................................................20 1.2 Related Documents ............................................................................................................20 2.0 General Description ....................................................................................................................21 3.0 Ball Assignments and Ball List Tables......................................................................................23 3.1 Ball Assignments ................................................................................................................23 3.2 Ball List Tables ...................................................................................................................24 3.2.1 Balls Listed in Alphabetic Order by Signal Name ..................................................24 3.2.2 Balls Listed in Alphabetic Order by Ball Location ..................................................30 4.0 Ball Assignments and Signal Descriptions ..............................................................................37 4.1 Naming Conventions ..........................................................................................................37 4.1.1 Signal Name Conventions .....................................................................................37 4.1.2 Register Address Conventions ..............................................................................37 4.2 Interface Signal Groups ......................................................................................................38 4.3 Signal Description Tables ...................................................................................................39 4.4 Ball Usage Summary ..........................................................................................................57 4.5 Multiplexed Ball Connections..............................................................................................58 4.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections........................................58 4.5.2 SPI3 MPHY/SPHY Ball Connections.....................................................................59 4.6 Ball State During Reset ......................................................................................................61 4.7 Power Supply Sequencing..................................................................................................63 4.7.1 Power-Up Sequence..............................................................................................63 4.7.2 Power-Down Sequence .........................................................................................63 4.8 Pull-Up/Pull-Down Ball Guidelines......................................................................................64 4.9 Analog Power Filtering........................................................................................................64 5.0 Functional Descriptions..............................................................................................................66 5.1 Media Access Controller (MAC) .........................................................................................66 5.1.1 Features for Fiber and Copper Mode ....................................................................67 5.1.1.1 Padding of Undersized Frames on Transmit .........................................67 5.1.1.2 Automatic CRC Generation ...................................................................67 5.1.1.3 Filtering of Receive Packets ..................................................................67 5.1.1.4 CRC Error Detection ..............................................................................69 5.1.2 Flow Control...........................................................................................................69 5.1.2.1 802.3x Flow Control (Full-Duplex Operation).........................................70 5.1.3 Mixed-Mode Operation ..........................................................................................75 5.1.3.1 Configuration..........................................................................................75 5.1.3.2 Key Configuration Registers ..................................................................75 5.1.4 Fiber Mode.............................................................................................................76 5.1.4.1 Fiber Auto-Negotiation...........................................................................77 5.1.4.2 Determining If Link Is Established in Auto-Negotiation Mode ................77 5.1.4.3 Fiber Forced Mode.................................................................................77 5.1.4.4 Determination of Link Establishment in Forced Mode ...........................77 5.1.5 Copper Mode .........................................................................................................77

Revision Number: 009 Revision Date: 27-Oct-2005 5.1.5.1 Speed.....................................................................................................78 5.1.5.2 Duplex....................................................................................................78 5.1.5.3 Copper Auto-Negotiation .......................................................................78 5.1.6 Jumbo Packet Support ..........................................................................................78 5.1.6.1 Rx Statistics ...........................................................................................79 5.1.6.2 TX Statistics...........................................................................................79 5.1.6.3 Loss-less Flow Control...........................................................................79 5.1.7 Packet Buffer Dimensions .....................................................................................80 5.1.7.1 TX and RX FIFO Operation ...................................................................80 5.1.8 RMON Statistics Support.......................................................................................80 5.1.8.1 Conventions...........................................................................................82 5.1.8.2 Advantages............................................................................................83 5.2 SPI3 Interface.....................................................................................................................83 5.2.1 MPHY Operation....................................................................................................84 5.2.1.1 SPI3 RX Round Robin Data Transmission ............................................84 5.2.2 MPHY Logical Timing ............................................................................................84 5.2.2.1 Transmit Timing .....................................................................................85 5.2.2.2 Receive Timing ......................................................................................85 5.2.2.3 Clock Rates............................................................................................87 5.2.2.4 Parity......................................................................................................87 5.2.2.5 SPHY Mode ...........................................................................................87 5.2.2.6 SPHY Logical Timing.............................................................................88 5.2.2.7 Transmit Timing (SPHY)........................................................................88 5.2.2.8 Receive Timing (SPHY).........................................................................88 5.2.2.9 SPI3 Flow Control..................................................................................91 5.2.3 Pre-Pending Function............................................................................................93 5.3 Gigabit Media Independent Interface (GMII) ......................................................................93 5.3.1 GMII Signal Multiplexing........................................................................................94 5.3.2 GMII Interface Signal Definition.............................................................................94 5.4 Reduced Gigabit Media Independent Interface (RGMII) ....................................................96 5.4.1 Multiplexing of Data and Control............................................................................96 5.4.2 Timing Specifics.....................................................................................................97 5.4.3 TX_ER and RX_ER Coding...................................................................................97 5.4.3.1 In-Band Status .......................................................................................99 5.4.4 10/100 Mbps Functionality.....................................................................................99 5.5 MDIO Control and Interface................................................................................................99 5.5.1 MDIO Address .....................................................................................................100 5.5.2 MDIO Register Descriptions ................................................................................100 5.5.3 Clear When Done ................................................................................................100 5.5.4 MDC Generation..................................................................................................100 5.5.4.1 MDC High-Frequency Operation .........................................................100 5.5.4.2 MDC Low-Frequency Operation ..........................................................100 5.5.5 Management Frames...........................................................................................101 5.5.6 Single MDI Command Operation.........................................................................101 5.5.7 MDI State Machine ..............................................................................................101 5.5.8 Autoscan Operation.............................................................................................103 5.6 SerDes Interface...............................................................................................................103 5.6.1 Features...............................................................................................................103 5.6.2 Functional Description .........................................................................................103 5.6.2.1 Transmitter Operational Overview .......................................................104 5.6.2.2 Transmitter Programmable Driver-Power Levels.................................104

Revision Number: 009 Revision Date: 27-Oct-2005 5.6.2.3 Receiver Operational Overview ...........................................................105 5.6.2.4 Selective Power-Down.........................................................................105 5.6.2.5 Receiver Jitter Tolerance .....................................................................105 5.6.2.6 Transmit Jitter ......................................................................................106 5.6.2.7 Receive Jitter .......................................................................................106 5.7 Optical Module Interface...................................................................................................107 5.7.1 Intel® IXF1104 MAC-Supported Optical Module Interface Signals .....................107 5.7.2 Functional Descriptions .......................................................................................108 5.7.2.1 High-Speed Serial Interface.................................................................108 5.7.2.2 Low-Speed Status Signaling Interface.................................................108 5.7.3 I²C Module Configuration Interface......................................................................110 5.7.3.1 I2C Control and Data Registers............................................................110 5.7.3.2 I2C Read Operation..............................................................................110 5.7.3.3 I2C Write Operation..............................................................................111 5.7.3.4 I²C Protocol Specifics...........................................................................112 5.7.3.5 Port Protocol Operation .......................................................................113 5.7.3.6 Clock and Data Transitions..................................................................113 5.8 LED Interface....................................................................................................................115 5.8.1 Modes of Operation .............................................................................................115 5.8.2 LED Interface Signal Description.........................................................................116 5.8.3 Mode 0: Detailed Operation.................................................................................116 5.8.4 Mode 1: Detailed Operation.................................................................................117 5.8.5 Power-On, Reset, Initialization ............................................................................118 5.8.6 LED DATA Decodes ............................................................................................118 5.8.6.1 LED Signaling Behavior .......................................................................119 5.9 CPU Interface ...................................................................................................................120 5.9.1 Functional Description .........................................................................................121 5.9.1.1 Read Access........................................................................................121 5.9.1.2 Write Access ........................................................................................121 5.9.1.3 CPU Timing Parameters ......................................................................122 5.9.2 Endian..................................................................................................................122 5.10 TAP Interface (JTAG) .......................................................................................................123 5.10.1 TAP State Machine..............................................................................................123 5.10.2 Instruction Register and Supported Instructions..................................................124 5.10.3 ID Register...........................................................................................................125 5.10.4 Boundary Scan Register......................................................................................125 5.10.5 Bypass Register...................................................................................................125 5.11 Loopback Modes ..............................................................................................................125 5.11.1 SPI3 Interface Loopback .....................................................................................125 5.11.2 Line Side Interface Loopback ..............................................................................126 5.12 Clocks ...............................................................................................................................127 5.12.1 System Interface Reference Clocks.....................................................................127 5.12.1.1 CLK125 ................................................................................................128 5.12.2 SPI3 Receive and Transmit Clocks .....................................................................128 5.12.3 RGMII Clocks.......................................................................................................128 5.12.4 MDC Clock...........................................................................................................128 5.12.5 JTAG Clock..........................................................................................................129 5.12.6 I2C Clock..............................................................................................................129 5.12.7 LED Clock............................................................................................................129

Revision Number: 009 Revision Date: 27-Oct-2005 6.0 Applications...............................................................................................................................130 6.1 Change Port Mode Initialization Sequence.......................................................................130 6.2 Disable and Enable Port Sequences................................................................................131 6.2.1 Disable Port Sequence........................................................................................131 6.2.2 Enable Port Sequence.........................................................................................131 7.0 Electrical Specifications ...........................................................................................................132 7.1 DC Specifications .............................................................................................................133 7.1.1 Undershoot / Overshoot Specifications ...............................................................135 7.1.2 RGMII Electrical Characteristics..........................................................................135 7.2 SPI3 AC Timing Specifications.........................................................................................137 7.2.1 Receive Interface Timing.....................................................................................137 7.2.2 Transmit Interface Timing....................................................................................139 7.3 RGMII AC Timing Specification ........................................................................................141 7.4 GMII AC Timing Specification...........................................................................................142 7.4.1 1000 Base-T Operation .......................................................................................142 7.4.1.1 1000 BASE-T Transmit Interface.........................................................142 7.4.1.2 1000BASE-T Receive Interface...........................................................143 7.5 SerDes AC Timing Specification.......................................................................................144 7.6 MDIO AC Timing Specification.........................................................................................145 7.6.1 MDC High-Speed Operation Timing....................................................................145 7.6.2 MDC Low-Speed Operation Timing.....................................................................145 7.6.3 MDIO AC Timing..................................................................................................146 7.7 Optical Module and I2C AC Timing Specification .............................................................147 7.7.1 I2C Interface Timing.............................................................................................147 7.8 CPU AC Timing Specification...........................................................................................149 7.8.1 CPU Interface Read Cycle AC Timing.................................................................149 7.8.2 CPU Interface Write Cycle AC Timing.................................................................149 7.9 Transmit Pause Control AC Timing Specification.............................................................151 7.10 JTAG AC Timing Specification .........................................................................................152 7.11 System AC Timing Specification.......................................................................................153 7.12 LED AC Timing Specification............................................................................................154 8.0 Register Set................................................................................................................................155 8.1 Document Structure..........................................................................................................155 8.2 Graphical Representation.................................................................................................155 8.3 Per Port Registers ............................................................................................................156 8.4 Register Map ....................................................................................................................156 8.4.1 MAC Control Registers........................................................................................163 8.4.2 MAC RX Statistics Register Overview.................................................................174 8.4.3 MAC TX Statistics Register Overview .................................................................178 8.4.4 PHY Autoscan Registers .....................................................................................181 8.4.5 Global Status and Configuration Register Overview ...........................................188 8.4.6 RX FIFO Register Overview ................................................................................193 8.4.7 TX FIFO Register Overview.................................................................................203 8.4.8 MDIO Register Overview.....................................................................................211 8.4.9 SPI3 Register Overview.......................................................................................213 8.4.10 SerDes Register Overview ..................................................................................220 8.4.11 Optical Module Register Overview ......................................................................222

Revision Number: 009 Revision Date: 27-Oct-2005 9.0 Mechanical Specifications........................................................................................................224 9.1 Overview...........................................................................................................................224 9.1.1 Features...............................................................................................................224 9.2 Package Specifics ............................................................................................................224 9.3 Package Information.........................................................................................................225 9.3.1 CBGA Package Diagrams ...................................................................................225 9.3.2 Flip Chip-Plastic Ball Grid Array Package Diagram.............................................227 9.3.3 Top Label Marking Example ................................................................................229 10.0 Product Ordering Information ..................................................................................................230 Figures 1 Block Diagram ............................................................................................................................21 2 Internal Architecture....................................................................................................................22 3 552-Ball CBGA Assignments (Top View) ...................................................................................23 4 Interface Signals ........................................................................................................................38 5 Power Supply Sequencing..........................................................................................................63 6 Analog Power Supply Filter Network ..........................................................................................65 7 Packet Buffering FIFO ................................................................................................................71 8 Ethernet Frame Format ..............................................................................................................71 9 PAUSE Frame Format................................................................................................................72 10 Transmit Pause Control Interface...............................................................................................74 11 MPHY Transmit Logical Timing ..................................................................................................85 12 MPHY Receive Logical Timing ...................................................................................................86 13 MPHY 32-Bit Interface................................................................................................................86 14 SPHY Transmit Logical Timing...................................................................................................88 15 SPHY Receive Logical Timing....................................................................................................89 16 SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit Interface) .....................................90 17 MAC GMII Interconnect ..............................................................................................................94 18 RGMII Interface ..........................................................................................................................96 19 TX_CTL Behavior .......................................................................................................................98 20 RX_CTL Behavior.......................................................................................................................98 21 Management Frame Structure (Single-Frame Format) ............................................................101 22 MDI State..................................................................................................................................102 23 SerDes Receiver Jitter Tolerance.............................................................................................106 24 I2C Random Read Transaction.................................................................................................111 25 Data Validity Timing..................................................................................................................113 26 Start and Stop Definition Timing...............................................................................................113 27 Acknowledge Timing.................................................................................................................114 28 Random Read...........................................................................................................................115 29 Mode 0 Timing..........................................................................................................................116 30 Mode 1 Timing..........................................................................................................................118 31 Read Timing Diagram - Asynchronous Interface......................................................................121 32 Write Timing Diagram - Asynchronous Interface......................................................................122 33 SPI3 Interface Loopback Path..................................................................................................126 34 Line Side Interface Loopback Path...........................................................................................127 35 SPI3 Receive Interface Timing .................................................................................................137 36 SPI3 Transmit Interface Timing ................................................................................................139

Revision Number: 009 Revision Date: 27-Oct-2005 37 RGMII Interface Timing ............................................................................................................141 38 1000BASE-T Transmit Interface Timing...................................................................................142 39 1000BASE-T Receive Interface Timing....................................................................................143 40 SerDes Timing Diagram ...........................................................................................................144 41 MDC High-Speed Operation Timing.........................................................................................145 42 MDC Low-Speed Operation Timing..........................................................................................145 43 MDIO Write Timing Diagram ....................................................................................................146 44 MDIO Read Timing Diagram ....................................................................................................146 45 Bus Timing Diagram .................................................................................................................147 46 Write Cycle Diagram.................................................................................................................147 47 CPU Interface Read Cycle AC Timing......................................................................................149 48 CPU Interface Write Cycle AC Timing......................................................................................149 49 Pause Control Interface Timing................................................................................................151 50 JTAG AC Timing.......................................................................................................................152 51 System Reset AC Timing .........................................................................................................153 52 LED AC Interface Timing..........................................................................................................154 53 Memory Overview Diagram ......................................................................................................155 54 Register Overview Diagram......................................................................................................156 55 CBGA Package Diagram..........................................................................................................225 56 CBGA Package Side View Diagram.........................................................................................226 57 FC-PBGA Package (Top and Bottom Views) ...........................................................................227 58 FC-PBGA Mechanical Specifications .......................................................................................228 59 Package Marking Example.......................................................................................................229 60 Ordering Information – Sample ................................................................................................230 Tables 1 Ball List in Alphanumeric Order by Signal Name........................................................................24 2 Ball List in Alphanumeric Order by Ball Location........................................................................30 3 SPI3 Interface Signal Descriptions .............................................................................................39 4 SerDes Interface Signal Descriptions.........................................................................................47 5 GMII Interface Signal Descriptions .............................................................................................48 6 RGMII Interface Signal Descriptions ..........................................................................................50 7 CPU Interface Signal Descriptions .............................................................................................51 8 Transmit Pause Control Interface Signal Descriptions ...............................................................53 9 Optical Module Interface Signal Descriptions.............................................................................53 10 MDIO Interface Signal Descriptions ...........................................................................................54 11 LED Interface Signal Descriptions..............................................................................................55 12 JTAG Interface Signal Descriptions............................................................................................55 13 System Interface Signal Descriptions.........................................................................................55 14 Power Supply Signal Descriptions..............................................................................................56 15 Ball Usage Summary..................................................................................................................57 16 Line Side Interface Multiplexed Balls..........................................................................................58 17 SPI3 MPHY/SPHY Interface.......................................................................................................59 18 Definition of Output and Bi-directional Balls During Hardware Reset.........................................61 19 Power Supply Sequencing .........................................................................................................64 20 Pull-Up/Pull-Down and Unused Ball Guidelines .........................................................................64 21 Analog Power Balls ....................................................................................................................65 22 CRC Errored Packets Drop Enable Behavior.............................................................................69 23 Valid Decodes for TXPAUSEADD[2:0].......................................................................................74 24 Operational Mode Configuration Registers ................................................................................76

Revision Number: 009 Revision Date: 27-Oct-2005 25 RMON Additional Statistics.........................................................................................................81 26 GMII Interface Signal Definitions ................................................................................................95 27 RGMII Signal Definitions.............................................................................................................97 28 TX_ER and RX_ER Coding Description.....................................................................................97 29 SerDes Driver TX Power Levels ...............................................................................................104 30 Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections........................................107 31 LED Interface Signal Descriptions............................................................................................116 32 Mode 0 Clock Cycle to Data Bit Relationship ...........................................................................117 33 Mode 1 Clock Cycle to Data Bit Relationship ...........................................................................118 34 LED_DATA# Decodes..............................................................................................................119 35 LED Behavior (Fiber Mode) ......................................................................................................119 36 LED Behavior (Copper Mode) ..................................................................................................120 37 Byte Swapper Behavior ............................................................................................................123 38 Instruction Register Description................................................................................................124 39 Absolute Maximum Ratings ......................................................................................................132 40 Recommended Operating Conditions.......................................................................................133 41 DC Specifications .....................................................................................................................134 42 SerDes Transmit Characteristics..............................................................................................134 43 SerDes Receive Characteristics ...............................................................................................135 44 Undershoot / Overshoot Limits .................................................................................................135 45 RGMII Power ............................................................................................................................136 46 SPI3 Receive Interface Signal Parameters ..............................................................................138 47 SPI3 Transmit Interface Signal Parameters .............................................................................140 48 RGMII Interface Timing Parameters.........................................................................................141 49 GMII 1000BASE-T Transmit Signal Parameters ......................................................................142 50 GMII 1000BASE-T Receive Signal Parameters .......................................................................143 51 SerDes Timing Parameters ......................................................................................................144 52 MDIO Timing Parameters .........................................................................................................146 53 I2C AC Timing Characteristics ..................................................................................................147 54 CPU Interface Write Cycle AC Signal Parameters ...................................................................150 55 Transmit Pause Control Interface Timing Parameters..............................................................151 56 JTAG AC Timing Parameters ...................................................................................................152 57 System Reset AC Timing Parameters ......................................................................................153 58 LED Interface AC Timing Parameters ......................................................................................154 59 MAC Control Registers ($ Port Index + Offset) ........................................................................156 60 MAC RX Statistics Registers ($ Port Index + Offset)................................................................157 61 MAC TX Statistics Registers ($ Port Index + Offset) ................................................................158 62 PHY Autoscan Registers ($ Port Index + Offset)......................................................................159 63 Global Status and Configuration Registers ($ 0x500 - 0X50C) ................................................159 64 RX FIFO Registers ($ 0x580 - 0x5BF)......................................................................................159 65 TX FIFO Registers ($ 0x600 - 0x63E) ......................................................................................160 66 MDIO Registers ($ 0x680 - 0x683) ...........................................................................................161 67 SPI3 Registers ($ 0x700 - 0x716).............................................................................................161 68 SerDes Registers ($ 0x780 - 0x798) ........................................................................................162 69 Optical Module Registers ($ 0x799 - 0x79F) ............................................................................162 70 Station Address ($ Port_Index +0x00 – +0x01)........................................................................163 71 Desired Duplex ($ Port_Index + 0x02) .....................................................................................163 72 FD FC Type ($ Port_Index + 0x03) ..........................................................................................163 73 Collision Distance ($ Port_Index + 0x05) .................................................................................164 74 Collision Threshold ($ Port_Index + 0x06) ...............................................................................164

Revision Number: 009 Revision Date: 27-Oct-2005 75 FC TX Timer Value ($ Port_Index + 0x07) ...............................................................................164 76 FD FC Address ($ Port_Index + 0x08 – + 0x09) ......................................................................164 77 IPG Receive Time 1 ($ Port_Index + 0x0A) .............................................................................165 78 IPG Receive Time 2 ($ Port_Index + 0x0B) .............................................................................165 79 IPG Transmit Time ($ Port_Index + 0x0C) ...............................................................................165 80 Pause Threshold ($ Port_Index + 0x0E) ..................................................................................166 81 Max Frame Size (Addr: Port_Index + 0x0F).............................................................................166 82 MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)..........................................................167 83 Flush TX ($ Port_Index + 0x11)................................................................................................167 84 FC Enable ($ Port_Index + 0x12).............................................................................................168 85 FC Back Pressure Length ($ Port_Index + 0x13).....................................................................168 86 Short Runts Threshold ($ Port_Index + 0x14)..........................................................................169 87 Discard Unknown Control Frame ($ Port_Index + 0x15)..........................................................169 88 RX Config Word ($ Port_Index + 0x16)....................................................................................169 89 TX Config Word ($ Port_Index + 0x17) ....................................................................................170 90 Diverse Config Write ($ Port_Index + 0x18).............................................................................171 91 RX Packet Filter Control ($ Port_Index + 0x19) .......................................................................172 92 Port Multicast Address ($ Port_Index +0x1A – +0x1B) ............................................................173 93 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)..................................................................174 94 MAC TX Statistics ($ Port_Index +0x40 – +0x58) ....................................................................178 95 PHY Control ($ Port Index + 0x60)...........................................................................................181 96 PHY Status ($ Port Index + 0x61) ............................................................................................182 97 PHY Identification 1 ($ Port Index + 0x62) ...............................................................................183 98 PHY Identification 2 ($ Port Index + 0x63) ...............................................................................184 99 Auto-Negotiation Advertisement ($ Port Index + 0x64) ............................................................184 100 Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)...................................185 101 Auto-Negotiation Expansion ($ Port Index + 0x66) ..................................................................186 102 Auto-Negotiation Next Page Transmit ($ Port Index + 0x67) ...................................................187 103 Port Enable ($0x500)................................................................................................................188 104 Interface Mode ($0x501) ..........................................................................................................188 105 Link LED Enable ($0x502)........................................................................................................189 106 MAC Soft Reset ($0x505).........................................................................................................189 107 MDIO Soft Reset ($0x506) .......................................................................................................190 108 CPU Interface ($0x508)............................................................................................................190 109 LED Control ($0x509)...............................................................................................................190 110 LED Flash Rate ($0x50A).........................................................................................................191 111 LED Fault Disable ($0x50B) .....................................................................................................191 112 JTAG ID ($0x50C) ....................................................................................................................192 113 RX FIFO High Watermark Port 0 ($0x580)...............................................................................193 114 RX FIFO High Watermark Port 1 ($0x581)...............................................................................193 115 RX FIFO High Watermark Port 2 ($0x582)...............................................................................193 116 RX FIFO High Watermark Port 3 ($0x583)...............................................................................194 117 RX FIFO Low Watermark Port 0 ($0x58A) ...............................................................................194 118 RX FIFO Low Watermark Port 1 ($0x58B) ...............................................................................194 119 RX FIFO Low Watermark Port 2 ($0x58C)...............................................................................195 120 RX FIFO Low Watermark Port 3 ($0x58D)...............................................................................195 121 RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)....................................195 122 RX FIFO Port Reset ($0x59E)..................................................................................................196 123 RX FIFO Errored Frame Drop Enable ($0x59F).......................................................................196 124 RX FIFO Overflow Event ($0x5A0) ..........................................................................................197

Revision Number: 009 Revision Date: 27-Oct-2005 125 RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) ......................................198 126 RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)........................................................199 127 RX FIFO Padding and CRC Strip Enable ($0x5B3) .................................................................200 128 RX FIFO Transfer Threshold Port 0 ($0x5B8) ..........................................................................201 129 RX FIFO Transfer Threshold Port 1 ($0x5B9) ..........................................................................201 130 RX FIFO Transfer Threshold Port 2 ($0x5BA)..........................................................................202 131 RX FIFO Transfer Threshold Port 3 ($0x5BB)..........................................................................202 132 TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) ..........................................................203 133 TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)............................................204 134 TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617) .............................................205 135 TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E)..............................................206 136 Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F) ...................................207 137 TX FIFO Port Reset ($0x620)...................................................................................................207 138 TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624) ....................................208 139 TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629) ......................................209 140 TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630)...............................................210 141 TX FIFO Port Drop Enable ($0x63D)........................................................................................210 142 MDIO Single Command ($0x680).............................................................................................211 143 MDIO Single Read and Write Data ($0x681)............................................................................211 144 Autoscan PHY Address Enable ($0x682).................................................................................212 145 MDIO Control ($0x683).............................................................................................................212 146 SPI3 Transmit and Global Configuration ($0x700) ...................................................................213 147 SPI3 Receive Configuration ($0x701) ......................................................................................215 148 Address Parity Error Packet Drop Counter ($0x70A) ...............................................................219 149 TX Driver Power Level Ports 0 - 3 ($0x784) .............................................................................220 150 TX and RX Power-Down ($0x787) ...........................................................................................220 151 RX Signal Detect Level Ports 0 - 3 ($0x793) ............................................................................220 152 Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794) ..............................................221 153 Optical Module Status Ports 0-3 ($0x799)................................................................................222 154 Optical Module Control Ports 0 - 3 ($0x79A) ............................................................................222 155 I2C Control Ports 0 - 3 ($0x79B)...............................................................................................223 156 I2C Data Ports 0 - 3 ($0x79F) ...................................................................................................223 157 Product Information ..................................................................................................................230

Revision Number: 009 Revision Date: 27-Oct-2005 Revision History Revision Number: 009 Revision Date: 27-Oct-2005 Page # Description 71 Modified Figure 8 “Ethernet Frame Format” [changed Preamble byte count to 7 bytes]. 136 Section 45, “RGMII Power” [changed VCC to VDD in IIH and IIL] 110 Added bullet to Section 5.7.3, “I²C Module Configuration Interface”: The I2C interface only supports random single-byte reads and does not guarantee coherency when reading two-byte registers. 227 Replaced Figure 57 “FC-PBGA Package (Top and Bottom Views)” on page 227. 215 Modified Table 147 “SPI3 Receive Configuration ($0x701)”. 222 Modified Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)”: changed default values. 223 Modified Table 155 “I2C Control Ports 0 - 3 ($0x79B)”. 249 Modified Table 208 “I2C Data Ports 0 - 9 ($0x79F)” (changed address from $0x79C to $0x79F). 229 Added Section 9.3.3, “Top Label Marking Example”. 230 Modifed Table 157 “Product Information” and Figure 60 “Ordering Information – Sample” under Section 10.0, “Product Ordering Information”. Revision Number: 008 Revision Date: August 1, 2005 (Sheet 1 of 2) Page # Description 1 Added 552-ball Ceramic Ball Grid Array (CBGA) compliant with RoHS and Product Ordering Number information. 55 Modified Table 12 “JTAG Interface Signal Descriptions”: changed Standard to 3.3 V LVTTL from 2.5 V CMOS. 72 Modified Figure 9 “PAUSE Frame Format” [changed Preamble byte count to 7 bytes]. 85 Modified Figure 11 “MPHY Transmit Logical Timing” [updated TDAT[31:0]]. 86 Modified Figure 12 “MPHY Receive Logical Timing” [updated RDAT[31:0]]. 88 Modified Figure 14 “SPHY Transmit Logical Timing” [updated TDAT[7:0]]. 89 Modified Figure 15 “SPHY Receive Logical Timing” [updated RDAT[7:0] and RPRTY]. 121 Modified Figure 31 “Read Timing Diagram - Asynchronous Interface”: changed uPx_ADD[12:0] to uPx_ADD[10:0]. 125 Added paragraphs two and three under Section 5.11, “Loopback Modes”. 129 Changed 3.3 V CMOS to 2.5 V CMOS under Section 5.12.5, “JTAG Clock” on page 129. 131 Added Section 6.2, “Disable and Enable Port Sequences”. 136 Modified Table 45 “RGMII Power” [changed VOH, VOL, VIH, VIL minimum conditions to VDD and changed VIN value to VDD + .3]. 138 Modified Table 46 “SPI3 Receive Interface Signal Parameters” [changed RFCLK duty cycle to 45 min and 55 max; Changed Min for RFCLK frequency to 90]. 140 Modified Table 47 “SPI3 Transmit Interface Signal Parameters” [changed TFCLK duty cycle to 45 min and 55 max]. 146 Changed MDC to MDIO Output delay max for t3 for 2.5 MHz from 200 to 300 in Table 52 “MDIO Timing Parameters” on page 146.

Revision Number: 009 Revision Date: 27-Oct-2005 170 Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [changed default value for the register from “0x0001A0” to “0x000001A0” and changed default value for bit 6 (Half Duplex) from 1 to 0]. 181 Modified Table 95 “PHY Control ($ Port Index + 0x60)” [added “Need one-sentence descriptions of register” and register default value]. 182 Modified Table 96 “PHY Status ($ Port Index + 0x61)” [added “Need one-sentence descriptions of register” and register default value]. 183 Modified Table 97 “PHY Identification 1 ($ Port Index + 0x62)” [added “Need one-sentence descriptions of register” and register default value]. 184 Modified Table 98 “PHY Identification 2 ($ Port Index + 0x63)” [added “Need one-sentence descriptions of register” and register default value]. 184 Modified Table 99 “Auto-Negotiation Advertisement ($ Port Index + 0x64)” [added “Need one- sentence descriptions of register” and register default value]. 185 Modified Table 100 “Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)” [added “Need one-sentence descriptions of register” and register default value]. 186 Modified Table 101 “Auto-Negotiation Expansion ($ Port Index + 0x66)” [added “Need one- sentence descriptions of register” and register default value]. 187 Modified Table 102 “Auto-Negotiation Next Page Transmit ($ Port Index + 0x67)” [added “Need one-sentence descriptions of register” and register default value]. 211 Modified Table 143 “MDIO Single Read and Write Data ($0x681)” [changed MDIO write data to “MDIO write data to external device”]. 213 Modified Table 146 “SPI3 Transmit and Global Configuration ($0x700)” [changed default value for bits 3:0 from “0” to “1” and changed default value for entire register from “0x0020000F” to “0x00200000”]. 215 Modified Table 147 “SPI3 Receive Configuration ($0x701)” [changed default value for bits 11:8 from “0xF” to “0x1”]. 222 Modified Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)” [changed default value for bits 16:13 from “0xF” to “0x1”]. 227 Added Figure 57 “FC-PBGA Package (Top and Bottom Views)” on page 227 and Figure 58 “FC-PBGA Mechanical Specifications” on page 228. 229 Replaced Figure 59 “Package Marking Example”. 229 Added Section 9.4, “RoHS Compliance” on page 229. 230 Added CBGA RoHS-compliant and FC-PBGA ordering information under Table 157 “Product Information”. Revision Number: 008 Revision Date: August 1, 2005 (Sheet 2 of 2) Page # Description

Revision Number: 009 Revision Date: 27-Oct-2005 Revision Number: 007 Revision Date: March 24, 2004 (Sheet 1 of 5) Page # Description All Globally replaced GBIC with Optical Module Interface. All Globally edited signal names. All Globally changed SerDes and PLL analog power ball names as follows: TXAVTT and RXAVTT changed to AVDD1P8_2 TXAV25 and RXAV25 changed to AVDD2P5_2 PLL1_VDDA and PLL2_VDDA changed to AVDD1P8_1 PLL3_VDDA changed to AVDD2P5_1 PLL1_GNDA, PLL2_GNDA, and PLL3_GNDA changed to GND 1 Reworded and rearranged the Product Features section on page one Changed Jumbo frame support from “10 kbytes” to “9.6 KB”. 21 Changed heading to Section 2.0, “General Description” [was Section 2.0, “Block Diagram”]. 23/37 Reversed sections as follows: Section 3.0, “Ball Assignments and Ball List Tables” Section 4.0, “Ball Assignments and Signal Descriptions” 24 Modified Table 1 “Ball List in Alphanumeric Order by Signal Name”: Changed A10 from VCC to VDD Changed C12 from VCC to VDD Changed D11 from VCC to VDD Changed J20 from GND to VDD Changed Ball A1 from NC to No Pad. Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball. 30 Modified Table 2 “Ball List in Alphanumeric Order by Ball Location” Changed A10 from VCC to VDD Changed C12 form VCC to VDD Changed D11 from VCC to VDD Changed J20 from GND to VDD Changed Ball A1 from NC to No Pad. Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball. 38 Updated Figure 4 “Interface Signals” [modified SPI3 interface signals and added MPHY and SPHY categories; modified signal names]. 39 Broke old Table 1, “IXF1104 Signal Descriptions” into the following: Table 3 “SPI3 Interface Signal Descriptions” on page 39 through Table 14 “Power Supply Signal Descriptions” on page 56 39 Modified Table 3 “SPI3 Interface Signal Descriptions” on page 39 [edited description for DTPA; added text to TFCLK description; added text to RFCLK description]. 50 Modified Table 6 “RGMII Interface Signal Descriptions” [Added Ball Designators; added notes under descriptions]. 51 Modified Table 7 “CPU Interface Signal Descriptions” [UPX_DATA[16]: deleted J10, added M10]. 53 Modified Table 9 “Optical Module Interface Signal Descriptions” [added Ball Designators]. 54 Modified Table 10 “MDIO Interface Signal Descriptions” [moved note from MDC to MDIO]. 56 Modified Table 14 “Power Supply Signal Descriptions” [added Ball Designators A4, A21, and AD21 to GND; added AVDD1P8_1, AVDD1P8_2, AVDD2P5_1, and AVDD2P5_2].

Revision Number: 009 Revision Date: 27-Oct-2005 39 Modified Section 4.3, “Signal Description Tables” [changed heading from “Signal Naming Conventions; added new headings Section 4.1.1, “Signal Name Conventions” and Section 4.1.2, “Register Address Conventions”; and added/enhanced material under headings. 58 Added new Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface Multiplexed Balls” and Table 17 “SPI3 MPHY/SPHY Interface”. 63 Modified Section 4.7, “Power Supply Sequencing” [changed language under this section and added Section 4.7.1, “Power-Up Sequence” and Section 4.7.2, “Power-Down Sequence”]. 63 Modified Table 5 “Power Supply Sequencing” [deleted 3.3 V Supplies Stable; changed Apply 1.8 V to VDD, AVDD1P8_1, and AVDD1P8_2; changed Apply 2.5 V to AVDD2P5_1 and AVDD2P5_2]. 61 Modified Table 18 “Definition of Output and Bi-directional Balls During Hardware Reset” [changed comments for Optical Modules]. 64 Modified Table 20 “Pull-Up/Pull-Down and Unused Ball Guidelines” [changed TRST_L to pull-down; added MDIO, UPX_RDY_L, I2C_DATA_3:0, and TX_DISABLE_3:0]. 64 Added new Section 4.9, “Analog Power Filtering” [including Figure 6 “Analog Power Supply Filter Network” on page 65 and Table 21 “Analog Power Balls” on page 65]. 66 Modified/edited text under Section 5.1, “Media Access Controller (MAC)” [rearranged and created new bullets]. 67 Modified first paragraph under Section 5.1.1.1, “Padding of Undersized Frames on Transmit”. 67 Modified entire Section 5.1.1.3, “Filtering of Receive Packets”. 68 Added new Section 5.1.1.3.6, “Filter CRC Error Packets”. 69 Added note under Table 22 “CRC Errored Packets Drop Enable Behavior”. 69 Added new Section 5.1.2, “Flow Control” including Figure 7 “Packet Buffering FIFO”, Figure 8 “Ethernet Frame Format”, and Figure 9 “PAUSE Frame Format”. 73 Replaced Section 5.1.2.1.5, “Transmit Pause Control Interface” [added Table 23 “Valid Decodes for TXPAUSEADD[2:0]” and modified Table 10 “Transmit Pause Control Interface”. 74 Modified Figure 10 “Transmit Pause Control Interface” 75 Added note under Section 5.1.3.1, “Configuration”. 76 Added table note to Table 24 “Operational Mode Configuration Registers”. 77 Added note under Section 5.1.4.3, “Fiber Forced Mode”. 79 Modified Section 5.1.6.2, “TX Statistics” [added text to third sentence in first paragraph]. 79 Modified Section 5.1.6.3, “Loss-less Flow Control” [changed “two kilometers” to “five kilometers” in last sentence. 80 Modified Section 5.1.7.1.2, “RX FIFO” [changed 10 KB to 9.6 KB; added text to last paragraph]. 83 Rewrote/replaced Section 5.2, “SPI3 Interface”. 86 Edited signal names in Figure 13 “MPHY 32-Bit Interface”. 90 Edited signal names in Figure 16 “SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit Interface)”. 91 Added new Section 5.2.2.9, “SPI3 Flow Control”. [Removed old “Packet-Level and Byte-Level Transfers” section.} 94 Modified Figure 17 “MAC GMII Interconnect” [edited signal names]. NA Removed old Section 5.3.3 Electrical Requirements and Table 27 “Electrical Requirements” – changed Input high current Max from 40 to 15 and Input low current Min from -600 to -15. 96 Added a note under Section 5.4, “Reduced Gigabit Media Independent Interface (RGMII)”. 96 Modified Figure 18 “RGMII Interface” [edited signal names]. Revision Number: 007 Revision Date: March 24, 2004 (Sheet 2 of 5) Page # Description

Revision Number: 009 Revision Date: 27-Oct-2005 98 Modified Figure 19 “TX_CTL Behavior” [changed signal names]. 98 Modified Figure 20 “RX_CTL Behavior” [changed signal names]. 99 Modified Section 5.5, “MDIO Control and Interface” [changed 3.3 us to 3.3 ms in fourth paragraph, third sentence]. 103 Modified/replaced all text under Section 5.6, “SerDes Interface” on page 103 [added Table 29 “SerDes Driver TX Power Levels”]. NA Removed old Section 5.6.2.4 AC/DC Coupling. NA Removed old Section 5.6.2.9 System Jitter. 107 Modified Table 30 “Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections” [edited signal names]. 107 Modified/replaced text and deleted old “Figure 19. Typical GBIC Module Functional Diagram” under Section 5.7, “Optical Module Interface”]. 108 Modified second sentence under Section 5.7.2.2.1, “MOD_DEF_0:3”. 109 Modified second sentence under Section 5.7.2.2.3, “RX_LOS_0:3”. 109 Removed third paragraph under Section 5.7.2.2.7, “RX_LOS_INT”. 110 Modified first and second paragraphs under Section 5.7.3, “I²C Module Configuration Interface”. 111 Modified Section 5.7.3.3, “I2C Write Operation” [edited portions of text]. 116 Modified Table 31 “LED Interface Signal Descriptions” [changed 0.5 MHz to 720 Hz for LED_CLK under Signal Description]. 119 Modified Table 35 “LED Behavior (Fiber Mode)” [changed links under Description to “Link LED Enable ($0x502)”]. NA Removed old Figure 30 “CPU – External and Internal Connections”. 123 Modified Table 37 “Byte Swapper Behavior” [edited/added new values]. 123 Modified second paragraph under Section 5.10, “TAP Interface (JTAG)” 126 Modified Figure 33 “SPI3 Interface Loopback Path”. 126 Added note under Section 5.11.2, “Line Side Interface Loopback”. 127 Modified Figure 34 “Line Side Interface Loopback Path”. 127 Changed Section 5.12, “Clocks” [from GBIC output clock to I2C Clock]. 129 Changed Section 5.12.6, “I2C Clock” [from GBIC Clock to I2C Clock]. 130 Added new Section 6.0, “Applications”. 132 Modified Table 39 “Absolute Maximum Ratings” [changed SerDes analog power to AVDD1P8_2 and AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed PLL3_VDDA to AVDD2P5_1. 133 Modified Table 40 “Recommended Operating Conditions” [changed SerDes analog power to AVDD1P8_2 and AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed PLL3_VDDA to AVDD2P5_1. 134 Modified Table 42 “SerDes Transmit Characteristics” [included SerDes power driver level information]. 142 Modified Table 49 “GMII 1000BASE-T Transmit Signal Parameters” (changed Min values for t1 and t2. 143 Modified Table 50 “GMII 1000BASE-T Receive Signal Parameters” (changed Min values for t1 and t2. 146 Replaced old MDIO Timing diagram and table with Figure 43 “MDIO Write Timing Diagram”, Figure 44 “MDIO Read Timing Diagram”, and Table 52 “MDIO Timing Parameters”. Revision Number: 007 Revision Date: March 24, 2004 (Sheet 3 of 5) Page # Description

Revision Number: 009 Revision Date: 27-Oct-2005 156 Broke up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Offset)”, Table 60 “MAC RX Statistics Registers ($ Port Index + Offset)”, Table 61 “MAC TX Statistics Registers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”, Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)”, Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)”, Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)”, Table 66 “MDIO Registers ($ 0x680 - 0x683)”, Table 67 “SPI3 Registers ($ 0x700 - 0x716)”, Table 68 “SerDes Registers ($ 0x780 - 0x798)”, and Table 69 “Optical Module Registers ($ 0x799 - 0x79F)”. 159 Edited Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)” [no offset]. 159 Edited Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)” [no offset]. 160 Edited Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)” [no offset]. 161 Edited Table 66 “MDIO Registers ($ 0x680 - 0x683)” [no offset]. 161 Edited Table 67 “SPI3 Registers ($ 0x700 - 0x716)” [no offset]. 162 Edited Table 68 “SerDes Registers ($ 0x780 - 0x798)” [no offset]. 162 Edited Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” [no offset]. 163 Modified Table 71 “Desired Duplex ($ Port_Index + 0x02)” [changed 100 Mbps to 1000 Mbps in register description. 167 Modified Table 82 “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” [Added text to register description.] 168 Modified Table 84 “FC Enable ($ Port_Index + 0x12)” [changed description for bits 1:0]. 169 Modified Table 88 “RX Config Word ($ Port_Index + 0x16)” [edited Register Description text; changed description and type for bits 13:12]. 170 Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [edited description and type for bits 14, 13:12. 171 Modified Table 90 “Diverse Config Write ($ Port_Index + 0x18)” [edited description and type for bits 18:8; changed bits 3:1 to Reserved; added table note 2]. 172 Renamed/modified Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)” [old register name - added RX to heading; added table note 2]. 174 Modified Table 93 “MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)” [added note to RxPauseMacControlReceivedCounter description; edited note 3 and added note 4]. 178 Modified Table 94 “MAC TX Statistics ($ Port_Index +0x40 – +0x58)” [changed “1526-max” to “1523 - max frame size” for Txpkts1519toMaxOctets description]. 193 Modified Table 113 “RX FIFO High Watermark Port 0 ($0x580)”, Table 114 “RX FIFO High Watermark Port 1 ($0x581)”, Table 115 “RX FIFO High Watermark Port 2 ($0x582)”, and Table 116 “RX FIFO High Watermark Port 3 ($0x583)” [changed bits 11:0 description]. 195 Renamed and modified Table 121 “RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)” [old register name: RX FIFO Number of Frames Removed Ports 0 to 3; renamed bit names to match register names; removed “This register gets updated after one cycle of sw reset is applied” under Description]. 196 Modified Table 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” [renamed bit names to match register name]. 198 Renamed/modified Table 125 “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)” on page 198 [older register name: RX FIFO Dropped Packet Counter for Ports 0 to 3; renamed bit names to match register name]. 199 Modified Table 126 “RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)” [renamed heading and bit name; changed description and type for bits 7:0]. 201 Renamed Table 128 “RX FIFO Transfer Threshold Port 0 ($0x5B8)” on page 201 [from “RX FIFO Jumbo Packet Size; changed bit names and edited/added text under description]. Revision Number: 007 Revision Date: March 24, 2004 (Sheet 4 of 5) Page # Description

Revision Number: 009 Revision Date: 27-Oct-2005 207 Modified Table 136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)” [renamed heading and bit name]. 208 Modified Table 138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)” [renamed from TX FIFO Number of Frames Removed Ports 3 - 0]. 209 Modified Table 139 “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)” [renamed from TX FIFO Number of Dropped Packets Ports 0-3 and text under the description]. 210 Modified Table 141 “TX FIFO Port Drop Enable ($0x63D)” [changed description for bits 3:0]. 211 Modified Table 142 “MDIO Single Command ($0x680)” [changed default; changed description and default for bits 9:8; changed default for bits 4:0]. 212 Modified Table 144 “Autoscan PHY Address Enable ($0x682)” [added note to register description]. 213 Modified Table 146 “SPI3 Transmit and Global Configuration ($0x700)” [broke out bits 19:16, 7:4, and 3:0 and changed description text]. 215 Modified Table 147 “SPI3 Receive Configuration ($0x701)” [broke out bits and modified all text adding SPHY and MPHY modes]. 221 Modified Table 152 “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” [deleted second paragraph of the Register Description; renamed bits to match caption; changed text under Description]. 222 Added note under Section 8.4.11, “Optical Module Register Overview”. 222 Modified Table 153 “Optical Module Status Ports 0-3 ($0x799)” [edited register description]. 222 Modified Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)” [changed register description]. NA Removed/Reserved Table 190 “TX and RX AC/DC Coupling Selection ($7x780)”. NA Deleted old Figure 19, “Typical GBIC Module Functional Diagram” under Section 5.7, “Optical Module Interface”. NA Removed old Section 5.1.1.5, “Pause Command Frames.” 180(old) Removed old Table 13. TX FIFO Mini Frame Size for MAC and Padding Enable Port 0 to 3 Register (Addr: 0x63E) and replaced with Reserved. Revision Number: 006 Revision Date: August 21, 2003 (Sheet 1 of 2) Page # Description 19 Modified Table 1 “Intel® IXF1104 Signal Descriptions” 53 Modified Section 5.1.1.1, “Padding of Undersized Frames on Transmit”. 60 Modified text for etherStatsCollision in Table 9 “RMON Additional Statistics”. 87 Modified Table 17 “Intel® IXF1104-to-Optical Module Interface Connections” 65 Modified first paragraph under Section 5.3.1.2, “Clock Rates”. 87 Modified Section 5.8.2.1, “High-Speed Serial Interface”. 100 Modified Figure 27 “Microprocessor — External and Internal Connections”. 110 Changed PECL to LVDS under Section 6.1, “DC Specifications”. 113 Modified table note 4 in Table 32 “SPI3 Receive Interface Signal Parameters”. 119 Modified Table 37 “SerDes Timing Parameters”. 125 Modified Table 40 “Microprocessor Interface Write Cycle AC Signal Parameters”. Revision Number: 007 Revision Date: March 24, 2004 (Sheet 5 of 5) Page # Description

Revision Number: 009 Revision Date: 27-Oct-2005 140 Modified Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – + 0x0C)”. 143 Modified Table 60 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”. 143 Modified Table 61 “Discard Unknown Control Frame Register (Addr: Port_Index + 0x15)”. 143 Modified Table 62 “RX Config Word Register Bit Definition (Addr: Port_Index + 0x16)”. 145 Modified Table 64 “DiverseConfigWrite Register (Addr: Port_Index + 0x18)”. 148 Modified Table 67 “RX Statistics Registers (Addr: Port_Index + 0x20 – + 0x39)”. 163 Modified Table 82 “Microprocessor Interface Register (Addr: 0x508)”. 164 Modified Table 84 “LED Flash Rate Register (Addr: 0x50A)”. 169 Modified Table 93 “RX FIFO Errored Frame Drop Enable Register (Addr: 0x59F)”. 170 Modified Table 96 “RX FIFO Loopback Enable for Ports 0 - 3 Register (Addr: 0x5B2)”. 171 Added Table 98 “RX FIFO Jumbo Packet Size 0-3 Register (Addr: 0x5B8 – 0x5BB”. 172 Added Table 99 “RX FIFO Jumbo Packet Size Port 0 Register Bit Definitions (Addr: 0x5B8)”. 172 Added Table 100 “RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions (Addr: 0x5B9)”. 172 Added Table 101 “RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions (Addr: 0x5BA)”. 172 Added Table 102 “RX FIFO Jumbo Packet Size Port 3 Register Bit Definitions (Addr: 0x5BB)”. 178 Modified Table 110 “TX FIFO Number of Dropped Packets Register Ports 0-3 (Addr: 0x625 – 0x629)”. 177 Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”. 177 Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”. 177 Modified Table 107 “Loop RX Data to TX FIFO Register Ports 0 - 3 (Addr: 0x61F)”. 179 Added Table 111 “TX FIFO Occupancy Counter for Ports 0 - 3 Registers (Addr: 0x62D – 0x630)”. 180 Added Table 112 “TX FIFO Port Drop Enable Register (Addr: 0x63D)”. 181 Modified Table 114 “MDI Single Command Register (Addr: 0x680)”. 186 Added Table 122 “Tx and Rx Power-Down Register (Addr: 0x787)”. 194 Replaced Figure 53 “Intel® IXF1104 Example Package Marking”. Revision 005 Revision Date: April 30, 2003 Page # Description Initial external release. Revisions 001 through 004 Revision Date: April 2001 – December 2002 Page # Description Internal releases. Revision Number: 006 Revision Date: August 21, 2003 (Sheet 2 of 2) Page # Description

Datasheet 20 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 1.0 Introduction This document contains information on the IXF1104 MAC, a four-port Gigabit Media Access Controller that supports IEEE 802.3 10/100/1000 Mbps applications. 1.1 What You Will Find in This Document This document contains the following sections: • Section 2.0, “General Description” on page 21 provides the block diagram system architecture. • Section 3.0, “Ball Assignments and Ball List Tables” on page 23 shows the signal naming methodology and signal descriptions. • Section 4.0, “Ball Assignments and Signal Descriptions” on page 37 illustrates and lists the IXF1104 ball grid diagram with two ball list tables (by signal name and ball location) • Section 5.0, “Functional Descriptions” on page 66 gives detailed information about the operation of the IXF1104 including general features, and interface types and descriptions. • Section 7.0, “Electrical Specifications” on page 132 provides information on the product- operating parameters, electrical specifications, and timing parameters. • Section 8.0, “Register Set” on page 155 illustrates and lists the memory map, detailed descriptions, default values for the register set, and detailed information on each register. • Section 9.0, “Mechanical Specifications” on page 224 illustrates the packaging information. • Section 10.0, “Product Ordering Information” on page 230 provides ordering information. 1.2 Related Documents Document Document Number Intel® IXF1104 Media Access Controller Design and Layout Guide 278696 Intel® IXF1104 Media Access Controller Thermal Design Considerations 278751 Intel® IXF1104 Media Access Controller Development Kit Manual 278785 Intel® IXF1104 Media Access Controller Specification Update 278756

21 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 2.0 General Description The IXF1104 MAC provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full- duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network processor is supported through a System Packet Interface Phase 3 (SPI3) media interface. The following PHY interfaces are selected on a per-port basis: • Serializer/Deserializer (SerDes) with Optical Module Interface support • Gigabit Media Independent Interface (GMII) • Reduced Gigabit Media Independent Interface (RGMII). Figure 1 illustrates the IXF1104 MAC block diagram. Figure 1. Block Diagram Forwarding Engine/Network Processor CPU Intel® IXF1104 MAC SerDes/RGMII/GMII Interface MDIO SPI3 uP IF PHY 1 Device PHY 2 Device PHY 3 Device PHY 4 Device B3175-01

Datasheet 22 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Figure 2 illustrates the IXF1104 MAC internal architecture. Figure 2. Internal Architecture SPI3 Interface CPU Interface RMON Statistics Packet TX Buffer RX Packet Buffer Packet Buffer Packet Buffer Clock Control Block Clock Register Block PLLs MDIO OMI TX TX TX RX RX RX 10/100/1000 MAC 10/100/1000 MAC 10/100/1000 MAC 10/100/1000 MAC RGMII/GMII Interface RGMII/GMII Interface RGMII/GMII Interface RGMII/GMII Interface PMA Layer SerDes PMA Layer SerDes PMA Layer SerDes PMA Layer SerDes B3176-01

23 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 3.0 Ball Assignments and Ball List Tables 3.1 Ball Assignments See Figure 3, Table 1 “Ball List in Alphanumeric Order by Signal Name” on page 24, and Table 2 “Ball List in Alphanumeric Order by Ball Location” on page 30 for the IXF1104 MAC ball assignments. Figure 3. 552-Ball CBGA Assignments (Top View) B1458-01 1 AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 V7 U7 T7 R7 P7 N7 M7 L7 K7 J7 H7 G7 F7 E7 D7 G7 B7 A7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N121 N22 N23 N24 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 B28 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 = No Ball (A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3, AD22, AD23, AD24) = No Pad (A1) W24 Y24 AA24 AB24 AC24 AD24 W23 Y23 AA23 AB23 AC23 AD23 W22 Y22 AA22 AB22 AC22 AD22 W21 Y21 AA21 AB21 AC21 AD21 W20 Y20 AA20 AB20 AC20 AD20 W19 Y19 AA19 AB19 AC19 AD19 W18 Y18 AA18 AB18 AC18 AD18 W17 Y17 AA17 AB17 AC17 AD17 W16 Y16 AA16 AB16 AC16 AD16 W15 Y15 AA15 AB15 AC15 AD15 W14 Y14 AA14 AB14 AC14 AD14 W13 Y13 AA13 AB13 AC13 AD13 W12 Y12 AA12 AB12 AC12 AD12 W11 Y11 AA11 AB11 AC11 AD11 W10 Y10 AA10 AB10 AC10 AD10 W9 Y9 AA9 AB9 AC9 AD9 W8 Y8 AA8 AB8 AC8 AD8 W7 Y7 AA7 AB7 AC7 AD7 A6 B6 C6 D6 F6 F6 G6 H6 J6 K6 L6 M6 N6 P6 R6 T6 U6 V6 W6 Y6 AA6 AB6 AC6 AD6 A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5 V5 W5 Y5 AA4 AB5 AC5 AD5 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4 AC4 AD4 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P13 R3 T3 U3 V3 W3 Y3 AA3 AB3 AC3 AD3 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2 AD2 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AC2 A1 AD1

24 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 3.2 Ball List Tables 3.2.1 Balls Listed in Alphabetic Order by Signal Name Table 1 shows the ball locations and signal names arranged in alphanumeric order by signal name. The following table notes relate to Table 1 and Table 2: 1. GMII Ball Connection: See Table 16 for connection in RGMII or fiber mode. 2. SPI3 Ball Connection: See Table 17 for proper SPHY and MPHY connection. 3. Fiber Mode Ball Connection: See Table 16 for use in RGMII and GMII (copper mode). Table 1. Ball List in Alphanumeric Order by Signal Name Signal Name Ball Location AVDD1P8_1 A5 AVDD1P8_1 A20 AVDD1P8_2 T23 AVDD1P8_2 AB16 AVDD2P5_1 AD20 AVDD2P5_2 R18 AVDD2P5_2 U14 CLK125 AD19 COL_01 AB6 COL_11 AB10 COL_21 AD15 COL_31 AB17 CRS_01 AA5 CRS_11 AA9 CRS_21 AB15 CRS_31 AC16 DTPA_02 D3 DTPA_12 L1 DTPA_22 A9 DTPA_32 J7 GND B6 GND B10 GND B15 GND B19 GND D4 GND D8 GND D12 GND D13 GND D17 GND D21 GND F2 GND F6 GND F10 GND F15 GND F19 GND F23 GND H4 GND H8 GND H12 GND H13 GND H17 GND H21 GND J10 GND J15 GND K2 GND K6 GND K9 GND K11 Signal Name Ball Location GND K14 GND K16 GND K19 GND K23 GND L10 GND L12 GND L13 GND L15 GND M4 GND M8 GND M11 GND M14 GND M17 GND M21 GND N4 GND N8 GND N11 GND N14 GND N17 GND N21 GND P10 GND P12 GND P13 GND P15 Signal Name Ball Location

Datasheet 25 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 GND R2 GND R6 GND R9 GND R11 GND R14 GND R16 GND R19 GND R23 GND T10 GND T15 GND U4 GND U8 GND U12 GND U13 GND U17 GND U21 GND W2 GND W6 GND W10 GND W15 GND W19 GND W23 GND AA4 GND AA8 GND AA12 GND AA13 GND AA17 GND AA21 GND AC6 GND AC10 GND AC15 GND AC19 GND AC14 GND L20 GND L5 GND R7 GND AB12 GND A4 Signal Name Ball Location GND A21 GND AD21 I2C_CLK L23 I2C_DATA_03 L24 I2C_DATA_13 M24 I2C_DATA_23 N24 I2C_DATA_33 P24 LED_CLK K24 LED_DATA M22 LED_LATCH L22 MDC4 W24 MDIO4 V21 MOD_DEF_INT N22 NC D24 NC E12 NC F11 NC G15 NC H7 NC H18 NC J21 NC K7 NC K18 NC K20 NC K22 NC L18 NC L19 NC L21 NC M7 NC M18 NC M20 NC N3 NC N18 NC P2 NC P4 NC P6 NC P7 NC P8 NC P17 Signal Name Ball Location NC P18 NC R5 NC R10 NC R12 NC R13 NC R15 NC R20 NC T6 NC T7 NC T8 NC T9 NC T21 NC T22 NC U5 NC U7 NC U9 NC U11 NC U18 NC V9 NC V10 NC V11 NC V13 NC AB18 NC AD4 NC AD5 No Ball A2 No Ball A3 No Ball A22 No Ball A23 No Ball A24 No Ball B1 No Ball B2 No Ball B23 No Ball B24 No Ball C1 No Ball C24 No Ball AB1 No Ball AB24 Signal Name Ball Location

26 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 No Ball AC1 No Ball AC2 No Ball AC23 No Ball AC24 No Ball AD1 No Ball AD2 No Ball AD3 No Ball AD22 No Ball AD23 No Ball AD24 No Pad A1 PTPA2 B11 RDAT_02 A15 RDAT_12 A14 RDAT_22 B14 RDAT_32 C14 RDAT_42 C13 RDAT_52 D14 RDAT_62 E14 RDAT_72 F14 RDAT_82 A17 RDAT_92 C17 RDAT_102 D16 RDAT_112 E16 RDAT_122 F16 RDAT_132 E17 RDAT_142 E18 RDAT_152 F18 RDAT_162 B20 RDAT_172 B22 RDAT_182 C20 RDAT_192 C21 RDAT_202 C22 RDAT_212 D22 RDAT_222 E22 RDAT_232 E21 RDAT_242 G18 RDAT_252 G19 Signal Name Ball Location RDAT_262 G20 RDAT_272 G21 RDAT_282 G22 RDAT_292 G23 RDAT_302 G24 RDAT_312 F24 RENB_02 A13 RENB_12 A18 RENB_22 C19 RENB_32 E24 REOP_02 C16 REOP_12 D18 REOP_22 C23 REOP_32 J19 RERR_02 A16 RERR_12 G17 RERR_22 D20 RERR_32 H20 RFCLK2 A19 RMOD02 G14 RMOD12 G13 RPRTY_02 E15 RPRTY_12 G16 RPRTY_22 E20 RPRTY_32 F20 RSOP_02 B16 RSOP_12 C18 RSOP_22 E23 RSOP_32 J18 RSX2 E13 RVAL_02 C15 RVAL_12 B18 RVAL_22 E19 RVAL_32 F22 RX_DV_01 V5 RX_DV_11 AB11 RX_DV_21 Y24 RX_DV_31 V18 Signal Name Ball Location RX_ER_01 W5 RX_ER_11 Y12 RX_ER_21 AA22 RX_ER_31 U20 RX_LOS_INT3 P19 RX_N_03 R22 RX_N_13 U22 RX_N_23 R24 RX_N_33 V24 RX_P_03 P22 RX_P_13 V22 RX_P_23 T24 RX_P_33 U24 RXC_01 V4 RXC_11 AD11 RXC_21 AA24 RXC_31 V23 RXD0_01 V8 RXD0_11 Y9 RXD0_21 Y20 RXD0_31 Y17 RXD1_01 V7 RXD1_11 Y11 RXD1_21 Y21 RXD1_31 Y18 RXD2_01 W7 RXD2_11 W11 RXD2_21 Y22 RXD2_31 Y19 RXD3_01 Y7 RXD3_11 W9 RXD3_21 Y23 RXD3_31 W18 RXD4_01 Y6 RXD4_11 AD10 RXD4_21 W22 RXD4_31 T16 RXD5_01 Y5 Signal Name Ball Location

Datasheet 27 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 RXD5_11 AC11 RXD5_21 V20 RXD5_31 T17 RXD6_01 AB5 RXD6_11 AA11 RXD6_21 V19 RXD6_31 T18 RXD7_01 AC5 RXD7_11 Y10 RXD7_21 W20 RXD7_31 T19 STPA2 C11 SYS_RST_L AD12 TADR02 A11 TADR12 A12 TCLK J22 TDAT02 B3 TDAT12 C2 TDAT22 C3 TDAT32 D1 TDAT42 C4 TDAT52 C5 TDAT62 B5 TDAT72 C6 TDAT82 F1 TDAT92 G1 TDAT102 G2 TDAT112 H1 TDAT122 J1 TDAT132 J2 TDAT142 J3 TDAT152 H3 TDAT162 E5 TDAT172 E6 TDAT182 E7 TDAT192 E8 TDAT202 E9 TDAT212 E10 Signal Name Ball Location TDAT222 F9 TDAT232 C8 TDAT242 G4 TDAT252 G5 TDAT262 G6 TDAT272 G7 TDAT282 G8 TDAT292 G9 TDAT302 F5 TDAT312 F7 TDI J24 TDO H24 TENB_02 B7 TENB_12 E2 TENB_22 C9 TENB_32 J4 TEOP_02 A7 TEOP_12 F3 TEOP_22 E4 TEOP_32 H5 TERR_02 A8 TERR_12 K1 TERR_22 E11 TERR_32 J8 TFCLK2 D7 TMOD02 A6 TMOD12 D9 TMS H22 TPRTY_02 D5 TPRTY_12 G3 TPRTY_22 B9 TPRTY_32 J6 TRST_L J23 TSOP_02 C7 TSOP_12 E3 TSOP_22 C10 TSOP_32 J5 TSX E1 Signal Name Ball Location TX_EN_01 AB2 TX_EN_11 Y8 TX_EN_21 AC22 TX_EN_31 V12 TX_ER_01 W1 TX_ER_11 AD6 TX_ER_21 AD17 TX_ER_31 AB13 TX_FAULT_INT3 P23 TX_N_03 Y14 TX_N_13 AD14 TX_N_23 Y16 TX_N_33 AD18 TX_P_03 Y13 TX_P_13 AD13 TX_P_23 W16 TX_P_33 AC18 TXC_01 AA1 TXC_11 AD7 TXC_21 AC20 TXC_31 AB14 TXD0_01 Y1 TXD0_11 AC7 TXD0_21 AB20 TXD0_31 V14 TXD1_01 Y2 TXD1_11 AB7 TXD1_21 AB21 TXD1_31 V15 TXD2_01 Y3 TXD2_11 AB9 TXD2_21 AB22 TXD2_31 V16 TXD3_01 AA3 TXD3_11 AD9 TXD3_21 AB23 TXD3_31 V17 TXD4_01 AB3 Signal Name Ball Location

28 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 TXD4_11 AA7 TXD4_21 AD16 TXD4_31 AA14 TXD5_01 AC3 TXD5_11 AB8 TXD5_21 AB19 TXD5_31 Y15 TXD6_01 AB4 TXD6_11 AD8 TXD6_21 AA20 TXD6_31 AA16 TXD7_01 Y4 TXD7_11 AC9 TXD7_21 AA18 TXD7_31 W14 TXPAUSE_ADD0 N20 TXPAUSE_ADD1 P20 TXPAUSE_ADD2 P21 TXPAUSEFR T20 UPX_ADD0 P3 UPX_ADD1 N1 UPX_ADD2 P1 UPX_ADD3 R1 UPX_ADD4 T1 UPX_ADD5 U1 UPX_ADD6 V1 UPX_ADD7 V2 UPX_ADD8 V3 UPX_ADD9 U3 UPX_ADD10 T3 UPX_BADD0 T2 UPX_BADD1 W3 UPX_CS_L R3 UPX_DATA0 L2 UPX_DATA1 K3 UPX_DATA2 L3 UPX_DATA3 M3 UPX_DATA4 L4 Signal Name Ball Location UPX_DATA5 N5 UPX_DATA6 M5 UPX_DATA7 K5 UPX_DATA8 P5 UPX_DATA9 L6 UPX_DATA10 L7 UPX_DATA11 N7 UPX_DATA12 L8 UPX_DATA13 H9 UPX_DATA14 J9 UPX_DATA15 N10 UPX_DATA16 M10 UPX_DATA17 K10 UPX_DATA18 G10 UPX_DATA19 H11 UPX_DATA20 G11 UPX_DATA21 K12 UPX_DATA22 G12 UPX_DATA23 K13 UPX_DATA24 H14 UPX_DATA25 K15 UPX_DATA26 N15 UPX_DATA27 M15 UPX_DATA28 J16 UPX_DATA29 H16 UPX_DATA30 J17 UPX_DATA31 L17 UPX_RD_L V6 UPX_RDY_L M1 UPX_WIDTH0 U16 UPX_WIDTH1 T5 UPX_WR_L T4 VDD D6 VDD D10 VDD D15 VDD D19 VDD F4 VDD F21 Signal Name Ball Location VDD H10 VDD H15 VDD J11 VDD J14 VDD K4 VDD K8 VDD K17 VDD K21 VDD L9 VDD L11 VDD L14 VDD L16 VDD P9 VDD P11 VDD P14 VDD P16 VDD R4 VDD R8 VDD R17 VDD R21 VDD T11 VDD T14 VDD U10 VDD U15 VDD W4 VDD W21 VDD AA6 VDD AA10 VDD AA15 VDD AA19 VDD C12 VDD D11 VDD J20 VDD A10 VDD2 B4 VDD2 B8 VDD2 B12 VDD2 D2 Signal Name Ball Location

Datasheet 29 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 VDD2 F8 VDD2 F12 VDD2 H2 VDD2 H6 VDD2 J12 VDD2 M2 VDD2 M6 VDD2 M9 VDD2 M12 VDD3 B13 VDD3 B17 VDD3 B21 VDD3 D23 VDD3 F13 VDD3 F17 VDD3 H19 VDD3 H23 VDD3 J13 VDD3 M13 VDD3 M16 VDD3 M19 VDD3 M23 VDD4 N13 VDD4 N16 VDD4 N19 VDD4 N23 VDD4 T13 VDD4 U19 VDD4 U23 VDD4 W13 VDD4 W17 VDD4 AA23 VDD4 AC13 VDD4 AC17 VDD4 AC21 VDD5 N2 VDD5 N6 VDD5 N9 Signal Name Ball Location VDD5 N12 VDD5 T12 VDD5 U2 VDD5 U6 VDD5 W8 VDD5 W12 VDD5 AA2 VDD5 AC4 VDD5 AC8 VDD5 AC12 Signal Name Ball Location

30 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 3.2.2 Balls Listed in Alphabetic Order by Ball Location Table 2 shows the ball locations and signal names arranged in order by ball location. Table 2. Ball List in Alphanumeric Order by Ball Location Ball Location Signal Name A1 No Pad A2 No Ball A3 No Ball A4 GND A5 AVDD1P8_1 A6 TMOD02 A7 TEOP_02 A8 TERR_02 A9 DTPA_22 A10 VDD A11 TADR02 A12 TADR12 A13 RENB_02 A14 RDAT_12 A15 RDAT_02 A16 RERR_02 A17 RDAT_82 A18 RENB_12 A19 RFCLK2 A20 AVDD1P8_1 A21 GND A22 No Ball A23 No Ball A24 No Ball B1 No Ball B2 No Ball B3 TDAT02 B4 VDD2 B5 TDAT62 B6 GND B7 TENB_02 B8 VDD2 B9 TPRTY_22 B10 GND B11 PTPA2 B12 VDD2 B13 VDD3 B14 RDAT_22 B15 GND B16 RSOP_02 B17 VDD3 B18 RVAL_12 B19 GND B20 RDAT_162 B21 VDD3 B22 RDAT_172 B23 No Ball B24 No Ball C1 No Ball C2 TDAT12 C3 TDAT22 C4 TDAT42 C5 TDAT52 C6 TDAT72 C7 TSOP_02 C8 TDAT232 C9 TENB_22 C10 TSOP_22 C11 STPA2 C12 VDD C13 RDAT_42 C14 RDAT_32 C15 RVAL_02 C16 REOP_02 C17 RDAT_92 C18 RSOP_12 C19 RENB_22 Ball Location Signal Name C20 RDAT_182 C21 RDAT_192 C22 RDAT_202 C23 REOP_22 C24 No Ball D1 TDAT32 D2 VDD2 D3 DTPA_02 D4 GND D5 TPRTY_02 D6 VDD D7 TFCLK2 D8 GND D9 TMOD12 D10 VDD D11 VDD D12 GND D13 GND D14 RDAT_52 D15 VDD D16 RDAT_102 D17 GND D18 REOP_12 D19 VDD D20 RERR_22 D21 GND D22 RDAT_212 D23 VDD3 D24 NC E1 TSX E2 TENB_12 E3 TSOP_12 E4 TEOP_22 E5 TDAT162 Ball Location Signal Name

Datasheet 31 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 E6 TDAT172 E7 TDAT182 E8 TDAT192 E9 TDAT202 E10 TDAT212 E11 TERR_22 E12 NC E13 RSX2 E14 RDAT_62 E15 RPRTY_02 E16 RDAT_112 E17 RDAT_132 E18 RDAT_142 E19 RVAL_22 E20 RPRTY_22 E21 RDAT_232 E22 RDAT_222 E23 RSOP_22 E24 RENB_32 F1 TDAT82 F2 GND F3 TEOP_12 F4 VDD F5 TDAT302 F6 GND F7 TDAT312 F8 VDD2 F9 TDAT222 F10 GND F11 NC F12 VDD2 F13 VDD3 F14 RDAT_72 F15 GND F16 RDAT_122 F17 VDD3 F18 RDAT_152 F19 GND Ball Location Signal Name F20 RPRTY_32 F21 VDD F22 RVAL_32 F23 GND F24 RDAT_312 G1 TDAT92 G2 TDAT102 G3 TPRTY_12 G4 TDAT242 G5 TDAT252 G6 TDAT262 G7 TDAT272 G8 TDAT282 G9 TDAT292 G10 UPX_DATA18 G11 UPX_DATA20 G12 UPX_DATA22 G13 RMOD12 G14 RMOD02 G15 NC G16 RPRTY_12 G17 RERR_12 G18 RDAT_242 G19 RDAT_252 G20 RDAT_262 G21 RDAT_272 G22 RDAT_282 G23 RDAT_292 G24 RDAT_302 H1 TDAT112 H2 VDD2 H3 TDAT152 H4 GND H5 TEOP_32 H6 VDD2 H7 NC H8 GND H9 UPX_DATA13 Ball Location Signal Name H10 VDD H11 UPX_DATA19 H12 GND H13 GND H14 UPX_DATA24 H15 VDD H16 UPX_DATA29 H17 GND H18 NC H19 VDD3 H20 RERR_32 H21 GND H22 TMS H23 VDD3 H24 TDO J1 TDAT122 J2 TDAT132 J3 TDAT142 J4 TENB_32 J5 TSOP_32 J6 TPRTY_32 J7 DTPA_32 J8 TERR_32 J9 UPX_DATA14 J10 GND J11 VDD J12 VDD2 J13 VDD3 J14 VDD J15 GND J16 UPX_DATA28 J17 UPX_DATA30 J18 RSOP_32 J19 REOP_32 J20 VDD J21 NC J22 TCLK J23 TRST_L Ball Location Signal Name

32 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 J24 TDI K1 TERR_12 K2 GND K3 UPX_DATA1 K4 VDD K5 UPX_DATA7 K6 GND K7 NC K8 VDD K9 GND K10 UPX_DATA17 K11 GND K12 UPX_DATA21 K13 UPX_DATA23 K14 GND K15 UPX_DATA25 K16 GND K17 VDD K18 NC K19 GND K20 NC K21 VDD K22 NC K23 GND K24 LED_CLK L1 DTPA_12 L2 UPX_DATA0 L3 UPX_DATA2 L4 UPX_DATA4 L5 GND L6 UPX_DATA9 L7 UPX_DATA10 L8 UPX_DATA12 L9 VDD L10 GND L11 VDD L12 GND L13 GND Ball Location Signal Name L14 VDD L15 GND L16 VDD L17 UPX_DATA31 L18 NC L19 NC L20 GND L21 NC L22 LED_LATCH L23 I2C_CLK L24 I2C_DATA_03 M1 UPX_RDY_L M2 VDD2 M3 UPX_DATA3 M4 GND M5 UPX_DATA6 M6 VDD2 M7 NC M8 GND M9 VDD2 M10 UPX_DATA16 M11 GND M12 VDD2 M13 VDD3 M14 GND M15 UPX_DATA27 M16 VDD3 M17 GND M18 NC M19 VDD3 M20 NC M21 GND M22 LED_DATA M23 VDD3 M24 I2C_DATA_13 N1 UPX_ADD1 N2 VDD5 N3 NC Ball Location Signal Name N4 GND N5 UPX_DATA5 N6 VDD5 N7 UPX_DATA11 N8 GND N9 VDD5 N10 UPX_DATA15 N11 GND N12 VDD5 N13 VDD4 N14 GND N15 UPX_DATA26 N16 VDD4 N17 GND N18 NC N19 VDD4 N20 TXPAUSE_ADD0 N21 GND N22 MOD_DEF_INT N23 VDD4 N24 I2C_DATA_23 P1 UPX_ADD2 P2 NC P3 UPX_ADD0 P4 NC P5 UPX_DATA8 P6 NC P7 NC P8 NC P9 VDD P10 GND P11 VDD P12 GND P13 GND P14 VDD P15 GND P16 VDD P17 NC Ball Location Signal Name

Datasheet 33 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 P18 NC P19 RX_LOS_INT3 P20 TXPAUSE_ADD1 P21 TXPAUSE_ADD2 P22 RX_P_03 P23 TX_FAULT_INT3 P24 I2C_DATA_33 R1 UPX_ADD3 R2 GND R3 UPX_CS_L R4 VDD R5 NC R6 GND R7 GND R8 VDD R9 GND R10 NC R11 GND R12 NC R13 NC R14 GND R15 NC R16 GND R17 VDD R18 AVDD2P5_2 R19 GND R20 NC R21 VDD R22 RX_N_03 R23 GND R24 RX_N_23 T1 UPX_ADD4 T2 UPX_BADD0 T3 UPX_ADD10 T4 UPX_WR_L T5 UPX_WIDTH1 T6 NC T7 NC Ball Location Signal Name T8 NC T9 NC T10 GND T11 VDD T12 VDD5 T13 VDD4 T14 VDD T15 GND T16 RXD4_31 T17 RXD5_31 T18 RXD6_31 T19 RXD7_31 T20 TXPAUSEFR T21 NC T22 NC T23 AVDD1P8_2 T24 RX_P_23 U1 UPX_ADD5 U2 VDD5 U3 UPX_ADD9 U4 GND U5 NC U6 VDD5 U7 NC U8 GND U9 NC U10 VDD U11 NC U12 GND U13 GND U14 AVDD2P5_2 U15 VDD U16 UPX_WIDTH0 U17 GND U18 NC U19 VDD4 U20 RX_ER_31 U21 GND Ball Location Signal Name U22 RX_N_13 U23 VDD4 U24 RX_P_33 V1 UPX_ADD6 V2 UPX_ADD7 V3 UPX_ADD8 V4 RXC_01 V5 RX_DV_01 V6 UPX_RD_L V7 RXD1_01 V8 RXD0_01 V9 NC V10 NC V11 NC V12 TX_EN_31 V13 NC V14 TXD0_31 V15 TXD1_31 V16 TXD2_31 V17 TXD3_31 V18 RX_DV_31 V19 RXD6_21 V20 RXD5_21 V21 MDIO4 V22 RX_P_13 V23 RXC_31 V24 RX_N_33 W1 TX_ER_01 W2 GND W3 UPX_BADD1 W4 VDD W5 RX_ER_01 W6 GND W7 RXD2_01 W8 VDD5 W9 RXD3_11 W10 GND W11 RXD2_11 Ball Location Signal Name

34 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 W12 VDD5 W13 VDD4 W14 TXD7_31 W15 GND W16 TX_P_23 W17 VDD4 W18 RXD3_31 W19 GND W20 RXD7_21 W21 VDD W22 RXD4_21 W23 GND W24 MDC4 Y1 TXD0_01 Y2 TXD1_01 Y3 TXD2_01 Y4 TXD7_01 Y5 RXD5_01 Y6 RXD4_01 Y7 RXD3_01 Y8 TX_EN_11 Y9 RXD0_11 Y10 RXD7_11 Y11 RXD1_11 Y12 RX_ER_11 Y13 TX_P_03 Y14 TX_N_03 Y15 TXD5_31 Y16 TX_N_23 Y17 RXD0_31 Y18 RXD1_31 Y19 RXD2_31 Y20 RXD0_21 Y21 RXD1_21 Y22 RXD2_21 Y23 RXD3_21 Y24 RX_DV_21 AA1 TXC_01 Ball Location Signal Name AA2 VDD5 AA3 TXD3_01 AA4 GND AA5 CRS_01 AA6 VDD AA7 TXD4_11 AA8 GND AA9 CRS_11 AA10 VDD AA11 RXD6_11 AA12 GND AA13 GND AA14 TXD4_31 AA15 VDD AA16 TXD6_31 AA17 GND AA18 TXD7_21 AA19 VDD AA20 TXD6_21 AA21 GND AA22 RX_ER_21 AA23 VDD4 AA24 RXC_21 AB1 No Ball AB2 TX_EN_01 AB3 TXD4_01 AB4 TXD6_01 AB5 RXD6_01 AB6 COL_01 AB7 TXD1_11 AB8 TXD5_11 AB9 TXD2_11 AB10 COL_11 AB11 RX_DV_11 AB12 GND AB13 TX_ER_31 AB14 TXC_31 AB15 CRS_21 Ball Location Signal Name AB16 AVDD1P8_2 AB17 COL_31 AB18 NC AB19 TXD5_21 AB20 TXD0_21 AB21 TXD1_21 AB22 TXD2_21 AB23 TXD3_21 AB24 No Ball AC1 No Ball AC2 No Ball AC3 TXD5_01 AC4 VDD5 AC5 RXD7_01 AC6 GND AC7 TXD0_11 AC8 VDD5 AC9 TXD7_11 AC10 GND AC11 RXD5_11 AC12 VDD5 AC13 VDD4 AC14 GND AC15 GND AC16 CRS_31 AC17 VDD4 AC18 TX_P_33 AC19 GND AC20 TXC_21 AC21 VDD4 AC22 TX_EN_21 AC23 No Ball AC24 No Ball AD1 No Ball AD2 No Ball AD3 No Ball AD4 NC AD5 NC Ball Location Signal Name

Datasheet 35 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 AD6 TX_ER_11 AD7 TXC_11 AD8 TXD6_11 AD9 TXD3_11 AD10 RXD4_11 AD11 RXC_11 AD12 SYS_RST_L AD13 TX_P_13 AD14 TX_N_13 AD15 COL_21 AD16 TXD4_21 AD17 TX_ER_21 AD18 TX_N_33 AD19 CLK125 AD20 AVDD2P5_1 AD21 GND AD22 No Ball AD23 No Ball AD24 No Ball Ball Location Signal Name

36 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005

37 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.0 Ball Assignments and Signal Descriptions 4.1 Naming Conventions 4.1.1 Signal Name Conventions Signal names begin with a Signal Mnemonic, and can also contain one or more of the following designations: a differential pair designation, a serial designation, a port designation (RGMII interface), and an active low designation. Signal naming conventions are as follows: Differential Pair + Port Designation. The positive and negative components of differential pairs tied to a specific port are designated by the Signal Mnemonic, immediately followed by an underscore and either P (positive component) or N (negative component), and an underscore followed by the port designation. For example, SerDes interface signals for port 0 are identified as TX_P_0 and TX_N_0. Serial Designation. A set of signals that are not tied to any specific port are designated by the Signal Mnemonic, followed by a bracketed serial designation. For example, the set of 11 CPU Address Bus signals is identified as UPX_ADD[10:0]. Port Designation. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by an underscore and the Port Designation. For example, RGMII Transmit Control signals are identified as TX_CTL_0, TX_CTL_1, TX_CTL_2, and so on. Port Bus Designation. A set of bus signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by a bracketed bus designation, followed by an underscore and the port designation. For example, RGMII transmit data bus signals are identified as TD[3:0]_0, TD[3:0]_1, TD[3:0]_2, and so on. Active Low Designation. A control input or indicator output that is active Low is designated by a final suffix consisting of an underscore followed by an upper case “L”. For example, the CPU cycle complete identifier is shown as UPX_RDY_L. 4.1.2 Register Address Conventions Registers located in on-chip memory are accessed using a register address, which is provided in Hex notation. A Register Address is indicated by the dollar sign ($), followed by the memory location in Hex.

Datasheet 38 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.2 Interface Signal Groups This section describes the IXF1104 MAC signals in groups according to the associated interface or function. Figure 4 shows the various interfaces available on the IXF1104 MAC. Figure 4. Interface Signals TDAT[31:0] TFCLK TENB_0 TERR_0 TPRTY_0 TMOD[1:0] TSX TSOP_0 TEOP_0 TADR[1:0] DTPA_0:3 STPA PTPA RDAT[31:0] RFCLK RENB_0 RVAL_0 RERR_0 RPRTY_0 RMOD[1:0] RSX RSOP_0 REOP_0 TMS TDI TDO TCLK MDIO MDC TXPAUSEADD[2:0] TXPAUSEFR UPX_WIDTH[1:0] UPX_DATA[31:0] UPX_ADD[10:0] UPX_BADD[1:0] UPX_WR_L UPX_RD_L UPX_CS_L UPX_RDY_L LED_CLK LED_DATA LED_LATCH SYS_RES_L CLK125 MOD_DEF_0:3 TX_DISABLE_0:3 TX_FAULT_0:3 RX_LOS_0:3 TX_FAULT_INT RX_LOS_INT MOD_DEF_INT I2C_CLK I2C_DATA_0:3 SPI3 Interface JTAG Interface MDIO Interface Pause Control Interface CPU Interface LED Interface System Interface GMII RGMII GMII and RGMII Interfaces* * Data and clock balls are shared for GMII and RGMII Interfaces SerDes Interface Optical Module Interface Signals* * ** These optical module signals are multiplexed on the GMII balls. RX_P/N_0:3 TX_P/N_0:3 TRST_L Intel® IXF1104 Media Access Controller B3181-01 MPHY SPHY TFCLK TENB_0:3 TERR_0:3 TPRTY_0:3 TSOP_0:3 TEOP_0:3 TDAT[7:0]_0:3 TADR[1:0] DTPA_0:3 PTPA RDAT[7:0]_0:3 RFCLK RENB_0:3 RVAL_0:3 RERR_0:3 RPRTY_0:3 RSOP_0:3 REOP_0:3 TXC_0:3 TXD[7:0]_3 TXC_0:3 TD[3:0]_3 TXD[7:0]_2 TD[3:0]_2 TXD[7:0]_1 TD[3:0]_1 TXD[7:0]_0 TD[3:0]_0 TX_EN_0:3 TX_ER_0:3 TX_CTL_0:3 RXC_0:3 RXC_0:3 RXD[7:0]_3 RD[3:0]_3 RXD[7:0]_2 RD[3:0]_2 RXD[7:0]_1 RD[3:0]_1 RXD[7:0]_0 RD[3:0]_0 RX_DV_0:3 RX_ER_0:3 CRS_0:3 COL_0:3 RX_CTL_0:3

39 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.3 Signal Description Tables The I/O signals, power supplies, or ground returns associated with each IXF1104 MAC connection ball are described in Table 3 through Table 14. Table 3. SPI3 Interface Signal Descriptions (Sheet 1 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY TDAT31 TDAT30 TDAT29 TDAT28 TDAT27 TDAT26 TDAT25 TDAT24 TDAT7_3 TDAT6_3 TDAT5_3 TDAT4_3 TDAT3_3 TDAT2_3 TDAT1_3 TDAT0_3 F7 F5 G9 G8 G7 G6 G5 G4 Input 3.3 V LVTTL Transmit Data Bus. Carries payload data to the IXF1104 MAC egress path. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits [31:24] [7:0] for port 3 TDAT23 TDAT22 TDAT21 TDAT20 TDAT19 TDAT18 TDAT17 TDAT16 TDAT7_2 TDAT6_2 TDAT5_2 TDAT4_2 TDAT3_2 TDAT2_2 TDAT1_2 TDAT0_2 C8 F9 E10 E9 E8 E7 E6 E5 Input 3.3 V LVTTL Transmit Data Bus. Carries payload data to the IXF1104 MAC egress path. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits [23:16] [7:0] for port 2 TDAT15 TDAT14 TDAT13 TDAT12 TDAT11 TDAT10 TDAT9 TDAT8 TDAT7_1 TDAT6_1 TDAT5_1 TDAT4_1 TDAT3_1 TDAT2_1 TDAT1_1 TDAT0_1 H3 J3 J2 J1 H1 G2 G1 F1 Input 3.3 V LVTTL Transmit Data Bus. Carries payload data to the IXF1104 MAC egress path. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits [15:8] [7:0] for port 1 TDAT7 TDAT6 TDAT5 TDAT4 TDAT3 TDAT2 TDAT1 TDAT0 TDAT7_0 TDAT6_0 TDAT5_0 TDAT4_0 TDAT3_0 TDAT2_0 TDAT1_0 TDAT0_0 C6 B5 C5 C4 D1 C3 C2 B3 Input 3.3 V LVTTL Transmit Data Bus. Carries payload data to the IXF1104 MAC egress path. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits 7:0] [7:0] for port 0 TFCLK TFCLK D7 Input 3.3 V LVTTL Transmit Clock. TFCLK is the clock associated with all transmit signals. Data and control lines are sampled on the rising edge of TFCLK (frequency operation range 90 - 133 MHz).

Datasheet 40 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 TPRTY_0 TPRTY_0 TPRTY_1 TPRTY_2 TPRTY_3 D5 G3 B9 J6 Input 3.3 V LVTTL Transmit Parity. TPRTY indicates odd parity for the TDAT bus. TPRTY is valid only when a channel asserts either TENB or TSX. Odd parity is the default configuration; however, even parity can be selected (see Table 146 “SPI3 Transmit and Global Configuration ($0x700)” on page 213). 32-bit Multi-PHY mode: TPRTY_0 is the parity bit covering all 32 bits. 4 x 8 Single-PHY mode: TPRTY_0:3 bits correspond to the respective TDAT[3:0]_n channels. TENB_0 TENB_0 TENB_1 TENB_2 TENB_3 B7 E2 C9 J4 Input 3.3 V LVTTL Transmit Write Enable. TENB_0:3 asserted causes an attached PHY to process TDAT[n], TMOD, TSOP, TEOP and TERR signals. 32-bit Multi-PHY mode: TENB_0 is the enable bit for all 32 bits. 4 x 8 Single-PHY mode: TENB_0:3 bits correspond to the respective TDAT[3:0]_n channels and their associated control and status signals. TERR_0 TERR_0 TERR_1 TERR_2 TERR_3 A8 K1 E11 J8 Input 3.3 V LVTTL Transmit Error. TERR indicates that there is an error in the current packet. TERR is valid when simultaneously asserted with TEOP and TENB. 32-bit Multi-PHY mode: TERR_0 is the bit asserted for all 32 bits. 4 x 8 Single-PHY mode: Each bit of TERR_0:3 corresponds to the respective TDAT[3:0]_n channel. TSOP_0 TSOP_0 TSOP_1 TSOP_2 TSOP_3 C7 E3 C10 J5 Input 3.3 V LVTTL Transmit Start-of-Packet. TSOP indicates the start of a packet and is valid when asserted simultaneously with TENB. 32-bit Multi-PHY mode: TSOP_0 is the bit asserted for all 32 bits. 4 x 8 Single-PHY mode: Each bit of TSOP_0:3 corresponds to the respective TDAT[3:0]_n channel. TEOP_0 TEOP_0 TEOP_1 TEOP_2 TEOP_3 A7 F3 E4 H5 Input 3.3 V LVTTL Transmit End-of-Packet. TEOP indicates the end of a packet and is valid when asserted simultaneously with TENB. 32-bit Multi-PHY mode: TEOP_0 is the bit asserted for all 32 bits. 4 x 8 Single-PHY mode: Each bit of TEOP_0:3 corresponds to the respective TDAT[3:0]_n channel. Table 3. SPI3 Interface Signal Descriptions (Sheet 2 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY

41 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 TMOD1 TMOD0 NA D9 A6 Input 3.3 V LVTTL TMOD[1:0] Transmit Word Modulo. 32-bit Multi-PHY mode: TMOD[1:0] indicates the valid data bytes of TDAT[31:0]. During transmission, TMOD[1:0] should always be “00” until the last double word is transferred on TDAT[31:0]. TMOD[1:0] specifies the valid bytes of TDAT when TEOP is asserted: TMOD[1:0] – Valid Bytes of TDAT 00 =4 bytes [31:0] 01 =3 bytes [31:8] 10 =2 bytes [31:16] 11 = 1 byte [31:24] TENB must be asserted simultaneously for TMOD[1:0] to be valid. 4 x 8 Single-PHY mode: MOD[1:0] is not required. TSX NA E1 Input 3.3 V LVTTL Transmit Start of Transfer. 32-bit Multi-PHY mode: TSX asserted with TENB = 1 indicates that the PHY address is present on TDAT[7:0]. The valid values on TDAT[7:0] are 3, 2, 1, and 0. When TENB = 0, TSX is not used by the PHY device. NOTE: Only TDAT[1:0] are relevant; all other bits are “Don’t Care”. 4 x 8 Single-PHY mode: TSX is not used. TADR1 TADR0 TADR1 TADR0 A12 A11 Input 3.3 V LVTTL TADR[1:0] Transmit PHY Address. The value on TADR[1:0] selects one of the PHY ports that drives the PTPA signal after the rising edge of TFCLK. Table 3. SPI3 Interface Signal Descriptions (Sheet 3 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY

Datasheet 42 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 DTPA_0 DTPA_1 DTPA_2 DTPA_3 DTPA_0 DTPA_1 DTPA_2 DTPA_3 D3 L1 A9 J7 Output 3.3 V LVTTL DTPA_0:3 Direct Transmit Packet Available. A direct status indication for transmit FIFOs of ports 0:3. When High, DTPA indicates that the amount of data in the TX FIFO is below the TX FIFO High watermark. When the High watermark is crossed, DTPA transitions Low to indicate that the TX FIFO is almost full. It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low watermark. At this point, DTPA transitions High to indicate that the programmed number of bytes are now available for data transfers. NOTE: For more information, see Table 132 “TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603)” on page 203 and Table 133 “TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)” on page 204. DTPA is updated on the rising edge of TFCLK. STPA NA C11 Output 3.3 V LVTTL Selected-PHY Transmit Packet Available. STPA is only meaningful in a 32-bit multi- PHY mode. STPA is a direct status indication for transmit FIFOs of ports 0:3. When High, STPA indicates that the amount of data in the TX FIFO, specified by the latest in-band address, is below the TX FIFO High watermark. When the High watermark is crossed, STPA transitions Low to indicate the TX FIFO is almost full. It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low watermark. At this point, STPA transitions High to indicate that the programmed number of bytes are now available for data transfers. NOTE: For more information, see Table 132 “TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603)” on page 203 and Table 133 “TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)” on page 204. STPA provides the status indication for the selected port to avoid FIFO overflows while polling is performed. The port reported by STPA is updated on the following rising edge of TFCLK after TSX is sampled as asserted. STPA is updated on the rising edge of TFCLK. Table 3. SPI3 Interface Signal Descriptions (Sheet 4 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY

43 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 PTPA PTPA B11 Output 3.3 V LVTTL Polled-PHY Transmit Packet Available. PTPA allows the polling of the port selected by the TADR address bus. When High, PTPA indicates that the amount of data in the TX FIFO is below the TX FIFO High watermark. When the High watermark is crossed, PTPA transitions Low to indicate that the TX FIFO is almost full. It stays Low until the amount data in the TX FIFO goes back below the TX FIFO Low watermark. At this point, PTPA transitions High to indicate that the programmed number of bytes are now available for data transfers. NOTE: For more information, see Table 132 “TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603)” on page 203 and Table 133 “TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)” on page 204. The port reported by PTPA is updated on the following rising edge of TFCLK after the port address on TADR is sampled by the PHY device. PTPA is updated on the rising edge of TFCLK. RDAT31 RDAT30 RDAT29 RDAT28 RDAT27 RDAT26 RDAT25 RDAT24 RDAT7_3 RDAT6_3 RDAT5_3 RDAT4_3 RDAT3_3 RDAT2_3 RDAT1_3 RDAT0_3 F24 G24 G23 G22 G21 G20 G19 G18 Output 3.3 V LVTTL Receive Data Bus. RDAT carries payload data and in-band addresses from the IXF1104 MAC. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits [31:24] [7:0] for port 3 RDAT23 RDAT22 RDAT21 RDAT20 RDAT19 RDAT18 RDAT17 RDAT16 RDAT7_2 RDAT6_2 RDAT5_2 RDAT4_2 RDAT3_2 RDAT2_2 RDAT1_2 RDAT0_2 E21 E22 D22 C22 C21 C20 B22 B20 Output 3.3 V LVTTL Receive Data Bus. RDAT carries payload data and in-band addresses from the IXF1104 MAC. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits [23:16] [7:0] for port 2 RDAT15 RDAT14 RDAT13 RDAT12 RDAT11 RDAT10 RDAT9 RDAT8 RDAT7_1 RDAT6_1 RDAT5_1 RDAT4_1 RDAT3_1 RDAT2_1 RDAT1_1 RDAT0_1 F18 E18 E17 F16 E16 D16 C17 A17 Output 3.3 V LVTTL Receive Data Bus. RDAT carries payload data and in-band addresses from the IXF1104 MAC. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits [15:8] [7:0] for port 1 Table 3. SPI3 Interface Signal Descriptions (Sheet 5 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY

Datasheet 44 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 RDAT7 RDAT6 RDAT5 RDAT4 RDAT3 RDAT2 RDAT1 RDAT0 RDAT7_0 RDAT6_0 RDAT5_0 RDAT4_0 RDAT3_0 RDAT2_0 RDAT1_0 RDAT0_0 F14 E14 D14 C13 C14 B14 A14 A15 Output 3.3 V LVTTL Receive Data Bus. RDAT carries payload data and in-band addresses from the IXF1104 MAC. Mode 32-bit Multi-PHY 4 x 8 Single-PHY Bits [7:0] [7:0] for port 0 RFCLK RFCLK A19 Input 3.3 V LVTTL Receive Clock. RFCLK is the clock associated with all receive signals. Data and controls are driven on the rising edge of RFCLK (frequency operation range 90 - 133 MHz). RPRTY_0 RPRTY_0 RPRTY_1 RPRTY_2 RPRTY_3 E15 G16 E20 F20 Output 3.3 V LVTTL Receive Parity. RPRTY indicates odd parity for the RDAT bus. RPRTY is valid only when a channel asserts RENB or RSX. Odd parity is the default configuration; however, even parity can be selected (see Table 147 on page 215). 32-bit Multi-PHY mode: RPRTY_0 is the parity bit for all 32 bits. 4 x 8 Single-PHY mode: Each bit of RPRTY_0:3 corresponds to the respective RDAT[3:0]_n channel. RENB_0 RENB_0 RENB_1 RENB_2 RENB_3 A13 A18 C19 E24 Input 3.3 V LVTTL Receive Read Enable. The RENB signal controls the flow of data from the receive FIFOs. During data transfer, RVAL must be monitored as it indicates if the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR, and RSX are valid. The system may de-assert RENB at any time if it is unable to accept data from the IXF1104 MAC. When RENB is sampled Low, a read is performed from the receive FIFO and the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals are updated on the following rising edge of RFCLK. When RENB is sampled High by the PHY device, a read is not performed, and the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX, and RVAL signals remain unchanged on the following rising edge of RFCLK. 32-bit Multi-PHY Mode: RENB_0 covers all receive bits. 4 x 8 Single-PHY Mode: The RENB_0:3 bits correspond to the per-port data and control signals. Table 3. SPI3 Interface Signal Descriptions (Sheet 6 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY

45 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 RERR_0 RERR_0 RERR_1 RERR_2 RERR_3 A16 G17 D20 H20 Output 3.3 V LVTTL Receive Error. RERR indicates that the current packet is in error. RERR is only asserted when REOP is asserted. Conditions that can cause RERR to be set include FIFO overflow, CRC error, code error, and runt or giant packets. NOTE: RERR can only be set for these conditions if bit 0 in the “SPI3 Receive Configuration ($0x701)” is set to 1. RERR is considered valid only when RVAL is asserted. 32-bit Multi-PHY mode: RERR_0 covers all 32 bits. 4 x 8 Single-PHY mode: The RERR_0:3 bits correspond to the RDAT[7:0]_n channels. (n = 0, 1, 2, or 3) RVAL_0 RVAL_0 RVAL_1 RVAL_2 RVAL_3 C15 B18 E19 F22 Output 3.3 V LVTTL Receive Data Valid. RVAL indicates the validity of the receive data signals. RVAL is Low between transfers and assertion of RSX. It is also Low when the IXF1104 MAC pauses a transfer due to an empty receive FIFO. When a transfer is paused by holding RENB High, RVAL holds its value unchanged, although no new data is present on RDAT[31:0] until the transfer resumes. When RVAL is High, the RDAT[31:0], RMOD[1:0], RSOP, REOP, and RERR signals are valid. When RVAL is Low, the RDAT[31:0], RMOD[1:0], RSOP, REOP, and RERR signals are invalid and must be disregarded. The RSX signal is valid only when RVAL is Low. 32-bit Multi-PHY mode: RVAL_0 covers all receive bits. 4 x 8 Single-PHY mode: The RVAL_0:3 bits correspond to the per-port data and control signals. RSOP_0 RSOP_0 RSOP_1 RSOP_2 RSOP_3 B16 C18 E23 J18 Output 3.3 V LVTTL Receive Start of Packet. RSOP indicates the start of a packet when asserted with RVAL. 32-bit Multi-PHY mode: RSOP_0 covers all 32 bits. 4 x 8 Single-PHY mode: The RSOP_0:3 bits correspond to the RDAT[7:0]_n channels. Table 3. SPI3 Interface Signal Descriptions (Sheet 7 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY

Datasheet 46 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 REOP_0 REOP_0 REOP_1 REOP_2 REOP_3 C16 D18 C23 J19 Output 3.3 V LVTTL Receive End of Packet. REOP indicates the end of a packet when asserted with RVAL. 32-bit Multi-PHY mode: REOP_0 covers all 32 bits. 4 x 8 Single-PHY mode: The REOP_0:3 bits correspond to the RDAT[7:0]_n channels. RMOD1 RMOD0 NA G13 G14 Output 3.3 V LVTTL Receive Word Modulo: 32-bit Multi-PHY mode: RMOD[1:0] indicates the valid bytes of data in RDAT[31:0]. During transmission, RMOD is always “00”, except when the last double- word is transferred on RDAT[31:0]. RMOD[1:0] specifies the valid packet data bytes on RDAT[31:0] when REOP is asserted. RMOD[1:0] Valid Bytes of RDAT 00 = 4 bytes [31:0] 01 = 3 bytes [31:8] 10 = 2 bytes [31:16] 11 = 1 byte [31:24] 4 x 8 Single-PHY mode: RMOD[1:0] is not required. RMOD is considered valid only when RVAL is simultaneously asserted. RENB must be asserted for RMOD[1:0] to be valid. RSX NA E13 Output 3.3 V LVTTL Receive Start of Transfer. 32-bit Multi-PHY mode: RSX indicates when the in-band port address is present on the RDAT bus. When RSX is High and RVAL = 0, the value of RDAT[7:0] is the address of the receive FIFO to be selected. Subsequent data transfers on RDAT are from the FIFO specified by this in-band address. Values of 0, 1, 2, and 3 select the corresponding port. RSX is ignored when RVAL is de-asserted. 4 x 8 Single-PHY mode: RSX is ignored. Table 3. SPI3 Interface Signal Descriptions (Sheet 8 of 8) Signal Name Ball Designator Type Standard Description MPHY SPHY

47 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 4. SerDes Interface Signal Descriptions Signal Name Ball Designator Type Standard Description TX_P_0 TX_P_1 TX_P_2 TX_P_3 Y13 AD13 W16 AC18 Output SerDes Transmit Differential Output, Positive. TX_N_0 TX_N_1 TX_N_2 TX_N_3 Y14 AD14 Y16 AD18 Output SerDes Transmit Differential Output, Negative. RX_P_0 RX_P_1 RX_P_2 RX_P_3 P22 V22 T24 U24 Input SerDes Receive Differential Input, Positive.1 RX_N_0 RX_N_1 RX_N_2 RX_N_3 R22 U22 R24 V24 Input SerDes Receive Differential Input, Negative.1 1. Internally terminated differentially with 100 Ω.

Datasheet 48 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 5. GMII Interface Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator Type Standard Description TXD7_0 TXD6_0 TXD5_0 TXD4_0 TXD3_0 TXD2_0 TXD1_0 TXD0_0 TXD7_1 TXD6_1 TXD5_1 TXD4_1 TXD3_1 TXD2_1 TXD1_1 TXD0_1 TXD7_2 TXD6_2 TXD5_2 TXD4_2 TXD3_2 TXD2_2 TXD1_2 TXD0_2 TXD7_3 TXD6_3 TXD5_3 TXD4_3 TXD3_3 TXD2_3 TXD1_3 TXD0_3 Y4 AB4 AC3 AB3 AA3 Y3 Y2 Y1 AC9 AD8 AB8 AA7 AD9 AB9 AB7 AC7 AA18 AA20 AB19 AD16 AB23 AB22 AB21 AB20 W14 AA16 Y15 AA14 V17 V16 V15 V14 Output 2.5 V CMOS Transmit Data. Each bus carries eight data bits [7:0] of the transmitted data stream to the PHY device. RGMII Mode: When a port is configured in copper mode and the RGMII interface is selected, only bits TXD[3:0]_n are used. The data is transmitted on both edges of TXC_0:3. Fiber Mode: The following signals have multiplexed functions when a port is configured in fiber mode: TXD4_n: TX_DISABLE_0:3 TX_EN_0 TX_EN_1 TX_EN_2 TX_EN_3 AB2 Y8 AC22 V12 Output 2.5 V CMOS Transmit Enable. TX_EN indicates that valid data is being driven on the corresponding Transmit Data: TXD_0, TXD_1, TXD_2, and TXD_3. TX_ER_0 TX_ER_1 TX_ER_2 TX_ER_3 W1 AD6 AD17 AB13 Output 2.5 V CMOS Transmit Error: TX_ER indicates a transmit error in the corresponding Transmit Data: TXD_0, TXD_1, TXD_2, and TXD_3. TXC_0 TXC_1 TXC_2 TXC_3 AA1 AD7 AC20 AB14 Output 2.5 V CMOS Source Synchronous Transmit Clock. This clock is supplied synchronous to the transmit data bus in either RGMII or GMII mode. NOTE: Shares the same balls as RXC on the RGMII interface. NOTE: Refer to the RGMII interface for shared data and clock signals.

49 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 RXD7_0 RXD6_0 RXD5_0 RXD4_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 RXD7_1 RXD6_1 RXD5_1 RXD4_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 RXD7_2 RXD6_2 RXD5_2 RXD4_2 RXD3_2 RXD2_2 RXD1_2 RXD0_2 RXD7_3 RXD6_3 RXD5_3 RXD4_3 RXD3_3 RXD2_3 RXD1_3 RXD0_3 AC5 AB5 Y5 Y6 Y7 W7 V7 V8 Y10 AA11 AC11 AD10 W9 W11 Y11 Y9 W20 V19 V20 W22 Y23 Y22 Y21 Y20 T19 T18 T17 T16 W18 Y19 Y18 Y17 Input 2.5 V CMOS Receive Data: Each bus carries eight data bits [7:0] of the received data stream. RGMII Mode: When a port ID is configured in copper mode and the RGMII interface is selected, only bits RXD[3:0]_n are used to receive data. Fiber Mode: The following signals have multiplexed functions when a port is configured in fiber mode: RXD4_n: MOD_DEF_0:3 RXD5_n: TX_FAULT_0:3 RXD6_n: RX_LOS_0:3 RX_DV_0 RX_DV_1 RX_DV_2 RX_DV_3 V5 AB11 Y24 V18 Input 2.5 V CMOS Receive Data Valid. RX_DV indicates that valid data is being driven on Receive Data: RXD[7:0]_n. RX_ER_0 RX_ER_1 RX_ER_2 RX_ER_3 W5 Y12 AA22 U20 Input 2.5 V CMOS Receive Error. RX_ER indicates an error in Receive Data: RXD[7:0]_n. CRS_0 CRS_1 CRS_2 CRS_3 AA5 AA9 AB15 AC16 Input 2.5 V CMOS Carrier Sense. CRS indicates the PHY device has detected a carrier. RXC_0 RXC_1 RXC_2 RXC_3 V4 AD11 AA24 V23 Input 2.5 V CMOS Receiver Reference Clock. RXC operates at: 125 MHz for 1 Gigabit NOTE: Shares the same balls as RXC on the RGMII interface. Table 5. GMII Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator Type Standard Description NOTE: Refer to the RGMII interface for shared data and clock signals.

Datasheet 50 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 6. RGMII Interface Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator Type Standard Description TXC_0 TXC_1 TXC_2 TXC_3 AA1 AD7 AC20 AB14 Output 2.5 V CMOS Source Synchronous Transmit Clock. This clock is supplied synchronous to the transmit data bus in either RGMII or GMII mode. TD3_0 TD2_0 TD1_0 TD0_0 TD3_1 TD2_1 TD1_1 TD0_1 TD3_2 TD2_2 TD1_2 TD0_2 TD3_3 TD2_3 TD1_3 TD0_3 AA3 Y3 Y2 Y1 AD9 AB9 AB7 AC7 AB23 AB22 AB21 AB20 V17 V16 V15 V14 Output 2.5 V CMOS Transmit Data. Bits [3:0] are clocked on the rising edge of TXC. Bits [7:4] are clocked on the falling edge of TXC. NOTE: Shares data signals TXD[3:0]_n with the GMII interface. TX_CTL_0 TX_CTL_1 TX_CTL_2 TX_CTL_3 AB2 Y8 AC22 V12 Output 2.5 V CMOS Transmit Control. TX_CTL is TX_EN on the rising edge of TXC and a logical derivative of TX_EN and TX_ER on the falling edge of TXC. NOTE: TX_CTL multiplexes with TX_EN_n on the GMII interface. RXC_0 RXC_1 RXC_2 RXC_3 V4 AD11 AA24 V23 Input 2.5 V CMOS Receiver Reference Clock. Operates at: 125 MHz for 1 Gigabit 25 MHz for 100 Mbps 2.5 MHz for 10 Mbps NOTE: Shares the same balls as RXC on the GMII interface.

51 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 RD3_0 RD2_0 RD1_0 RD0_0 RD3_1 RD2_1 RD1_1 RD0_1 RD3_2 RD2_2 RD1_2 RD0_2 RD3_3 RD2_3 RD1_3 RD0_3 Y7 W7 V7 V8 W9 W11 Y11 Y9 Y23 Y22 Y21 Y20 W18 Y19 Y18 Y17 Input 2.5 V CMOS Receive Data. Bits [3:0] are clocked on the rising edge of RXC. Bits [7:4] are clocked on the falling edge of RXC. NOTE: Shares balls with RXD[3:0]_0 on the GMII interface. RX_CTL_0 RX_CTL_1 RX_CTL_2 RX_CTL_3 V5 AB11 Y24 V18 Input 2.5 V CMOS Receive Control. RX_CTL is RX_DV on the rising edge of RXC and a logical derivative of RX_DV and RERR on the falling edge of RXC. NOTE: RX_CTL shares the same balls as RX_DV on the GMII interface. Table 7. CPU Interface Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator Type Standard Description UPX_ADD10 UPX_ADD9 UPX_ADD8 UPX_ADD7 UPX_ADD6 UPX_ADD5 UPX_ADD4 UPX_ADD3 UPX_ADD2 UPX_ADD1 UPX_ADD0 T3 U3 V3 V2 V1 U1 T1 R1 P1 N1 P3 Input 3.3 V LVTTL UPX_ADD is the address bus from the microprocessor. UPX_BADD1 UPX_BADD0 W3 T2 Input 3.3 V LVTTL 16-bit mode: The data word select uses UPX_BADD1. 8-bit mode: UPX_BADD[1:0] selects the individual bytes. Table 6. RGMII Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator Type Standard Description

Datasheet 52 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 UPX_DATA31 UPX_DATA30 UPX_DATA29 UPX_DATA28 UPX_DATA27 UPX_DATA26 UPX_DATA25 UPX_DATA24 UPX_DATA23 UPX_DATA22 UPX_DATA21 UPX_DATA20 UPX_DATA19 UPX_DATA18 UPX_DATA17 UPX_DATA16 UPX_DATA15 UPX_DATA14 UPX_DATA13 UPX_DATA12 UPX_DATA11 UPX_DATA10 UPX_DATA9 UPX_DATA8 UPX_DATA7 UPX_DATA6 UPX_DATA5 UPX_DATA4 UPX_DATA3 UPX_DATA2 UPX_DATA1 UPX_DATA0 L17 J17 H16 J16 M15 N15 K15 H14 K13 G12 K12 G11 H11 G10 K10 M10 N10 J9 H9 L8 N7 L7 L6 P5 K5 M5 N5 L4 M3 L3 K3 L2 Input/ Output 3.3 V LVTTL Data bus. 32-bit mode: Uses [31:0] 16-bit mode: Uses [15:0] 8-bit mode: Uses [7:0] UPX_CS_L R3 Input 3.3 V LVTTL Chip Select. Active Low. UPX_WR_L T4 Input 3.3 V LVTTL Write Strobe. Active Low. UPX_RD_L V6 Input 3.3 V LVTTL Read Strobe. Active Low. UPX_RDY_L M1 Open Drain Output* 3.3 V LVTTL Cycle complete indicator. Active Low. NOTE: An external pull-up resistor is required for proper operation. NOTE: *Dual-mode I/O Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output UPX_WIDTH1 UPX_WIDTH0 T5 U16 Input 3.3 V LVTTL Data bus width select. UPX_WIDTH[1:0] specifies the CPU bus width. UPX_WIDTH[1:0] 00 01 1x Mode 8-bit 16-bit 32-bit Table 7. CPU Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator Type Standard Description

53 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 8. Transmit Pause Control Interface Signal Descriptions Signal Name Ball Designator Type Standard Description TXPAUSEADD2 TXPAUSEADD1 TXPAUSEADD0 P21 P20 N20 Input 2.5 V CMOS TXPAUSEADD[2:0] is the port selection address for pause frame insertion. TXPAUSEFR T20 Input 2.5 V CMOS TX Pause Interface Strobe. Table 9. Optical Module Interface Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator Type Standard Description TX_DISABLE_0 TX_DISABLE_1 TX_DISABLE_2 TX_DISABLE_3 AB3 AA7 AD16 AA14 Open Drain Output* 2.5 V CMOS Transmit Disable: TX_DISABLE_0:3 outputs disable the Optical Module Interface transmitter. An external pull-up resistor usually resident in an optical module is required for proper operation. NOTE: These signals are multiplexed with the TXD[4]_n bits of the GMII Interface NOTE: *Dual-mode I/O Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output MOD_DEF_0 MOD_DEF_1 MOD_DEF_2 MOD_DEF_3 Y6 AD10 W22 T16 Input 2.5 V CMOS MOD_DEF_0:3 inputs determine when an Optical Module Interface is present. NOTE: These signals are multiplexed with the RXD[4]_n bits of the GMII interface. RX_LOS_0 RX_LOS_1 RX_LOS_2 RX_LOS_3 AB5 AA11 V19 T18 Input 2.5 V CMOS RX_LOS_0:3 inputs determine when the Optical Module Interface receiver loses synchronization. NOTE: These signals are multiplexed with the RXD[6]_n bits of the GMII interface. TX_FAULT_0 TX_FAULT_1 TX_FAULT_2 TX_FAULT_3 Y5 AC11 V20 T17 Input 2.5 V CMOS TX_FAULT_0:3 inputs determine an Optical Module Interface transmitter fault. NOTE: These signals are multiplexed with the RXD[5]_n bits of the GMII Interface. RX_LOS_INT P19 Open Drain Output* 2.5 V CMOS Receiver Loss of Signal Interrupt. RX_LOS_INT is an open drain interrupt output to signal an RX_LOS condition. NOTE: An external pull-up resistor is required for proper operation. NOTE: *Dual-mode I/O Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output

Datasheet 54 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 TX_FAULT_INT P23 Open Drain Output* 2.5 V CMOS Transmitter Fault Interrupt. TX_FAULT_INT is an open drain interrupt output that signals a TX_FAULT condition. NOTE: An external pull-up resistor is required for proper operation. NOTE: *Dual-mode I/O Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output MOD_DEF_INT N22 Open Drain Output* 2.5 V CMOS Module Definition Interrupt. MOD_DEF_INT is an open drain interrupt output that signals a MOD_DEF condition. NOTE: An external pull-up resistor is required for proper operation. NOTE: *Dual-mode I/O Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output I2C_CLK L23 Output 2.5 V CMOS I2C_CLK is the clock used for the I2C bus interface. I2C DATA_0 I2C DATA_1 I2C DATA_2 I2C DATA_3 L24 M24 N24 P24 Input/ Open Drain Output* 2.5 V CMOS I2C Data Bus. I2C DATA_0:3 are the data I/Os for the I2C bus interface. NOTE: An external pull-up resistor is required for proper operation. NOTE: *Dual-mode I/O Normal operation: Input/ open drain output Boundary Scan Mode: Standard CMOS output Table 10. MDIO Interface Signal Descriptions Signal Name Ball Designator Type Standard Description MDIO V21 Input/ Output 2.5 V CMOS MDIO is the management data input and output. NOTE: An external pull-up resistor is required for proper operation. MDC W24 Output 2.5 V CMOS MDC is the management clock to external devices. Table 9. Optical Module Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator Type Standard Description

55 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 11. LED Interface Signal Descriptions Signal Name Ball Designator Type Standard Description LED_CLK K24 Output 2.5 V CMOS LED_CLK is the clock output for the LED block. LED_DATA M22 Output 2.5 V CMOS LED_DATA is the data output for the LED block. LED_LATCH L22 Output 2.5 V CMOS LED_LATCH is the latch enable for the LED block. Table 12. JTAG Interface Signal Descriptions Signal Name Ball Designator Type Standard Description TCLK J22 Input 3.3 V LVTTL JTAG Test Clock TMS H22 Input 3.3 V LVTTL Test Mode Select TDI J24 Input 3.3 V LVTTL Test Data Input TDO H24 Output 3.3 V LVTTL Test Data Output TRST_L J23 Input 3.3 V LVTTL Test Reset; reset input for JTAG test Table 13. System Interface Signal Descriptions Signal Name Ball Designator Type Standard Description CLK125 AD19 Input 2.5 V CMOS CLK125 is the input clock to PLL; 125 MHz +/- 50 ppm SYS_RES_L AD12 Input 2.5 V CMOS SYS_RES_L is the system hard reset (active Low).

Datasheet 56 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 14. Power Supply Signal Descriptions Signal Name Ball Designator Type Standard Description GND A4 B15 D12 F2 F19 H12 J10 K9 K19 L12 M4 M17 N11 P10 R2 R11 R23 U8 U21 W15 AA8 AA21 AC14 A21 B19 D13 F6 F23 H13 J15 K11 K23 L13 M8 M21 N14 P12 R6 R14 T10 U12 W2 W19 AA12 AB12 AC15 B6 D4 D17 F10 H4 H17 K2 K14 L5 L15 M11 N4 N17 P13 R7 R16 T15 U13 W6 W23 AA13 AC6 AC19 B10 D8 D21 F15 H8 H21 K6 K16 L10 L20 M14 N8 N21 P15 R9 R19 U4 U17 W10 AA4 AA17 AC10 AD21 Input – Digital ground AVDD1P8_1 A5 A20 Input 1.8 V Analog 1.8 V supply AVDD1P8_2 AB16 T23 Input 1.8 V Analog 1.8 V supply AVDD2P5_1 AD20 Input 2.5 V Analog 2.5 V supply AVDD2P5_2 U14 R18 Input 2.5 V Analog 2.5 V supply VDD A10 D11 F21 J14 K17 L14 P14 R17 U10 AA6 C12 D15 H10 J20 K21 L16 P16 R21 U15 AA10 D6 D19 H15 K4 L9 P9 R4 T11 W4 AA15 D10 F4 J11 K8 L11 P11 R8 T14 W21 AA19 Input 1.8 V Digital 1.8 V supply VDD2 B4 F8 J12 M12 B8 F12 M2 B12 H2 M6 D2 H6 M9 Input 3.3 V Digital 3.3 V supply VDD3 B13 F13 J13 M23 B17 F17 M13 B21 H19 M16 D23 H23 M19 Input 3.3 V Digital 3.3 V supply VDD4 N13 T13 W17 AC21 N16 U19 AA23 N19 U23 AC13 N23 W13 AC17 Input 2.5 V Digital 2.5 V supply VDD5 N2 T12 W12 AC12 N6 U2 AA2 N9 U6 AC4 N12 W8 AC8 Input 2.5 V Digital 2.5 V supply

57 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.4 Ball Usage Summary Table 15. Ball Usage Summary Type Quantity Inputs 158 Outputs 126 Bi-directional 37 Total Signals 321 Power 75 Ground 82 No Connects 74 Total 552

Datasheet 58 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.5 Multiplexed Ball Connections 4.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections Table 16 lists the balls used for the line-side interfaces (GMII, RGMII, SerDes/OMI) and provides a guide to connect these balls. Some of these balls are multiplexed depending on the mode of operation selected for that port. Note: Do not connect any balls marked as unused (NC). Table 16. Line Side Interface Multiplexed Balls (Sheet 1 of 2) Copper Mode Fiber Mode Unused Port Ball Designator GMII Signal RGMII Signal Optical Module/ SerDes Signal TXC_0:3 TXC_0:3 NC NC AA1 AD7 AC20 AB14 TXD[3:0]_0 TXD[3:0]_1 TXD[3:0]_2 TXD[3:0]_3 TD[3:0]_0 TD[3:0]_1 TD[3:0]_2 TD[3:0]_3 NC NC AA3 AD9 AB23 V17 Y3 AB9 AB22 V16 Y2 AB7 AB21 V15 Y1 AC7 AB20 V14 TXD4_0:3 NC TX_DISABLE_0:32 NC AB3 AA7 AD16 AA14 TXD[7:5]_0 TXD[7:5]_1 TXD[7:5]_2 TXD[7:5]_3 NC NC NC Y4 AC9 AA18 W14 AB4 AD8 AA20 AA16 AC3 AB8 AB19 Y15 TX_EN_0:3 TX_CTL_0:3 NC NC AB2 Y8 AC22 V12 TX_ER_0:3 NC NC NC W1 AD6 AD17 AB13 RXC_0:3 RXC_0:3 GND GND V4 AD11 AA24 V23 RXD[3:0]_0 RXD[3:0]_1 RXD[3:0]_2 RXD[3:0]_3 RD[3:0]_0 RD[3:0]_1 RD[3:0]_2 RD[3:0]_3 GND GND Y7 W9 Y23 W18 W7 W11 Y22 Y19 V7 Y11 Y21 Y18 V8 Y9 Y20 Y17 RXD4_0:3 GND MOD_DEF_0:31 GND Y6 AD10 W22 T16 RXD5_0:3 GND TX_FAULT_0:31 GND Y5 AC11 V20 T17 RXD6_0:3 GND RX_LOS_0:31 GND AB5 AA11 V19 T18 RXD7_0:3 GND GND GND AC5 Y10 W20 T19 RX_DV_0:3 RX_CTL_0:3 GND GND V5 AB11 Y24 V18 RX_ER_0:3 GND GND GND W5 Y12 AA22 U20 CRS_0:3 GND GND GND AA5 AA9 AB15 AC16 COL_0:3 GND GND GND AB6 AB10 AD15 AB17 GND GND RX_P_0:3 GND P22 V22 T24 U24 GND GND RX_N_0:3 GND R22 U22 R24 V24 NC NC TX_P_0:3 NC Y13 AD13 W16 AC18 NC NC TX_N_0:3 NC Y14 AD14 Y16 AD18 1. An external pull-up resistor is required with most optical modules. 2. An open drain I/O, external 4.7 k Ω pull-up resistor is required.

59 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.5.2 SPI3 MPHY/SPHY Ball Connections Table 17 lists the balls used for the SPI3 Interface and provides a guide to connect these balls in MPHY and SPHY mode. NC NC TX_FAULT_INT2 NC P23 NC NC RX_LOS_INT2 NC P19 NC NC MOD_DEF_INT2 NC N22 MDC MDC NC NC W24 MDIO2 MDIO2 NC NC V21 NC NC I2C_CLK NC L23 NC NC I2C_DATA_0:32 NC L24 M24 N24 P24 Table 16. Line Side Interface Multiplexed Balls (Sheet 2 of 2) Copper Mode Fiber Mode Unused Port Ball Designator GMII Signal RGMII Signal Optical Module/ SerDes Signal 1. An external pull-up resistor is required with most optical modules. 2. An open drain I/O, external 4.7 k Ω pull-up resistor is required. Table 17. SPI3 MPHY/SPHY Interface (Sheet 1 of 3) SPI3 Signals Ball Number Comments MPHY SPHY TDAT[31:24] TDAT[7:0]_3 F7 G7 F5 G6 G9 G5 G8 G4 MPHY: Consists of a single 32-bit data bus SPHY: Separate 8-bit data bus for each Ethernet port TDAT[23:16] TDAT[7:0]_2 C8 E8 F9 E7 E10 E6 E9 E5 TDAT[15:8] TDAT[7:0]_1 H3 H1 J3 G2 J2 G1 J1 F1 TDAT[7:0] TDAT[7:0]_0 C6 D1 B5 C3 C5 C2 C4 B3 TFCLK TFCLK D7 To achieve maximum bandwidth, set TFCLK as follows: MPHY: 133 MHz SPHY: 125 MHz. TPRTY_0 TPRTY_0 D5 MPHY: Use TPRTY_0 as the TPRTY signal. SPHY: Each port has its own dedicated TPRTY_n signal. GND TPRTY_1 G3 GND TPRTY_2 B9 GND TPRTY_3 J6 TENB_0 TENB_0 B7 MPHY: Use TENB_0 as the TENB signal. SPHY: Each port has its own dedicated TENB_n signal. VDD2 TENB_1 E2 VDD2 TENB_2 C9 VDD2 TENB_3 J4

Datasheet 60 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 TERR_0 TERR_0 A8 MPHY: Use TERR_0 as the TERR signal. SPHY: Each port has its own dedicated TERR_n signal GND TERR_1 K1 GND TERR_2 E11 GND TERR_3 J8 TSOP_0 TSOP_0 C7 MPHY: Use TSOP_0 as the TSOP signal. SPHY: Each port has a dedicated TSOP_n signal. GND TSOP_1 E3 GND TSOP_2 C10 GND TSOP_3 J5 TEOP_0 TEOP_0 A7 MPHY: Use TEOP_0 as the TEOP signal. SPHY: Each port has a dedicated TEOP_n signal. GND TEOP_1 F3 GND TEOP_2 E4 GND TEOP_3 H5 TMOD[1:0] GND D9 A6 TSX and TMOD[1:0] are only applicable in MPHY mode. TSX GND E1 TADR[1:0] TADR[1:0] A12 A11 Used to address port for PTPA signal. PTPA PTPA B11 PTPA can be used in MPHY and SPHY modes. DTPA_0:3 DTPA_0:3 D3 L1 A9 J7 DTPA is available on a per-port basis in both MPHY and SPHY modes. STPA NC C11 STPA is only applicable in MPHY mode. RDAT[31:24] RDAT[7:0]_3 F24 G21 G24 G20 G23 G19 G22 G18 MPHY: Consists of a single 32 bit data bus. SPHY: Separate 8-bit data bus for each Ethernet port. RDAT[23:16] RDAT[7:0]_2 E21 C21 E22 C20 D22 B22 C22 B20 RDAT[15:8] RDAT[7:0]_1 F18 E16 E18 D16 E17 C17 F16 A17 RDAT[7:0] RDAT[7:0]_0 F14 C14 E14 B14 D14 A15 C13 A14, RFCLK RFCLK A19 To achieve maximum bandwidth, set RFCLK as follows: MPHY: 133 MHz. SPHY: 125 MHz. RPRTY_0 RPRTY_0 E15 MPHY: Use RPRTY_0 as the RPRTY signal. SPHY: Each port has a dedicated RPRTY_n signal. NC RPRTY_1 G16 NC RPRTY_2 E20 NC RPRTY_3 F20 RENB_0 RENB_0 A13 MPHY: Use RENB_0 as the RENB signal. SPHY: Each port has a dedicated RENB_n signal VDD2 RENB_1 A18 VDD2 RENB_2 C19 VDD2 RENB_3 E24 Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3) SPI3 Signals Ball Number Comments MPHY SPHY

61 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.6 Ball State During Reset RERR_0 RERR_0 A16 MPHY: Use RERR_0 as the RERR signal. SPHY: Each port has a dedicated RERR_n signal NC RERR_1 G17 NC RERR_2 D20 NC RERR_3 H20 RVAL_0 RVAL_0 C15 MPHY: Use RVAL_0 as the RVAL signal. SPHY: Each port has a dedicated RVAL_n signal. NC RVAL_1 B18 NC RVAL_2 E19 NC RVAL_3 F22 RSOP_0 RSOP_0 B16 MPHY: Use TSOP_0 as the TSOP signal. SPHY: Each port has a dedicated TSOP_n signal. NC RSOP_1 C18 NC RSOP_2 E23 NC RSOP_3 J18 REOP_0 REOP_0 C16 MPHY: Use TEOP_0 as the TEOP signal. SPHY: Each port has a dedicated TEOP_n signal. NC REOP_1 D18 NC REOP_2 C23 NC REOP_3 J19 RMOD[1:0] NC G13 G14 RSX and RMOD[1:0] are applicable only in MPHY mode. RSX NC E13 Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 1 of 2) Interface Ball Name Ball Reset State Comment SPI3 DTPA_0:3 0x0 – STPA 0x0 – PTPA 0x0 – RDAT[31:0] 0x00000000 – RVAL_0:3 0x0 – RERR_0:3 0x0 – RPRTY_0:3 0x0 – RMOD[1:0] 0x0 – RSX 0x0 – RSOP_0:3 0x0 – REOP_0:3 0x0 – NOTE: Z = High impedance. Table 17. SPI3 MPHY/SPHY Interface (Sheet 3 of 3) SPI3 Signals Ball Number Comments MPHY SPHY

Datasheet 62 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 JTAG TDO 0x0 – MDIO MDIO High Z Bi-directional MDC 0x0 – CPU UPX_DATA[31:0] High Z Bi-directional UPX_RDY_L 0X1 Open-drain output, requires an external pull-up LED LED_CLK 0x0 – LED_DATA 0x0 – LED_LATCH 0x0 – GMII/RGMII TXC_0:3 High Z Fiber mode is the default. Copper interfaces are disabled. TXD[7:0]_0 High Z Fiber mode is the default. Bit 4 is driven by the optical module as MOD_DEF_0. TXD[7:0]_1 High Z Fiber mode is the default. Bit 4 is driven by the optical module as MOD_DEF_1. TXD[7:0]_2 High Z Fiber mode is the default. Bit 4 is driven by the optical module as MOD_DEF_2. TXD[7:0]_3 High Z Fiber mode is the default. Bit 4 is driven by the optical module as MOD_DEF_3. TX_EN_0:3 High Z Fiber mode is the default. Copper interfaces are disabled. TX_ER_0:3 High Z Fiber mode is the default. Copper interfaces are disabled. RGMII TX_CTL_0:3 High Z Fiber mode is the default. Copper interfaces are disabled. SerDes TX_P_0:3 0x0 – TX_N_0:3 0x0 – Optical Module TX_FAULT_INT High Z Open-drain output, requires external pull-up. RX_LOS_INT High Z Open-drain output, requires external pull-up. MOD_DEF_INT High Z Open-drain output, requires external pull-up. I2C_CLK 0x1 – I2C_DATA_0:3 0xF Open-drain output, requires external pull-up. Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 2 of 2) Interface Ball Name Ball Reset State Comment NOTE: Z = High impedance.

63 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.7 Power Supply Sequencing Follow the power-up and power-down sequences described in this section to ensure correct IXF1104 MAC operation. The sequence described in Section 4.7 covers all IXF1104 MAC digital and analog supplies. Caution: Failure to follow the sequence described in this section might damage the IXF1104 MAC. 4.7.1 Power-Up Sequence Ensure that the 1.8 V analog and digital supplies are applied and stable prior to application of the 2.5 V analog and digital supplies. 4.7.2 Power-Down Sequence Remove the 2.5 V supplies prior to removing the 1.8 V power supplies (the reverse of the power-up sequence). Caution: Damage can occur to the ESD structures within the analog I/Os if the 2.5 V digital and analog supplies exceed the 1.8 V digital and analog supplies by more than 2.0 V during power-up or power-down. Figure 5 and Table 19 provide the IXF1104 MAC power supply sequencing. Figure 5. Power Supply Sequencing Time t=0 1.8 V Supplies Stable 2.5 V Supplies Stable Sys_Res Apply VDD, AVDD1P8_1, and AVDD1P8_2 Apply VDD4, VDD5, AVDD2P5_1 and AVDD2P5_2 NOTE: The 3.3 V supply (VDD2 and VDD3) can be applied at any point during this sequence.

Datasheet 64 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 4.8 Pull-Up/Pull-Down Ball Guidelines The signals shown in Table 20 require the addition of a pull-up or pull-down resistor to the board design for normal operation. Any balls marked as unused (NC) should be unconnected. 4.9 Analog Power Filtering Figure 21 illustrates an analog power supply filter network and Table 21 lists the analog power balls. Table 19. Power Supply Sequencing Power Supply Power-Up Order Time Delta to Next Supply1 Notes VDD, AVDD1P8_1, AVDD1P8_2 First 0 1.8 V supplies VDD4, VDD5, AVDD2P5_1, AVDD2P5_2 Second 10 µs 2.5 V supplies 1. The value of 10 µs given is a nominal value only. The exact time difference between the application of the 2.5 V analog supply is determined by a number of factors, depending on the power management method used. NOTE: To avoid damage to the IXF1104 MAC, the TXAV25 supply must not exceed the VDD supply by more than 2 V at any time during the power-up or power-down sequence. NOTE: The 3.3 V supply (VDD2 and VDD3) can be applied at any point during this sequence. Table 20. Pull-Up/Pull-Down and Unused Ball Guidelines Pin Name Pull-Up/Pull-Down Comments TX_FAULT_INT Pull-up 4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O. RX_LOS_INT Pull-up 4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O. MOD_DEF_INT Pull-up 4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O. TDI Pull-up 10 k Ω to 3.3 V. JTAG test pin. TDO Pull-up 10 k Ω to 3.3 V. JTAG test pin. TMS Pull-up 10 k Ω to 3.3 V. JTAG test pin. TCLK Pull-up 10 k Ω to 3.3 V. JTAG test pin. TRST_L Pull-down 10 k Ω to 3.3 V. JTAG test pin. MDIO Pull-up 4.7 k Ω to 2.5 V UPX_RDY_L Pull-up 4.7 k Ω to 3.3 V I2C_DATA_0:3 Pull-up 4.7 k Ω to 2.5 V TX_DISABLE_0:3 Pull-up 4.7 k Ω to 2.5 V

65 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Figure 6. Analog Power Supply Filter Network Table 21. Analog Power Balls Signal Name Ball Designator Comments AVDD1P8_1 A5 A20 Need to provide a filter (see Figure 6). R: AVDD1P8_1 and AVDD2P5_1 = 5.6 Ω resistor. AVDD2P5_1 AD20 AVDD1P8_2 AB16 T23 Need to provide a filter (see Figure 6). R: AVDD1P8_2 and AVDD2P5_2 = 1.0 Ω resistor. AVDD2P5_2 U14 R18

Datasheet 66 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.0 Functional Descriptions 5.1 Media Access Controller (MAC) The IXF1104 MAC main functional block consists of four independent 10/100/1000 Mbps Ethernet MACs, which support interfaces for fiber and copper connectivity. • Copper Mode: — RGMII for 10/100/1000 Mbps full-duplex operation and 10/100 Mbps half-duplex operation — GMII for 1000 Mbps full-duplex operation • Fiber Mode: — Integrated SerDes/OMI interface for direct connection to optical modules — 1000 Mbps full-duplex operation in fiber mode The following features support copper and fiber modes: • Programmable Options: — Automatic padding of transmitted packets that are less than the minimum frame size — Broadcast, multicast, and unicast address filtering on frames received — Filter and drop packets with errors — Pre-padded RX frames with two bytes (aligns the Ethernet payload on SPI3 and in network processor memories) — Remove CRC from RX frames — Append CRC to transmitted frames • Performance Monitoring and Diagnostics: — Loopback modes — Detection of runt and overly large packets — Cyclic Redundancy Check (CRC) calculation and error detection — RMON statistics for dropped packets, packets with errors, etc. • Compliant with IEEE Spec 802.3x standard for flow control — Receive and execute PAUSE Command Frames • Support for non-standard packet sizes up to 10 KB including loss-less flow control Note: The IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode. The IXF1104 MAC is fully integrated, designed for use with Ethernet 802.3 frame types, and compliant to all of the IEEE 802.3 MAC requirements. The IXF1104 MAC adds preamble and Start-of-Frame Delimiter (SFD) to all frames sent to it (transmit path) and removes preamble and SFD on all frames received by it (receive path). A CRC check is also applied to all transmit and receive packets. CRC is optionally appended to transmit

67 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 packets. CRC is removed optionally from receive packets after validation, and is not forwarded to SPI3. Packets with a bad CRC are marked, counted in the statistics block, and may be optionally dropped. A bad packet may be signaled with RERR on the SPI3 interface if it is not dropped. The IXF1104 MAC operates only in full-duplex mode at 1000 Mbps rates on both SerDes and GMII interface connections. The IXF1104 MAC is capable of operation at 1000 Mbps, full-duplex in RGMII mode, and at full-duplex and half-duplex operation for 10/100 Mbps links. 5.1.1 Features for Fiber and Copper Mode Section 5.1.1.1 through Section 5.1.1.4 cover IXF1104 MAC functions that are independent of the line-side interface. 5.1.1.1 Padding of Undersized Frames on Transmit The padding feature allows Ethernet frames smaller than 64 bytes to be transferred from the SPI3 interface to the TX MAC and padded up to 64 bytes automatically by the MAC. This feature is enabled by setting bit 7 of the “Diverse Config Write ($ Port_Index + 0x18)". Note: When the user selects the padding function, the MAC core adds an automatically calculated CRC to the end of the transmitted packet. 5.1.1.2 Automatic CRC Generation Automatic CRC Generation is used in conjunction with the padding feature to generate and append a correct CRC to any transmit frame. This feature is enabled by setting bit 6 of the “Diverse Config Write ($ Port_Index + 0x18)". 5.1.1.3 Filtering of Receive Packets This feature allows the IXF1104 MAC to filter receive packets under various conditions and drop the packets through an interaction with the Receive FIFO control. 5.1.1.3.1 Filter on Unicast Packet Match This feature is enabled when bit 0 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. Any frame received in this mode that does not match the Station Address (MAC address) is marked by the IXF1104 MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 215). When bit 0 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all unicast frames are sent out the SPI3 interface. Note: The VLAN filter overrides the unicast filter. Therefore, a VLAN frame cannot be filtered based on the unicast address.

Datasheet 68 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.1.1.3.2 Filter on Multicast Packet Match This feature is enabled when bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. Any frame received in this mode that does not match the Port Multicast Address (reserved multicast address recognized by IXF1104 MAC) is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 215). When bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all multicast frames are sent out the SPI3 interface. 5.1.1.3.3 Filter Broadcast Packets This feature is enabled when bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. Any broadcast frame received in this mode is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 215). When bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all broadcast frames are sent out the SPI3 interface. 5.1.1.3.4 Filter VLAN Packets This feature is enabled when bit 3 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. VLAN frames received in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the VLAN frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 215). When bit 3 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all VLAN frames are sent out the SPI3 interface. 5.1.1.3.5 Filter Pause Packets This feature is enabled when bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0. Pause frames received in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the pause frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 215). When bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1, all pause frames are sent out the SPI3 interface. Note: Pause packets are not filtered if flow control is disabled in the “FC Enable ($ Port_Index + 0x12)”. 5.1.1.3.6 Filter CRC Error Packets This feature is enabled when bit 5 of the “RX Packet Filter Control ($ Port_Index + 0x19)” = 0. Frames received with an errored CRC are marked as bad frames and may optionally be dropped in the RX FIFO. Otherwise, the frames are sent to the SPI3 interface and may be optionally signaled with an RERR (see Table 22 “CRC Errored Packets Drop Enable Behavior” on page 69).

69 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 When the CRC Error Pass Filter bit = 0 (“RX Packet Filter Control ($ Port_Index + 0x19)”), it takes precedence over the other filter bits. Any packet (Pause, Unicast, Multicast or Broadcast packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0. 5.1.1.4 CRC Error Detection Frames received by the MAC are checked for a correct CRC. When an incorrect CRC is detected on a received frame, the RX FCSError RMON statistic counter is incremented for each CRC errored frame. Received frames with CRC errors may optionally be dropped in the RX FIFO (refer to Section 5.1.1.3.6, “Filter CRC Error Packets” on page 68). Otherwise, the frames are sent to the SPI3 interface and may be dropped by the switch or system controller. Frames transmitted by the MAC are also checked for correct CRC. When an incorrect CRC is detected on a transmitted frame, the TX CRCError RMON statistic counter is incremented for each incorrect frame. 5.1.2 Flow Control Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link partner take a temporary “Pause” in packet transmission. This allows the requesting network node to prevent FIFO overruns and dropped packets, by managing incoming traffic to fit its available memory. The temporary pause allows the device to process packets already received or in transit, thus freeing up the FIFO space allocated to those packets. Table 22. CRC Errored Packets Drop Enable Behavior CRC Error Pass1 RX FIFO Errored- Frame Drop Enable2 RERR Enable3 Actions 1 x x When CRC Errored PASS = 1, CRC errored packets are not filtered and are passed to the SPI3 interface. They are not marked as bad, cannot be dropped, and cannot be signaled with RERR. 0 0 1 Packets are marked as bad but not dropped in the RX FIFO. These packets are sent to the SPI3 interface, and are signaled with an RERR to the switch or Network Processor. 0 0 0 Packets are marked as bad but not dropped in the RX FIFO. These packets are sent to the SPI3 interface, and are not signaled with an RERR. 0 1 x CRC errored packets are marked as bad, dropped in the RX FIFO, and never appear at the SPI3 interface. NOTE: Packet sizes above the RX FIFO Transfer Threshold (see Table 128 through Table 131) cannot be dropped in the RX FIFO and are passed to the SPI3 interface. These packets can optionally be signaled with RERR on the SPI3 interface if the RERR Enable bit = 1. 1. See Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)” on page 172. 2. See Table 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196. 3. See Table 147 “SPI3 Receive Configuration ($0x701)” on page 215. NOTE: x = “DON’T CARE”

Datasheet 70 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 The IXF1104 MAC implements the IEEE 802.3x standard RX FIFO threshold-based Flow Control in copper and fiber modes. When appropriately programmed, the MAC can both generate and respond to IEEE standard pause frames in full-duplex operation. The IXF1104 MAC also supports externally triggered flow control through the Transmit Pause Control interface. In half-duplex operation, the MAC generates collisions instead of sending pause frames to manage the incoming traffic from the link partner 5.1.2.1 802.3x Flow Control (Full-Duplex Operation) The IEEE 802.3x standard identifies four options related to system flow control: • No Pause • Symmetric Pause (both directions) • Asymmetric Pause (Receive direction only) • Asymmetric Pause (Transmit direction only) The IXF1104 supports all four options on a per-port basis. Bits 2:0 of the “FC Enable ($ Port_Index + 0x12)” on page 168 provide programmable control for enabling or disabling flow control in each direction independently. The IEEE 802.3x flow control mechanism is accomplished within the MAC sublayer, and is based on RX FIFO thresholds called watermarks. The RX FIFO level rises and falls as packets are received and processed. When the RX FIFO reaches a watermark (either exceeding a High or dropping below a Low after exceeding a High), the IXF1104 control sublayer signals an internal state machine to transmit a PAUSE frame. The FIFOs automatically generate PAUSE frames (also called control frames) to initiate the following: • Halt the link partner when the High watermark is reached. • Restart the link partner when the data stored in the FIFO falls below the Low watermark. Figure 7 illustrates the IEEE 802.3 FIFO flow control functions.

71 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.1.2.1.1 Pause Frame Format PAUSE frames are MAC control frames that are padded to the minimum size (64 bytes). Figure 8 and Figure 9 illustrate the frame format and contents. Figure 7. Packet Buffering FIFO MDI High Watermark Data Flow MAC Transfer Threshold Low Watermark High Watermark Data Flow Low Watermark RX FIFO High TXPAUSEFR (External Strobe) 802.3x Pause Frame Generation TX FIFO TX Side MAC RX FIFO 802.3 Flow Control RX Side MAC SPI3 Interface B3231-01 Figure 8. Ethernet Frame Format                    Number of bytes Note:    !""#  $  % ! &"#

Datasheet 72 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 An IEEE 802.3 MAC PAUSE frame is identified by detecting all of the following: • OpCode of 00-01 • Length/Type field of 88-08 • DA matching the unique multicast address (01-80-C2-00-00-01) XOFF. A PAUSE frame informs the link partner to halt transmission for a specified length of time. The PauseLength octets specify the duration of the no-transmit period. If this time is greater than zero, the link partner must stop sending any further packets until this time has elapsed. This is referred to as XOFF. XON. The MAC continues to transmit PAUSE frames with the specified Pause Length as long as the FIFO level exceeds the threshold. If the FIFO level falls below the threshold before the Pause Length time expires, the MAC sends another PAUSE frame with the Pause Length time specified as zero. This is referred to as XON and informs the link partner to resume normal transmission of packets. 5.1.2.1.2 Pause Settings The MAC must send PAUSE frames repeatedly to maintain the link partner in a Pause state. The following two inter-related variables control this process: • Pause Length is the amount of time, measured in multiples of 512 bit times, that the MAC requests the link partner to halt transmission for. • Pause Threshold is the amount of time, measured in multiples of 512 bit times, prior to the expiration of the Pause Length that the MAC transmits another Pause frame to maintain the link partner in the pause state. The transmitted Pause Length in the IXF1104 MAC is set by the “FC TX Timer Value ($ Port_Index + 0x07)” on page 164. The IXF1104 PAUSE frame transmission interval is set by the “Pause Threshold ($ Port_Index + 0x0E)” on page 166. Figure 9. PAUSE Frame Format                      !  "#$%&     '(%& !   )%      *# %& *#%+ *,  &(%% - %& ., / 0 %& 1  % %&(  %&  %(%  2 3 .& 4, (#% 0 0 %& 1  '(  %&(  %&  %(% %& 1   2

73 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.1.2.1.3 Response to Received PAUSE Command Frames When Flow Control is enabled in the receive direction (bit 0 in the “FC Enable ($ Port_Index + 0x12)"), the IXF1104 responds to PAUSE Command frames received from the link partner as follows: 1. The IXF1104 checks the entire frame to verify that it is a valid PAUSE control frame addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE 802.3, Annex 31B) or has a Destinations Address matching the address programmed in the “Station Address ($ Port_Index +0x00 – +0x01)". 2. If the PAUSE frame is valid, the transmit side of the IXF1104 pauses for the required number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31. 3. PAUSE does not begin until completion of the frame currently being transmitted. The IXF1104 response to valid received PAUSE frames is independent of the PAUSE frame filter settings. Refer to Section 5.1.1.3.5, “Filter Pause Packets” on page 68 for additional details. Note: Pause packets are not filtered if flow control is disabled in bit 0 of the “FC Enable ($ Port_Index + 0x12)”. 5.1.2.1.4 Half-Duplex Operation Transmit flow control is implemented only in half-duplex operation. Upon entering the flow control state, the MAC generates a collision for all subsequent receive packets until exiting the flow control state. Any receive packet in progress when the MAC enters the flow control state will not be collided with but could be lost due if there is insufficient FIFO depth to complete packet reception. Bit 2 of the “FC Enable ($ Port_Index + 0x12)" enables the transmit flow control function. 5.1.2.1.5 Transmit Pause Control Interface The Transmit Pause Control interface allows an external device to trigger the generation of pause frames. The Transmit Pause Control interface is completely asynchronous. It consists of three address signals (TXPAUSEADD[2:0]) and a strobe signal (TXPAUSEFR). The required address for this interface operation is placed on the TXPAUSEADD[2:0] signals and the TXPAUSEFR is pulsed High and returned Low. Refer to Figure 10 “Transmit Pause Control Interface” on page 74 and Table 55 “Transmit Pause Control Interface Timing Parameters” on page 151. Table 23 shows the valid decodes for the TXPAUSEADD[2:0] signals. Figure 10 illustrates the transmit pause control interface. Note: Flow control must be enabled in the “FC Enable ($ Port_Index + 0x12)” for Transmit Pause Control interface operation. Note: There are two additional decodes provided that allow the user to generate either an XOFF frame or XON frame from all ports simultaneously. The default pause quanta for each port is held by the “FC TX Timer Value ($ Port_Index + 0x07)"). The default value of this register is 0x05E after reset is applied.

Datasheet 74 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 23. Valid Decodes for TXPAUSEADD[2:0] TXPAUSEADD_2:0 Operation of TX Pause Control Interface 0x0 Transmits a PAUSE frame on every port with a pause_time = ZERO (XON) (Cancels all previous pause commands). 0x1 Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed in the port 0 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF). 0x2 Transmits a PAUSE frame on port 1 with pause_time equal to the value programmed in the port 1 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF). 0x3 Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed in the port 2 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF). 0x4 Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed in the port 3 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF). 0x5 to 0x6 Reserved. Do not use these addresses. The TX Pause Control interface will not operate under these conditions. 0x7 Transmits a PAUSE frame on every port with pause_time equal to the value programmed in the “FC TX Timer Value ($ Port_Index + 0x07)" for each port (XOFF). Figure 10. Transmit Pause Control Interface B3234-01 TXPAUSEFR TXPAUSEADD0 TXPAUSEADD1 TXPAUSEADD2 This example shows the following conditions: Strobe 1: Port 0: Transmit Pause Packet (XOFF) Strobe 2: All Ports: Transmit Pause Packet with pause_time = 0 (XON) Strobe 3: Port 3: Transmit Pause Packet (XOFF)

75 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.1.3 Mixed-Mode Operation The IXF1104 MAC gives the user the option of configuring each port for 10/100 Mbps half-duplex copper, 10/100/1000 Mbps full-duplex copper, or 1000 Mbps full-duplex fiber operation. This gives the IXF1104 MAC the ability to support both copper and fiber operation line-side interfaces operating at the same time within a single device. (Refer to Figure 16 “Line Side Interface Multiplexed Balls” on page 58.) The IXF1104 MAC provides complete flexibility in line-side connectivity by offering RGMII, integrated SerDes, and GMII. 5.1.3.1 Configuration The memory maps (Table 59 “MAC Control Registers ($ Port Index + Offset)” on page 156 through Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” on page 162) are logically split into the following two distinct regions: • Per-Port Registers • Global Registers To achieve a desired configuration for a given port, the relevant per-port registers must be configured correctly by the user. The Table 59 through Table 69 also contain registers that affect the operation of all ports, such as the SPI3 interface configuration. See Section 8.0, “Register Set” on page 155 for a complete description of IXF1104 MAC configuration and status registers. The Register Maps (Table 59 through Table 69) present a summary of important configuration registers. Note: The initialization sequence provided in Section 6.1, “Change Port Mode Initialization Sequence” on page 130 must be followed for proper configuration of the IXF1104 MAC. 5.1.3.2 Key Configuration Registers The following key registers select the operational mode of a given port:

Datasheet 76 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.1.4 Fiber Mode When the IXF1104 MAC is configured for fiber mode, the TX Data path from the MAC is an internal 10-bit interface as described in the IEEE 802.3z specification. It is connected directly to an internal SerDes block for serialization/deserialization and transmission/reception on the fiber medium to and from the link partner. The MAC contains all of the PCS (8B/10B encoding and 10B/8B decoding) required to encode and decode the data. The MAC also supports auto-negotiation per the IEEE 802.3z specification via access to the “TX Config Word ($ Port_Index + 0x17)", “RX Config Word ($ Port_Index + 0x16)", and “Diverse Config Write ($ Port_Index + 0x18)". Table 24. Operational Mode Configuration Registers Register Name Register Address Description “Desired Duplex ($ Port_Index + 0x02)" 0x002 – Port 0 0x082 – Port 1 0x102 – Port 2 0x182 – Port 3 The “Desired Duplex ($ Port_Index + 0x02)” on page 163 defines whether a port is to be configured for full-duplex or half-duplex operation. NOTE: Half-duplex operation is only valid for 10/100 speeds where the RGMII line interface has been selected. “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" 0x010 – Port 0 0x090 – Port 1 0x110 – Port 2 0x190 – Port 3 The “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” on page 167 determines the MAC operational frequency and mode for a given port. NOTE: Set the “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” on page 221 to 0x0 prior to any change in the register value. This ensures that a change in the MAC clock frequency is controlled correctly. If the “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)" is not used correctly, the IXF1104 MAC may not be configured to the proper mode. “Port Enable ($0x500)" 0x500 Bit 0 – Port 0 Bit 1 – Port 1 Bit 2 – Port 2 Bit 3 – Port 3 Each “Port Enable ($0x500)" bit relates to a port. Set the appropriate bit to 0x1 to enable a port. This should be the last step in the configuration process for a port. “Interface Mode ($0x501)" 0x501 Bit 0 – Port 0 Bit 1 – Port 1 Bit 2 – Port 2 Bit 3 – Port 3 The “Interface Mode ($0x501)" selects whether a port operates with a copper (RGMII or GMII) line-side interface an integrated SerDes fiber line-side interface. For copper operation for a given port, set the relevant bit to 0x1. For fiber operation for a given port, set the relevant bit to 0x0. NOTE: All ports are configured for fiber operation in the IXF1104 MAC default mode of operation. “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)" 0x794 Bit 0 – Port 0 Bit 1 – Port 1 Bit 2 – Port 2 Bit 3 – Port 3 The “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)" indicates to an internal clock generator when to sample the new value of the “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" and the “Interface Mode ($0x501)" (copper/fiber). When any of these two configuration values are changed for a port, the corresponding bits must be kept in this register under reset by writing 0x0 to the relevant bit. NOTE: The initialization sequence provided in Section 6.1, “Change Port Mode Initialization Sequence” on page 130 must be followed for proper configuration of the IXF1104 MAC.

77 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 When configured for fiber mode, the full set of Optical Module interface control and status signals is presented through re-use of GMII signals on a per-port basis (see Table 4.5 “Multiplexed Ball Connections” on page 58). Fiber mode supports only full-duplex Gigabit operation. 5.1.4.1 Fiber Auto-Negotiation Auto-negotiation is performed by using the “TX Config Word ($ Port_Index + 0x17)", “RX Config Word ($ Port_Index + 0x16)", and “Diverse Config Write ($ Port_Index + 0x18)". When autoneg_enable (“Diverse Config Write ($ Port_Index + 0x18)") is set, the IXF1104 MAC performs hardware-defined auto-negotiation with the “TX Config Word ($ Port_Index + 0x17)" used as an “Auto-Negotiation Advertisement ($ Port Index + 0x64)" and the “RX Config Word ($ Port_Index + 0x16)" used as an “Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)". Note: While the MAC supports auto-negotiation functions, the IXF1104 MAC does not automatically configure the MAC or other device blocks to be consistent with the auto-negotiation results. This configuration is done by the user and system software. 5.1.4.2 Determining If Link Is Established in Auto-Negotiation Mode A valid link is established when the AN_complete bit is set and the RX_Sync bit reports that synchronization has occurred. Both register bits are located in the “RX Config Word ($ Port_Index + 0x16)". If the link goes down after auto-negotiation is completed, RX_Sync indicates that a loss of synchronization occurred. The IXF1104 MAC restarts auto-negotiation and attempts to reestablish a link. Once a link is reestablished, the AN_complete bit is set and the RX_Sync bit shows that synchronization has occurred. To manually restart auto-negotiation, bit 5 of the “Diverse Config Write ($ Port_Index + 0x18)” (AN_enable) must be de-asserted, then re-asserted. 5.1.4.3 Fiber Forced Mode The MAC fiber operation can be forced to operate at 1000 Mbps full-duplex without completion of the auto-negotiation function. In this mode, the MAC RX path must achieve synchronization with the link partner. Once achieved, the MAC TX path is enabled to allow data transmission. This forced mode is limited to operation with a link partner that operates with a full-duplex link at 1000 Mbps. 5.1.4.4 Determination of Link Establishment in Forced Mode When the IXF1104 MAC is in forced mode operation, the “RX Config Word ($ Port_Index + 0x16)” bit 20 RX Sync indicates when synchronization occurs and a valid link establishes. Note: The RX Sync bit indicates a loss of synchronization when the link is down. 5.1.5 Copper Mode In copper mode, the IXF1104 MAC transmits data on the egress path of the RGMII or GMII interface, depending on the port configuration defined by the user. The copper MAC receives data on the ingress path of the RGMII or GMII interface, depending on the port configuration defined

Datasheet 78 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 by the user. The RGMII interface supports operation at 10/100/1000 Mbps when a full-duplex link is established, and supports 10/100 Mbps when a half-duplex link is established. The GMII interface only supports a 1000 Mbps full-duplex link. 5.1.5.1 Speed The copper MAC supports 10 Mbps, 100 Mbps, and 1000 Mbps. All required speed adjustments, clocks, etc., are supplied by the MAC. The operating speed of the MAC is programmable through the “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" (MAC_IF_Mode). The IXF1104 MAC speed setting must be programmed by the system software to match the speed of the attached PHY for proper IXF1104 MAC operation. Note: When the IXF1104 MAC is configured to use the GMII interface, the only mode of operation that is supported is 1000 Mbps full-duplex. If 10/100 Mbps operation is required in either full-duplex or half-duplex, the IXF1104 MAC must be configured to use the RGMII interface. 5.1.5.2 Duplex The MAC supports full-duplex or half-duplex depending on the line-side interface that is configured by the “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" (MAC_IF_Mode). The duplex of the MAC is set in the “Desired Duplex ($ Port_Index + 0x02)” on page 163. The IXF1104 MAC duplex setting must be programmed by the system software to match the attached PHY duplex for proper IXF1104 MAC operation. 5.1.5.3 Copper Auto-Negotiation In the copper MAC, auto-negotiation and all other controls of the PHY devices are achieved through the MDIO interface, and are independent of the MAC controller. See Section 5.5, “MDIO Control and Interface” on page 99 for further operation details. Note: In copper mode, auto-negotiation is accomplished by the attached PHY, not the IXF1104 MAC. Thus, the IXF1104 MAC does not automatically configure the MAC or other blocks in the device to be consistent with attached PHY auto-negotiation results. This must be accomplished by the user and system software. 5.1.6 Jumbo Packet Support The IXF1104 MAC supports jumbo frames. The jumbo frame length is dependent on the application and the IXF1104 MAC design is optimized for a 9.6 KB jumbo frame length. Larger lengths can be programmed, but limited system performance may lead to data loss during certain flow-control conditions The value programmed into the“Max Frame Size (Addr: Port_Index + 0x0F)" determines the maximum length frame size the MAC can receive or transmit without activating any error counters, and without truncation. The“Max Frame Size (Addr: Port_Index + 0x0F)" bits 13:0 set the frame length. The default value programmed into this register is 0x05EE (1518). The value is internally adjusted by +4 if the frame has a VLAN tag. The overall programmable maximum is 0x3FFF or 16383 bytes.

79 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 The register should be programmed to 0x2667 for the 9.6 KB length jumbo frame, optimized for the IXF1104 MAC. The RMON counters are also implemented for jumbo frame support as follows: 5.1.6.1 Rx Statistics • RxOctetsTotalOK (Addr: Port_Index + 0x20) • RxPkts1519toMaxOctets (Addr: Port_Index + 0x2B) • RxFCSErrors (Addr: Port_Index + 0x2C) • RxDatatError (Addr: Port_Index = 0x02E) • RxAlignErrors (Addr: Port_Index + 0x2F) • RxLongErrors (Addr: Port_Index + 0x30) • RxJabberErrors (Addr: Port_Index + 0x31) • RxVeryLongErrors (Addr: Port_Index + 0x34) 5.1.6.2 TX Statistics • OctetsTransmittedOK (Addr: Port_Index + 0x40) • TxPkts1519toMaxOctets (Addr: Port_Index + 0x4B) • TxExcessiveLengthDrop (Addr: Port_Index + 0x53) • TxCRCError (Addr: Port_Index + 0x56) The IXF1104 MAC checks the CRC for all legal-length jumbo frames (frames between 1519 and the Max Frame Size). On transmission, the MAC can be programmed to append the CRC to the frame or check the CRC and increment the appropriate counter. On reception, the MAC transmits these frames across the SPI3 interface (jumbo frames above the setting in the “RX FIFO Transfer Threshold Port 0 ($0x5B8)” with a bad CRC cannot be dropped and are sent across the SPI3 interface). If the receive frame has a bad CRC, the appropriate counter is incremented and the RxERR flag is asserted on the SPI3 receive interface. Jumbo frames also impact flow control. The maximum frame size needs to be taken into account when determining the FIFO watermarks. The current transmission must be completed before a Pause frame is transmitted (needed when the receiver FIFO High watermark is exceeded). If the current transmission is a jumbo frame, the delay may be significant and increase data loss due to insufficient available FIFO space. 5.1.6.3 Loss-less Flow Control The IXF1104 MAC supports loss-less flow control when the size of a Jumbo packet is restricted to 9.6 k bytes. If this condition is met, the IXF1104 MAC has sufficient memory resources allocated to each MAC port to ensure that, if both the IXF1104 MAC and link partner are required to send Pause packets simultaneously during jumbo packet transfers across a medium of five kilometers of fiber, no packet data should be lost due to FIFO overflows.

Datasheet 80 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.1.7 Packet Buffer Dimensions 5.1.7.1 TX and RX FIFO Operation 5.1.7.1.1 TX FIFO The IXF1104 MAC TX FIFOs are implemented with 10 KB for each channel. This provides enough space for at least one maximum size (10 KB) packet per-port storage and ensures that no under-run conditions occur, assuming that the sending device can supply data at the required data rate. A transfer to MAC Threshold parameter, which is user-programmable, determines when the FIFO signals to the MAC that it has data to send. This is configured for specific block sizes, and the user must ensure that an under-run does not occur. Also, the threshold can be set above the maximum size of a normal Ethernet packet. This causes the FIFO to send only data to the MAC when this threshold is exceeded or when the End-of-Packet marker is received. This second condition eliminates the possibility of under-run, except when the controlling switch device fails. It can, however, cause idle times on the media. 5.1.7.1.2 RX FIFO The IXF1104 MAC RX FIFOs are provisioned so that each port has its own 32 KB of memory space. This is enough memory to ensure that there is never an over-run on any channel while transferring normal Ethernet frame size data. The FIFOs automatically generate Pause control frames to halt the link partner when the High watermark is reached and to restart the link partner when the data stored in the FIFO falls below the low-watermark. The RX and TX FIFOs have been sized to support lossless flow control with 9.6 KB packets. The RX FIFO has a programmable transfer threshold that sets the threshold at which packets become “cut through” and starts transitioning to the SPI3 interface before the EOP is received. Packets sizes below this threshold are treated as “store and forward.” Once a packet size exceeds the RX FIFO transfer threshold, it can no longer be dropped by the RX FIFO even if it is marked to be dropped by the MAC. 5.1.8 RMON Statistics Support The IXF1104 MAC supplies RMON statistics through the CPU interface. These statistics are available in the form of counter values that can be accessed at specific addresses in the register maps (Table 59 through Table 69). Once read, these counters automatically reset and begin counting from zero. A separate set of RMON statistics is available for each MAC device in the IXF1104 MAC. Implementation of the RMON Statistics block is similar to the functionality provided by existing Intel switch and router products. This implementation allows the IXF1104 MAC to provide all of the RMON Statistics group as defined by RFC2819. The IXF1104 MAC supports the RMON RFC2819 Group 1 statistics counters. Table 25 notes the differences and additional statistics registers supported by the IXF1104 MAC that are outside the scope of the RMON RFC2819 document.

81 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 25. RMON Additional Statistics (Sheet 1 of 2) RMON Ethernet Statistics Group 1 Statistics Type IXF1104 MAC-Equivalent Statistics Type Definition of RMON Versus IXF1104 MAC Documentation etherStatsindex Integer 32 NA NA NA etherStatsDataSource Object identifier NA NA NA etherStatsDropEvents Counter 32 RX Number of Frames Removed/ TX Number of Frames Removed Counter 32 See table note 1 etherStatsOctets Counter 32 RxOctetsTotalOK RxOctetsBad OctetsTransmittedOK OctetsTransmittedBad Counter 32 The IXF1104 MAC has two counters for receive and transmit that use different naming conventions for the total Octets and Octets Bad. These counters must be combined to meet the RMON definition for this statistic. etherStatsPkts Counter32 RxUCPkts/TxUCPkts RxBCPkts/TxBCPkts RxMCPkts/TxMCPkts Counter 32 The IXF1104 MAC has three counters for the etherStatsPkts that must be combined to give the total packets as defined by the RMON specification. etherStatsBroadcastPkts Counter32 RxBCPkts/TxBCPkts Counter 32 Same as RMON specification etherStatsMulticastPkts Counter32 RxMCPkts/TxMCPkts Counter 32 See table note 2 etherStatsCRCAlignErrors Counter32 RxAlignErrors RxFCSErrors TxCRCError Counter 32 The IXF1104 MAC has two counters for the alignment and CRC errors for the RX side only. The IXF1104 MAC has a CRC Error counter for the TX side. etherStatsUndersizedPkts Counter32 RxRuntErrors RxShortErrors Rx Statistics ONLY Counter 32 The IXF1104 MAC has two counters, one for Runt errors and one for ShortErrors. NOTE: The RMON specification requires that this is, “The total number of events where packets were dropped by the probe due to a lack of resources. This number is not necessarily the number of packets dropped; it is the number of times this condition is detected." The “RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)" and “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)" in the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows. If any IXF1104 MAC programmable packet filtering is enabled, the “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)" and “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)" increment with every frame removed in addition to the existing frames counted due to FIFO overflow.

Datasheet 82 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.1.8.1 Conventions The following conventions are used throughout the RMON Management Information Base (MIB) and its companion documents. • Good Packets: Error-free packets that have a valid frame length. For example, on Ethernet, good packets are error-free packets that are between 64 and 1518 octets long. They follow the form defined in IEEE 802.3, Section 3.2. • Bad Packets: Bad packets are packets that have proper framing and recognized as packets, but contain errors within the packet or have an invalid length. For example, on Ethernet, bad etherStatsOversizePkts Counter32 RxLongErrors TxExcessiveLength Drop Counter 32 Same as RMON specification etherStatsFragments Counter32 RuntErrors Counter 32 Same as RMON specification etherStatsJabbers Counter32 JabberErrors Counter 32 Same as RMON specification etherStatsCollisions Counter32 TxSingleCollision TxMultipleCollision TxLateCollision TxTotalCollision Counter 32 The TxTotalCollision count value is equivalent to the RMON specification minus the TxLateCollision etherStatsPkts64Octets Counter32 RxPkts64Octets/ TxPkts64Octets Counter 32 Same as RMON specification etherStatsPkts65to127Octets Counter32 RxPkts65to127Octets/ TxPkts65to127Octets Counter 32 Same a RMON specification etherStatsPkts128to255Octets Counter32 RxPkts128to255Octets/ TxPkts128to255Octets Counter32 Same a RMON specification etherStatsPkts256to511Octets Counter32 RxPkts256to511Octets/ TxPkts256to511Octets Counter32 Same a RMON specification etherStatsPkts512to1023Octets Counter32 RxPkts512to1023Octets/ TxPkts512to1023Octets Counter32 Same a RMON specification etherStatsPkts1023to1518Octets Counter32 RxPkts1023to1518Octets/ TxPkts1023to1518Octets Counter32 Same as RMON specification etherStatOwner Owner String NA NA NA etherStatsStatus Entry Status NA NA NA Table 25. RMON Additional Statistics (Sheet 2 of 2) RMON Ethernet Statistics Group 1 Statistics Type IXF1104 MAC-Equivalent Statistics Type Definition of RMON Versus IXF1104 MAC Documentation NOTE: The RMON specification requires that this is, “The total number of events where packets were dropped by the probe due to a lack of resources. This number is not necessarily the number of packets dropped; it is the number of times this condition is detected." The “RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)" and “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)" in the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows. If any IXF1104 MAC programmable packet filtering is enabled, the “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)" and “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)" increment with every frame removed in addition to the existing frames counted due to FIFO overflow.

83 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 packets have a valid preamble and SFD, but have a bad CRC, or are either shorter than 64 octets or longer than 1518 octets. 5.1.8.2 Advantages The following lists additional IXF1104 MAC registers that support features not documented in RMON: • MAC (flow) control frames • VLAN Tagged • Sequence Errors • Symbol Errors • CRC Error These additional counters allow for differentiation beyond standard RMON probes. Note: In fiber mode, a packet transfer with an invalid 10-bit symbol does not always update the statistics registers correctly. • Behavior: The IXF1104 MAC 8B10B decoder substitutes a valid code word octet in its place. The packet transfer is aborted and marked as bad. The new internal length of the packet is equal to the byte position where the invalid symbol was. No packet fragments are seen at the next packet transfer. • Issue: If the invalid 10-bit code is inserted in a byte position of 64 or greater, expected RX statistics are reported. However, if the invalid code is inserted in a byte position of less than 64, expected RX statistics are not stored. 5.2 SPI3 Interface The IXF1104 MAC SPI3 Interface is implemented to the System Packet Interface Level 3 (SPI3) Physical Layer Interface standard. The interface function allows the IXF1104 MAC blocks to interface to higher-layer network processors or switch fabric. The IXF1104 MAC transmit interface allows data flows from a network processor or switch fabric device to the IXF1104 MAC. The receive interface allows data to flow from the IXF1104 MAC to the network processor or switch fabric device. This interface receives and transmits data between the MAC and the Network Processor with compliant SPI3 interfaces. The SPI3 interface operation is defined in the OIF-SPI3-01.0 (available from the Optical Internet Working Forum [www.oiforum.com]). The OIF specification defines operation for the transfer of data at data rates of up to 3.2 Gbps when operating at a frequency of 104 MHz. The IXF1104 MAC defines operation for the transfer of data at data rates of up to 4.256 Gbps when operating at a maximum frequency of 133 MHz in MPHY mode and 125 MHz in SPHY Mode. There is no guarantee of the number of bytes available since the size of packets is variable. An IXF1104 MAC port-transmit packet available status is provided on signals DTPA, STPA or PTPA, indicating the TX FIFO is nearly full. In the receive direction, RVAL indicates if valid data is available on the receive data bus and is defined so that data transfers can be aligned with packet boundaries.

Datasheet 84 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 The SPI3 interface supports the following two modes of operation: • MPHY or 32 bit mode (one 32-bit data bus) • SPHY or 4 x 8 mode (four individual 8-bit data buses) 5.2.1 MPHY Operation The MPHY operation mode is selected when bit 21 of the“SPI3 Transmit and Global Configuration ($0x700)” is set to 0 and bit 7 of the “SPI3 Receive Configuration ($0x701)" is set to 1. Data Path The IXF1104 MAC SPI3 interface has a single 32-bit data path in the MPHY configuration mode (see Figure 13). The bus interface is point-to-point (one output driving only one input load), so a 32-bit data bus would support only one IXF1104 MAC. To support variable-length packets, the RMOD[1:0]/TMOD[1:0] signals are defined to specify valid bytes in the 32-bit data bus structure. Each double-word must contain four valid bytes of packet data until the last double-word of the packet transfer, which is marked with the end of packet REOP/TEOP signal. This last double-word of the transfer contains up to four valid bytes specified by the RMOD[1:0]/TMOD[1:0] signals. The IXF1104 MAC port selection is performed using in-band addressing. In the transmit direction, the network processor device selects an IXF1104 MAC port by sending the address on the TDAT[1:0] bus marked with the TSX signal active and TENB signal inactive. All subsequent TDAT[1:0] bus operations marked with the TSX signal inactive and the TENB active are packet data for the specified port. In the receive direction, the IXF1104 MAC specifies the selected port by sending the address on the RDAT[1:0] bus marked with the RSX signal active and RVAL signal inactive. All subsequent RDAT[1:0] bus operations marked with RSX inactive and RVAL active are packet data from the specified port. Note: See Table 17 “SPI3 MPHY/SPHY Interface” on page 59 for a complete list of the MPHY mode signals. The control signals with the port designator for Port 0 are the only ones used in MPHY mode and they apply to all 4 ports. Table 3 “SPI3 Interface Signal Descriptions” on page 39 provides a comprehensive list of SPI3 signal descriptions. 5.2.1.1 SPI3 RX Round Robin Data Transmission The IXF1104 MAC uses a round-robin protocol to service each of the 4 ports dependent upon the enable status of the port and if there is data available to be taken from the RX FIFO. The round robin order goes from port 0, port 1, port 2, port 3, and back to port 0. A port is skipped and the next port is serviced if it has no available transmit data. The data transfer bursts are user- configurable burst lengths of 64, 128, or 256 bytes. The IXF1104 MAC also has a configurable pause interval between data transfer bursts on the receive side of the interface. The RX SPI3 burst lengths and the pause interval can be set in the “SPI3 Receive Configuration ($0x701)"). 5.2.2 MPHY Logical Timing The SPI3 interface AC timing for MPHY can be found in Section 7.2, “SPI3 AC Timing Specifications” on page 137. Logical timing in the following diagrams illustrates all signals associated with MPHY mode.

85 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.2.2.1 Transmit Timing In MPHY mode a packet transmission starts with the TSX signal indicating port address information is on the data bus. The next clock cycle TENB and TSOP indicate present data on the bus is the first word in the packet and all subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted. Data transmission can be temporally halted when TENB goes high then resumed when TENB is low. The valid bytes in the final word, during an active TEOP, are indicated by state of TMOD [1:0]. 5.2.2.2 Receive Timing A packet is received when RSX indicates port address information on the data bus followed by RSOP to indicate the data bus contains the first word of a packet. All subsequent data is valid only while RVAL is High and until REOP is asserted. Receive data can be temporarily halted when RENB is de-asserted and starts again on the second rising edge of RFCLK following the assertion of RENB. RMOD indicates the number of valid bytes in the last transfer when REOP is asserted. Figure 11. MPHY Transmit Logical Timing B3216-02 TFCLK TENB TSOP TEOP TMOD [1:0] TERR TSX TDAT [31:0] TPRTY 0000 B0-B3 B4-B7 B48-B51 B44-B47 B52-B55 B60-B64 B56-B59 0001 B0-B3 B4-B7 1. Applies to all transmit packet available signals (STPA, PTPA, DTPA_0:3).

Datasheet 86 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Figure 12. MPHY Receive Logical Timing Figure 13. MPHY 32-Bit Interface                         B0660-02 TFCLK TENB TDAT[31:0] TPRTY TERR TSX TSOP TEOP Network Processor SPI3 Bus IXF1104 MPHY Mode Transceiver TFCLK TENB_0 TDAT[31:0] TPRTY_0 TMOD[1:0] TMOD[1:0] RMOD[1:0] RMOD[1:0] TERR_0 TSX TSOP_0 TEOP_0 RFCLK RENB RDAT[31:0] RPRTY RPRTY RVAL RERR RSX RSOP REOP RPRTY_0 RFCLK RENB_0 RDAT[31:0] RVAL_0 RERR_0 RSX RSOP_0 REOP_0 DTPA_0:3 STPA PTPA TADR[1:0] DTPA_0:3 STPA PTPA TADR[1:0] Transceiver Transceiver Transceiver Line-Side Interface Port 0 Port 1 Port 3 Port 2

87 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.2.2.3 Clock Rates In MPHY mode, the TFCLK and RFCLK can be independent of each other. TFCLK and RFCLK should be common to the IXF1104 MAC and the Network Processor. The IXF1104 MAC requires a single clock source for the transmit path and a single clock source for the receive path. To allow all four IXF1104 MAC ports to operate at 1 Gbps, the IXF1104 MAC is designed to allow this interface to be overclocked. This allows operation for data transfer at data rates of up to 4.256 Gbps when operating at an overclocked frequency of 133 MHz. Note: MPHY mode operates at a maximum clock frequency of 133 MHz (TFCLK and RFCLK). 5.2.2.4 Parity The IXF1104 MAC can be odd or even (the IXF1104 MAC is odd by default) when calculating parity on the data bus. This can be changed to accommodate even parity if desired, and can be set for transmit and receive independently. The RX Parity is set in bit 12 of the “SPI3 Receive Configuration ($0x701)” and the TX Parity is set in bit 4 of the “SPI3 Transmit and Global Configuration ($0x700)”. 5.2.2.5 SPHY Mode The SPHY operation mode is selected when bit 21 of the Table 146 “SPI3 Transmit and Global Configuration ($0x700)” on page 213 is set to 1. The SPHY mode is the default operation for the IXF1104 MAC SPI3 interface. 5.2.2.5.1 Data Path The IXF1104 MAC SPI3 interface has four 8-bit data paths that can support four independent 8-bit point-to-point connections in SPHY mode (see Figure 16). Since each MAC port has its own dedicated 8-bit SPI3 data bus, each port has it own status signal (unlike MPHY). See the For a detailed list of all the signals refer to the SPI3 pin multiplexing table.... Furthermore since each port has it own dedicated bus the in band port addressing is not needed. The 8 bit data bus eliminates the need to have separate control signals determine the number of valid bytes on an EOP.Therefore TSX, RSX, TMOD[1:0] RMOD[1:0] are not used in SPHY mode. Note: See Table 17 “SPI3 MPHY/SPHY Interface” on page 59 for a complete list of the SPHY mode signals. Unlike MPHY mode, each port has a dedicated control signal associated with each of the per-port 8-bit data buses. Table 3 “SPI3 Interface Signal Descriptions” on page 39 provides signal descriptions for all SPI3 signals. 5.2.2.5.2 Receive Data Transmission Packets are transmitted on each port as they become available from the RX FIFO. The burst length is determined by the setting of per port burst size and the B2B pause settings in the “SPI3 Receive Configuration ($0x701)". If the B2B pause setting is zero pause cycles inserted, then the entire packet will be burst without any pauses unless the Network Processor de-asserts RENB. If the B2B_Pause setting calls for the insertion of two pause cycles on a port, these are inserted after each data burst for that port. The data bursts are user configurable for each port in the “SPI3 Receive Configuration ($0x701)".

Datasheet 88 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.2.2.6 SPHY Logical Timing SPI3 interface AC timing for SPHY can be found in Section 7.2, “SPI3 AC Timing Specifications” on page 137. Logical timing in the following diagrams illustrates all signals associated with SPHY mode. SPHY mode is similar to MPHY mode except the following signals are not used: • TMOD[1:0] • RMOD[1:0] • TSX • RSX • Address Data appearing on the data bus 5.2.2.7 Transmit Timing (SPHY) Packet transmission starts when TENB and TSOP indicate present data on the bus is the first word in the packet. All subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted. Data transmission can be temporally halted when TENB goes high then resumed when TENB is low. 5.2.2.8 Receive Timing (SPHY) A packet is received when RSOP is asserted to indicate the data bus contains the first word of the packet. All subsequent data is valid only while RVAL is high and until REOP is asserted. Receive data can be temporarily halted when RENB is de-asserted and starts again on the second rising edge of RFCLK following the assertion of RENB. When REOP is asserted RMOD indicates the number of valid bytes in the last transfer. Figure 14. SPHY Transmit Logical Timing B3249-02 TFCLK TENB TSOP TEOP TERR TDAT [7:0] TPRTY B0 B1 B60 B59 B61 B63 B62 B0 B1 B2

89 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Figure 15. SPHY Receive Logical Timing              

Datasheet 90 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.2.2.8.1 Clock Rates The TFCLK and RFCLK can be independent of each other in SPHY mode operation. TFCLK and RFCLK should be common to all the Network Processor devices. The IXF1104 MAC requires an individual single clock source for the device transmit path and a single clock source for the device receive path. The IXF1104 MAC allows this interface to be overclocked so that all four IXF1104 MAC ports can operate at 1 Gbps. This allows data transfer at data rates of up to 4.0 Gbps when operating at an overclocked frequency of 125 MHz. Note: SPHY operates at a maximum frequency of 125 MHz. Figure 16. SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit Interface) B0659-02 TFCLK TENB[0] TDAT[7:0][0] TPRTY[0] TERR[0] TSOP[0] TEOP[0] Network Processor SPI3 Bus Intel® IXF1104 Port 0 TFCLK TENB_0 TDAT[7:0]_0 TPRTY_0 TERR_0 TSOP_0 TEOP_0 RFCLK RENB[0] RDAT[7:0][0] RPRTY[0] RPRTY_0 RVAL[0] RERR[0] RSOP[0] REOP[0] RFCLK RENB_0 RDAT[7:0]_0 RVAL_0 RERR_0 RSOP_0 REOP_0 DTPA[0] TFCLK TENB[1] TDAT[7:0][1] TPRTY[1] TERR[1] TSOP[1] TEOP[1] RFCLK RENB[1] RDAT[7:0][1] RPRTY[1] RPRTY_1 RVAL[1] RERR[1] RSOP[1] REOP[1] DTPA[1] DTPA_0 Transceiver Port 1 SPI3 Flow Control TFCLK TENB_1 TDAT[7:0]_1 TPRTY_1 TERR_1 TSOP_1 TEOP_1 RFCLK RENB_1 RDAT[7:0]_1 RVAL_1 RERR_1 RSOP_1 REOP_1 DTPA_1 Transceiver Port 0 Port 1 Line-Side Interface Line-Side Interface PTPA TADR[1:0] PTPA TADR[1:0]

91 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.2.2.8.2 Parity The IXF1104 MAC can be odd or even (the IXF1104 MAC defaults to odd) when calculating parity on the data bus. This can be changed to accommodate even parity if desired, and can be set for transmit and receive ports independently. The RX and TX parity sense bits have a direct relationship to the port parity in SPHY mode. The per port RX parity is set in the “SPI3 Receive Configuration ($0x701)" and the per port TX Parity is set in the “SPI3 Transmit and Global Configuration ($0x700)". 5.2.2.9 SPI3 Flow Control The SPI3 packet interface supports transmit and receive data transfers at clock rates independent of the line bit rate. As a result, the IXF1104 MAC supports packet rate decoupling using internal FIFOs. These FIFOs are 10 KB per port in the transmit direction (egress from the IXF1104 MAC to the line interfaces) and 32 KB per port in the receive direction (ingress to the IXF1104 MAC from the line interfaces). Control signals are provided to the network processor and the IXF1104 MAC to allow either one to exercise flow control. Since the bus interface is point-to-point, the receive interface of the IXF1104 MAC pushes data to the link-layer device. For the transmit interface, the packet available status granularity is byte-based. 5.2.2.9.1 RX SPI3 Flow Control In the receive direction, when the IXF1104 MAC has stored an end-of-packet (a complete small packet or the end of a larger packet) or some predefined number of bytes in its receive FIFO, it sends the in-band address followed by FIFO data to the link-layer device (in MPHY mode). The data on the interface bus is marked with the valid signal (RVAL) asserted. The network processor device can pause the data flow by de-asserting the Receive Read Enable (RENB) signal. RENB_0:3 RENB_0:3 controls the flow of data from the IXF1104 MAC RX FIFOs. In SPHY mode, there is a dedicated RENB for each port. In MPHY mode, RENB_0 is used as the global signal covering all ports. When RENB is sampled Low, the network processor can accept data. A read is performed from the RX FIFO and the RDAT, RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX, and RVAL signals are updated on the following rising edge of RFCLK. RENB can be asserted High by the Network Processor at any time if it is unable to accept any more data. When the RENB is sampled High by the IXF1104 MAC, a read of the RX FIFO is not performed, and the RDAT, RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals remain unchanged on the following rising edge of RFCLK. 5.2.2.9.2 TX SPI3 Flow Control In the transmit direction, when the IXF1104 MAC has space for some predefined number of bytes in its transmit FIFO, it informs the Network Processor device by asserting one of the Transmit Packet Available (TPA) signals. The Network Processor device writes the in-band address followed by packet data to the IXF1104 MAC using an enable signal (TENB). The network processor device monitors the TPA signals for a High-to-Low transition, which indicates that the transmit FIFO is almost full (the number of bytes left in the FIFO is user-selectable by setting the “TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603)", and suspends data transfer to avoid an overflow. The Network Processor device can pause the data flow by de-asserting the enable signal (TENB).

Datasheet 92 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 The IXF1104 MAC provides the following three types of TPA signals: • Dedicated per port Direct Transmit Packet Available (DTPA) • Selected-PHY Transmit Packet Available (STPA), which is based on the current in-band port address in MPHY mode. • Polled-PHY Transmit packet Available (PTPA), which provides FIFO information on the port selected by the TADR[1:0] signals. The following three TPA signals (DTPA_0:3, STPA, and PTPA) provide flow control based on the programmable TX FIFO High and Low watermarks. Refer to Table 132 “TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603)” on page 203 and Table 133 “TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)” on page 204 for more information. DTPA_0:3: A direct status indication for the TX FIFOs of ports [0:3]. When DTPA is High, it indicates the amount of data in the TX FIFO is below the TX FIFO High watermark. When the High watermark is crossed, DTPA transitions Low to indicate the TX FIFO is almost full. It stays low until the amount data in the TX FIFO goes back below the TX FIFO Low watermark. At this point, DTPA transitions High to indicate the programmed number of bytes are now available for data transfers. DTPA_0:3 is updated on the rising edge of the TFCLK. STPA: STPA provides TX FIFO status for the currently selected port in MPHY mode. When High, STPA indicates that the amount of data in the TX FIFO for the port selected, specified by the latest in- band address, is below the TX FIFO High watermark. When the High watermark is crossed, STPA transitions Low to indicate the TX FIFO is almost full. It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low watermark. At this point, STPA transitions High to indicate the programmed number of bytes are now available for data transfers. The port reported by STPA is updated on the rising edge of TFCLK after TSX is sampled as asserted. STPA is updated on the rising edge of TFCLK. Note: STPA is only used when the IXF1104 MAC is configured for MPHY mode of operation. PTPA: PTPA provides status of the TX FIFO based on the port selected by the TADR[1:0] address bus. When High, PTPA indicates that the amount of data in the TX FIFO for the port selected is below the TX FIFO High watermark. When the High watermark is crossed, PTPA transitions Low to indicate the TX FIFO is almost full. It stays Low until the amount of data in the TX FIFO goes back below the TX FIFO Low watermark. PTPA then transitions High to indicate the programmed number of bytes are now available for data transfers. The port reported by PTPA is updated on the rising edge of TFCLK after the TADR{1:0] port address is sampled. PTPA is updated on the rising edge of TFCLK.

93 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.2.3 Pre-Pending Function The IXF1104 MAC implements a pre-pending feature to allow 1518-byte Ethernet packets to be pre-padded with two additional bytes of data so that the packet becomes low-word aligned. The 2-byte pre-pend value is all zeros and is inserted before the destination address of the packet being pre-pended. This value is fixed and cannot be changed. This function is enabled by writing the appropriate data to the “RX FIFO Padding and CRC Strip Enable ($0x5B3)" for each port. A standard 1518-byte Ethernet packet occupies 379 long words (four bytes) with two additional bytes left over (1518/4 = 379.5). To eliminate the memory-management problems for a network processor or switch fabric, the two remaining bytes are dealt with by the addition of two bytes to the start of a packet. This results in a standard 1518-byte Ethernet packet received by the IXF1104 MAC being forwarded to the higher-layer device as a 380-long-word packet. The upper-layer device is responsible for stripping the additional two bytes. This feature was added to the IXF1104 MAC to assist in the design of higher-layer memory management. The addition of the two extra bytes is not the default operation of the IXF1104 MAC and must be enabled by the user. The default operation of the IXF1104 MAC SPI3 receive interface forwards data exactly as it is received by the IXF1104 MAC line interface. 5.3 Gigabit Media Independent Interface (GMII) The IXF1104 MAC supports a subset of the GMII interface standard as defined in IEEE 802.3 2000 Edition for 1 Gbps operation only. This subset is limited to operation at 1000 Mbps full- duplex. The GMII Interface operates as a source synchronous interface only and does not accept a TXC clock provided by a PHY device when operating at 10/100 Mbps speeds. Note: The RGMII interface must be used for applications that require 10/100/1000 Mbps operation. The IXF1104 MAC does NOT support 10/100 Mbps copper PHY devices that are implemented using the MII Interface. Note: MII operation is not supported by the IXF1104 MAC. The user can select GMII, RGMII, or Optical Module/SerDes functionality on a per-port basis. This mode of operation is controlled through a configuration register. While IEEE 802.3 specifies 3.3 V operation of GMII devices, most PHYs use 2.5 V signaling. The IXF1104 MAC provides a 2.5 V drive and is 3.3 V-tolerant on inputs.

Datasheet 94 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.3.1 GMII Signal Multiplexing The GMII balls are reassigned when using the RGMII mode or fiber mode. Table 16 “Line Side Interface Multiplexed Balls” on page 58 specifies the multiplexing of GMII balls in these modes. See Section 5.1.3, “Mixed-Mode Operation” on page 75 for proper configuration of the IXF1104 MAC in GMII mode. 5.3.2 GMII Interface Signal Definition Table 26 “GMII Interface Signal Definitions” on page 95 provides the GMII interface signal definitions. For information on 1000BASE-T GMII transmit and receive timing diagrams and tables, please refer to Table 49 “GMII 1000BASE-T Transmit Signal Parameters” on page 142, Figure 38 “1000BASE-T Transmit Interface Timing” on page 142, Figure 39 “1000BASE-T Receive Interface Timing” on page 143, and Table 50 “GMII 1000BASE-T Receive Signal Parameters” on page 143 Figure 17. MAC GMII Interconnect TXC_3:0 TX_EN_3:0 TX_ER_3:0 RXC_3:0 TXD[7:0]_0 TXD[7:0]_3 TXD[7:0]_2 TXD[7:0]_1 RX_EN_3:0 RX_ER_3:0 RXD[7:0]_0 RXD[7:0]_3 RXD[7:0]_2 RXD[7:0]_1 COL_3:0 CRS_3:0 Intel® IXF1104 Media Access Controller TXC_3:0 TX_EN_3:0 TX_ER_3:0 TXD[7:0]_0 TXD[7:0]_3 TXD[7:0]_2 TXD[7:0]_1 RXC_3:0 RX_EN_3:0 RX_ER_3:0 RXD[7:0]_0 RXD[7:0]_3 RXD[7:0]_2 RXD[7:0]_1 COL_3:0 CRS_3:0 Quad PHY Device B3203-01

95 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Table 26. GMII Interface Signal Definitions IXF1104 MAC Signal GMII Standard Signal Source Description TXC_0 TXC_1 TXC_2 TXC_3 GTX_CLK IXF1104 MAC Transmit Reference Clock: 125 MHz for Gigabit operation. MII operation for 10/100 Mbps operation is not supported. TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_3 TXD[7:0] IXF1104 MAC Transmit Data Bus: Width of this synchronous output bus varies with the speed/mode of operation. In 1000 Mbps mode, all 8 bits are used. TX_EN_0 TX_EN_1 TX_EN_2 TX_EN_3 TX_EN IXF1104 MAC Transmit Enable: Synchronous input that indicates Valid data is being driven on the TXD[7:0] data bus. TX_ER_0 TX_ER_1 TX_ER_2 TX_ER_3 TX_ER IXF1104 MAC Transmit Error: Synchronous input to PHY causes the transmission of error symbols in 1000 Mbps links. RXC_0 RXC_1 RXC_2 RXC_3 RX_CLK PHY Receive Clock: Continuous reference clock is 125 MHz +/– 100 ppm. RXD[7:0]_0 RXD[7:0]_1 RXD[7:0]_2 RXD[7:0]_3 RXD<3:0> PHY Receive Data Bus: Width of the bus varies with the speed and mode of operation. In 1000 Mbps mode, all 8 bits are driven by the PHY device. Note: MII operation at 10/100 Mbps is not supported. RX_DV_0 RX_DV_1 RX_DV_2 RX_DV_3 RX_DV PHY Receive Data Valid: This signal is asserted when valid data is present on the corresponding RXD bus. RX_ER_0 RX_ER_1 RX_ER_2 RX_ER_3 RX_ER PHY Receive Error: In 1000 Mbps mode, asserted when error symbols or carrier extension symbols are received. Always synchronous to RX_CLK. CRS_0 CRS_1 CRS_2 CRS_3 CRS PHY Carrier Sense: Asserted when valid activity is detected at the line- side interface. COL_0 COL_1 COL_2 COL_3 COL PHY Collision: Asserted when a collision is detected and remains asserted for the duration of the collision event. In full- duplex mode, the PHY should force this signal Low.

Datasheet 96 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.4 Reduced Gigabit Media Independent Interface (RGMII) The IXF1104 MAC supports the RGMII interface standard as defined in the RGMII Version 1.2 specification. The RGMII interface is an alternative to the IEEE 802.3u MII interface. The RGMII interface is intended as an alternative to the IEEE 802.3u MII and the IEEE 802.3z GMII. The principle objective of the RGMII is to reduce the number of balls (from a maximum of 28 balls to 12 balls) required to interconnect the MAC and the PHY. This reduction is both cost- effective and technology-independent. To accomplish this objective, the data paths and all associated control signals are reduced, control signals are multiplexed together, and both edges of the clock are used. • 1000 Mbps operation – clocks operate at 125 MHz • 100 Mbps operation – clocks operate at 25 MHz • 10 Mbps operation – clocks operate at 2.5 MHz. Note: The IXF1104 MAC RGMII interface is multiplexed with signals from the GMII interface. See Table 16 “Line Side Interface Multiplexed Balls” on page 58 for detailed information. 5.4.1 Multiplexing of Data and Control Multiplexing of data and control information is achieved by utilizing both edges of the reference clocks and sending the lower four bits on the rising edge and the upper four bits on the falling edge. Control signals are multiplexed into a single clock cycle using the same technique. For further information on timing parameters, see Figure 37 “RGMII Interface Timing” on page 141 and Table 48 “RGMII Interface Timing Parameters” on page 141. Figure 18. RGMII Interface TXC_3:0 TX_CTL_3:0 TXD[3:0]_3 TXD[3:0]_0 TXD[3:0]_1 TXD[3:0]_2 Intel® IXF1104 Media Access Controller TXC_3:0 Quad PHY Device B3203-01 TX_CTL_3:0 TXD[3:0]_3 TXD[3:0]_0 TXD[3:0]_1 TXD[3:0]_2 RXC_3:0 RX_CTL_3:0 RXD[3:0]_3 RXD[3:0]_0 RXD[3:0]_1 RXD[3:0]_2 RXC_3:0 RX_CTL_3:0 RXD[3:0]_3 RXD[3:0]_0 RXD[3:0]_1 RXD[3:0]_2

97 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.4.2 Timing Specifics The IXF1104 MAC RGMII complies with RGMII Rev1.2a requirements. Table 27 provides the timing specifics. 5.4.3 TX_ER and RX_ER Coding To reduce interface power, the transmit error condition (TX_ER) and the receive error condition (RX_ER) are encoded on the RGMII interface to minimize transitions during normal network operation (refer to Table 28 on page 97 for the encoding method). Table 27 provides signal definitions for RGMII. The value of RGMII_TX_ER and RGMII_TX_EN are valid at the rising edge of the clock while TX_ER is presented on the falling edge of the clock. RX_ER coding behaves in the same way (see Table 28, Figure 19, and Figure 20). Table 27. RGMII Signal Definitions IXF1104 MAC Signal RGMII Standard Signal Source Description TXC_0:3 TXC MAC Depending on speed, the transmit reference clock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50ppm. TD[3:0]_n TD<3:0> MAC Contains register bits 3:0 on the rising edge of TXC and register bits 7:4 on the falling edge of TXC. TX_EN TX_CTL MAC TXEN is on the leading edge of TXC. TX_EN xor TX_ER is on the falling edge of TXC. RXC_0:3 RXC PHY Continuous reference clock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50 ppm. RD[3:0]_n RD<3:0> PHY Contains register bits 3:0 on the leading edge of RXC and register bits 7:4 on the trailing edge of RXC. RX_DV RX_CTL PHY RX_DV is on the leading edge of RXC. RX_DV or RXERR is the falling edge of RXC. Table 28. TX_ER and RX_ER Coding Description Condition Description Receiving valid frame, no errors RX_DV = true Logic High on rising edge of RXC RX_ER = false Logic High on the falling edge of RXC Receiving valid frame, with errors RX_DV = true Logic High on rising edge of RXC RX_ER = true Logic Low on the falling edge of RXC Receiving invalid frame (or no frame) RX_DV = false Logic Low on rising edge of RXC RX_ER = false Logic Low on the falling edge of RXC Transmitting valid frame, no errors TX_EN = true Logic High on rising edge of TXC TX_ER =false Logic High on the falling edge of TXC Transmitting valid frame with errors TX_EN = true Logic High on rising edge of TXC TX_ER = true Logic Low on the falling edge of TXC Transmitting invalid frame (or no frame) TX_EN = false Logic Low on rising edge of TXC TX_ER = false Logic low on the falling edge of TXC NOTE: Refer to Figure 19 for TX_CTL behavior, and Figure 20 for RX_CTL behavior.

Datasheet 98 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 Figure 19. TX_CTL Behavior Figure 20. RX_CTL Behavior B0616-02 TXC_0:3 (at Transmitter) TD[3:0]_0:3 TX_CTL_0:3 End-of-Frame TD[3:0] TD[7:4] TX_EN=True TX_ER=False TX_EN=False TX_ER=False TXC_0:3 (at Transmitter) TD[3:0]_0:3 TX_CTL_0:3 End-of-Frame TD[3:0] TD[7:4] TX_EN=True TX_ER=False TX_EN=False TX_ER=False Valid Frame Frame with Error B3237-01 RXC_0:3 (at PHY) RD[3:0]_0:3 RX_CTL_0:3 End-of-Frame RD[3:0] RD[7:4] RX_DV=True RX_ER=False RX_DV=False RX_ER=False RXC_0:3 (at PHY) RD[3:0]_0:3 RX_CTL_0:3 End-of-Frame RD[3:0] RD[7:4] RX_DV=True RX_ER=True RX_DV=False RX_ER=False Valid Frame Frame with Error

99 Datasheet Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.4.3.1 In-Band Status Carrier Sense (CRS) is generated by the PHY when a packet is received from the network interface. CRS is indicated when: • RXDV = true. • RXDV = false, RXERR = true, and a value of FF exists on the RXD[7:0] bits simultaneously. • Carrier Extend, Carrier Extend Error, or False Carrier occurs (please reference the Hewlett- Packard* Version 1.2a RGMII Specification for details.). Carrier Extend and Carrier Extend Error are applicable to Gigabit speeds only. Collision is determined at the MAC by the assertion of TXEN being true while either CRS or RXDV are true. The PHY will not assert CRS as a result of TXEN being true. 5.4.4 10/100 Mbps Functionality The RGMII interface implements the 10/100 Mbps Ethernet Media Independent Interface (MII) by reducing the clock rate to 25 MHz for 100 Mbps operation and 2.5 MHz for 10 Mbps. The TXC is generated by the MAC and the RXC is generated by the PHY. During packet reception, the RXC is stretched on either the positive or negative pulse to accommodate transition from the free-running clock to a data-synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or negative pulses is allowed. No glitching of the clocks is allowed during speed transitions. This interface operates at 10 Mbps and 100 Mbps speeds in the same manner as 1000 Mbps speed, although the data may be duplicated on the falling edge of the appropriate clock. The MAC holds TX_CTL Low until it is operating at the same speed as the PHY. Note: The IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode 5.5 MDIO Control and Interface The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows the IXF1104 MAC to monitor and control each of the PHY devices that are connected to the four ports of IXF1104 MAC when those ports are in copper mode. The MDIO Master Interface block is implemented once in the IXF1104 MAC. The MDIO Interface block contains the logic through which the user accesses the registers in PHY devices connected to the MDIO/MDC interface, which is controlled by each port. The MDIO Master Interface block supports the management frame format, specified by IEEE 802.3, clause 22.2.4.5. This block also supports single MDI access through the CPU interface and an autoscan mode. Autoscan allows the IXF1104 MAC MDIO master to read all 32 registers of the per-port copper PHYs and store the contents in the IXF1104 MAC. This provides external-CPU- ready access to the PHY register contents through a single CPU read without the latency of waiting on the low-speed serial MDIO data bus for each register access. Scan of a single register with low-frequency operation takes approximately 25.6 µs. Scan of a 32- register block takes approximately 820 µs, or 3.3 ms for all four ports. Autoscan data is not valid until approximately 19.2 µs after enabling scan. These numbers scale by 7/50 for high-frequency operation.

Datasheet 100 Document Number: 278757 Revision Number: 009 Revision Date: 27-Oct-2005 5.5.1 MDIO Address The 5-bit PHY address for the MDIO transactions can be set in the “MDIO Single Command ($0x680)". Bits 5:2 of the PHY address are fixed to a value of 0. Bits 1 and 0 are programmable in bits 9 and 8 of “MDIO Single Command ($0x680)". 5.5.2 MDIO Register Descriptions For complete information on the MDI registers, refer to the Table 142 “MDIO Single Command ($0x680)” on page 211, Table 143 “MDIO Single Read and Write Data ($0x681)” on page 211, Table 144 “Autoscan PHY Address Enable ($0x682)” on page 212, and Table 145 “MDIO Control ($0x683)” on page 212. 5.5.3 Clear When Done The MDI Command register bit, in the “MDIO Single Command ($0x680)", clears upon command completion and is set by the user to start the requested single MDIO Read or Write operation. This bit is cleared automatically upon operation completion. 5.5.4 MDC Generation The MDC clock is used for the MDIO/MDC interface. The frequency of the MDC clock is selectable by setting bit 0, MDC Speed, in an IXF1104 MAC configuration register (see Table 145 “MDIO Control ($0x683)” on page 212). 5.5.4.1 MDC High-Frequency Operation The high-frequency MDC is 18 MHz, derived from the 125-MHz system clock by dividing the frequency by 7. The duty cycle is as follows: • MDC High duration: 3 x (1/125 MHz) = 3 x 8 ns = 24 ns • MDC Low duration: 4 x (1/125 MHz) = 4 x 8 ns = 32 ns • MDC runs continuously after reset Refer to Figure 41 “MDC High-Speed Operation Timing” on page 145 for the high-frequency MDC timing diagram. 5.5.4.2 MDC Low-Frequency Operation The low-frequency MDC is 2.5 MHz, which is derived from the 125-MHz system clock by dividing the frequency by 50. The duty cycle is as follows: • MDC High duration: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns • MDC Low duration: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns • MDC runs continuously after reset