Quatech QS-300M Operation & User’s Manual

be free of defects for o n e ( 1 ) y e a r from the date of purchase. Qua Tech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights. Although every attempt has been made to guarantee the accuracy of this manual, Qua Tech Inc. assumes no l i a b i l i t y f o r d a m a g e s r e s u l t i n g f r o m e r r o r s i n t h i s document. Qua Tech Inc. reserves the right to edit or append to this document at any time without notice. Please complete the following information and retain for your records. Have this information available when requesting warranty service. DATE OF PURCHASE: MODEL NUMBER: QS-200M/QS-300M PRODUCT DESCRIPTION: FOUR CHANNEL RS-422/RS-485 ASYNC. COMMUNICATIONS ADAPTER SERIAL NUMBER: IBM PCTM, PC/XTTM, and PC/ATTM are trademarks of International Business Machines. i

WARRANTY INFORMATION . . . . . . . . . . . . i LIST OF FIGURES . . . . . . . . . . . . . iii I. INTRODUCTION . . . . . . . . . . . . . . . . 1 II. BOARD DESCRIPTION . . . . . . . . . . . . . 1 III. 16450/16550 * FUNCTIONAL DESCRIPTION . . . . 1 A. INTERRUPT ENABLE REGISTER . . . . . . . . 4 B. INTERRUPT IDENTIFICATION REGISTER . . . . 5 C. FIFO CONTROL REGISTER *. . . . . . . . . . 7 D. LINE CONTROL REGISTER . . . . . . . . . . 8 E. MODEM CONTROL REGISTER . . . . . . . . . 10 F. LINE STATUS REGISTER . . . . . . . . . . 11 G. MODEM STATUS REGISTER . . . . . . . . . . 13 H. SCRATCHPAD REGISTER . . . . . . . . . . . 14 IV. FIFO INTERRUPT MODE OPERATION * . . . . . . . 14 V. BAUD RATE SELECTION . . . . . . . . . . . . 14 VI. ADDRESSING . . . . . . . . . . . . . . . . . 16 VII. INTERRUPTS . . . . . . . . . . . . . . . . . 18 INTERRUPT STATUS REGISTER . . . . . . . . 19 VIII. OUTPUT CONFIGURATIONS . . . . . . . . . . . 20 IX. EXTERNAL CONNECTIONS . . . . . . . . . . . . 21 X. INSTALLATION . . . . . . . . . . . . . . . . 22 XI. SPECIFICATIONS . . . . . . . . . . . . . . . 22 *For optional 16550 only. i

Figure 1. QS-200M/QS-300M board layout . . . . . 2 Figure 2. 16450/16550 internal registers . . . . 3 Figure 3. Interrupt enable register . . . . . . 4 Figure 4. Interrupt identification register . . 5 Figure 5. Interrupt source identification . . . 6 Figure 6. FIFO control register * . . . . . . . . 7 Figure 7. FIFO receiver trigger levels *. . . . . 7 Figure 8. Line control register . . . . . . . . 8 Figure 9. Parity options . . . . . . . . . . . . 9 Figure 10. Word length and stop bit options . . . 9 Figure 11. MODEM control register . . . . . . . . 10 Figure 12. Line status register . . . . . . . . . 11 Figure 13. MODEM status register . . . . . . . . 13 Figure 14. Clock options . . . . . . . . . . . . 15 Figure 15. Divisor latch options . . . . . . . . 15 Figure 16. Address selection switches . . . . . . 16 Figure 17. Address selection examples . . . . . . 17 Figure 18. Interrupt selection jumper . . . . . . 18 Figure 19. Interrupt status register selection . 19 Figure 20. Interrupt status register definition . 19 Figure 21. Half duplex configuration jumpers . . 20 Figure 22. Output connectors . . . . . . . . . . 21 *For optional 16550 only. iii

serial communication adapter. The QS-300M is an RS-485 version of the adapter. Both are designed to be hardware c o m p a t i b l e w i t h t h e I B M P C / X T / A T p e r s o n a l c o m p u t e r s . D a t a i s c o m m u n i c a t e d t h r o u g h f o u r s h i e l d e d R J - 1 1 "modular" phone jack connectors which provide shielding from environmental noise. The serial interface is accomplished through four 16450 Asynchronous Communication Elements (ACEs). The 16450 is an improved specification version of the 8250 ACEs used in the IBM PC/XT models. Optional 16550 ACEs are available to reduce CPU overhead at higher data rates when used with software supporting this feature. Addressing for the adapter is selected by a pair of six position switches. These switches allow a full range o f a d d r e s s c h o i c e s b e t w e e n 0 a n d F F F F h e x . T h e Q S - 2 0 0 M / Q S - 3 0 0 M h a s t h e o p t i o n o f s e l e c t i n g o n e o f s i x possible Interrupt Request lines (IRQ 2 - IRQ 7). A hardware selectable clock divider is also available for producing unusual baud rates. II. BOARD DESCRIPTION A component diagram of the QS-200M/QS-300M is shown i n f i g u r e 1 . T h e b a s e a d d r e s s i s c o n t r o l l e d b y t h e address selection switches SW1 & SW2. The interrupt l e v e l f o r t h e a d a p t e r i s s e l e c t e d u s i n g j u m p e r J 3 . Channels 1 - 4 are controlled by the 16450 ACEs labeled U5 - U8 and are output through connectors CON1 - CON4 respectively. III. 16450/16550 FUNCTIONAL DESCRIPTION The 16450 is an improved specification version of t h e 8 2 5 0 A s y n c h r o n o u s C o m m u n i c a t i o n s E l e m e n t ( A C E ) . Functionally, the 16450 is equivalent to the 8250. The ACE performs serial-to-parallel conversion on received data and parallel-to-serial conversion on data output from the CPU. iii

16550 ACE enters character mode on reset and in this m o d e a p p e a r s a s a 1 6 4 5 0 t o u s e r s o f t w a r e . A n a d d i t i o n a l m o d e , F I F O m o d e , c a n b e i n v o k e d t h r o u g h s o f t w a r e t o r e d u c e C P U o v e r h e a d . T h e F I F O m o d e increases performance by providing two 16-byte FIFOs ( o n e t r a n s m i t a n d o n e r e c e i v e ) t o b u f f e r d a t a a n d reduce the number of interrupts issued to the CPU. Other features of the 16450/16550 include: Programmable baud rate, character length, parity, and number of stop bits. Automatic addition and removal of start, stop, and parity bits. Independent and prioritized transmit, receive and status interrupts. Transmitter clock output to drive receive logic. External receiver clock input. The following pages provide a brief summary of the internal registers available within the 16450 and 16550 ACEs. The registers are addressed as shown in figure 2 below. Registers and functions specific to the 16550 will be marked with an asterisk(*). +---------------+-----------------------------------+ | DLAB A2 A1 A0 | REGISTER DESCRIPTION | +---------------+-----------------------------------+ | 0 0 0 0 | Receive buffer (read only) | | | Transmit holding register | | | (write only) | | 0 0 0 1 | Interrupt enable | | x 0 1 0 | Interrupt identification | | | (read only) | | | FIFO control (write only) * | | x 0 1 1 | Line control | | x 1 0 0 | MODEM control | | x 1 0 1 | Line status | | x 1 1 0 | MODEM status | | x 1 1 1 | Scratch | | 1 0 0 0 | Divisor latch (LSB) | | 1 0 0 1 | Divisor latch (MSB) | +---------------+-----------------------------------+ Figure 2. Internal Register map for 16450/16550 ACE. D L A B i s a c c e s s e d t h r o u g h t h e L i n e C o n t r o l Register. *For optional 16550 only.

+-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmit holding register empty +-------+ D0 | ERBFI |----- Received data available +-------+ Figure 3. Interrupt Enable Register bit definitions. EDSSI - MODEM Status Interrupt: When set (logic 1), enables interrupt on clear to send, data set ready, ring indicator, and data carrier detect. ELSI - Receiver Line Status Interrupt: When set (logic 1), enables interrupt on overrun, parity, framing errors, and break indication. ETBEI - Transmitter Holding Register Empty Interrupt: When set (logic 1), enables interrupt on transmitter register empty. ERBFI - Received Data Available Interrupt: When set (logic 1), enables interrupt on received data available or FIFO trigger level.

REGISTER +------+ D7 | FFE |----- FIFO enable (FIFO only) * +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |--+ +------+ D0 | IP |----- Interrupt pending +------+ F i g u r e 4 . I n t e r r u p t I d e n t i f i c a t i o n R e g i s t e r b i t definitions. FFE - FIFO Enable: * When logic 1, indicates FIFO mode enabled. IIDx - Interrupt Identification: Indicates highest priority interrupt pending if a n y . S e e I P a n d f i g u r e 5 . N O T E : I I D 2 i s always a logic 0 in character mode. IP - Interrupt Pending: When logic 0, indicates that an interrupt is p e n d i n g a n d t h e c o n t e n t s o f t h e i n t e r r u p t identification register may be used to determine the interrupt source. See IIDx and figure 5. *For optional 16550 only

+---------------------+----------+---------------------+ | x x x 1 | N/A | None | | 0 1 1 0 | Highest | Receiver Line Status| | 0 1 0 0 | Second | Received Data Ready | | 1 1 0 0 | Second | Character Timeout | | | | (FIFO only) * | | 0 0 1 0 | Third | Transmitter Holding | | | | Register Empty | | 0 0 0 0 | Fourth | MODEM Status | +---------------------+----------+---------------------+ Figure 5. Interrupt Identification bit definitions. Receiver Line Status: I n d i c a t e s o v e r r u n , p a r i t y , f r a m i n g e r r o r s o r break interrupts. The interrupt is cleared by reading the line status register. Received Data Ready: Indicates receive data available. The interrupt is cleared by reading the receive buffer. FIFO mode:* Indicates the receiver FIFO trigger level has been reached. The interrupt is reset when the FIFO drops below the the trigger level. Character Timeout: * (FIFO mode only) Indicates no characters have been removed from or input to the receiver FIFO for the last four character times and there is data present in the r e c e i v e r F I F O . T h e i n t e r r u p t i s c l e a r e d b y reading the receiver FIFO. Transmitter Holding Register Empty: Indicates the transmitter holding register is empty. The interrupt is cleared by reading the interrupt identification register or writing to the transmitter holding register. MODEM Status: Indicates clear to send, data set ready, ring indicator, or data carrier detect have changed state. The interrupt is cleared by reading the MODEM status register. *For optional 16550 only.

+------+ D7 | RXT1 |--+ +------+ +-- Receiver trigger * D6 | RXT0 |--+ +------+ D5 | x |--+ +------+ +-- Reserved D4 | x |--+ +------+ D3 | DMAM |----- DMA mode select * +------+ D2 | XRST |----- Transmit FIFO reset * +------+ D1 | RRST |----- Receive FIFO reset * +------+ D0 | FE |----- FIFO enable * +------+ Figure 6. FIFO Control Register bit definitions. RXTx - Receiver FIFO Trigger Level: * Determines the trigger level for the receiver FIFO interrupt as given in figure 7 below. +-----------+-----------------------+ | | RCVR FIFO | | RXT1 RXT0 | Trigger level (bytes) | +-----------+-----------------------+ | 0 0 | 1 | | 0 1 | 4 | | 1 0 | 8 | | 1 1 | 14 | +-----------+-----------------------+ Figure 7. FIFO Trigger Levels. DMAM - DMA Mode Select: * When set (logic 1), RxRDY and TxRDY change from mode 0 to mode 1 for DMA transfers. (DMA mode not supported on QS-200M/QS-300M.) XRST - Transmit FIFO Reset: * When set (logic 1), all bytes in the transmitter FIFO are cleared and the counter is reset. The shift register is not cleared. XRST is self- clearing. *For optional 16550 only.

* When set (logic 1), all bytes in the receiver FIFO are cleared and the counter is reset. The shift register is not cleared. RRST is self- clearing. FE - FIFO Enable: * W h e n s e t ( l o g i c 1 ) , e n a b l e s t r a n s m i t t e r a n d receiver FIFOs. When cleared (logic 0), all bytes in both FIFOs are cleared. This bit must b e s e t w h e n o t h e r b i t s i n t h e F I F O c o n t r o l r e g i s t e r a r e w r i t t e n t o o r t h e b i t s w i l l b e ignored. I I I D . LINE CONTROL REGISTER +------+ D7 | DLAB |----- Divisor latch access bit +------+ D6 | BKCN |----- Break control +------+ D5 | STKP |----- Stick parity +------+ D4 | EPS |----- Even parity select +------+ D3 | PEN |----- Parity enable +------+ D2 | STB |----- Number of stop bits +------+ D1 | WLS1 |--+ +------+ +-- Word length select D0 | WLS0 |--+ +------+ Figure 8. Line Control Register bit definitions. DLAB - Divisor Latch Access Bit: DLAB must be set to logic 1 to access the baud rate divisor latches. DLAB must be set to logic 0 to access the receiver buffer, transmitting holding register and interrupt enable register. BKCN - Break Control: When set (logic 1), the serial output (SOUT) is forced to the spacing state (logic 0). *For optional 16550 only.

Forces parity to logic 1 or logic 0 if parity is enabled. See EPS, PEN, and figure 9. EPS - Even Parity Select: Selects even or odd parity if parity is enabled. See STKP, PEN, and figure 9. PEN - Parity Enable: Enables parity on transmission and verification on reception. See EPS, STKP, and figure 9. +--------------+---------+ | STKP EPS PEN | Parity | +--------------+---------+ | x x 0 | None | | 0 0 1 | Odd | | 0 1 1 | Even | | 1 0 1 | Logic 1 | | 1 1 1 | Logic 0 | +--------------+---------+ Figure 9. 16450 Parity Selections. STB - Number of Stop Bits: Sets the number of stop bits transmitted. See WLSx and figure 10. WLSx - Word Length Select: Determines the number of bits per transmitted word. See STB and figure 10. +---------------+-------------+-----------+ | STB WLS1 WLS0 | Word length | Stop bits | +---------------+-------------+-----------+ | 0 0 0 | 5 bits | 1 | | 0 0 1 | 6 bits | 1 | | 0 1 0 | 7 bits | 1 | | 0 1 1 | 8 bits | 1 | | 1 0 0 | 5 bits | 1½ | | 1 0 1 | 6 bits | 2 | | 1 1 0 | 7 bits | 2 | | 1 1 1 | 8 bits | 2 | +---------------+-------------+-----------+ Figure 10. Word Length and Stop Bit selections.

+------+ D7 | 0 | +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | LOOP |----- Loopback enable +------+ D3 | OUT2 |----- Output 2 +------+ D2 | OUT1 |----- Output 1 +------+ D1 | RTS |----- Request to send +------+ D0 | DTR |----- Data terminal ready +------+ Figure 11. MODEM Control Register bit definitions. LOOP - Loopback Enable: W h e n s e t ( l o g i c 1 ) , t h e t r a n s m i t t e r s h i f t register is connected directly to the receiver shift register. The MODEM control inputs are i n t e r n a l l y c o n n e c t e d t o t h e M O D E M c o n t r o l o u t p u t s a n d t h e o u t p u t s a r e f o r c e d t o t h e inactive state. All characters transmitted are i m m e d i a t e l y r e c e i v e d t o v e r i f y t r a n s m i t a n d receive data paths. Transmitter and receiver i n t e r r u p t s s t i l l o p e r a t e n o r m a l l y . M O D E M c o n t r o l i n t e r r u p t s a r e a v a i l a b l e b u t a r e n o w controlled through the MODEM control register. B i t s O U T 2 , O U T 1 , R T S , a n d D T R p e r f o r m i d e n t i c a l functions on their respective outputs. When these b i t s a r e s e t ( l o g i c 1 ) i n t h e r e g i s t e r , t h e a s s o c i a t e d o u t p u t i s f o r c e d t o a l o g i c 0 . W h e n cleared (logic 0), the output is forced to a logic1. OUT2 - Output 2: Controls the OUT2 output as described above. OUT1 - Output 1: Controls the OUT1 output as described above. RTS - Request To Send: Controls the RTS output as described above. DTR - Data Terminal Ready: C o n t r o l s t h e D T R o u t p u t a s d e s c r i b e d a b o v e . Used for transmitter enable (see section VIII).

+------+ D7 | FFRX |----- Error in FIFO RCVR (FIFO only) * +------+ D6 | TEMT |----- Transmitter empty +------+ D5 | THRE |----- Transmitter holding register empty +------+ D4 | BI |----- Break interrupt +------+ D3 | FE |----- Framing error +------+ D2 | PE |----- Parity error +------+ D1 | OE |----- Overrun error +------+ D0 | DR |----- Data ready +------+ Figure 12. Line Status register bit definitions. FFRX - FIFO Receiver Error: * Always logic 0 in character mode. FIFO mode: * I n d i c a t e s o n e o r m o r e p a r i t y e r r o r s , f r a m i n g e r r o r s , o r b r e a k i n d i c a t i o n s i n t h e r e c e i v e r FIFO. FFRX is reset by reading the line status register. TEMT - Transmitter Empty: Indicates the transmitter holding register (or FIFO*) and the transmitter shift register are empty and are ready to receive new data. TEMT i s r e s e t b y w r i t i n g a c h a r a c t e r t o t h e transmitter holding register. THRE - Transmitter Holding Register Empty: Indicates the transmitter holding register (or FIFO*) is empty and it is ready to accept new d a t a . T H R E i s r e s e t b y w r i t i n g d a t a t o t h e transmitter holding register. *For optional 16550 only.

l i n e s t a t u s i n t e r r u p t s . T h e b i t s a r e r e s e t b y reading the line status register. In FIFO mode*, these bits are associated with a specific character in the FIFO and the exception is revealed only when that character reaches the top of the FIFO. BI - Break Interrupt: Indicates the receive data input has been in the spacing state (logic 0) for longer than one full word transmission time. FIFO mode: * Only one zero character is loaded into the FIFO and transfers are disabled until SIN goes to the mark state (logic 1) and a valid start bit is received. FE - Framing Error: Indicates the received character had an invalid stop bit. The stop bit following the last data or parity bit was a 0 bit (spacing level). PE - Parity Error: Indicates that the received data does not have the correct parity. OE - Overrun Error: Indicates the receive buffer was not read before t h e n e x t c h a r a c t e r w a s r e c e i v e d a n d t h e character is destroyed. FIFO mode: * Indicates the FIFO is full and another character has been shifted in. The character in the shift register is destroyed but is not transferred to the FIFO. DR - Data ready: Indicates data is present in the receive buffer or FIFO. DR is reset by reading the receive buffer register or receiver FIFO. *For optional 16550 only.

+------+ D7 | DCD |----- Data carrier detect +------+ D6 | RI |----- Ring indicator +------+ D5 | DSR |----- Data set ready +------+ D4 | CTS |----- Clear to send +------+ D3 | DDCD |----- Delta data carrier detect +------+ D2 | TERI |----- Trailing edge ring indicator +------+ D1 | DDSR |----- Delta data set ready +------+ D0 | DCTS |----- Delta clear to send +------+ Figure 13. MODEM Status register bit definitions. DCD - Data Carrier Detect: Complement of the DCD input. RI - Ring Indicator: Complement of the RI input. DSR - Data Set Ready: Complement of the DSR input. CTS - Clear To Send: Complement of the CTS input. Bits DDCD, TERI, DDSR, and DCTS are the sources of MODEM status interrupts. These bits are reset when the MODEM status register is read. DDCD - Delta Data Carrier Detect: I n d i c a t e s t h e D a t a C a r r i e r D e t e c t i n p u t h a s changed state. TERI - Trailing Edge Ring Indicator: Indicates the Ring Indicator input has changed from a low to a high state. DDSR - Delta Data Set Ready: Indicates the Data Set Ready input has changed state. DCTS - Delta Clear To Send: Indicates the Clear to Send input has changed state.

This register is not used by the 16450/16550. It may be used by the programmer for data storage. IV. FIFO INTERRUPT MODE OPERATION * 1. The receive data interrupt is issued when the FIFO reaches the trigger level. The interrupt is c l e a r e d a s s o o n a s t h e F I F O f a l l s b e l o w t h e trigger level. 2. The interrupt identification register's receive data available indicator is set and cleared along with the receive data interrupt above. 3. The data ready indicator is set as soon as a character is transferred into the receiver FIFO and is cleared when the FIFO is empty. V. BAUD RATE SELECTION The 16450 ACE determines the baud rate of the serial o u t p u t a n d u s e s a c o m b i n a t i o n o f t h e c l o c k i n p u t frequency and the value written to the divisor latches. Standard PC, PC/XT, PC/AT, and PS/2 serial interfaces use an input clock of 1.8432 MHz. To increase versatility, the QS-200M/QS-300M uses an 18.432 MHz crystal and a frequency divider circuit to produce the standard clock frequency. Jumper block J1 is used to set the frequency input to the 16450. It may be connected to divide the clock input by 1, 2, 5, or 10. For compatibility as stated above, J1 should be configured to divide by 10 as shown in figure 14(d). A table of baud rates available using the 1.8432 MHz input is given in figure 14. *For optional 16550 only.

J1 J1 +-----------+ +-----------+ 4| _ _+ _ |6 4| _ _--_ |6 1| _ _+ _ |3 1| _--_ _ |3 +-----------+ +-----------+ (a) ÷1 input clock (b) ÷2 input clock J1 J1 +-----------+ +-----------+ 4| _--_ _ |6 4| _+ _--_ |6 1| _ _--_ |3 1| _+ _--_ |3 +-----------+ +-----------+ (c) ÷5 input clock (d) ÷10 input clock Figure 14. Input Clock Frequency Options. For compatibility, the jumper should be set at ÷10 ( 18.432 MHz ÷ 10 = 1.8432 MHz ). +-----------+-------------+-----------------------+ | Desired | Divisor | Error Between Desired | | Baud Rate | Latch Value | and Actual Value (%) | +-----------+-------------+-----------------------+ | 50 | 2304 | - | | 75 | 1536 | - | | 110 | 1047 | 0.026 | | 150 | 768 | - | | 300 | 384 | - | | 600 | 192 | - | | 1200 | 96 | - | | 1800 | 64 | - | | 2000 | 58 | 0.69 | | 2400 | 48 | - | | 3600 | 32 | - | | 4800 | 24 | - | | 7200 | 16 | - | | 9600 | 12 | - | | 19200 | 6 | - | | 38400 | 3 | - | | 56000 | 2 | 2.86 | +-----------+-------------+-----------------------+ Figure 15. Divisor latch settings for common baud r a t e s u s i n g a n 1 . 8 4 3 2 M H z i n p u t c l o c k . For compatibility, connect jumper in the divide by 10 configuration (figure 14(d)).

VI. ADDRESSING The QS-200M/QS-300M uses 8 I/O address locations per channel. Full sixteen bit address decoding allows base address selections in the range 0000 - FFFF Hex. Two six position switches, SW1 & SW2 are used to specify t h e b a s e a d d r e s s o f t h e a d a p t e r . S W 1 c o n t r o l s t h e a d d r e s s s e t t i n g f o r A 1 5 - A 1 0 t h r o u g h p o s i t i o n s 1 - 6 respectively. Switch SW2, positions 1-5 control address selections for A9-A5. The remaining address inputs are used by the adapter to determine the channel and register being accessed. A switch in the "ON" position indicates that the corresponding address bit be a logic 0 for selection. A switch in the "OFF" position forces the corresponding address bit to be a logic 1 for selection. Some example switch settings for the QS-200M/QS-300M are shown in figures 16 and 17. The base address of each channel is incremented by a f a c t o r o f 8 f r o m t h e b a s e a d d r e s s o f t h e a d a p t e r . Therefore 32 address locations are used by the QS-200M/ QS-300M. PORT ADDRESS RANGE 1 Base Address+0 - Base Address+7 2 Base Address+8 - Base Address+15 3 Base Address+16 - Base Address+23 4 Base Address+24 - Base Address+31 +--------------------+ +--------------------+ | 1 2 3 4 5 6 | | 1 2 3 4 5 6 | On| +-++-++-++-++-++-+ | On| +-++-++-++-++-++-+ | | |_||_||_||_||_||_| | | | || ||_||_||_|| | | | | || || || || || | | | |_||_|| || || || | | Off| +-++-++-++-++-++-+ | Off| +-++-++-++-++-++-+ | +--------------------+ +--------------------+ SW1 SW2 Figure 16. Factory address switch settings. Address shown is 0300H.

1 2 3 4 5 6 1 2 3 4 5 6 On +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ |_||_||_||_| |_||_|| || | |_||_||_| | | | || || || | | || ||_||_| | || || | | | Off +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ 0 0 0 0 0 0 2 1 0 0 0 0 3 0 0 = 0300H BASE ADDRESS = 06A0H 1 2 3 4 5 6 1 2 3 4 5 6 On +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ |_||_||_||_| |_|| || ||_| | ||_|| | | | | || || || | | ||_||_|| | |_|| ||_| | | Off +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ 0 0 0 0 0 4 2 0 8 0 2 0 6 A 0 = 06A0H BASE ADDRESS = 5220H 1 2 3 4 5 6 1 2 3 4 5 6 On +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ |_|| ||_|| | |_||_|| ||_| |_||_|| | | | | ||_|| ||_| | || ||_|| | | || ||_| | | Off +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ 0 4 0 1 0 0 2 0 0 0 2 5 2 2 0 = 5220H Figure 17. Address switch selection examples.

interrupt levels, IRQ 2-7. All of the channels share the same interrupt. The selection of interrupt levels can be changed through a hardware jumper, J3, as shown below: Source + | | 1 7 +--_ _-- IRQ 2(9) | _ _-- IRQ 3 | _ _-- IRQ 4 J3 | _ _-- IRQ 5 | _ _-- IRQ 6 | _ _-- IRQ 7 6 12 Figure 18. Interrupt level selection jumper. T h e Q S - 2 0 0 M / Q S - 3 0 0 M i s a l s o e q u i p p e d w i t h a n interrupt sharing circuit. This circuit allows the QS- 200M/QS-300M to share its interrupt with other Qua Tech adapters supporting this feature.

An interrupt status register is implemented on the Q S - 2 0 0 M / Q S - 3 0 0 M t o r e d u c e t h e i n t e r r u p t s e r v i c i n g o v e r h e a d a s s o c i a t e d w i t h m u l t i - p o r t c o m m u n i c a t i o n s . S c r a t c h p a d / I n t e r r u p t S t a t u s r e g i s t e r s e l e c t i o n i s controlled by position 6 on SW2. When position 6 is in the OFF position, there is no Interrupt Status register, a n d a l l o f t h e 1 6 4 5 0 / 1 6 5 5 0 s b e h a v e n o r m a l l y . W h e n position 6 is in the ON position, the Interrupt Status register overrides the ACEs internal Scratchpad register. I n t h i s m o d e , a n i n p u t f r o m t h e S c r a t c h p a d r e g i s t e r address (BASE ADDRESS + 7) of any channel will return the interrupt status of the entire card. SW2 +---------------------------+ | 1 2 3 4 5 6 | |ON +-+ +-+ +-+ +-+ +-+ +-+ |Interrupt Status | | | | | | | | | | | |_| | | | | | | | | | | | | | | | | +-+ +-+ +-+ +-+ +-+ +-+ |Scratchpad +---------------------------+ Figure 19. Scratchpad/Interrupt Status select. +------+ D7 | 0 | +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IP4 | +------+ D4 | IP3 | +------+ D1 | IP2 | +------+ D0 | IP1 | +------+ Figure 20. Interrupt Status register for the QS-200M/QS-300M. IPx set (logic 1), indicates an interrupt is pending on the associated channel.

T h e f u n c t i o n o f j u m p e r J 2 i s t o c o n f i g u r e t h e communication channels in half or full duplex mode. Half duplex operation is achieved by installing a jumper block over the pins for the specific channel (figure 21). This c o n n e c t i o n a l l o w s t h e t r a n s m i t t e r t o b e e n a b l e d a n d disabled using the data terminal ready (DTR) output which is controlled through the modem control register of the 16450/16550. When DTR is set (logic 1), the transmitter d r i v e r i s e n a b l e d f o r o u t p u t o n t h e c h a n n e l . W h e n cleared, (logic 0), the transmitter output enters a high impedance state. Full duplex operation is restored by removing the associated jumper. C A U T I O N : W h e n o p e r a t i n g i n h a l f d u p l e x m o d e , t h e transmitter must be disabled before receiving any information. Failure to do so may result in multiple output drivers being connected together which may cause damage to the QS- 200M/QS-300M, the computer and the peripheral equipment. +---------- Output enable 1 | +------- Output enable 2 | | +---- Output enable 3 | | | +- Output enable 4 +--------------+ 5 | _ _ _ _ | 8 1 | _ _ _ _ | 4 J2 +--------------+ DTR 1 -+ | | | DTR 2 ----+ | | DTR 3 -------+ | DTR 4 ----------+ Figure 21. Half duplex jumper configuration.

output configuration jumpers on the card. 2. Turn unit off. 3. Remove system cover as instructed in the computer reference guide. 4. Insert card into a vacant slot following the guidelines for installation. 5. Replace system cover. XI. SPECIFICATIONS Bus interface: IBM 8-bit bus (PC/XT) Dimensions: 8.25" x 3.9" Controllers: 4 - 16450 Asynchronous Communication Elements Transmit drivers: MC3487 or compatible Receive buffers: MC3486 or compatible RS-422 interface: 4 - RJ-11 shielded connectors I/O Address range: 0000-FFFFH (See section VI) Interrupt levels: IRQ 2(9),3-7 Power requirements: +--------+--------+-----------+ | I T | I MS | Supply | +--------+--------+-----------+ | 501mA | 576mA | +5 Volts | +--------+--------+-----------+ | -- | -- | +12 Volts | +--------+--------+-----------+ | -- | -- | -12 Volts | +--------+--------+-----------+ I T - Typical adapter current I MS - Maximum statistical adapter current