Motorola MVME2300 Series Programmer's Reference Manual

Programmer’s Reference Guide V2300A/PG5 Edition of June 2001

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equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment. Ground the Instrument. To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes. Do Not Operate in an Explosive Atmosphere. Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage. Keep Away From Live Circuits Inside the Equipment. Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Service personnel should not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel should always disconnect power and discharge circuits before touching components. Use Caution When Exposing or Handling a CRT. Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves. Do Not Substitute Parts or Modify Equipment. Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that all safety features are maintained. Observe Warnings in Manual. Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment. Warning To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its components.

of 94V-0 by UL-recognized manufacturers. EMI Caution ! Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection. Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry. ! Caution Danger of explosion if battery is replaced incorrectly. Replace battery only with the same or equivalent type recommended by the equipment manufacturer. Dispose of used batteries according to the manufacturer’s instructions. Attention ! Il y a danger d’explosion s’il y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du même type ou d’un type équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fabricant. Vorsicht ! Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ. Entsorgung gebrauchter Batterien nach Angaben des Herstellers.

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Summary of Changes..................................................................................................xx Overview of Contents ................................................................................................xxi Comments and Suggestions .......................................................................................xxi Conventions Used in This Manual............................................................................xxii CHAPTER 1 Board Description and Memory Maps Introduction................................................................................................................1-1 Overview....................................................................................................................1-1 Summary of Features .................................................................................................1-2 System Block Diagram ..............................................................................................1-3 Functional Description...............................................................................................1-6 VMEbus Interface...............................................................................................1-6 Front Panel..........................................................................................................1-6 PCI interface .......................................................................................................1-7 P2 I/O...........................................................................................................1-7 Programming Model ..................................................................................................1-7 Processor Memory Maps ....................................................................................1-7 Default Processor Memory Map..................................................................1-8 Processor CHRP Memory Map...................................................................1-9 Processor PREP Memory Map..................................................................1-11 PCI Configuration Access .........................................................................1-12 PCI Memory Maps............................................................................................1-13 Default PCI Memory Map.........................................................................1-13 PCI CHRP Memory Map ..........................................................................1-13 PCI PREP Memory Map ...........................................................................1-16 VMEbus Mapping.............................................................................................1-20 VMEbus Master Map ................................................................................1-20 VMEbus Slave Map...................................................................................1-21 Falcon-Controlled System Registers ................................................................1-24 System Configuration Register (SYSCR) .................................................1-25 Memory Configuration Register (MEMCR).............................................1-27 System External Cache Control Register (SXCCR)..................................1-29 Processor 0 External Cache Control Register (P0XCCR).........................1-30 Processor 1 External Cache Control Register (P1XCCR).........................1-30

ISA Local Resource Bus..........................................................................................1-31 W83C553 PIB Registers ..................................................................................1-31 16550 UART ....................................................................................................1-31 General-Purpose Readable Jumpers.................................................................1-32 NVRAM/RTC and Watchdog Timer Registers................................................1-32 Module Configuration and Status Registers.....................................................1-33 CPU Configuration Register .....................................................................1-34 Base Module Feature Register ..................................................................1-35 Base Module Status Register (BMSR)......................................................1-36 Seven-Segment Display Register..............................................................1-37 VME Registers .................................................................................................1-37 LM/SIG Control Register..........................................................................1-38 LM/SIG Status Register ............................................................................1-39 Location Monitor Upper Base Address Register ......................................1-41 Location Monitor Lower Base Address Register......................................1-41 Semaphore Register 1 ...............................................................................1-42 Semaphore Register 2 ...............................................................................1-42 VME Geographical Address Register (VGAR)........................................1-43 Emulated Z8536 CIO Registers and Port Pins .................................................1-43 Emulated Z8536 Registers ........................................................................1-43 Z8536 CIO Port Pins.................................................................................1-44 ISA DMA Channels .........................................................................................1-45 CHAPTER 2 Raven PCI Bridge ASIC Introduction ............................................................................................................... 2-1 Features......................................................................................................................2-1 Block Diagram...........................................................................................................2-2 Functional Description .............................................................................................. 2-4 MPC Bus Interface ............................................................................................. 2-4 MPC Address Mapping...............................................................................2-4 MPC Slave .................................................................................................. 2-6 MPC Write Posting .....................................................................................2-8 MPC Master ................................................................................................2-8 MPC Arbiter..............................................................................................2-10 MPC Bus Timer ........................................................................................2-10 PCI Interface.....................................................................................................2-10 PCI Address Mapping...............................................................................2-11 PCI Slave...................................................................................................2-14 PCI Write Posting .....................................................................................2-17

Endian Conversion............................................................................................2-25 When MPC Devices are Big-Endian.........................................................2-25 When MPC Devices are Little-Endian ......................................................2-27 Raven Registers and Endian Mode............................................................2-27 Error Handling..................................................................................................2-28 Transaction Ordering ........................................................................................2-29 Raven Registers .......................................................................................................2-30 MPC Registers..................................................................................................2-30 Vendor ID/Device ID Registers ................................................................2-32 Revision ID Register .................................................................................2-33 General Control-Status/Feature Registers .................................................2-33 MPC Arbiter Control Register...................................................................2-36 Prescaler Adjust Register...........................................................................2-36 MPC Error Enable Register.......................................................................2-37 MPC Error Status Register ........................................................................2-39 MPC Error Address Register.....................................................................2-40 MPC Error Attribute Register - MERAT ..................................................2-41 PCI Interrupt Acknowledge Register ........................................................2-43 MPC Slave Address (0,1 and 2) Registers ................................................2-43 MPC Slave Address (3) Register...............................................................2-44 MPC Slave Offset/Attribute (0,1 and 2) Registers....................................2-45 MPC Slave Offset/Attribute (3) Registers.................................................2-46 General-Purpose Registers ........................................................................2-47 PCI Registers ....................................................................................................2-47 Vendor ID/ Device ID Registers ...............................................................2-49 PCI Command/ Status Registers................................................................2-50 Revision ID/ Class Code Registers............................................................2-52 I/O Base Register.......................................................................................2-52 Memory Base Register ..............................................................................2-53 PCI Slave Address (0,1,2 and 3) Registers................................................2-54 PCI Slave Attribute/ Offset (0,1,2 and 3) Registers ..................................2-55 CONFIG_ADDRESS Register..................................................................2-56 CONFIG_DATA Register.........................................................................2-58 Raven Interrupt Controller.......................................................................................2-60 Features.............................................................................................................2-60 Architecture ......................................................................................................2-60 Readability of CSR....................................................................................2-61 Interrupt Source Priority............................................................................2-61 Processor’s Current Task Priority..............................................................2-61

Spurious Vector Generation......................................................................2-62 Interprocessor Interrupts (IPI)...................................................................2-62 8259 Compatibility....................................................................................2-62 Raven-Detected Errors..............................................................................2-63 Timers .......................................................................................................2-63 Interrupt Delivery Modes..........................................................................2-64 Block Diagram Description..............................................................................2-65 Program-Visible Registers ........................................................................2-66 Interrupt Pending Register (IPR) ..............................................................2-66 Interrupt Selector (IS) ...............................................................................2-66 Interrupt Request Register (IRR) ..............................................................2-67 In-Service Register (ISR)..........................................................................2-67 Interrupt Router.........................................................................................2-67 MPIC Registers ................................................................................................2-69 RavenMPIC Registers...............................................................................2-69 Feature Reporting Register .......................................................................2-73 Global Configuration Register ..................................................................2-74 Vendor Identification Register..................................................................2-75 Processor Init Register ..............................................................................2-75 IPI Vector/Priority Registers.....................................................................2-76 Spurious Vector Register ..........................................................................2-77 Timer Frequency Register.........................................................................2-77 Timer Current Count Registers .................................................................2-78 Timer Base Count Registers......................................................................2-78 Timer Vector/Priority Registers................................................................2-79 Timer Destination Registers......................................................................2-80 External Source Vector/Priority Registers................................................2-81 External Source Destination Registers......................................................2-82 Raven-Detected Errors Vector/Priority Register ......................................2-83 Raven-Detected Errors Destination Register ............................................2-84 Interprocessor Interrupt Dispatch Registers..............................................2-84 Interrupt Task Priority Registers...............................................................2-85 Interrupt Acknowledge Registers..............................................................2-86 End-of-Interrupt Registers ........................................................................2-86 Programming Notes..........................................................................................2-87 External Interrupt Service .........................................................................2-87 Reset State.................................................................................................2-88 Interprocessor Interrupts ...........................................................................2-89 Dynamically Changing I/O Interrupt Configuration.................................2-89 EOI Register..............................................................................................2-90 Interrupt Acknowledge Register ...............................................................2-90

Architectural Notes...........................................................................................2-91 CHAPTER 3 Falcon ECC Memory Controller Chip Set Introduction................................................................................................................3-1 Features......................................................................................................................3-1 Block Diagrams .........................................................................................................3-2 Functional Description...............................................................................................3-5 Bit Ordering Convention ....................................................................................3-5 Performance........................................................................................................3-5 Four-beat Reads/Writes...............................................................................3-5 Single-beat Reads/Writes ............................................................................3-6 DRAM Speeds.............................................................................................3-6 ROM/Flash Speeds....................................................................................3-10 PowerPC 60x Bus Interface..............................................................................3-11 Responding to Address Transfers..............................................................3-11 Completing Data Transfers........................................................................3-11 Cache Coherency.......................................................................................3-11 Cache Coherency Restrictions...................................................................3-12 L2 Cache Support ......................................................................................3-12 ECC...................................................................................................................3-12 Cycle Types...............................................................................................3-12 Error Reporting..........................................................................................3-13 Error Logging ............................................................................................3-14 DRAM Tester....................................................................................................3-14 ROM/Flash Interface ........................................................................................3-14 Refresh/Scrub....................................................................................................3-18 Blocks A and/or B Present, Blocks C and D Not Present .........................3-18 Blocks A and/or B Present, Blocks C and/or D Present............................3-19 DRAM Arbitration............................................................................................3-20 Chip Defaults....................................................................................................3-20 External Register Set ........................................................................................3-21 CSR Accesses ...................................................................................................3-21 Programming Model ................................................................................................3-21 CSR Architecture..............................................................................................3-21 Register Summary.............................................................................................3-27 Detailed Register Bit Descriptions ...................................................................3-27 Vendor/Device Register ............................................................................3-30 Revision ID/ General Control Register .....................................................3-31

DRAM Base Register................................................................................3-35 CLK Frequency Register...........................................................................3-35 ECC Control Register ...............................................................................3-36 Error Logger Register ...............................................................................3-39 Error Address Register..............................................................................3-42 Scrub/Refresh Register..............................................................................3-43 Refresh/Scrub Address Register ...............................................................3-44 ROM A Base/Size Register.......................................................................3-45 ROM B Base/Size Register.......................................................................3-48 DRAM Tester Control Registers...............................................................3-50 32-Bit Counter...........................................................................................3-50 Test SRAM................................................................................................3-50 Power-Up Reset Status Register 1 ............................................................3-51 Power-Up Reset Status Register 2 ............................................................3-51 External Register Set.................................................................................3-52 Software Considerations..........................................................................................3-53 Parity Checking on the PowerPC Bus..............................................................3-53 Programming ROM/Flash Devices ..................................................................3-53 Writing to the Control Registers.......................................................................3-53 Sizing DRAM...................................................................................................3-54 ECC Codes .......................................................................................................3-57 Data Paths.........................................................................................................3-60 CHAPTER 4 Universe (VMEbus to PCI) Chip Introduction ............................................................................................................... 4-1 Features......................................................................................................................4-1 Block Diagram...........................................................................................................4-3 Functional Description .............................................................................................. 4-3 VMEbus Interface .............................................................................................. 4-4 Universe as VMEbus Slave.........................................................................4-4 Universe as VMEbus Master ...................................................................... 4-5 PCI Bus Interface ...............................................................................................4-5 Universe as PCI Slave................................................................................. 4-6 Universe as PCI Master...............................................................................4-6 Interrupter...........................................................................................................4-6 VMEbus Interrupt Handling ....................................................................... 4-7 DMA Controller .................................................................................................4-7 Universe Control and Status Registers (UCSR)................................................. 4-8 Universe Register Map................................................................................4-9

Description.................................................................................................4-14 Workarounds .............................................................................................4-15 Examples...........................................................................................................4-16 Example 1: MVME2600 Series Board Exhibits PCI Reset Problem........4-16 Example 2: MVME3600 Series Board Acts Differently...........................4-17 Example 3: Universe Chip is Checked at Tundra......................................4-19 CHAPTER 5 Programming Details Introduction................................................................................................................5-1 PCI Arbitration...........................................................................................................5-1 Interrupt Handling......................................................................................................5-2 RavenMPIC ........................................................................................................5-3 8259 Interrupts....................................................................................................5-4 ISA DMA Channels...................................................................................................5-7 Exceptions..................................................................................................................5-8 Sources of Reset..................................................................................................5-8 Soft Reset............................................................................................................5-9 Universe Chip Problems after PCI Reset............................................................5-9 Error Notification and Handling.......................................................................5-10 Endian Issues ...........................................................................................................5-11 Processor/Memory Domain..............................................................................5-13 Role of the Raven ASIC ...................................................................................5-13 PCI Domain ......................................................................................................5-13 PCI-SCSI ...................................................................................................5-13 PCI/Ethernet ..............................................................................................5-13 PCI-Graphics .............................................................................................5-14 Role of the Universe ASIC...............................................................................5-14 VMEbus Domain..............................................................................................5-14 ROM/Flash Initialization .........................................................................................5-15 APPENDIX A Related Documentation Motorola Computer Group Documents ....................................................................A-1 Manufacturers’ Documents.......................................................................................A-2 Related Specifications...............................................................................................A-4

Figure 1-1. MVME2300 Series System Block Diagram ...........................................1-5 Figure 1-2. VMEbus Master Mapping.....................................................................1-20 Figure 1-3. VMEbus Slave Mapping.......................................................................1-22 Figure 1-4. General-Purpose Software-Readable Header........................................1-32 Figure 2-1. Raven Block Diagram.............................................................................2-3 Figure 2-2. MPC-to-PCI Address Decoding..............................................................2-5 Figure 2-3. MPC to PCI Address Translation............................................................2-6 Figure 2-4. PCI to MPC Address Decoding ............................................................2-12 Figure 2-5. PCI to MPC Address Translation..........................................................2-13 Figure 2-6. PCI Spread I/O Address Translation.....................................................2-22 Figure 2-7. Big- to Little-Endian Data Swap...........................................................2-26 Figure 2-8. RavenMPIC Block Diagram .................................................................2-65 Figure 3-1. Falcon Pair Used with DRAM in a System ............................................3-2 Figure 3-2. Falcon Internal Data Paths (Simplified)..................................................3-3 Figure 3-3. Overall DRAM Connections...................................................................3-4 Figure 3-4. Data Path for Reads from the Falcon Internal CSRs.............................3-22 Figure 3-5. Data Path for Writes to the Falcon Internal CSRs.................................3-23 Figure 3-6. Memory Map for Byte Reads to CSR...................................................3-24 Figure 3-7. Memory Map for Byte Writes to Internal Register Set and Test SRAM........................................................................................................3-25 Figure 3-8. Memory Map for 4-Byte Reads to CSR................................................3-26 Figure 3-9. Memory Map for 4-Byte Writes to Internal Register Set and Test SRAM........................................................................................................3-26 Figure 3-10. PowerPC Data to DRAM Data Correspondence.................................3-60 Figure 4-1. Architectural Diagram for the Universe..................................................4-4 Figure 4-2. UCSR Access Mechanisms.....................................................................4-9 Figure 5-1. MVME2300 Series Interrupt Architecture..............................................5-2 Figure 5-2. PIB Interrupt Handler Block Diagram ....................................................5-5 Figure 5-3. Big-Endian Mode..................................................................................5-11 Figure 5-4. Little-Endian Mode ...............................................................................5-12

Table 1-1. Features: MVME2300 Series....................................................................1-2 Table 1-2. Default Processor Memory Map...............................................................1-8 Table 1-3. CHRP Memory Map Example..................................................................1-9 Table 1-4. Raven MPC Register Values for CHRP Memory Map...........................1-10 Table 1-5. PREP Memory Map Example.................................................................1-11 Table 1-6. Raven MPC Register Values for PREP Memory Map ...........................1-12 Table 1-7. PCI CHRP Memory Map........................................................................1-13 Table 1-8. Raven PCI Register Values for CHRP Memory Map.............................1-15 Table 1-9. Universe PCI Register Values for CHRP Memory Map.........................1-15 Table 1-10. PCI PREP Memory Map.......................................................................1-16 Table 1-11. Raven PCI Register Values for PREP Memory Map............................1-18 Table 1-12. Universe PCI Register Values for PREP Memory Map........................1-19 Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example ........1-23 Table 1-14. VMEbus Slave Map Example...............................................................1-24 Table 1-15. System Register Summary....................................................................1-24 Table 1-16. 16550 Access Registers ........................................................................1-31 Table 1-17. M48T59/559 Access Registers .............................................................1-33 Table 1-18. Module Configuration and Status Registers .........................................1-33 Table 1-19. VME Registers......................................................................................1-38 Table 1-20. Emulated Z8536 Access Registers .......................................................1-43 Table 1-21. Z8536 CIO Port Pin Assignments ........................................................1-44 Table 2-1. Features of the Raven ASIC .....................................................................2-1 Table 2-2. Command Types — MPC Slave Response...............................................2-7 Table 2-3. MPC Transfer Types.................................................................................2-9 Table 2-4. Command Types — PCI Slave Response...............................................2-15 Table 2-5. PCI Master Command Codes .................................................................2-18 Table 2-6. Address Modification for Little-Endian Transfers .................................2-27 Table 2-7. Raven MPC Register Map......................................................................2-31 Table 2-8. Raven PCI Configuration Register Map.................................................2-48 Table 2-9. Raven PCI I/O Register Map..................................................................2-49 Table 2-10. RavenMPIC Register Map....................................................................2-69 Table 3-1. Features of the Falcon Chip Set................................................................3-1 Table 3-2. PowerPC 60x Bus to DRAM Access Timing — 70ns Page Devices.......3-7 Table 3-3. PowerPC 60x Bus to DRAM Access Timing — 60ns Page Devices.......3-8

Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing — 64 Bits (32 Bits per Falcon).................................................................................................3-10 Table 3-6. PowerPC 60x Bus to ROM/Flash Access Timing — 16 Bits (8 Bits per Falcon)...............................................................................................................3-10 Table 3-7. Error Reporting.......................................................................................3-13 Table 3-8. PowerPC 60x to ROM/Flash Address Mapping — ROM/Flash 16 Bits Wide (8 Bits per Falcon) .............................................................................3-16 Table 3-9. PowerPC 60x to ROM/Flash Address Mapping — ROM/Flash 64 Bits Wide (32 Bits per Falcon) ...........................................................................3-17 Table 3-10. Register Summary ................................................................................3-28 Table 3-11. ram spd1,ram spd0 and DRAM Type...................................................3-32 Table 3-12. Block_A/B/C/D Configurations...........................................................3-34 Table 3-13. rtest Encodings .....................................................................................3-43 Table 3-14. ROM Block A Size Encoding ..............................................................3-46 Table 3-15. rom_a_rv and rom_b_rv Encoding.......................................................3-46 Table 3-16. Read/Write to ROM/Flash....................................................................3-47 Table 3-17. ROM Block B Size Encoding ..............................................................3-49 Table 3-18. Sizing Addresses ..................................................................................3-56 Table 3-19. PowerPC 60x Address to DRAM Address Mappings..........................3-56 Table 3-20. Syndrome Codes Ordered by Bit in Error............................................3-57 Table 3-21. Single-Bit Errors Ordered by Syndrome Code.....................................3-59 Table 3-22. PowerPC Data to DRAM Data Mapping .............................................3-61 Table 4-1. Features of the Universe ASIC................................................................. 4-2 Table 4-2. Universe Register Map...........................................................................4-10 Table 5-1. PCI Arbitration Assignments ...................................................................5-1 Table 5-2. RavenMPIC Interrupt Assignments .........................................................5-3 Table 5-3. PIB PCI/ISA Interrupt Assignments ........................................................5-6 Table 5-4. Reset Sources and Devices Affected........................................................5-9 Table 5-5. Error Notification and Handling.............................................................5-10 Table 5-6. ROM/Flash Bank Default......................................................................5-15

The MVME2300 Series VME Processor Module Programmer’s Reference Guide provides board-level information and detailed ASIC information, including register bit descriptions, for the MVME2300 and MVME2300SC series of VME processor modules. The MVME2300 series VME processor module is based on an MPC603 or MPC604 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O. In addition, the MVME2300SC versions of the board give both PMC slots access (via P2) to an SCSA (Signal Computing System Architecture) backplane bus, if the system supports one. The MVME2300 series VME processor module is compatible with optional double-width or single-width PMCs, and with the PMCspan PCI expansion mezzanine module. By utilizing the two onboard PMC slots and stacking PMCspan(s), the MVME2300SC can provide support for up to six PMCs. As of the publication date, the information presented in this manual applies to the following MVME2300 and MVME2300SC models: Model Memory Processor MVME2301 16MB ECC DRAM MPC603 @ 200 MHz MVME2302 32MB ECC DRAM MVME2303 64MB ECC DRAM MVME2304 128MB ECC DRAM MVME2304-0111, -0113, MVME2305* 16MB ECC DRAM MPC604 @ 300*/333 MHz MVME2304-0121, -0121SC, -0123, MVME2306* 32MB ECC DRAM MVME2304-0131, -0131SC, -0133, MVME2307* 64MB ECC DRAM MVME2304-0141, -0141SC, -0143, MVME2308* 128MB ECC DRAM MVME2306SC-1 32MB ECC DRAM MPC604 @ 300 MHz MVME2307SC-1 64MB ECC DRAM

capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in Appendix A, Related Documentation. Summary of Changes This is the fifth edition of the Programmer’s Reference Guide. It supersedes the March 2001 edition and incorporates the following updates. Date Description of Change January 2001 A caution about DRAM component requirements was added to the DRAM Attributes Register and Sizing DRAM sections of Chapter 3. January 2001 In descriptions of the general-purpose software-readable header (J10/J17), such as Figure 1-4 in Chapter 1, information on bit 1 (SRH1) was updated to correctly reflect the functionality of that bit. March 2001 At various locations in the manual, such as P2 I/O on page 1-7, information has been added to accommodate the MVME2300SC variants of the board. The contents of the manual have also been reorganized somewhat to conform with present Computer Group practice for board manuals. June 2001 All data referring to the VME CSR Bit Set Register (VCSR_SET) and VME CSR Bit Clear Register (VCSR_CLR) has been deleted. These registers of the Universe II are unavailable for implementation as intended by the MVME materials and the Universe II User Manual.

Chapter 1, Board Description and Memory Maps, describes the board- level hardware features of MVME2300 series VME processor modules. It includes memory maps and a discussion of some general software considerations such as cache coherency, interrupts, and bus errors. Chapter 2, Raven PCI Bridge ASIC, describes the Raven ASIC, the PCI local bus/PowerPC processor bus interface chip used on MVME2300 series boards. Chapter 3, Falcon ECC Memory Controller Chip Set, describes the Falcon memory controller chip set, which provides the interface between the PowerPC processor bus and memory systems on MVME2300 series boards. Chapter 4, Universe (VMEbus to PCI) Chip, describes the Universe ASIC, the VMEbus/PCI local bus interface chip used on MVME2300 series boards. Chapter 5, Programming Details, examines aspects of several programming functions that are not tied to any specific ASIC on MVME2300 series boards. Appendix A, Related Documentation, lists all documentation related to the MVME2300 and MVME2300SC series boards. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to: Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way Tempe, Arizona 85282 You can also submit comments to the following e-mail address: [email protected]

Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements. Conventions Used in This Manual The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms. courier is used for system output (for example, screen displays, reports), examples, and system prompts. , or represents the carriage return or Enter key. CTRL represents the Control key. Execute control characters by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d. Data and address parameters are preceded by a character identifying the numeric format as follows: $ % & dollar percent ampersand specifies a hexadecimal character specifies a binary number specifies a decimal number

number eighteen. Unless otherwise specified, all address references are in hexadecimal. In descriptions of the VMEbus interface, an asterisk (∗) following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low. An asterisk (∗) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition. In references to other bus signals (such as PCI) found on MVME2300 series boards, an underscore (_) or pound sign (#) following the signal name denotes an active low signal. In this manual, assertion and negation signify the forcing of a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent. Data and address sizes for MPC60x chips are defined as follows: J A byte is eight bits, numbered 0 through 7, with bit 0 being the least significant. J A half-word is 16 bits, numbered 0 through 15, with bit 0 being the least significant. J A word or single word is 32 bits, numbered 0 through 31, with bit 0 being the least significant. J A double word is 64 bits, numbered 0 through 63, with bit 0 being the least significant. Refer to Endian Issues in Chapter 5 for a discussion of which elements on MVME2300 series boards use big-endian byte ordering, and which use small-endian byte ordering. The terms control bit and status bit are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls. The term false is used to

all tables, the terms 0 and 1 are used to describe the actual value that should be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a register that reflects a specific condition. The status bit can be read by software to determine operational or exception conditions.

Maps Introduction This manual provides programming information for MVME2300 and MVME2300SC VME processor modules. Extensive programming information is provided for several Application-Specific Integrated Circuit (ASIC) devices used on the boards. Reference information is included in Appendix A for the Large Scale Integration (LSI) devices used on the boards and sources for additional information are listed. This chapter briefly describes the board level hardware features of the MVME2300-series VME processor modules. The chapter begins with a board level overview and features list. Memory maps are next, and are the major feature of this chapter. Programmable registers that reside in ASICs in the MVME2300 series are covered in the chapters on those ASICs. Chapter 2, Raven PCI Bridge ASIC covers the Raven chip, Chapter 3, Falcon ECC Memory Controller Chip Set covers the Falcon chip set, Chapter 4, Universe (VMEbus to PCI) Chip covers the Universe chip, and Chapter 5, Programming Details covers certain programming features, such as interrupts and exceptions. Appendix A, Related Documentation lists all related documentation. Overview The MVME2300-series VME Processor Module family, hereafter sometimes referred to simply as the MVME230x or the MVME2300 series, provides many standard features required by a computer system: Ethernet interface, async serial port, boot Flash, and up to 128MB of ECC DRAM.

Board Description and Memory Maps 1 Summary of Features There are many models based on the MVME2300 series architecture. The following table summarizes the major features of the MVME2300 series: Table 1-1. Features: MVME2300 Series Feature MVME2300 MVME2300SC Microprocessor 200 MHZ MPC603 PowerPC® processor (MVME2301 - 2304 models) 300 MHZ MPC604 PowerPC® processor (All models) 300 MHZ MPC604 PowerPC® processor (MVME2305 - 2308 models) Form factor 6U VMEbus ECC DRAM Two-way interleaved, ECC- protected 16MB, 32MB, 64MB, or 128MB Two-way interleaved, ECC- protected 32MB or 64MB Flash memory Bank B: Two 32-pin PLCC sockets that can be populated with 1MB 8-bit Flash devices Bank A: Four 16-bit Smart Voltage SMT devices that can be populated with 8Mbit Flash devices (4MB) or 4Mbit devices (2MB) Bank A: Four 16-bit Smart Voltage SMT devices populated with 8Mbit Flash devices (4MB) Real-time clock 8KB NVRAM with RTC, battery backup, and watchdog function (SGS-Thomson M48T59/T559) 8KB NVRAM with RTC, battery backup, and watchdog function (SGS-Thomson M48T559) Switches Reset (RST) and Abort (ABT) Status LEDs Four: Board fail (BFL), CPU, PMC (one for PMC slot 2, one for slot 1) Four: Board Fail (BFL), CPU, System Controller (SCON), Fuses (FUS) Timers One 16-bit timer in W83C553 PCI/ISA bridge; four 32-bit timers in Raven (MPIC) device Watchdog timer provided in SGS-Thomson M48T59/T559 Interrupts Software interrupt handling via Raven (PCI/MPU bridge) and Winbond (PCI/ISA bridge) controllers VME I/O VMEbus P2 connector

http://www.motorola.com/computer/literature 1-3 1 System Block Diagram The MVME2300 series does not provide any look-aside external cache option. The Falcon chip set controls the boot Flash and the ECC DRAM. The Raven ASIC functions as the 64-bit PCI host bridge and the MPIC interrupt controller. PCI devices include: VME, Ethernet, and two PMC Serial I/O One asynchronous debug port via RJ45 connector on front panel One asynchronous debug port via DB9 connector on front panel, also via P2 and transition module Ethernet I/O 10BaseT/100BaseTX connections via RJ45 connector on front panel 10BaseT/100BaseTX connections via RJ45 connector on front panel; AUI connections via P2 and transition module PCI interface Two IEEE P1386.1 PCI Mezzanine Card (PMC) slots for one double- width or two single-width PMCs Front panel and/or VMEbus P2 I/O on both PMC slots One 114-pin Mictor connector for optional PMCspan expansion module SCSA I/O Not available Connections from both PMC slots to SCSA backplane TDM bus (if present in system) via shared pins on P2 connector VMEbus interface VMEbus system controller functions VME64 extension VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block transfer [D8/D16/D32/D64]) Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) VMEbus interrupter VMEbus interrupt handler Global Control/Status Register (GCSR) for interprocessor communications DMA for fast local memory/VMEbus transfers (A16/A24/A32, D16/D32/D64) Table 1-1. Features: MVME2300 Series (Continued) Feature MVME2300 MVME2300SC

Board Description and Memory Maps 1 slots. Standard I/O functions are provided by the UART device which resides on the ISA bus. The NVRAM/RTC also resides on the ISA bus. The general system block diagram for MVME2300 series is shown below:

http://www.motorola.com/computer/literature 1-5 1 Figure 1-1. MVME2300 Series System Block Diagram SYSTEM REGISTERS 2067 9708 PMC FRONT I/O SLOT DEBUG CONNECTOR CLOCK GENERATOR PROCESSOR MPC603/604 Flash 3MB or 5MB PHB & MPIC RAVEN ASIC MEMORY CONTROLLER FALCON CHIP SET 64-BIT PMC SLOT PCI EXPANSION 33MHz 32/64-BIT PCI LOCAL BUS PIB W83C553 VME BRIDGE UNIVERSE BUFFERS VME P2 VME P1 RTC/NVRAM/WD MK48T59/559 ETHERNET DEC21140 10BT/100BTX FRONT PANEL ISA BUS 66MHz MPC604 PROCESSOR BUS DRAM 16/32/64/128MB PMC FRONT I/O SLOT SERIAL PORT PC16550 UART ISA REGISTERS

Board Description and Memory Maps 1 Functional Description The MVME2300 series is a family of single-slot VME processor modules. It consists of the MPC603/604 processor, the Raven PCI Bridge and Interrupt Controller, the Falcon ECC Memory Controller chip set, 3MB or 5MB of Flash memory, 16MB to 128MB of ECC-protected DRAM, and a rich set of I/O features. I/O peripheral devices on the PCI bus are: Ethernet chip, Universe VMEbus interface ASIC, and two PMC slots. Functions provided from the ISA bus are: one asynchronous serial port, a real-time clock, counters/timers, and a software-readable header. VMEbus Interface MVME2300 series boards interface to the VMEbus via the P1 and P2 backplane connectors. MVME2300SC boards use the three-row 96-pin connectors specified in the original VMEbus standard; non-SCbus MVME2300 boards use the 5-row 160-pin connectors specified in the VME64 Extension standard. Both types of boards draw +5V, +12V, and –12V power from the VMEbus backplane through these two connectors. 3.3V and 2.5V supplies are regulated onboard from the +5 power. Front Panel Front panel connectors on the non-SCbus MVME2300 series boards include an RJ45 connector for the Ethernet 10BaseT/100BaseTX interface, and a second RJ45 connector for the asynchronous serial debug port. Front panel connectors on the MVME2300SC include an RJ45 connector for the Ethernet 10BaseT/100BaseTX interface, and a 9-pin DB9 connector for the asynchronous serial debug port.

1386.1 PCI Mezzanine Card (PMC) slots. The PMC slots are 64-bit capable and support both front and rear I/O. P2 I/O Certain pins of each PMC slot connector are routed to VME backplane connector P2 for use in rear I/O configurations. On MVME2300 boards, pins 1-64 of PMC slot 1 connector J14 are routed to rows C and A of the 5-row DIN P2 connector. Pins 1-46 of PMC slot 2 connector J24 are routed to rows D and Z of connector P2. On MVME2300SC boards, pins 1-32 of PMC slot 1 connector J14 are routed to rows C and A of the 3-row DIN P2 connector. Pins 1-32 of PMC slot 2 connector J24 (as with J14) are routed to rows C and A of connector P2. Additional PCI expansion is supported with a 114-pin Mictor connector. This connection allows stacking of one or two PMCspan dual-PMC carrier boards, to increase the I/O capability. Each PMCspan board requires an additional VME slot. Programming Model The following sections describe the memory maps for the MVME2300 series boards. Processor Memory Maps The Processor memory map is controlled by the Raven ASIC and the Falcon chip set. The Raven ASIC and the Falcon chip set have flexible programming Map Decoder registers to customize the system for many different applications.

Board Description and Memory Maps 1 Default Processor Memory Map After a reset, the Raven ASIC and the Falcon chip set provide the default processor memory map as shown in the following table. Notes 1. This default map for PCI/ISA I/O space allows software to determine whether the system is MPC105-based or Falcon/Raven- based by examining either the PIB Device ID or the CPU Type register. 2. The first Megabyte of ROM/Flash bank A appears at this range after a reset if the rom_b_rv control bit is cleared. If the rom_b_rv control bit is set, then this address range maps to ROM/Flash bank B. Table 1-2. Default Processor Memory Map Processor Address Size Definition Notes Start End 0000 0000 7FFF FFFF 2G Not mapped 8000 0000 8001 FFFF 128K PCI/ISA I/O Space 1 8002 0000 FEF7 FFFF 2G - 16M - 640K Not mapped FEF8 0000 FEF8 FFFF 64K Falcon Registers FEF9 0000 FEFE FFFF 384K Not mapped FEFF 0000 FEFF FFFF 64K Raven Registers FF00 0000 FFEF FFFF 15M Not mapped FFF0 0000 FFFF FFFF 1M ROM/Flash Bank A or Bank B 2

The following table shows a recommended CHRP memory map from the point of view of the processor. Notes 1. Programmable via Falcon chip set. For the MVME2300 series, RAM size is limited to 128MB and ROM/Flash to 4MB. 2. To enable the “Processor-hole” area, program the Falcon chip set to ignore 0x000A0000 - 0x000BFFFF address range and program the Raven to map this address range to PCI memory space. Table 1-3. CHRP Memory Map Example Processor Address Size Definition Notes Start End 0000 0000 top_dram dram_size System Memory (onboard DRAM) 1, 2 4000 0000 FCFF FFFF 3G - 48M PCI Memory Space: 4000 0000 to FCFF FFFF 3,4,8 FD00 0000 FDFF FFFF 16M Zero-Based PCI/ISA Memory Space (mapped to 00000000 to 00FFFFFF) 3,8 FE00 0000 FE7F FFFF 8M Zero-Based PCI/ISA I/O Space (mapped to 00000000 to 007FFFFF) 3,5,8 FE80 0000 FEF7 FFFF 7.5M Reserved FEF8 0000 FEF8 FFFF 64K Falcon Registers FEF9 0000 FEFE FFFF 384K Reserved FEFF 0000 FEFF FFFF 64K Raven Registers 9 FF00 0000 FF7F FFFF 8M ROM/Flash Bank A 1,7 FF80 0000 FF8F FFFF 1M ROM/Flash Bank B 1,7 FF50 0000 FFEF FFFF 6M Reserved FFF0 0000 FFFF FFFF 1M ROM/Flash Bank A or Bank B 7

Board Description and Memory Maps 1 3. Programmable via Raven ASIC. 4. CHRP requires the starting address for the PCI memory space to be 256MB-aligned. 5. Programmable via Raven ASIC for either contiguous or spread-I/O mode. 6. The actual size of each ROM/Flash bank may vary. 7. The first Megabyte of ROM/Flash bank A appears at this range after a reset if the rom_b_rv control bit is cleared. If the rom_b_rv control bit is set then this address range maps to ROM/Flash bank B. 8. This range can be mapped to the VMEbus by programming the Universe ASIC accordingly. The map shown is the recommended setting which uses the Special PCI Slave Image and two of the four programmable PCI Slave Images. 9. The only method of generating a PCI Interrupt Acknowledge cycle (8259 IACK) is to perform a read access to the Raven’s PIACK register at 0xFEFF0030. The following table shows the programmed values for the associated Raven MPC registers for the processor CHRP memory map. Table 1-4. Raven MPC Register Values for CHRP Memory Map Address Register Name Register Value FEFF 0040 MSADD0 4000 FCFF FEFF 0044 MSOFF0 & MSATT0 0000 00C2 FEFF 0048 MSADD1 FD00 FDFF FEFF 004C MSOFF1 & MSATT1 0300 00C2 FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 & MSATT2 0000 0002 FEFF 0058 MSADD3 FE00 FE7F FEFF 005C MSOFF3 & MSATT3 0200 00C0

The Raven/Falcon chip set can be programmed for PREP-compatible memory map. The following table shows the PREP memory map of the MVME2300 series from the point of view of the processor. Notes 1. Programmable via Falcon chip set. For the MVME2300 series, RAM size is limited to 128MB and ROM/Flash to 4MB. 2. Programmable via Raven ASIC. 3. The actual size of each ROM/Flash bank may vary. Table 1-5. PREP Memory Map Example Processor Address Size Definition Notes Start End 0000 0000 top_dram dram_size System Memory (onboard DRAM) 1 8000 0000 BFFF FFFF 1G Zero-Based PCI I/O Space: 0000 0000 - 3FFFF FFFF 2 C000 0000 FCFF FFFF 1G - 48M Zero-Based PCI/ISA Memory Space: 0000 0000 - 3CFFFFFF 2, 5 FD00 0000 FEF7 FFFF 40.5M Reserved FEF8 0000 FEF8 FFFF 64K Falcon Registers FEF9 0000 FEFE FFFF 384K Reserved FEFF 0000 FEFF FFFF 64K Raven Registers 6 FF00 0000 FF7F FFFF 8M ROM/Flash Bank A 1, 3 FF80 0000 FF8F FFFF 1M ROM/Flash Bank B 1, 3 FF90 0000 FFEF FFFF 6M Reserved FFF0 0000 FFFF FFFF 1M ROM/Flash Bank A or Bank B 4

Board Description and Memory Maps 1 4. The first Megabyte of ROM/Flash bank A appears at this range after a reset if the rom_b_rv control bit is cleared. If the rom_b_rv control bit is set then this address range maps to ROM/Flash bank B. 5. This range can be mapped to the VMEbus by programming the Universe ASIC accordingly. 6. The only method of generating a PCI Interrupt Acknowledge cycle (8259 IACK) is to perform a read access to the Raven’s PIACK register at 0xFEFF0030. The following table shows the programmed values for the associated Raven MPC registers for the processor PREP memory map. PCI Configuration Access PCI Configuration accesses are accomplished via the CONFIG_ADD and CONFIG_DAT registers. These two registers are implemented in the Raven ASIC. In the CHRP memory map example, the CONFIG_ADD and CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC, respectively. With the PREP memory map, the CONFIG_ADD register and the CONFIG_DAT register are located at 0x80000CF8 and 0x80000CFC, respectively. Table 1-6. Raven MPC Register Values for PREP Memory Map Address Register Name Register Value FEFF 0040 MSADD0 C000 FCFF FEFF 0044 MSOFF0 & MSATT0 4000 00C2 FEFF 0048 MSADD1 0000 0000 FEFF 004C MSOFF1 & MSATT1 0000 0002 FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 & MSATT2 0000 0002 FEFF 0058 MSADD3 8000 BFFF FEFF 005C MSOFF3 & MSATT3 8000 00C0

The PCI memory map is controlled by the Raven ASIC and the Universe ASIC. The Raven ASIC and the Universe ASIC have flexible programming Map Decoder registers to customize the system to fit many different applications. Default PCI Memory Map After a reset, the Raven ASIC and the Universe ASIC turn all the PCI slave map decoders off. Software must program the appropriate map decoders for a specific environment. PCI CHRP Memory Map The following table shows a PCI memory map of the MVME2300 series that is CHRP-compatible from the point of view of the PCI local bus. Table 1-7. PCI CHRP Memory Map PCI Address Size Definition Notes Start End 0000 0000 top_dram dram_size Onboard ECC DRAM 1 4000 0000 EFFF FFFF 3G - 256M VMEbus A32/D32 (Super/Program) 3 F000 0000 F7FF FFFF 128M VMEbus A32/D16 (Super/Program) 3 F800 0000 F8FE FFFF 16M - 64K VMEbus A24/D16 (Super/Program) 4 F8FF 0000 F8FF FFFF 64K VMEbus A16/D16 (Super/Program) 4 F900 0000 F9FE FFFF 16M - 64K VMEbus A24/D32 (Super/Data) 4 F9FF 0000 F9FF FFFF 64K VMEbus A16/D32 (Super/Data) 4 FA00 0000 FAFE FFFF 16M - 64K VMEbus A24/D16 (User/Program) 4 FAFF 0000 FAFF FFFF 64K VMEbus A16/D16 (User/Program) 4 FB00 0000 FBFE FFFF 16M - 64K VMEbus A24/D32 (User/Data) 4 FBFF 0000 FBFF FFFF 64K VMEbus A16/D32 (User/Data) 4

Board Description and Memory Maps 1 Notes 1. Programmable via the Raven’s PCI Configuration registers. For the MVME2300 series, RAM size is limited to 128MB. 2. To enable the CHRP “io-hole”, program the Raven to ignore the 0x000A0000 - 0x000FFFFF address range. 3. Programmable mapping via the four PCI Slave Images in the Universe ASIC. 4. Programmable mapping via the Special Slave Image (SLSI) in the Universe ASIC. FC00 0000 FC03 FFFF 256K RavenMPIC 1 FC04 0000 FCFF FFFF 16M - 256K PCI Memory Space FD00 0000 FDFF FFFF 16M PCI Memory Space or System Memory Alias Space (mapped to 00000000 to 00FFFFFF) 1 FE00 0000 FFFF FFFF 48M Reserved Table 1-7. PCI CHRP Memory Map (Continued) PCI Address Size Definition Notes Start End

Raven PCI registers for the PCI CHRP memory map. The next table shows the programmed values for the associated Universe PCI registers for the PCI CHRP memory map. Table 1-8. Raven PCI Register Values for CHRP Memory Map Configuration Address Offset Configuration Register Name Register Value (Aliasing OFF) Register Value (Aliasing ON) $14 RavenMPIC MBASE FC00 0000 FC00 0000 $80 PSADD0 0000 3FFF 0100 3FFF $84 PSOFF0 & PSATT0 0000 00FX 0000 00FX $88 PSADD1 0000 0000 FD00 FDFF $8C PSOFF1 & PSATT1 0000 0000 0000 00FX $90 PSADD2 0000 0000 0000 0000 $94 PSOFF2 & PSATT2 0000 0000 0000 0000 $98 PSADD3 0000 0000 0000 0000 $9C PSOFF3 & PSATT3 0000 0000 0000 0000 Table 1-9. Universe PCI Register Values for CHRP Memory Map Configuration Address Offset Configuration Register Name Register Value $100 LSI0_CTL C082 5100 $104 LSI0_BS 4000 0000 $108 LSI0_BD F000 0000 $10C LSI0_TO XXXX 0000 $114 LSI1_CTL C042 5100 $118 LSI1_BS F000 0000 $11C LSI1_BD F800 0000

Board Description and Memory Maps 1 PCI PREP Memory Map The following table shows a PCI memory map of the MVME2300 series boards that is PREP-compatible from the point of view of the PCI local bus. $120 LSI1_TO XXXX 0000 $128 LSI2_CTL 0000 0000 $12C LSI2_BS XXXX XXXX $130 LSI2_BD XXXX XXXX $134 LSI2_TO XXXX XXXX $13C LSI3_CTL 0000 0000 $140 LSI3_BS XXXX XXXX $144 LSI3_BD XXXX XXXX $148 LSI3_TO XXXX XXXX $188 SLSI C0A053F8 Table 1-10. PCI PREP Memory Map PCI Address Size Definition Notes Start End 0000 0000 00FF FFFF 16M PCI/ISA Memory Space 0100 0000 2FFF FFFF 752M VMEbus A32/D32 (Super/Program) 3 3000 0000 37FF FFFF 128M VMEbus A32/D16 (Super/Program) 3 3800 0000 38FE FFFF 16M - 64K VMEbus A24/D16 (Super/Program) 4 Table 1-9. Universe PCI Register Values for CHRP Memory Map (Continued) Configuration Address Offset Configuration Register Name Register Value

MVME2300 series, RAM size is limited to 128MB. 2. To enabled the CHRP “io-hole”, program the Raven to ignore the 0x000A0000 - 0x000FFFFF address range. 3. Programmable mapping via the four PCI Slave Images in the Universe ASIC. 4. Programmable mapping via the Special Slave Image (SLSI) in the Universe ASIC. 38FF 0000 38FF FFFF 64K VMEbus A16/D16 (Super/Program) 4 3900 0000 39FE FFFF 16M - 64K VMEbus A24/D32 (Super/Data) 4 39FF 0000 39FF FFFF 64K VMEbus A16/D32 (Super/Data) 4 3A00 0000 3AFE FFFF 16M - 64K VMEbus A24/D16 (User/Program) 4 3AFF 0000 3AFF FFFF 64K VMEbus A16/D26 (User/Program) 4 3B00 0000 3BFE FFFF 16M - 64K VMEbus A24/D32 (User/Data) 4 3BFF 0000 3BFF FFFF 64K VMEbus A16/D32 (User/Data) 4 3C00 0000 7FFF FFFF 1G + 64M PCI Memory Space 8000 0000 FBFF FFFF 2G - 64M Onboard ECC DRAM 1 FC00 0000 FC03 FFFF 256K RavenMPIC 1 FC04 0000 FFFF FFFF 64M - 256K PCI Memory Space Table 1-10. PCI PREP Memory Map (Continued) PCI Address Size Definition Notes Start End

Board Description and Memory Maps 1 The following table shows the programmed values for the associated Raven PCI registers for the PREP-compatible memory map. Table 1-11. Raven PCI Register Values for PREP Memory Map Configuration Address Offset Configuration Register Name Register Value $14 RavenMPIC MBASE FC00 0000 $80 PSADD0 8000 FBFF $84 PSOFF0 & PSATT0 8000 00FX $88 PSADD1 0000 0000 $8C PSOFF1 & PSATT1 0000 0000 $90 PSADD2 0000 0000 $94 PSOFF2 & PSATT2 0000 0000 $98 PSADD3 0000 0000 $9C PSOFF3 & PSATT3 0000 0000

PCI registers for the PCI PREP memory map. Table 1-12. Universe PCI Register Values for PREP Memory Map Configuration Address Offset Configuration Register Name Register Value $100 LSI0_CTL C082 5100 $104 LSI0_BS 0100 0000 $108 LSI0_BD 3000 0000 $10C LSI0_TO XXXX 0000 $114 LSI1_CTL C042 5100 $118 LSI1_BS 3000 0000 $11C LSI1_BD 3800 0000 $120 LSI1_TO XXXX 0000 $128 LSI2_CTL 0000 0000 $12C LSI2_BS XXXX XXXX $130 LSI2_BD XXXX XXXX $134 LSI2_TO XXXX XXXX $13C LSI3_CTL 0000 0000 $140 LSI3_BS XXXX XXXX $144 LSI3_BD XXXX XXXX $148 LSI3_TO XXXX XXXX $188 SLSI C0A05338

Board Description and Memory Maps 1 VMEbus Mapping The processor can access any address range in the VMEbus with the help of the Universe ASIC’s address translation capabilities. The Processor Memory Map section shows the recommended mapping. VMEbus Master Map The figure below illustrates how VMEbus master mapping is accomplished. (Note that for MVME2300 series boards, RAM size is limited to 128MB.) Figure 1-2. VMEbus Master Mapping VMEBUS 11553.00 9609 VME A24 VME A16 VME A24 VME A16 VME A24 VME A16 VME A24 VME A16 PROGRAMMABLE SPACE PCI MEMORY PROCESSOR PCI MEMORY SPACE PCI/ISA MEMORY SPACE PCI I/O SPACE MPC RESOURCES NOTE 1 NOTE 1 NOTE 2 NOTE 3 ONBOARD MEMORY

2. Programmable mapping via the four PCI Slave Images in the Universe ASIC. 3. Programmable mapping via the Special Slave Image (SLSI) in the Universe ASIC. VMEbus Slave Map The four programmable VME Slave images in the Universe ASIC give other VMEbus masters access to any devices on the board. The combination of the four Universe VME Slave images and the four Raven PCI Slave decoders offers great flexibility in mapping the system resources as seen from the VMEbus. In most applications, the VMEbus needs to see only the system memory and, perhaps, the software interrupt registers (SIR1 and SIR2 registers). For an example of the VMEbus slave map, refer to the figure below:

Board Description and Memory Maps 1 Figure 1-3. VMEbus Slave Mapping Notes 1. Programmable mapping via the four VME Slave Images in the Universe ASIC. 2. Programmable mapping via PCI Slave Images in the Raven ASIC. 3. Fixed mapping via the PIB device. 1896 9609 PCI Memory NOTE 2 NOTE 1 Software INT Registers Processor ISA Space Onboard Memory VMEbus NOTE 1 PCI I/O Space NOTE3

Universe registers for the VMEbus slave function. Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example Configuration Address Offset Configuration Register Name Register Value (CHRP) Register Value (PREP) $F00 VSI0_CTL C0F2 0001 C0F2 0001 $F04 VSI0_BS 4000 0000 4000 0000 $F08 VSI0_BD 4000 1000 4000 1000 $F0C VSI0_TO C000 1000 C000 1000 $F14 VSI1_CTL E0F2 00C0 E0F2 00C0 $F18 VSI1_BS 1000 0000 1000 0000 $F1C VSI1_BD 2000 0000 2000 0000 $F20 VSI1_TO F000 0000 7000 0000 $F28 VSI2_CTL 0000 0000 0000 0000 $F2C VSI2_BS XXXX XXXX XXXX XXXX $F30 VSI2_BD XXXX XXXX XXXX XXXX $F34 VSI2_TO XXXX XXXX XXXX XXXX $F3C VSI3_CTL 0000 0000 0000 0000 $F40 VSI3_BS XXXX XXXX XXXX XXXX $F44 VSI3_BD XXXX XXXX XXXX XXXX $F48 VSI3_TO XXXX XXXX XXXX XXXX

Board Description and Memory Maps 1 The register values in the table yield the following VMEbus slave map: Falcon-Controlled System Registers The Falcon chip set latches the states of the DRAM data lines onto the PR_STAT1 and PR_STAT2 registers. MVME2300 series boards use these status registers to provide the system configuration information. In addition, the Falcon chip set performs the decode and control for an external register port. This function is utilized by MVME2300 series boards to provide the system control registers. The following subsections describe these system registers in detail. Table 1-14. VMEbus Slave Map Example VMEbus Address Size CHRP Map PREP Map Range Mode 4000 0000 - 4000 0FFF A32 U/S/P/D D08/16/32 4K PCI/ISA I/O Space: 0000 1000 - 0000 1FFF PCI/ISA I/O Space: 0000 1000 - 0000 1FFF 1000 0000 - 1FFF FFFF A32 U/S/P/D D08/16/32/64 RMW 256M PCI/ISA Memory Space (On-board DRAM) 0000 0000 - 0FFF FFFF PCI/ISA Memory Space (On-board DRAM) 8000 0000 - 8FFF FFFF Table 1-15. System Register Summary BIT # ----> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FEF80400 System Configuration Register (Upper Falcon’s PR_STAT1) FEF80404 Memory Configuration Register (Lower Falcon’s PR_STAT1) FEF88000 System External Cache Control Register FEF88300 CPU Control Register

The states of the RD[0:31] DRAM data pins, which have weak internal pull-ups, are latched by the upper Falcon chip at a rising edge of the power- up reset and stored in this System Configuration register to provide some information about the system. Configuration is accomplished with external pull-down resistors. This 32-bit read-only register is defined as follows: SYSID System Identification. This field specifies the type of the overall system configuration so that the software may appropriately handle any software visible differences. For the MVME2300 series, this field returns a value of $FD. SYSCLK System Clock Speed. This field relays the system clock speed and the PCI clock speed information as follows: REG System Configuration Register - $FEF80400 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FIELD SYSID SYSCLK SYSXC P0STAT P1STAT OPER Read Only RESET $FD 1111 1111 0111 1111 1 1 $F SYSCLK Value System Clock Speed PCI Clock Speed 0B0000 to 0B1100 Reserved Reserved 0B1101 50MHz 25MHz 0B1110 60MHz 30MHz 0B1111 66.66MHz 33.33MHz

Board Description and Memory Maps 1 SYSXC System External Cache Size. The MVME2300 series does not offer any external caching options. Reads from this field will always return a hardwired value of 0b1111 indicating the absence of external caching. P0/1STAT Processor 0/1 Status. This field is encoded as follows: P0/1STAT Value Processor 0/1 Present External In-line Cache Size 0B0000 to 0B0011 Reserved Reserved 0B0100 Yes 1M 0B0101 Yes 512K 0B0110 Yes 256K 0B0111 Yes None 0B1000 to 0B1111 No N/A

The states of the RD[00:31] DRAM data pins, which have weak internal pull-ups, are latched by the lower Falcon chip at a rising edge of the power- up reset and stored in this Memory Configuration register to provide some information about the system memory. Configuration is accomplished with external pull-down resistors. This 32-bit read-only register is defined as follows: M_SIZE[0:1] Memory Size. This field is encoded as follows: M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it indicates that a DRAM block requires faster refresh rate. If any of the four blocks requires faster refresh rate then the ram ref control bit should be set. REG Memory Configuration Register - $FEF80404 BIT 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 FIELD M_SIZE0 M_SIZE1 M_FREF M_SPD0 M_SPD1 R_A_TYP0 R_A_TYP1 R_A_TYP2 R_B_TYP0 R_B_TYP1 R_B_TYP2 L2_TYPE0 L2_TYPE1 L2_TYP2 L3_TYPE3 L2_PLL0 L2_PLL1 L2_PLL2 L2_PLL3 FLSHP0_ FLSHP1_ FLSHP2- OPER RESET X X 1 X 1 1 X X 1 X X X 1 X X X X X X X X X X X 1 1 X X X 1 1 1 M_SIZE[0:1] Total Memory On Board 0B00 16 Megabytes 0B01 32 Megabytes 0B10 64 Megabytes 0B11 128 Megabytes

Board Description and Memory Maps 1 M_SPD[0:1] Memory Speed. This field relays the memory speed information as follows: These two bits reflect the combined status of the four blocks of DRAM. Initialization software uses this information to program the ram_spd0 and ram_spd1 control bits in the Falcon’s Chip Revision register. R_A/B_TYP[0:2] ROM/Flash Type. This field is encoded as follows: Note The device width differs from the width of the Flash bank. If the bank width is 64 bits and the device width is 16 bits, then the Flash bank consists of four Flash devices. L2_TYPE[0:3] L2 Memory Type. This field is encoded as follows: M_SPD[0:1] DRAM Speed DRAM Type 0B00 70ns Past Page 0B01 60ns Fast Page 0B10 Reserved Reserved 0B11 50ns EDO ROM_A/B_TYP[0:2] ROM/Flash Type 0B000 to 0B101 Reserved 0B110 Intel 16-bit wide Flash with 16K Bottom Boot Block 0B111 Unknown type (i.e. ROM/Flash sockets) L2_TYPE[0:3] Configuration 0B0000 Late write Sync 0B0001 Pipelined Sync Burst 0B0010 to 0B1111 Reserved

encoded as follows: FLSHP[0:2] Bank A Flash memory size. This field is encoded as follows: System External Cache Control Register (SXCCR) The MVME2300 and MVME2300SC boards do not implement this register. Writes to this register location ($FEF88000) will have no system effects. Reads from this register location will return undefined data. PLL Value] Size 0B0000 Disable 0B0001 1 0B0010 1.5 0B0011 2 0B0100 2.5 0B0101 3 0B0110 to 0B1111 Reserved Flash Size FLSHP0_ FLSHP1_ FLSHP2_ 1MB 0 0 0 2MB 0 0 1 4MB 0 1 0 8MB 0 1 1 16MB 1 0 0 32MB 1 0 1 64MB 1 1 0 No Flash 1 1 1

Board Description and Memory Maps 1 Processor 0 External Cache Control Register (P0XCCR) The MVME2300 and MVME2300SC boards do not implement this register. Writes to this register location ($FEF88100) will have no system effects. Reads from this register location will return undefined data. Processor 1 External Cache Control Register (P1XCCR) The MVME2300 and MVME2300SC boards do not implement this register. Writes to this register location ($FEF88200) will have no system effects. Reads from this register location will return undefined data. CPU Control Register The CPU Control register is accessed via the RD[32:39] data lines of the upper Falcon device. This 8-bit register is defined as follows: LEMODE Little Endian Mode. This bit must be set in conjunction with the LEND bit in the Raven for little-endian mode. P0_TBEN Processor 0 Time Base Enable. When this bit is cleared, the TBEN pin of the processor will be driven low. REG CPU Control Register - $FEF88300 BIT 0 1 2 3 4 5 6 7 FIELD LEMODE P0_TBEN OPER R R R R/W R R R R RESET 1 0 0 1 X X X X

http://www.motorola.com/computer/literature 1-31 1 ISA Local Resource Bus W83C553 PIB Registers The PIB contains ISA Bridge I/O registers for various functions. These registers are actually accessible from the PCI bus. Refer to the W83C553 Data Book for details. 16550 UART The 16550 UART provides the MVME2300 series boards with an asynchronous serial port. Refer to the 16550 Data Sheet for additional details and programming information. The following table shows the mapping of the 16550 registers within the MVME2300 series boards’ ISA I/O space beginning at address 0x3F8: Table 1-16. 16550 Access Registers ISA I/O Address Function 0000 03F8 Receiver Buffer (Read); Transmitter Holding (Write) 0000 03F9 Interrupt Enable 0000 03FA Interrupt Identification (Read); FIFO Control (Write) 0000 03FB Line Control 0000 03FC MODEM control 0000 03FD Line Status 0000 03FE MODEM Status 0000 03FF Scratch

Board Description and Memory Maps 1 General-Purpose Readable Jumpers Headers J10 (on the MVME2300SC) and J17 (on the MVME2300) provide eight software-readable jumpers. These jumpers can be read as a register at ISA I/O address $801 (hexadecimal). Bit 0 is associated with header pins 1-2; bit 7 is associated with pins 15-16. The bit values are read as a 0 when a jumper is installed, and as a 1 when the jumper is removed. The PowerPC firmware, PPCBug, reserves all bits, SRH0 to SRH7. The board is shipped from the factory with J10 / J17 set to all 0s (jumpers on all pins), as shown in Figure 1-4. Figure 1-4. General-Purpose Software-Readable Header NVRAM/RTC and Watchdog Timer Registers The M48T59/559 provides the MVME2300 series boards with 8K of non- volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to the M48T59/559 are accomplished via three registers: J The NVRAM/RTC Address Strobe 0 register J The NVRAM/RTC Address Strobe 1 register J The NVRAM/RTC Data Port register J10/J17 15 Bit 0 (SRH0) Bit 1 (SRH1) Bit 2 (SRH2) Bit 6 (SRH6) Bit 3 (SRH3) Bit 4 (SRH4) Bit 5 (SRH5) 1 2 16 Bit 7 (SRH7) Reserved for future use Reserved for future use Reserved for future use PPCBug INSTALLED Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use

http://www.motorola.com/computer/literature 1-33 1 The NVRAM/RTC Address Strobe 0 register latches the lower 8 bits of the address and the NVRAM/RTC Address Strobe 1 register latches the upper 5 bits of the address. The NVRAM and RTC are accessed through the above three registers. When accessing an NVRAM/RTC location, follow this procedure: 1. Write the low address (A7-A0) of the NVRAM to the NVRAM/RTC STB0 register, 2. Write the high address (A15-A8) of the NVRAM to the NVRAM/RTC STB1 register, and 3. Then read or write the NVRAM/RTC Data Port. Refer to the M48T59 Data Sheet for additional details and programming information. Module Configuration and Status Registers Four registers provide the configuration and status information about the board. These registers are listed in the following table: Table 1-17. M48T59/559 Access Registers PCI I/O Address Function 0000 0074 NVRAM/RTC Address Strobe 0 (A7 - A0) 0000 0075 NVRAM/RTC Address Strobe 1 (A15 - A8) 0000 0077 NVRAM/RTC Data Register Table 1-18. Module Configuration and Status Registers PCI I/O Address Function 0000 0800 CPU Configuration Register 0000 0802 Base Module Feature Register 0000 0803 Base Module Status Register 0000 08C0 - 0000 08C1 Seven-Segment Display Register

Board Description and Memory Maps 1 The following subsections describe the configuration and status registers in detail. CPU Configuration Register The CPU Configuration register is an 8-bit register located at ISA I/O address x0800. This register is defined for the MVME2300 series to provide some backward compatibility with older MVME1600 products. The Base Module Status register should be used to identify the base module type and the System Configuration register should be used to obtain information about the overall system. CPUTYPE CPU Type. This field will always read as $E for the MVME2300 series. (The whole register will read $EF.) The System Configuration register should be used for additional information. REG Old CPU Configuration Register - $FE000800 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD CPUTYPE OPER R R RESET $E $F

http://www.motorola.com/computer/literature 1-35 1 Base Module Feature Register The Base Module Feature register is an 8-bit register providing the configuration information about the MVME2300-series VME processor module. This read-only register is located at ISA I/O address x0802. PCIXP_ PCI Expansion Slot present. If set, there is no PCIX device installed. If cleared, the PCIX slot contains a PCI Mezzanine Card. PMC2P_ PMC Slot 2 present. If set, there is no PCI Mezzanine Card installed in PMC Slot 2. If cleared, PMC Slot 2 contains a PMC. PMC1P_ PMC Slot 1 present. If set, there is no PCI Mezzanine Card installed in PMC Slot 1. If cleared, PMC Slot 1 contains a PMC. VMEP_ VMEbus present. If set, there is no VMEbus interface. If cleared, VMEbus interface is supported. LANP_ Ethernet present. If set, there is no Ethernet transceiver interface. If cleared, there is on-board Ethernet support. REG Base Module Feature Register - Offset $0802 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD PCIXP_ PMC2P_ PMC1P_ VMEP_ LANP_ OPER R R R R R R R R RESET X 1 X X X 1 X 1

Board Description and Memory Maps 1 Base Module Status Register (BMSR) The Base Module Status register is an 8-bit read-only register located at ISA I/O address x0803. BASE_TYPE Base Module Type. This four-bit field is used to provide the category of the base module and is defined as follows: REG Base Module Status Register - Offset $0803 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD BASE_TYPE OPER R RESET 1 1 1 1 N/A BASE_TYPE Value Base Module Type $0 to $8 Reserved $9 MVME2300 $A to $F Reserved

http://www.motorola.com/computer/literature 1-37 1 Seven-Segment Display Register Note This register is NOT USED on the MVME2300-series boards. This 16-bit register allows data to be sent to the 4-digit hexadecimal diagnostic display. The register also allows the data to be read back. DIG3[3:0] Hexadecimal value of the most significant digit. DIG2[3:0] Hexadecimal value of the third significant digit. DIG1[3:0] Hexadecimal value of the second significant digit. DIG0[3:0] Hexadecimal value of the least significant digit. VME Registers The registers listed in the table below provide the following functions for the VMEbus interface: J A software interrupt capability J A location monitor function J A geographical address status For these registers to be accessible from the VMEbus, the Universe ASIC must be programmed to map VMEbus Slave Image 0 into the appropriate PCI I/O address range. Refer to the VMEbus Slave Map section for additional details. REG 7-Segment Display Register - Offset $08C0 BIT SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD DIG3[3:0] DIG2[3:0] DIG1[3:0] DIG0[3:0] OPER R/W RESET X X X X X X X X X X X X X X X X

Board Description and Memory Maps 1 These registers are described in the following subsections. LM/SIG Control Register The LM/SIG Control register is an 8-bit register located at ISA I/O address x1000. This register provides a method to generate software interrupts. The Universe ASIC is programmed so that this register can be accessed from the VMEbus to generate software interrupts to the processor(s). SET_SIG1 Writing a 1 to this bit will set the SIG1 status bit. SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit. Table 1-19. VME Registers PCI I/O Address Function 0000 1000 SIG/LM Control Register 0000 1001 SIG/LM Status Register 0000 1002 VMEbus Location Monitor Upper Base Address 0000 1003 VMEbus Location Monitor Lower Base Address 0000 1004 VMEbus Semaphore Register 1 0000 1005 VMEbus Semaphore Register 2 0000 1006 VMEbus Geographical Address Status REG LM/SIG Control Register - Offset $1000 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD SET SIG1 SET SIG0 SET LM1 SET LM0 CLR SIG1 CLR SIG0 CLR LM1 CLR LM0 OPER WRITE-ONLY RESET 0 0 0 0 0 0 0 0

http://www.motorola.com/computer/literature 1-39 1 SET_LM1 Writing a 1 to this bit will set the LM1 status bit. SET_LM0 Writing a 1 to this bit will set the LM0 status bit. CLR_SIG1 Writing a 1 to this bit will clear the SIG1 status bit. CLR_SIG0 Writing a 1 to this bit will clear the SIG0 status bit. CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit. CLR_LM0 Writing a 1 to this bit will clear the LM0 status bit. LM/SIG Status Register The LM/SIG Status register is an 8-bit register located at ISA I/O address x1001. This register, in conjunction with the LM/SIG Control register, provides a method to generate interrupts. The Universe ASIC is programmed so that this register can be accessed from the VMEbus to provide a capability to generate software interrupts to the onboard processor(s) from the VMEbus. EN_SIG1 When the EN_SIG1 bit is set, an LM/SIG Interrupt 1 is generated if the SIG1 bit is asserted. EN_SIG0 When the EN_SIG0 bit is set, an LM/SIG Interrupt 0 is generated if the SIG0 bit is asserted. REG LM/SIG Status Register - Offset $1001 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD EN SIG1 EN SIG0 EN LM1 EN LM0 SIG1 SIG0 LM1 LM0 OPER R/W READ-ONLY RESET 0 0 0 0 0 0 0 0

Board Description and Memory Maps 1 EN_LM1 When the EN_LM1 bit is set, an LM/SIG Interrupt 1 is generated and the LM1 bit is asserted. EN_LM0 When the EN_LM0 bit is set, an LM/SIG Interrupt 0 is generated and the LM0 bit is asserted. SIG1 SIG1 status bit. This bit can only be set by the SET_LM1 control bit. It can only be cleared by a reset or by writing a 1 to the CLR_LM1 control bit. SIG0 SIG0 status bit. This bit can only be set by the SET_LM0 control bit. It can only be cleared by a reset or by writing a 1 to the CLR_LM0 control bit. LM1 LM1 status bit. This bit can be set by either the location monitor function or the SET_LM1 control bit. LM1 correspond to offset 3 from the location monitor base address. This bit can only be cleared by a reset or by writing a 1 to the CLR_LM1 control bit. LM0 LM0 status bit. This bit can be set by either the location monitor function or the SET_LM0 control bit. LM0 correspond to offset 1 from the location monitor base address. This bit can only be cleared by a reset or by writing a 1 to the CLR_LM0 control bit.

http://www.motorola.com/computer/literature 1-41 1 Location Monitor Upper Base Address Register The Location Monitor Upper Base Address register is an 8-bit register located at ISA I/O address x1002. The Universe ASIC is programmed so that this register can be accessed from the VMEbus to provide VMEbus location monitor function. VA[15:8] Upper Base Address for the location monitor function. Location Monitor Lower Base Address Register The Location Monitor Lower Base Address register is an 8-bit register located at ISA I/O address x1003. The Universe ASIC is programmed so that this register can be accessed from the VMEbus to provide VMEbus location monitor function. VA[7:4] Lower Base Address for the location monitor function. LMEN This bit must be set to enable the location monitor function. REG Location Monitor Upper Base Address Register - Offset $1002 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 OPER R/W RESET 0 0 0 0 0 0 0 0 REG Location Monitor Lower Base Address Register - Offset $1003 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD VA7 VA6 VA5 VA4 LMEN OPER R/W R R R RESET 0 0 0 0 0 0 0 0

Board Description and Memory Maps 1 Semaphore Register 1 Semaphore Register 1 is an 8-bit register located at ISA I/O address x1004. The Universe ASIC is programmed so that this register can be accessible from the VMEbus. This register can only be updated if bit 7 is low or if the new value has the most significant bit cleared. When bit 7 is high, this register will not latch in the new value if the new value has the most significant bit set. Semaphore Register 2 Semaphore Register 2 is an 8-bit register located at ISA I/O address x1005. The Universe ASIC is programmed so that this register can be accessible from the VMEbus. This register can only be updated if bit 7 is low or if the new value has the most significant bit cleared. When bit 7 is high, this register will not latch in the new value if the new value has the most significant bit set. REG Semaphore Register 1 - Offset $1004 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD SEM1 OPER R/W RESET 0 0 0 0 0 0 0 0 REG Semaphore Register 2 - Offset $1005 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD SEM2 OPER R/W RESET 0 0 0 0 0 0 0 0

http://www.motorola.com/computer/literature 1-43 1 VME Geographical Address Register (VGAR) The VME Geographical Address register is an 8-bit read-only register located at ISA I/O address x1006. This register reflects the states of the geographical address pins at the P1 connector. Emulated Z8536 CIO Registers and Port Pins Although MVME2300 series boards do not use a Z8536 device, several of its functions are emulated within an ISA Register PLD. These functions are accessed by reading/writing the Port A, B, C Data registers and Control register. Note that the Pseudo IACK function is not implemented in the MVME2300 series. Emulated Z8536 Registers The MVME2300 series implements the Z8536 CIO functions according to the following table. REG VME Geographical Address Register - Offset $1006 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD GAP# GA4# GA3# GA2# GA1# GA0# OPER READ ONLY RESET X X X X X X X X Table 1-20. Emulated Z8536 Access Registers PCI I/O Address Function 0000 0844 Port C’s Data Register 0000 0845 Port B’s Data Register 0000 0846 Port A’s Data Register 0000 0847 Control Register

Board Description and Memory Maps 1 Z8536 CIO Port Pins The following table shows the signal function and port mapping for the Z8536 CIO emulation. The signal directions are fixed in hardware. Table 1-21. Z8536 CIO Port Pin Assignments Port Pin Signal Name Direction Descriptions PA0 I/O Not used PA1 I/O Not used PA2 I/O Not used PA3 I/O Not used PA4 I/O Not used PA5 I/O Not used PA6 BRDFAIL Output Board Fail: When set, will illuminate BFL LED. PA7 I/O Not used PB0 I/O Not used PB1 I/O Not used PB2 I/O Not used PB3 I/O Not used PB4 I/O Not used PB5 I/O Not used PB6 I/O Not used PB7 ABORT_ Input Status of ABORT# signal PC0 I/O Not used PC1 I/O Not used

http://www.motorola.com/computer/literature 1-45 1 ISA DMA Channels No ISA DMA channels are implemented on MVME2300 series boards. PC2 BASETYP0 Input Genesis Base Module Type: 00b = Genesis II (see Base Module Status Register) 01b = MVME1600-011 10b = Reserved 11b = MVME1600-001 PC3 BASETYP1 Input Table 1-21. Z8536 CIO Port Pin Assignments (Continued) Port Pin Signal Name Direction Descriptions

Introduction This chapter describes the architecture and usage of the Raven ASIC, a PowerPC-to-PCI-Local-Bus bridge controller chip. The Raven is intended to provide PowerPC 60x (MPC60x) compliant devices access to devices residing on the PCI Local Bus. In the remainder of this chapter, the MPC60x bus is referred to as the "MPC bus" and the PCI Local Bus is referred to as "PCI". PCI is a high-performance 32-bit or 64-bit, burst mode, synchronous bus capable of transfer rates of 132 MB/sec in 32-bit mode or 264 MB/sec in 64-bit mode using a 33MHz clock. Features The following table summarizes the characteristics of the Raven ASIC. Table 2-1. Features of the Raven ASIC Function Features MPC Bus Interface Direct interface to MPC603 or MPC604 processors 64-bit data bus, 32-bit address bus Four independent software-programmable slave map decoders Multi-level write-post FIFO for writes to PCI Support for MPC bus clock speeds up to 66MHz Selectable big- or little-endian operation 3.3V signal levels PCI Interface Fully PCI Rev. 2.0 compliant 32-bit or 64-bit address/data bus Support for accesses to all four PCI address spaces Single-level write-posting buffers for writes to the MPC bus Read-ahead buffer for reads from the MPC bus Four independent software-programmable slave map decoders

Raven PCI Bridge ASIC 2 Block Diagram Figure 2-1 shows a functional block diagram of the Raven ASIC. The Raven control logic is subdivided into the following functions: J PCI slave J PCI master J MPC slave J MPC master Interrupt Controller MPIC compliant Support for 16 external interrupt sources and two processors Multiprocessor interrupt control allowing any interrupt source to be directed to either processor Multilevel cross-processor interrupt control for multiprocessor synchronization Four 31-bit tick timers Processor Coordination Two 64-bit general purpose registers for cross-processor messaging Table 2-1. Features of the Raven ASIC (Continued) Function Features

1914 9702 Data Path ‘B’ Mux FIFO Endian Mux FIFO Endian Data Path ‘A’ PCI Regs MPIC PCI Dec Mux Reg Mux Reg PCI Slave MPC Slave Reg Reg MPC Dec PCIADIN PCI Master Mux PCI MPC Master MPC Regs Raven PCI Bus MPC Bus Mux MPC MPCADIN

Raven PCI Bridge ASIC 2 Functional Description The Raven data path logic is subdivided into the following functions: J Data Path ‘A’ FIFOs/muxes J Data Path ‘B’ FIFOs/muxes J PCIADIN, MPCADIN, Mux PCI, and Mux MPC Address decoding is handled in the PCI Decode and MPC Decode blocks. The control register logic is contained in the PCI Registers and MPC Registers blocks. The interrupt controller (RavenMPIC) and the MPC arbiter functions make up the remainder of the Raven design. The data path function imposes some restrictions on access to the RavenMPIC, the PCI registers, and the MPC registers. The RavenMPIC and the PCI registers are only accessible to PCI-originated transactions. The MPC registers are only accessible to MPC-originated transactions. MPC Bus Interface The MPC Bus interface is designed to be coupled directly to up to two MPC603 or MPC604 microprocessors as well as a memory/cache subsystem. It uses a subset of the capabilities of the MPC60x bus protocol. MPC Address Mapping The Raven will map either PCI memory space or PCI I/O space into MPC address space using four programmable map decoders. These decoders provide windows into the PCI bus from the MPC bus. The most significant 16 bits of the MPC address are compared with the address range of each map decoder, and if the address falls within the specified range, the access is passed on to PCI. An example of this appears in Figure 2-2.

The Raven ASIC imposes no limits on how large an address space a map decoder can represent. There is a minimum of 64KB due to the resolution of the address compare logic. For each map, there is an associated set of attributes. These attributes are used to enable read accesses, enable write accesses, enable write-posting, and define the PCI transfer characteristics. Each map decoder also includes a programmable 16-bit address offset. The offset is added to the 16 most significant bits of the MPC address, and the result is used as the PCI address. This offset allows PCI devices to reside at any PCI address, independent of the MPC address map. An example of this appears in Figure 2-3. MPC Bus Address 8 0 8 0 1 2 3 4 31 16 15 0 MSADDx Register 7 0 8 0 9 0 0 0 31 16 15 0 >= <= and Decode is

Raven PCI Bridge ASIC 2 Figure 2-3. MPC to PCI Address Translation You should take care to assure that all programmable decoders decode unique address ranges, since overlapping address ranges will lead to undefined operation. MPC Slave The MPC slave provides the interface between the MPC bus and the Raven FIFOs. The MPC slave is responsible for tracking and maintaining coherency to the 60x processor bus protocol. The MPC slave divides MPC command types into three categories: Address Only; Write; and Read. If a command is of type address-only and the address presented at the time of the command is a valid Raven address, the MPC slave will respond immediately. The Raven will not respond to address-only cycles where the address presented is not a Raven address. The response of the MPC slave to command types is listed in Table 2-2. MPC Bus Address 8 0 8 0 1 2 3 4 31 16 15 0 MSOFFx Register 9 0 0 0 15 0 + PCI Bus Address 1 0 8 0 1 2 3 4 0 15 16 31 =

MPC Transfer Type Transfer Encoding Transaction Clean Block 00000 Addr Only Flush Block 00100 Addr Only SYNC 01000 Addr Only Kill Block 01100 Addr Only EIEIO 10000 Addr Only ECOWX 10100 No Response TLB Invalidate 11000 Addr Only ECIWX 11100 No Response LWARX 00001 Addr Only STWCX 00101 Addr Only TLBSYNC 01001 Addr Only ICBI 01101 Addr Only Reserved 1XX01 No Response Write-with-flush 00010 Write Write-with-kill 00110 Write Read 01010 Read Read-with-intent-to-modify 01110 Read Write-with-flush-atomic 10010 Write Reserved 10110 No Response Read-atomic 11010 Read Read-with-intent-to-modify-atomic 11110 Read Reserved 00011 No Response Reserved 00111 No Response Read-with-no-intent-to-cache 01011 Read Reserved 01111 No Response Reserved 1xx11 No Response

Raven PCI Bridge ASIC 2 MPC Write Posting The MPC write FIFO stores up to eight data beats in any combination of single- and four-beat (burst) transactions. If write-posting is enabled, Raven stores the data necessary to complete an MPC write transfer to the PCI bus and immediately acknowledges the transaction on the MPC bus. This frees the MPC bus from waiting for the potentially long PCI arbitration and transfer. The MPC bus may be used for more useful work while the Raven manages the completion of the write-posted transaction on PCI. All transactions will be completed on the PCI bus in the same order that they are completed on the MPC bus. A read or a compelled write transaction will force all previously issued write-posted transactions to be flushed from the FIFO. All write-posted transfers will be completed before a non-write-posted read or write is begun, to assure that all transfers are completed in the order issued. All write-posted transfers will also be completed before any access to the Raven’s registers is begun. MPC Master The MPC master will attempt to move data using burst transfers wherever possible. A 64-bit-by-16 entry FIFO is used to hold data between the PCI slave and the MPC master to ensure that optimum data throughput is maintained. While the PCI slave is filling the FIFO with one cache line worth of data, the MPC master can be moving another cache line worth onto the MPC bus. This will allow the PCI slave to receive long block transfers without stalling. When programmed in “read ahead” mode (the RAEN bit in the PSATTx register is set) and the PCI slave receives a Memory Read Line or Memory Read Multiple command, the MPC master will fetch data in bursts and store it in the FIFO. The contents of the FIFO will then be used to attempt to satisfy the data requirements for the remainder of the PCI block transaction. If the data requested is not in the FIFO, the MPC master will read another cache line. The contents of the FIFO are “invalidated” at the end of each PCI block transaction.

a problem, as there is no way to snoop all MPC bus transactions and invalidate the contents of the FIFO. 2. Accesses near the top of local memory with read-ahead mode enabled could cause the MPC master to perform reads beyond the top of local memory, which could produce an MPC bus timeout error. The MPC bus transfer types generated by the MPC master depend on the PCI command code and the INV/GBL bits in the PSATTx registers. The GBL bit determines whether or not the GBL∗ signal is asserted for all portions of a transaction, and is fully independent of the PCI command code and INV bit. Table 2-3 shows the relationship between PCI command codes and the INV bit. Table 2-3. MPC Transfer Types The MPC master incorporates an optional operating mode called Bus Hog. When Bus Hog is enabled, the MPC master will continually request the MPC bus for the entire duration of each PCI transfer. When Bus Hog is not PCI Command Code INV MPC Transfer Type MPC Transfer Size TT0-TT4 Memory Read Memory Read Multiple Memory Read Line 0 Read Burst/Single Beat 01010 Memory Read Memory Read Multiple Memory Read Line 1 Read With Intent to Modify Burst/Single Beat 01110 Memory Write Memory Write and Invalidate x Write with Kill Burst 00110 Memory Write Memory Write and Invalidate x Write with Flush Single Beat 00010

Raven PCI Bridge ASIC 2 enabled, the MPC master will structure its bus request actions according to the requirements of the FIFO. Use this mode with caution, since the over- generosity of bus ownership to the MPC master can be detrimental to the host CPU’s performance. The Bus Hog mode can be controlled by the BHOG bit within the GCSR. The default state for BHOG is disabled. MPC Arbiter The MPC Arbiter is an optional feature in the Raven ASIC. It is not used on MVME2300 series boards. Arbitration for the MPC bus on the MVME2300 series is performed external to the Raven. MPC Bus Timer The MPC bus timer allows the current bus master to recover from a lock- up condition resulting from no slave response to the transfer request. The timeout duration of the bus timer is determined by the MBT field in the Global Control/Status register. The bus timer starts ticking at the beginning of an address transfer (TS∗ asserted). If the address transfer is not terminated (AACK∗ asserted) before the timeout period has elapsed, the Raven will assert the MATO bit in the MPC Error Status register, latch the MPC address in the MPC Error Address register, and then terminate the cycle. The MATO bit may be configured to generate an interrupt or a machine check through the MEREN register. The timer is disabled if the transfer is intended for PCI. PCI-bound transfers will be timed by the PCI master. PCI Interface The Raven PCI interface is designed for direct connection to a PCI Local Bus. It supports Master and Target transactions within Memory space, I/O space, and Configuration space.

PCLK input must be externally synchronized with the MCLK input, and the frequency of the PCLK input must be exactly half the frequency of the MCLK input. PCI Address Mapping The Raven ASIC provides three resources to PCI: J Configuration registers mapped into PCI Configuration space J MPC bus address space mapped into PCI Memory space J RavenMPIC control registers mapped into either PCI I/O space or PCI Memory space Configuration Registers The Raven has no IDSEL pin. Instead, an internal connection made within the Raven logically associates the assertion of IDSEL with the assertion of AD31. Raven provides a configuration space that is fully compliant with the PCI Local Bus Specification 2.0 definition for configuration space. Two base registers within the standard 64-byte header are used to control the mapping of RavenMPIC. One register is dedicated to mapping RavenMPIC into PCI I/O space; the other register is dedicated to mapping RavenMPIC into PCI Memory space. The mapping of MPC address space is handled by device-specific registers located above the 64-byte header. These control registers support a mapping scheme that is functionally similar to the PCI-to-MPC mapping scheme described in the section on MPC Address Mapping earlier in this chapter.

Raven PCI Bridge ASIC 2 MPC Bus Address Space The Raven will map MPC address space into PCI Memory space using four programmable map decoders. The most significant 16 bits of the PCI address are compared with the address range of each map decoder; if the address falls within the specified range, the access is passed on to the MPC bus. An example of this appears in Figure 2-4. Figure 2-4. PCI to MPC Address Decoding The Raven ASIC imposes no limits on how large an address space a map decoder can represent. There is a minimum of 64KB due to the resolution of the address compare logic. For each map, there is an associated set of attributes. These attributes are used to enable read accesses, enable write accesses, enable write-posting, and define the MPC bus transfer characteristics. Each map decoder also includes a programmable 16-bit address offset. The offset is added to the 16 most significant bits of the PCI address, and the result is used as the MPC address. This offset allows devices to reside at any MPC address, independent of the PCI address map. An example of this appears in Figure 2-5. PCI Bus Address 8 0 8 0 1 2 3 4 0 15 16 31 PSADDx Register 7 0 8 0 9 0 0 0 0 15 16 31 >= <= and Decode is

All Raven address decoders are prioritized so that programming multiple decoders to respond to the same address is not a problem. When the PCI address falls into the range of more than one decoder, only the highest priority one will respond. The decoders are prioritized as shown below. RavenMPIC Control Registers The RavenMPIC control registers are located within either PCI memory or PCI I/O space using traditional PCI-defined base registers within the predefined 64-byte header. Refer to the section on Raven Interrupt Controller for more information. Decoder Priority PCI Slave 0 highest PCI Slave 1 PCI Slave 2 PCI Slave 3 lowest PCI Bus Address 8 0 8 0 1 2 3 4 0 15 16 31 PSOFFx Register 9 0 0 0 16 31 + MPC Bus Address 1 0 8 0 1 2 3 4 31 16 15 0 =

Raven PCI Bridge ASIC 2 PCI Slave The PCI slave provides the control logic needed to interface the PCI bus to the Raven’s FIFO buffers. The PCI slave can accept either 32-bit or 64-bit transactions, but it can accept only 32-bit addressing. There is no limit to the length of the transfer that the slave can handle. During posted write cycles, the slave will continue to accept write data until the write-post FIFO is full. If the write-post FIFO is full, the slave will hold off the master with wait states until there is more room in the FIFO. The slave will not initiate a disconnect. If the write transaction is compelled, the slave will hold off the master with wait states while each beat of data is being transferred. The slave will acknowledge the completion of the transfer only after the data transfer has successfully completed on the MPC bus. If a read transaction is occurring within an address space marked for prefetching, the slave (in conjunction with the MPC master) will attempt to read far enough ahead on the MPC bus to allow for an uninterrupted burst transaction on the PCI bus. Read transactions within address spaces marked for no prefetching will be acknowledged on the PCI bus only after a single beat read has successfully completed on the MPC bus. Each read on the MPC bus will begin only after the previous read has been acknowledged on the PCI bus and there is an indication that the PCI master wishes more data to be transferred. The following paragraphs identify some associations between the operation of the PCI slave and the requirements of the PCI 2.0 Local Bus Specification.

accept. Addressing The slave will accept any combination of byte enables during read or write cycles. During write cycles, a discontinuity (i.e., a ‘hole’) in the byte enables will force the slave to issue a disconnect. During all read cycles, the slave will return an entire word of data regardless of the byte enables. During I/O read cycles, the slave will perform integrity checking of the byte enables against the address being presented and assert SERR∗ in the event there is an error. Table 2-4. Command Types — PCI Slave Response Command Type Slave Response? Interrupt Acknowledge No Special Cycle No I/O Read Yes I/O Write Yes Reserved No Reserved No Memory Read Yes Memory Write Yes Reserved No Reserved No Configuration Read Yes Configuration Write Yes Memory Read Multiple Yes Dual Address Cycle No Memory Read Line Yes Memory Write and Invalidate Yes

Raven PCI Bridge ASIC 2 The slave will honor only the Linear Incrementing addressing mode. The slave will perform a disconnect with data if any other mode of addressing is attempted. Device Selection The PCI slave will always respond to valid decoded cycles as a medium responder. Target-Initiated Termination The PCI slave normally strives to complete transactions without issuing disconnects or retries. One exception is when the slave performs configuration cycles. All configuration cycles are terminated with a disconnect after one data beat has been transferred. Another exception is the issue of a disconnect when asked to perform a transaction with byte enable ‘holes’. Fast Back-to-Back Transactions The PCI slave supports both of the fundamental target requirements for fast back-to-back transactions. The PCI slave meets the first criteria of being able to successfully track the state of the PCI bus without the existence of an IDLE state between transactions. The second criteria, associated with signal turn-around timing, is met by default since the slave functions as a medium responder. Latency The PCI slave has no hardware mechanisms in place to guarantee that the initial and subsequent target latency requirements are met. This is typically not a problem, since the bandwidth of the MPC bus far exceeds the bandwidth of the PCI bus. The Raven MPC arbiter has been designed to give the highest priority to its own transactions, which further reduces PCI bus latency. Exclusive Access The PCI slave has no mechanism to support exclusive access.

generation and data parity error detection. Cache Support The PCI slave does not participate in the PCI caching protocol. PCI Write Posting If write-posting is enabled, the Raven stores the target address, attributes, and up to 128 bytes of data from one PCI write transaction and immediately acknowledges the transaction on the PCI bus. This allows the slower PCI to continue to transfer data at its maximum bandwidth, and the faster MPC bus to accept data in high-performance cache-line burst transfers. Only one PCI transaction may be write-posted at any given time. If the Raven is busy processing a previous write-posted transaction when a new PCI transaction begins, the next PCI transaction is delayed (TRDY∗ is not asserted) until the previous transaction has completed. If during a transaction the write-post buffer is filled, subsequent PCI data transfers are delayed (TRDY∗ is not asserted) until the Raven has removed some data from the FIFO. Under normal conditions, the Raven should be able to empty the FIFO faster than the PCI bus can fill it. PCI Configuration cycles intended for internal Raven registers are also delayed if the Raven is busy, so that control bits which may affect write- posting do not change until all write-posted transactions have completed. PCI Master The PCI master, in conjunction with the capabilities of the MPC slave, will attempt to move data in either single-beat or four-beat (burst) transactions. All single-beat transactions will be subdivided into one or two 32-bit transfers, depending on the alignment and size of the transaction. The PCI master will attempt to transfer all four-beat transactions in 64-bit mode if the PCI bus has 64-bit mode enabled. If at any time during the transaction the PCI target indicates that it cannot support 64-bit mode, the PCI master will continue to transfer the remaining data in 32-bit mode.

Raven PCI Bridge ASIC 2 The PCI master can support Critical Word First (CWF) burst transfers. The PCI master will divide this transaction into two parts. The first part will start on the address presented with the CWF transfer request and continue up to the end of the current cache line. The second transfer will start at the beginning of the associated cache line and work its way up to (but not including) the word addressed by the CWF request. It should be noted that even though the master can support burst transactions, a majority of the transaction types handled are single-beat transfers. Since PCI space is typically not configured as cacheable, burst transactions to PCI space would not naturally occur. Burst transactions must be supported, however, since it is conceivable that bursting could happen. For example, nothing prevents the processor from loading up a cache line with PCI write data and manually flushing the cache line. The following paragraphs identify some associations between the operation of the PCI master and the requirements of the PCI 2.0 Local Bus Specification. Command Types The PCI command codes generated by the PCI master depend on the type of transaction being performed on the MPC bus. Please refer to the MPC Slave section earlier in this chapter for a further description of MPC bus read and MPC bus write transactions. Table 2-5 summarizes the command types supported and shows how they are generated. Table 2-5. PCI Master Command Codes Entity Addressed MPC Transfer Type TBST∗ MEM C/BE PCI Command PIACK Read x x 0000 Interrupt Acknowledge CONADD/CONDAT Write x x 0001 Special Cycle MPC Mapped PCI Space Read x 0 0010 I/O Read Write x 0 0011 I/O Write -- Unsupported -- 0100 Reserved -- Unsupported -- 0101 Reserved MPC Mapped PCI Space Read 1 1 0110 Memory Read Write x 1 0111 Memory Write

incrementing addressing mode. Combining, Merging, and Collapsing The PCI master does not participate in any of these protocols. Master Initiated Termination The PCI master can handle any defined method of target retry, target disconnect, or target abort. If the target responds with a retry, the PCI master will wait for the required two clock periods and attempt the transaction again. The attempts will continue indefinitely until the transaction either completes, or is aborted by the target, or is aborted due to a Raven-detected bridge lock. The same happens if the target responds with a disconnect and there is still data to be transferred. If the PCI master detects a target abort during a read, any untransferred read data will be filled with 1s. If the PCI master detects a target abort during a write, any untransferred portions of data will be dropped. The same rule applies if the PCI master generates a Master Abort cycle. -- Unsupported -- 1000 Reserved -- Unsupported -- 1001 Reserved CONADD/CONDAT Read x x 1010 Configuration Read CONADD/CONDAT Write x x 1011 Configuration Write -- Unsupported -- 1100 Memory Read Multiple -- Unsupported -- 1101 Dual Address Cycle MPC Mapped PCI Space Read 0 1 1110 Memory Read Line -- Unsupported -- 1111 Memory Write and Invalidate Table 2-5. PCI Master Command Codes (Continued) Entity Addressed MPC Transfer Type TBST∗ MEM C/BE PCI Command

Raven PCI Bridge ASIC 2 Arbitration The PCI master can support parking on the PCI bus. If the PCI master starts a transaction that is going to take more than one beat, the PCI master will continuously assert its request until the transaction has completed. The one exception is when the PCI master receives a disconnect or a retry. Fast Back-to-Back Transactions The PCI master does not generate fast back-to-back transactions. Arbitration Latency Because the bulk of the transactions on PCI are limited to single-beat transfers, the PCI master does not implement a Master Latency timer. Exclusive Access The PCI master is not able to initiate exclusive access transactions. Address/Data Stepping The PCI master does not participate in the Address/Data Stepping protocol. Parity The PCI master supports address parity generation, data parity generation, and data parity error detection. Cache Support The PCI master does not participate in the PCI caching protocol.

Four basic types of bus cycles can be generated on the PCI bus: J Memory and I/O J Configuration J Special Cycle J Interrupt Acknowledge Generating PCI Memory and I/O Cycles Each programmable slave may be configured to generate PCI I/O or memory accesses through the MEM and IOM fields in its Attribute register as shown below. : If the MEM bit is set, the Raven will perform Memory addressing on the PCI bus. The Raven will take the MPC bus address, apply the offset specified in the MSOFFx register, and map the result directly to the PCI bus. The IBM CHRP specification describes two approaches for handling PCI I/O addressing: contiguous or spread address modes. When the MEM bit is cleared, the IOM bit is used to select between these two modes whenever a PCI I/O cycle is to be performed. The Raven will perform contiguous I/O addressing when the MEM bit is clear and the IOM bit is clear. The Raven will take the MPC address, apply the offset specified in the MSOFFx register, and map the result directly to PCI. MEM IOM PCI Cycle Type 1 x Memory 0 0 Contiguous I/O 0 1 Spread I/O

Raven PCI Bridge ASIC 2 The Raven will perform spread I/O addressing when the MEM bit is clear and the IOM bit is set. The Raven will take the MPC address, apply the offset specified in the MSOFFx register, and map the result to PCI as shown in Figure 2-6. . Figure 2-6. PCI Spread I/O Address Translation Spread I/O addressing allows each PCI device’s I/O registers to reside on a different MPC memory page, so device drivers can be protected from each other using memory page protection. All I/O accesses must be performed within natural word boundaries. Any I/O access that is not contained within a natural word boundary will result in unpredictable operation. For example, an I/O transfer of four bytes starting at address $80000010 is considered a valid transfer. An I/O transfer of four bytes starting at address $80000011 is considered an invalid transfer since it crosses the natural word boundary at address $80000013/$80000014. Generating PCI Configuration Cycles The Raven uses configuration mechanism #1 as defined in PCI Local Bus Specification 2.0 to generate configuration cycles. Please refer to the specification for a complete description of this function. 1915 9702 MPC Address + Offset 31 12 11 5 4 0 31 0 PCI Address 25 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4

Performing a configuration access is a two-step process. The first step is to place the address of the configuration cycle within the CONFIG_ADDRESS register. Note that this action does not generate any cycles on the PCI bus. The second step is to either read or write configuration data into the CONFIG_DATA register. If the CONFIG_ADDRESS register has been set up correctly, the Raven will pass this access on to the PCI bus as a configuration cycle. The addresses of the CONFIG_ADDRESS and CONFIG_DATA registers are actually embedded within PCI I/O space. If the CONFIG_ADDRESS register has been set incorrectly or the access to either the CONFIG_ADDRESS or CONFIG_DATA register is not 1,2, or 4 bytes wide, the Raven will pass the access on to PCI as a normal I/O Space transfer. The CONFIG_ADDRESS register is located at offset $CF8 from the bottom of PCI I/O space. The CONFIG_DATA register is located at offset $CFC from the bottom of PCI I/O space. The Raven address decode logic has been designed such that MSADD3 and MSOFF3 must be used for mapping to PCI Configuration (consequently I/O) space. The MSADD3/MSOFF3 register group is initialized at reset to allow PCI I/O access starting at address $80000000. The powerup location (that is, little- endian disabled) of the CONFIG_ADDRESS register is $80000CF8, and the CONFIG_DATA register is located at $80000CFC. The CONFIG_ADDRESS register must be prefilled with four fields: 1. Register Number 2. Function Number 3. Device Number 4. Bus Number The Register Number and Function Number are passed along to the PCI bus as portions of the lower address bits. When performing a configuration cycle, the Raven uses the upper 20 address bits as IDSEL lines. During the address phase of a configuration cycle, only one of the upper address bits will be set. The device that has its

Raven PCI Bridge ASIC 2 IDSEL connected to the address bit being asserted will be selected for a configuration cycle. The Raven decodes the Device Number to determine which of the upper address lines to assert. The decoding of the five-bit Device Number is show below:. The Bus Number determines which bus is the target for the configuration read cycle. The Raven will always host PCI bus #0. Accesses that are to be performed on the PCI bus connected to the Raven must have zero programmed into the Bus Number. If the configuration access is targeted for another PCI bus, then that bus number should be programmed into the Bus Number field. The Raven will detect a nonzero field and convert the transaction to a Type 1 Configuration cycle. Generating PCI Special Cycles The Raven supports the method stated in PCI Local Bus Specification 2.0 to generate special cycles using Configuration Mechanism #1. To prime the Raven for a special cycle, the host processor must write a 32-bit value to the CONFIG_ADDRESS register. The contents of the write are defined later in this chapter under the CONFIG_ADDRESS register definition. After the write to CONFIG_ADDRESS has been accomplished, the next write to the CONFIG_DATA register causes the Raven to generate a special cycle on the PCI bus. The write data is driven onto AD[31:0] during the special cycle’s data phase. Device Number Address Bit 00000 AD31 00001 - 01010 All Zeros 01011 AD11 01100 AD12 (etc.) (etc.) 11101 AD29 11110 AD30 11111 All Zeros

Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge cycle. Any single byte or combination of bytes may be read from, and the actual byte enable pattern used during the read will be passed on to the PCI bus. Upon completion of the PCI interrupt acknowledge cycle, the Raven will present the resulting vector information obtained from the PCI bus as read data. Endian Conversion The Raven ASIC supports both big- and little-endian data formats. Since the PCI bus is inherently little-endian, conversion is necessary if all MPC devices are configured for big-endian operation. The Raven may be programmed to perform the endian conversion described below. When MPC Devices are Big-Endian When all MPC devices are operating in big-endian mode, all data to/from the PCI bus must be swapped such that the PCI bus looks big-endian from the MPC bus’s perspective. This association is true regardless of whether the transaction originates on the PCI bus or the MPC bus. Figure 2-7 illustrates the concept.

Raven PCI Bridge ASIC 2 . Figure 2-7. Big- to Little-Endian Data Swap 1916 9610 DH07-00 DH15-08 DH23-16 DH31-24 DL07-00 DL15-08 DL23-16 DL31-24 D0 D1 D2 D3 D4 D5 D6 D7 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 AD63-56 AD55-48 AD47-40 AD39-32 AD31-24 AD23-16 AD15-08 AD07-00 DH07-00 DH15-08 DH23-16 DH31-24 DL07-00 DL15-08 DL23-16 DL31-24 D7 D6 D5 D4 D3 D2 D1 D0 AD31-24 AD23-16 AD15-08 AD07-00 PPC Bus 64-bit PCI PPC Bus 32-bit PCI

When all MPC devices are operating in little-endian mode, the originating address is modified to remove the exclusive-ORing applied by MPC60x processors before being passed on to the PCI bus. Note that no data swapping is performed. Address modification happens to the originating address regardless of whether the transaction originates from the PCI bus or the MPC bus. The three low-order address bits are exclusive-ORed with a three-bit value that depends on the length of the operand, as shown in Table 2-6. Table 2-6. Address Modification for Little-Endian Transfers Note The only legal data lengths supported in little-endian mode are 1-, 2-, 4-, or 8-byte aligned transfers. Since there are some difficulties with this method in dealing with unaligned PCI-originated transfers, the Raven MPC master will break up all unaligned PCI transfers into multiple aligned PCI transfers into multiple aligned transfers on the MPC bus. Raven Registers and Endian Mode The Raven ASIC’s registers are not sensitive to changes in big-endian and little-endian mode. With respect to the MPC bus (but not always the address internal to the processor), the MPC registers are always represented in big-endian mode. This means that the processor’s internal view of the MPC registers will vary depending on the processor’s operating mode. Data Length (bytes) Address Modification 1 XOR with 111 2 XOR with 110 4 XOR with 100 8 No change

Raven PCI Bridge ASIC 2 With respect with the PCI bus, the RavenMPIC registers and the configuration registers are always represented in little-endian mode. The CONFIG_ADDRESS and CONFIG_DATA registers are actually represented in PCI space to the processor and are subject to the endian functions. For example, the powerup location of the CONFIG_ADDRESS register with respect to the MPC bus is $80000CF8 when the Raven is in big-endian mode. When the Raven is switched to little-endian mode, the CONFIG_ADDRESS register with respect to the MPC bus is $80000CFC. Note that in both cases the address generated internal to the processor will be $80000CF8. The contents of the CONFIG_ADDRESS register are not subject to the endian function. The data associated with PIACK accesses is subject to the endian swapping function. Because the address of a PIACK cycle is undefined, address modification during little-endian mode is not an issue. Error Handling The Raven is capable of detecting and reporting the following errors to one or more MPC masters: J MPC address bus time-out J PCI master signalled master abort J PCI master received target abort J PCI parity error J PCI system error Each of these error conditions will set an error status bit in the MPC Error Status register. If a second error is detected while any of the error bits is set, the OVFL bit is asserted, but none of the error bits are changed. You can clear each bit in the MPC Error Status register by writing a 1 to it; writing a 0 to it has no effect. New error bits may be set only when all previous error bits have been cleared.

attempt to latch as much information as possible about the error in the MPC Error Address and Attribute registers. Information is saved as follows: Each MERST error bit may be programmed to generate a machine check and/or a standard interrupt. The error response is programmed through the MPC Error Enable register on a source-by-source basis. When a machine check is enabled, either the MID field in the MPC Error Attribute register or the DFLT bit in the MEREN register determine the master to which the machine check is directed. For errors in which the master that originated the transaction can be determined, the MID field is used, provided the MID is%00 (processor 0), %01 (processor 1), or %10 (processor 2). For errors not associated with a particular MPC master, or associated with masters other than processor 0, 1, or 2, the DFLT bit is used. One example of an error condition which cannot be associated with a particular MPC master would be a PCI system error. Transaction Ordering The Raven ASIC supports transaction ordering with an optional FIFO flushing option. The FLBRD (Flush Before Read) bit within the GCSR register controls the flushing of PCI write-posted data when performing MPC-originated read transactions. Error Status Error Address and Attributes MATO From MPC bus SMA From PCI bus RTA From PCI bus PERR Invalid SERR Invalid

Raven PCI Bridge ASIC 2 When the FLBRD bit is set, Raven will handle read transactions originating from the MPC bus in the following manner: J Write-posted transactions originating from the processor bus are flushed by the nature of the FIFO architecture. The Raven will hold the processor with wait states until the PCI-bound FIFO is empty. J Write-posted transactions originating from the PCI bus are flushed whenever the PCI slave has accepted a write-posted transaction and the transaction has not completed on the MPC bus. Raven Registers This section provides a detailed description of all registers in the Raven ASIC. The registers are organized in two groups: MPC registers and PCI Configuration registers. The MPC registers are accessible only from the MPC bus, but accept any valid transfer size. The PCI Configuration registers reside in PCI configuration space. They are accessible from the MPC bus through the Raven ASIC. The MPC registers are described first; the PCI Configuration registers are described next. A complete discussion of the RavenMPIC registers can be found later in this chapter. The following conventions are used in the Raven register charts: J R Read Only field. J R/W Read/Write field. J S Writing a ONE to this field sets this field. J C Writing a ONE to this field clears this field. MPC Registers The Raven MPC register map is shown in Table 2-7. 2Raven PCI Bridge ASIC 0Raven Registers