Lattice Semiconductor ECP5 Operation & User’s Manual

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-EB-02001-1.2 Contents Acronyms in This Document ................................................................................................................................................. 4 Introduction ................................................................................................................................................................... 5 Headers and Test Connections ...................................................................................................................................... 7 Programming Circuit ...................................................................................................................................................... 8 ECP5 Interface Support .................................................................................................................................................. 9 4.1. Clock Interface ..................................................................................................................................................... 9 4.2. DDR3 Interface .................................................................................................................................................... 9 4.3. Nanovesta Interface ............................................................................................................................................ 9 4.4. Upstream and Downstream interface ............................................................................................................... 10 4.5. ispClock5406D Interface .................................................................................................................................... 10 4.6. Debugging Interface .......................................................................................................................................... 11 Power Supply ............................................................................................................................................................... 12 ECP5 I/O Ball Mapping to Connectors ......................................................................................................................... 14 Status Indicators .......................................................................................................................................................... 18 Ordering Information .................................................................................................................................................. 19 References .......................................................................................................................................................................... 20 Technical Support Assistance............................................................................................................................................... 20 Appendix A. ECP5 VIP Processor Board Schematics ........................................................................................................... 21 Appendix B. ECP5 VIP Processor Board Bill of Materials .................................................................................................... 29 Revision History ................................................................................................................................................................... 38 Figures Figure 1.1. Top View of ECP5 VIP Processor Board and its Key Components ....................................................................... 6 Figure 1.2. Bottom View of ECP5 VIP Processor Board ......................................................................................................... 6 Figure 3.1. Programming Block using USB Interface ............................................................................................................. 8 Figure 4.1. DDR3 Interface .................................................................................................................................................... 9 Figure 4.2. Nanovesta Connector Interface .......................................................................................................................... 9 Figure 4.3. Upstream and Downstream Connector ............................................................................................................ 10 Figure 4.4. ispClock5406D Interface ................................................................................................................................... 10 Figure 5.1. Power Supply Block ........................................................................................................................................... 12 Figure A.1. Block Diagram ................................................................................................................................................... 21 Figure A.2. FTDI and Programming Interface ...................................................................................................................... 22 Figure A.3. Power Regulator Interface ................................................................................................................................ 23 Figure A.4. MIPI and GPIO Connector Interface ................................................................................................................. 24 Figure A.5. DDR3 Interface ................................................................................................................................................. 25 Figure A.6. SERDES Interface .............................................................................................................................................. 26 Figure A.7. ECP5 Decoupling ............................................................................................................................................... 27 Figure A.8. HISPI/CSI2 Connector ....................................................................................................................................... 28

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 3 Tables Table 2.1. Headers and Test Connectors .............................................................................................................................. 7 Table 4.1. Header (J14) ....................................................................................................................................................... 11 Table 4.2. Switch (SW3) ...................................................................................................................................................... 11 Table 4.3. JTAG Connector (J1) ........................................................................................................................................... 11 Table 5.1. Power LEDs ........................................................................................................................................................ 12 Table 5.2. Device Power Rail Summary and Test Points ..................................................................................................... 13 Table 6.1. Upstream Connector Mapping .......................................................................................................................... 14 Table 6.2. Downstream Connector Pin Mapping ................................................................................................................ 15 Table 6.3. Nanovesta Connector Pin Mapping ................................................................................................................... 17 Table 7.1. Status LED I/O Map ............................................................................................................................................ 18 Table 8.1. Reference Part Number...................................................................................................................................... 19

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-EB-02001-1.2 Acronyms in This Document A list of acronyms used in this document. Acronym Definition CMOS Complementary Metal-Oxide Semiconductor CSI-2 Camera Serial Interface DDR Double Data Rate DSI Display Serial Interface FTDI Future Technology Devices International GPIO General Purpose Input/Output I2C Inter-Integrated Circuit LVDS Low-Voltage Differential Signaling SPI Serial Peripheral Interface VIP Video Interface Platform VTT Tracking Termination Voltage

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 5 1. Introduction This document describes the Lattice Semiconductor ECP5 VIP Processor Board which is a key component of Lattice’s Video Interface Platform (VIP) board interconnect. Lattice VIP boards can be interconnected to create solutions for MIPI® CSI-2/DSI, SERDES, LVDS and more. The content of this user guide includes descriptions of onboard jumper settings, programming circuit, a complete set of schematics, and bill of materials for ECP5 VIP processor board. Key features of the ECP5 VIP processor board include:  ECP5/5G  SERDES interface  Dual DDR3 interface  LVDS/MIPI Transmitter/Receiver interface  SPI flash configuration  General Purpose Input/Output  Programming Circuit  Mini-B USB connector to FTDI  FTDI to ECP5 using JTAG  FTDI to ispClock using JTAG  ispClock  SERDES reference clock generation interface Figure 1.1 on the next page shows the top view of the ECP5 VIP processor board and its key components. Figure 1.2 shows the bottom view of the board. Further Information  For more information on boards and kits available for the VIP system, visit www.latticesemi.com/boards  The board‘s key component is the ECP5™ FPGA. For details about ECP5, refer to FPGA-DS-02012, ECP5 and ECP5- 5G Family Data Sheet.  For the latest information about this board, demo files, further documentation and more, visit www.latticesemi.com/Products/FPGAandCPLD/ECP5.aspx  Refer to Appendix A and Appendix B for the schematics and BOM of the ECP5 VIP processor board.

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-EB-02001-1.2 Figure 1.1. Top View of ECP5 VIP Processor Board and its Key Components Figure 1.2. Bottom View of ECP5 VIP Processor Board

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 7 2. Headers and Test Connections Figure 1.1 shows the top view of the ECP5 VIP processor board. The headers and test connections on the board provide access to ECP5 VIP processor board circuits. Table 2.1 lists the headers and test connectors. Table 2.1. Headers and Test Connectors Part Description Setting J1 External JTAG interface — J2 Mini-B USB connector for programming — J52 JTAG/SPI Selection header 1–2 (SPI), 2–3 (JTAG) J50 JTAG Daisy Chain connector Refer to Schematic note in Appendix A J3 ECP5 Configuration mode selection header Refer to Schematic note in Appendix A J53 FTDI Mode selection 1–2 (Normal), 2–3 (Reset) J4 12 V DC power jack — J5, J6, J51, J9 ECP5 Banks 8, 1, 3, 4 voltage selection 1–2 (3V3), 2–3 (2V5) J7, J55 ECP5 Banks 0, 2 voltage selection 1–2 (3V3), 2–3 (2V5), 2–4 (CN1/CN2_VCC) J14 Debug Header — SW1 Global reset — SW4 Program reset for reprogram — SW3 General purpose DIP switches — SW2 Power on switch — J54 ispClock 5406 reference clock selector 1–2 (External), 2–3 (Internal) CN2 Nanovesta serial interface connector — CN1 Nanovesta parallel interface connector — J10, J11 General purpose upstream connector — J12, J13 General purpose downstream connector —

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-EB-02001-1.2 3. Programming Circuit The Mini-B USB connector is used for programming the board by using Lattice Diamond® Programmer software. Figure 3.1 shows the programming block of ECP5 VIP processor board. The Mini-B USB connector interfaces to the FTDI FT2232H IC. The FTDI IC works with Diamond programmer software to provide interfaces for:  JTAG – to program LFE5UM-85F and its SPI Flash and ispClock  SPI – to program external devices connected to the ECP5 VIP processor board USB Mini-B (J2) FTDI Chip (U1) SPI Flash (U52) Upstream connector (J10) LFE5UM-85F- BG756 (U17) JTAG SPI/ JTAG ispCLOCK5406D (U53) Downstream connector (J12) SPI/ JTAG JTAG SPI/JTAG Figure 3.1. Programming Block using USB Interface

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 9 4. ECP5 Interface Support The ECP5 VIP processor board supports various onboard interfaces and external interfaces through board-to-board connectors. The sections below describe key onboard interfaces supported on ECP5 VIP processor board. Clock Interface Clocking for the ECP5 device on the ECP5 VIP processor board can be done through onboard fixed frequency crystal oscillators, and also internal OSC built inside the ECP5 device. The board has 100 MHz fixed frequency OSC to support DDR3 Memory controller, and 27 MHz to support MIPI/LVDS related interfaces. DDR3 Interface Figure 4.1 shows the block diagram of the DDR3 Interface. The LFE5UM-85F-BG756 (U17) device DDR3 memory controller is used to interface with onboard DD3 memory device and it supports a single rank and multiple memory devices connected on the board. Each memory device supports 16-bit parallel data with 1 Gb memory capacity. The combined capacity supported is 2 Gb. The DDR3 memory controller can be configured to support either 32-bit or 16-bit wide memory interface by enabling the chip select signals for both memory devices. This board is designed to support both on board VTT termination as well as on-die termination and can be configured by memory controller. LFE5UM-85F-BG756 (U17) DDR3 Chip 1 (U12) 16-bit data DDR3 Chip 2 (U19) 16-bit data CNTRL Figure 4.1. DDR3 Interface Nanovesta Interface Figure 4.2 shows the block diagram of the Nanovesta connector interface. The LFE5UM-85F-BG756 (U17) device receives camera input from the Nanovesta connectors. Pin mapping of the Nanovesta connector interface is designed such that the legacy Lattice Nanovesta camera sensor boards can be interfaced with ECP5 VIP processor board. It supports both parallel and SLVS interface for receiving camera input from sensor module. LFE5UM-85F-BG756 (U17) Nanovesta Serial Interface Connector (CN2) GPIO/SLVS I/F SLVS I/F Nanovesta Parallel Interface Connector (CN1) Figure 4.2. Nanovesta Connector Interface

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-EB-02001-1.2 Upstream and Downstream interface Figure 4.3 shows the block diagram of the Upstream and Downstream connector. Upstream and Downstream connectors act as board to board connector and are used to interface the ECP5 VIP processor board to any other external boards for bridging applications. These connectors support interfaces, such as LVDS, MIPI, SPI, JTAG, SERDES and general purpose interface. LFE5UM-85F-BG756 (U17) Downstream connector 1 ( J12) Downstream connector 2 (J13) LVDS/MIPI Rx, SPI, JTAG, SERDES Rx MIPI/LVDS Tx, GPIO I/F LVDS/MIPI Tx, SPI, JTAG, SERDES Tx Upstream connector 2 (J11) Upstream connector 1 (J10) LVDS/MIPI Rx, GPIO I/F Figure 4.3. Upstream and Downstream Connector ispClock5406D Interface Figure 4.4 shows the block diagram of the ispClock5406D interface. For more information on Lattice ispClock, visit www.latticesemi.com/ispclock. The ispClock5406D device can be programmed using JTAG through FTDI interface. This circuitry is used as a reference clock generation circuit for the ECP5 SERDES interface. The input clock source for the reference clock generation circuit can be onboard oscillator or the PLL output from ECP5 FPGA which can be selected by the ref_sel input of the ispClock5406D. ispClock5406D (U53) LFE5UM-85F-BG756 (U17) 156.25 MHz Clock OSC (X4) JTAG Ref_Sel ECP5_PLL SERDES RefCLK LFE5UM-85F-BG756 (U17) Figure 4.4. ispClock5406D Interface

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 11 Debugging Interface The ECP5 VIP processor board supports onboard debugging in the form of JTAG, GPIO Headers and onboard DIP switches. Table 4.1–Table 4.3 list the ECP5 ball mapping for the debugging interfaces. Table 4.1. Header (J14) Header (J14) Pin Number Net Name ECP5 Ball number 4 Header1 AK32 6 Header2 AJ32 8 Header3 AM30 10 Header4 AL30 1 Header5 AQK31 3 Header6 AJ31 5 Header7 AM31 7 Header8 AL32 2 VCCIO2 — 9 GND — Table 4.2. Switch (SW3) Switch (SW3) Pin Number Net Name ECP5 Ball Number 1 SW1 B26 2 SW2 C26 3 SW3 D26 4 SW4 A28 5 SW5 A29 6 SW6 A30 7 SW7 A31 8 SW8 B28 Table 4.3. JTAG Connector (J1) JTAG Connector (J1) Pin Number Net Name 1 3V3 2 FTDI_TDO 3 FTDI_TDI 4 NC 5 NC 6 FTDI_TMS 7 GND 8 FTDI_TCK

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-EB-02001-1.2 5. Power Supply The power supply to the development kit is provided from an external 12 V DC adaptor. Figure 5.1 shows the power supply block of the ECP5 VIP processor board. The Mini-B USB connector is used only for programming and the external power adaptor must be connected to source power for the on board regulators for the normal operation and successful programming. The external adaptor provides 12 V power source through voltage regulators on the board as well as to the external boards connected to Nanovesta, upstream and downstream connectors. Each I/O bank voltage can be selected by putting jumpers on J5, J6, J7, J9, J51, J55. See Table 5.1 for the voltage selection. All voltage generation from the onboard regulator can be measured by a respective test point on the board. J4 12 V to 5 V converter (U54) LDO (U10) LDO (U11) Mini-B USB 1.1 V J3 12 V VUSB 12 V to 2.5 V or 3.3 V dual converter (U8) 12 V to 1.5 V or 1.1 V dual converter (U9) 5 V 3.3 V 1.5 V 2.5 V 1.1 V 1.1 V Power Jack SW2 U7 FUSE Figure 5.1. Power Supply Block Table 5.1 lists the device power rails. There are five voltage regulators on the board used to supply the 5 V, 3.3 V, 2.5 V 1.5 V, and 1.1 V rails. The input to these regulators is either the external 12 V adaptor or on board regulators that is connected to the board. Switch SW2 is used to connect or disconnect the external adaptor power to the board. Table 5.1. Power LEDs Voltage Rail LEDs Colour 12 D15 Green 5 D23 Green 3.3 D17 Green 2.5 D14 Green 1.5 D16 Green VCC_CORE D18 Green VCCA D19 Green VCCHTX D20 Green

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 13 Table 5.2 lists the board voltage rails, including the rail source voltage, test point number, and voltage on net. Table 5.2. Device Power Rail Summary and Test Points Net Name Source Rail Test Points Voltage on Net (V) 12 V 12_Ext — 12 5 V 12 V 5V 5 3V3 12 V 3V3 3.3 2V5 12 V 2V5 2.5 1V5 12 V 1V5 1.5 VCC_CORE 12 V VCC_CORE 1.1 VCCHTX 5 V VCCHTX 1.1 VCCA 5 V VCCA 1.1

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-EB-02001-1.2 6. ECP5 I/O Ball Mapping to Connectors Table 6.1. Upstream Connector Mapping J10 J11 Pin number on Connector Net Name ECP5 Ball Pin Number on Connector Net Name ECP5 Ball 1 3V3 — 1 3V3 — 2 5V — 2 3V3 — 3 3V3 — 3 3V3 — 4 5V — 4 3V3 — 5 GND — 5 UP_GPIO9 F29 6 5V — 6 UP_GPIO17 A13 7 LVDS_CP P27 7 UP_GPIO10 F28 8 GND — 8 UP_GPIO18 A8 9 LVDS_CN P26 9 UP_GPIO1 C29 10 LVDS_D2P J30 10 UP_GPIO19 F9 11 GND — 11 UP_GPIO2 C30 12 LVDS_D2N K30 12 UP_GPIO20 D9 13 LVDS_D0P D30 13 LDI_RX_D3_P F32 14 GND — 14 UP_GPIO21 C9 15 LVDS_D0N D31 15 LDI_RX_D3_N H32 16 LVDS_D3P L31 16 UP_GPIO22 A9 17 GND — 17 GND — 18 LVDS_D3N L30 18 GND — 19 LVDS_D1P K32 19 GND — 20 GND — 20 GND — 21 LVDS_D1N L32 21 LDI_RX_D2_P J29 22 2V5 — 22 GND — 23 GND — 23 LDI_RX_D2_N K29 24 2V5 — 24 UP_GPIO25 C10 25 DIR_GPIO3 — 25 UP_GPIO33 D13 26 GND — 26 UP_GPIO26 B10 27 UP_MCLK — 27 UP_GPIO34 C13 28 GSRN AH1 28 UP_GPIO27 A10 29 UP_SISPI — 29 LDI_RX_D0_P K27 30 UP_GPIO48 C16 30 UP_GPIO28 E11 31 UP_SPISO — 31 LDI_RX_D0_N K26 32 UP_GPIO49 B16 32 UP_GPIO29 D11 33 UP_CSSPIN — 33 GND — 34 GND — 34 UP_GPIO30 C11 35 UP_CDONE — 35 GND — 36 HDRXP0_D1CH0 AM17 36 GND — 37 UP_CRESETB — 37 LDI_RX_D1_P J26 38 HDRXN0_D1CH0 AM18 38 GND — 39 DIR_GPIO4 — 39 LDI_RX_D1_N J27 40 GND — 40 GND — 41 SCL AG1 41 UP_GPIO31 B11 42 HDRXP0_D1CH1 AM20 42 UP_GPIO39 B14

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 15 Table 6.1. Upstream Connector Mapping (Continued) J10 J11 Pin number on Connector Net Name ECP5 Ball Pin Number on Connector Net Name ECP5 Ball 43 SDA AJ1 43 UP_GPIO32 F13 44 HDRXN0_D1CH1 AM21 44 UP_GPIO40 A14 45 FTDI_TCK AK5 45 UP_GPIO37 D14 46 GND — 46 UP_GPIO41 B4 47 FTDI_TDO — 47 UP_GPIO38 C14 48 HDRXP0_D0CH0 AM8 48 UP_GPIO42 F15 49 FTDI_TDI — 49 UP_GPIO45 A15 50 HDRXN0_D0CH0 AM9 50 UP_GPIO43 D15 51 FTDI_TMS AM5 51 UP_GPIO50 D17 52 GND — 52 UP_GPIO44 C15 53 DIR_GPIO5 — 53 GND — 54 HDRXP0_D0CH1 AM11 54 GND — 55 GND — 55 GND — 56 HDRXN0_D0CH1 AM12 56 GND — 57 GND — 57 2V5 — 58 GND — 58 2V5 — 59 GND — 59 2V5 — 60 DIR_GPIO1 — 60 2V5 — Table 6.2. Downstream Connector Pin Mapping J12 J13 Pin number on Connector Net Name ECP5 Ball Pin number on Connector Net Name ECP5 Ball 1 GND — 1 3V3 — 2 12V — 2 3V3 — 3 MIPITX_CLKP A18 3 3V3 — 4 12V — 4 3V3 — 5 MIPITX_CLKN C18 5 LDI_TX_D0_P W31 6 12V — 6 LDI_TX_D1_P AB30 7 GND — 7 LDI_TX_D0_N Y32 8 12V — 8 LDI_TX_D1_N AB29 9 MIPITX_DATA0P F18, R27 9 LDI_TX_D3_P R32 10 MIPITX_DATA2P D19, U29 10 LDI_TX_D2_P AD27 11 MIPITX_DATA0N A19, T27 11 LDI_TX_D3_N T31 12 MIPITX_DATA2N E19, V29 12 LDI_TX_D2_N AE27 13 GND — 13 DW_GPIO5 T29 14 GND — 14 DW_GPIO27 AB28 15 MIPITX_DATA1P B19, R29 15 DW_GPIO6 U28 16 MIPITX_DATA3P F19, P31 16 DW_GPIO28 AB27 17 MIPITX_DATA1N C19, T28 17 DW_GPIO7 V27 18 MIPITX_DATA3N P30, A20 18 DW_GPIO29 AC26 19 GND — 19 DW_GPIO8 V26 20 GND — 20 GND — 21 DW_GPIO46 A25 21 GND —

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-EB-02001-1.2 Table 6.2. Downstream Connector Pin Mapping (Continued) J12 J13 Pin number on Connector Net Name ECP5 Ball Pin number on Connector Net Name ECP5 Ball 22 DW_GPIO48 D25 22 DW_GPIO30 AD26 23 DW_GPIO47 C25 23 DW_GPIO44 C24 24 DW_GPIO49 E25 24 DW_GPIO23 Y27 25 DIR_GPIO3 — 25 DW_GPIO45 D24 26 GND — 26 DW_GPIO24 W28 27 ECP_SCLK AM3 27 DW_GPIO11 P32 28 GSRN AH1 28 DW_GPIO33 AE29 29 ECP_MOSI AK2 29 DW_GPIO12 U31 30 DW_GPIO50 F25 30 DW_GPIO25 Y29 31 ECP_MISO AJ2 31 DW_GPIO3 U27 32 DW_GPIO51 F17 32 DW_GPIO26 W29 33 FPGA_CSN AG3 33 DW_GPIO4 U26 34 GND — 34 DW_GPIO36 AC28 35 DW_DONE AJ4 35 DW_GPIO15 W30 36 HDTXP0_D0CH0 AK9 36 DW_GPIO1 T30 37 DW_INITN AG4 37 DW_GPIO16 Y30 38 HDTXN0_D0CH0 AK10 38 DW_GPIO2 N32 39 DIR_GPIO4 — 39 GND — 40 GND — 40 GND — 41 SCL AG1 41 DW_GPIO17 T32 42 HDTXP0_D0CH1 AK12 42 DW_GPIO39 AC31 43 SDA AJ1 43 DW_GPIO18 AC30 44 HDTXN0_D0CH1 AK13 44 DW_GPIO40 AB32 45 FTDI_TCK AK5 45 DW_GPIO19 AB31 46 GND — 46 DW_GPIO41 AC32 47 FTDI_TDO — 47 DW_GPIO20 V32 48 HDTXP0_D1CH0 AK18 48 DW_GPIO42 AD32 49 FTDI_TDI — 49 DW_GPIO21 W32 50 HDTXN0_D1CH0 AK19 50 DW_GPIO43 A24 51 FTDI_TMS AM5 51 DW_GPIO22 Y26 52 GND — 52 LDI_TX_CK_P R26 53 DIR_GPIO5 — 53 GND — 54 HDTXP0_D1CH1 AK21 54 LDI_TX_CK_N T26 55 GND — 55 GND — 56 HDTXN0_D1CH1 AK22 56 GND — 57 VCCHTX — 57 2V5 — 58 GND — 58 2V5 — 59 VCCHTX — 59 2V5 — 60 DIR_GPIO1 — 60 2V5 —

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 17 Table 6.3. Nanovesta Connector Pin Mapping Connector 1 (CN2) Top - High SPI to Sensor Connector 1 (CN1) Top - Parallel up to Sensor1 Pin number on Connector Net Name ECP5 Ball Pin number on Connector Net Name ECP5 Ball 1 5V — 1 5V — 2 5V — 2 5V — 3 CN2_VCC — 3 CN1_VCC — 4 VDDIO_RP — 4 VDDIO_RH A16 5 GND — 5 GND — 6 GND — 6 GND — 7 GND — 7 GND — 8 GND — 8 GND — 9 — — 9 EXTCLK_FPGA B17 10 HISPI_RESETN C8 10 PIXCLK C17 11 SLVS_3N E30 11 LINE_VALID A4 12 SLVS_5N N29 12 FRAME_VALID A5 13 SLVS_3P F30 13 DOUT6 F11 14 SLVS_5P N30 14 DOUT4 E10 15 PANASONIC_B1N H30 15 SLVS_6N D32 16 SLVS_CN N26 16 SLVS_8N H28 17 PANASONIC_B1P H31 17 SLVS_6P C32 18 SLVS_CP N27 18 SLVS_8P H27 19 SLVS_2N C31 19 SLVS_7N L29 20 PANASONIC_B0N J32 20 SLVS_9N L27 21 SLVS_2P B32 21 SLVS_7P K28 22 PANASONIC_B0P K31 22 SLVS_9P L26 23 SLVS_4N E32 23 DOUT11 F14 24 SLVS_0N D28 24 DOUT9 A11 25 SLVS_4P F31 25 SIGNAL_TRIGGER D7 26 SLVS_0P C28 26 SADDR F8 27 SLVS_1N E29 27 RESET_BAR C7 28 RESERVED B8 28 SDCLK E8 29 SLVS_1P D29 29 OUTPUT_EN_BAR B7 30 HISPI_SDA A2 30 SDATA D8 31 — — 31 STANDBY A7 32 HISPI_SCLK A3 32 OSC_EN B3 33 GND — 33 GND — 34 GND — 34 GND — 35 GND — 35 GND — 36 GND — 36 GND — 37 CN2_VCC — 37 CN1_VCC — 38 CN2_VCC — 38 CN1_VCC — 39 5V — 39 5V — 40 5V — 40 5V — SHIELD1 5V — SHIELD1 5V — SHIELD2 5V — SHIELD2 5V —

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-EB-02001-1.2 7. Status Indicators The LED status indicators on the board show power, configuration, and application status. Table 7.1 lists the status LED I/O map. Table 7.1. Status LED I/O Map Device LED Net Name Colour LFE5UM-85F-BG756 D24 LED1 Green LFE5UM-85F-BG756 D25 LED2 Green LFE5UM-85F-BG756 D26 LED3 Green LFE5UM-85F-BG756 D27 LED4 Green LFE5UM-85F-BG756 D28 LED5 Green LFE5UM-85F-BG756 D29 LED6 Green LFE5UM-85F-BG756 D30 LED7 Green LFE5UM-85F-BG756 D31 LED8 Green ispClock5406D D21 — Blue LFE5UM-85F-BG756 D3 FPGA_CSN Blue LFE5UM-85F-BG756 D4 FPGA_CSN1 Blue LFE5UM-85F-BG756 D1 DW_INITN Blue LFE5UM-85F-BG756 D2 DW_DONE Green

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 19 8. Ordering Information This board is included as part of a kit, and not available as a separate item. The below part number is for reference only, so it is clear which board is described in this document. Please visit www.latticesemi.com/boards for the latest ordering information. Table 8.1. Reference Part Number Description Ordering Part Number ECP5 VIP Processor Board LFE5-VIP-P-EVN

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 FPGA-EB-02001-1.2 References For more information, refer to:  FPGA-DS-02012 (previously DS1044), ECP5 and ECP5-5G Family Data Sheet  FPGA-UG-02015, Lattice Embedded Vision Development Kit User Guide  FPGA-EB-02002, CrossLink VIP Input Bridge Board  FPGA-EB-02003, HDMI VIP Output Bridge Board For more information on ispClock, visit www.latticesemi.com/ispclock Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport.

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 21 Appendix A. ECP5 VIP Processor Board Schematics Figure A.1. Block Diagram 5 5 4 4 3 3 2 2 1 1 D D C C B B A A ECP5 VIP Processor Board Ext Power Adaptor (12V) OnBoard LDO'S & Buck 1V2,1V8,2V5,3V3 USB CONNECTOR USB to JTAG FTDI CHIP USP Programming only JTAG SPI Flash Downstream Connector 1&2 UP stream Connector 1&2 LFE5UM-85F-BG756 SPI MIPI Rx SERDES Rx GPIO I/F MIPI Tx SERDES Tx GPIO I/F 1G/2G DDR3 2 X DDR3 SPI SHA-256 Au I2C (Pg5) (Pg4) (Pg4) (Pg3) (Pg3) (Pg5) (Pg3) (Pg3) (Pg6) ispCLOCK (Pg7) CSI2 Sensor connector1 CSI2 Sensor connector2 CNTRL SLVS (Pg9) (Pg9) DDDattee::: Sizee Schhem mattic RRReevv o fff Sheeeettt Titttlee Latttttticee Sem m micooondductttor Appllicattionns Em m maaail::: ttechsuuppporrtt@Laatttttticesem mi..cooom Board RReev Fridaayy,,, 16--Dec-1116 B 0..1 9 2 BLOCCK DIIIAGRAM M M Prrojecttt ECP5 VIIIP PPPrrocesssorr Board B

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 FPGA-EB-02001-1.2 Figure A.2. FTDI and Programming Interface 5 5 4 4 3 3 2 2 1 1 D D C C B B A A PROGRAMMING INTERFACE Place R187 near U1 NOTE : PLACE SWITCH IN THE TOP SIDE EXTERNAL RESET DONE indicator will light when configuration is successfully completed INITN indicator will light if an error occurs during configuration programming DONE INITN USED AS LED Indicator in User mode USED AS LED Indicator in User mode EEPROM CRYPTOKEY CONFIG FLASH MODE BUS SIZE CLOCK CFG2 CFG1 CFG0 CONFIGURATION TABLE (J3) SSPI MSPI SCM SPCM 1 CCLK MCLK CCLK CCLK 1-4 1 8 0 0 1 0 1 0 1 0 1 1 1 1 DAISY CHAIN ECP5 Only isp Only 1-2 For SPI 2-3 For JTAG FT_EECS FT_EECLK FT_EEDATA GSRN PROGRAMN DW_INITN DW_DONE FPGA_WRITEN ECP_MISO FPGA_CSN ECP_SCLK I2C_SDA I2C_SCL CFG1 CFG0 CFG2 ECP5_TDI FTDI_TCK FTDI_TMS ECP5_TDO GSRN DW_INITN DW_DONE FPGA_WRITEN FPGA_CSN FPGA_CSN1 DW_DONE DW_INITN FPGA_CSN FPGA_CSN1 SCL SDA EEPROM_CS1 EEPROM_CS2 FPGA_CSN1 I2C_SCL I2C_SDA I2C_SDA I2C_SCL EEPROM_CS1 EEPROM_CS2 PROGRAMN SCL SDA ECP_MOSI ECP_CSSPIN ECP5_TDO FTDI_TDI FTDI_TDO ECP5_TDI FTDI_TCK FTDI_TDI FTDI_TDO FTDI_TMS FTDI_TDO FTDI_TDI FTDI_TCK FTDI_TCK FTDI_RST ECP_MISO ECP_SCLK ECP_MOSI ECP_CSSPIN VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO8 3V3 3V3 3V3 3V3 VUSB VCC1V8FT VCC1V8FT 3V3 3V3 3V3 VCCIO8 3V3 VCCIO8 VCCIO8 VCCIO8 VCC1V8FT VCCIO8 VCCIO8 VCCIO8 3V3 3V3 UP_CDONE {5} UP_CRESETB {5} SCL {5,7} SDA {5,7} DW_DONE {5} DW_INITN {5} ECP_MOSI {5} ECP_SCLK {5} {5} ECP_MISO FPGA_CSN {5} ISPCLOCK_TDI {7} ISPCLOCK_TDO {7} GSRN {5} UART_RX {7} UP_SISPI {5} UP_MCLK {5} UP_SPISO {5} FTDI_TCK {5,7} FTDI_TDO {5} FTDI_TMS {5,7} FTDI_TDI {5} UP_CSSPIN {5} UART_TX {7} DDDaaateee: Size SSchhheeematic RReevv o f SShhheeeet TTittle LLLaaattiiceee SSeeemicooonnnddduuuctooorrr AAApppppplliicaaatiooons EEmaaaiil: [email protected] Boooaaarrrddd RRRev PPrrrooojeeect FFrrridddaaay, 11166---DDeeec---11666 C 00.111 99 33 FFTTTDI && PPPrrrooogggrrraaammmiinnggg iinntteerrfaaceee EECCPP55 VVIPPP PPrrroooceeessoorrr BBBooaarrrdd BB R18 10K TP2 1 C23 0.1uF R12 0 R46 10K R32 1K C10 0.1uF C290 18pF DNI C18 0.1uF C4 0.1uF R4 0 J53 CON3 1 2 3 R48 4.7k C3 4u7 1 2 100nF 16V C7 C15 0.1uF J52 CON3 1 2 3 R49 4.7k SW1 SYS_RST 1 2 3 4 J1 header_1x8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 R28 0 0 DNI R11 R26 680R TP18 1 R54 4.7k R50 680R L3 600ohm 500mA 1 2 R475 0 C5 100nF 16V J50 HEADER 3X2 2 4 6 1 3 5 D2 Green 1 2 R53 4.7k R7 0 C280 0.1uF R537 4.7k D1 blue 1 2 R52 680R R474 0 C1 4u7 1 2 R543 0 U3 M24M01 VCC 8 E1 2 E2 3 GND 4 WC# NC 7 1 SCL 6 SDA 5 C11 0.1uF R17 10K R43 10K J3 HEADER 3X2 2 4 6 1 3 5 R477 0 R2 4.7k SW4 SYS_RST 1 2 3 4 D3 blue 1 2 R540 0 L2 600ohm 500mA 1 2 R27 680R R45 10K R15 12k R538 2k2 R479 4.7k D4 blue 1 2 U1 ATSHA204A SCL 6 SDA 5 E-PAD 9 GND 4 NC3 NC2 3 NC1 2 1 NC4 7 VCC 8 R10 0 R539 0 R8 0 33E R33 R30 1K C13 18pF C287 18pF DNI R3 4.7k R542 0 R29 10K R51 4.7k C12 18pF R480 4.7k R19 0 C20 0.1uF R6 4.7k TP3 R25 2k2 C19 0.1uF R20 0 TP1 L1 600ohm 500mA 1 2 R9 0 R44 10K C238 100nF 10V R5 4.7k X1 12MHZ 1 1 3 3 G1 2 G2 4 FTDI High-Speed USB FT2232H FT2232HL U2 VREGIN 50 VREGOUT 49 DM 7 DP 8 REF 6 RESET# 14 EECS 63 EECLK 62 EEDATA 61 OSCI 2 OSCO 3 TEST 13 ADBUS0 16 ADBUS1 17 ADBUS2 18 ADBUS3 19 VPHY 4 VPLL 9 VCORE 12 VCORE 37 VCORE 64 VCCIO 20 VCCIO 31 VCCIO 42 VCCIO 56 AGND 10 GND 1 GND 5 GND 11 GND 15 GND 25 GND 35 GND 47 GND 51 PWREN# 60 SUSPEND# 36 ADBUS4 21 ADBUS5 22 ADBUS6 23 ADBUS7 24 ACBUS0 26 ACBUS1 27 ACBUS2 28 ACBUS3 29 ACBUS4 30 ACBUS5 32 ACBUS6 33 ACBUS7 34 BDBUS0 38 BDBUS1 39 BDBUS2 40 BDBUS3 41 BDBUS4 43 BDBUS5 44 BDBUS6 45 BDBUS7 46 BCBUS0 48 BCBUS1 52 BCBUS2 53 BCBUS3 54 BCBUS4 55 BCBUS5 57 BCBUS6 58 BCBUS7 59 C8 0.1uF R31 1K C237 100nF 10V R481 1k R16 10K 93LC56-SO8 U4 CS 1 CLK 2 DI 3 DO 4 VSS 5 ORG 6 NU 7 VCC 8 LFE5UM-85F-BG756 U17H VCCIO8 AB10 VCCIO8 AC10 AM3 AM4 AL4 AK4 AJ4 AG4 AJ2 AK2 AG3 AH3 AJ3 AK3 AL3 AG1 AH1 AJ1 AK1 AL1 AM2 AH4 AG5 AK5 CCLK CFG_0 CFG_1 CFG_2 DONE INITN PB11A/ D1/MISO/IO1 PB11B/ D0/MOSI/IO0 PB13A/ SN/CSN/SCAN_SHFT_EN PB13B/ CS1N PB15A/ HOLDN/DI/BUSY/CSSPIN/CEN PB15B/ DOUT/CSON/ATB_FORCE PB18A/ WRITEN/ATB_SENSE PB4A/ D7/IO7 PB4B/ D6/IO6 PB6A/ D5/MISO2/IO5 PB6B/ D4/MOSI2/IO4 PB9A/ D3/IO3 PB9B/ D2/IO2 PROGRAMN TDO TCK/ TEST_CLK TDI AJ5 TMS AM5 C17 0.1uF C2 100nF 16V C21 0.1uF C288 18pF DNI R482 4.7k R14 2k2 R559 1K J2 SKT_MINIUSB_B_RA VCC 1 D- 2 D+ 3 ID 4 GND 5 SHIELD3 8 SHIELD2 7 SHIELD1 6 SHIELD4 9 C9 10uF R1 4.7k C6 0.1uF C25 100nF 16V 2N2222 Q1 3 1 2 C289 18pF DNI C16 0.1uF R38 4.7k R47 4.7k C14 0.1uF TP17 1 C24 100nF 16V U52 N25Q128A13ESE40E S# 1 DQ1 2 W#/VPP/DQ2 3 VSS 4 DQ0 C 5 HOLD#/DQ3 6 VCC 7 8

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 23 Figure A.3. Power Regulator Interface 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR3 2_5V Current +1.5v 1.1 A 3_3V Current 1.2v/ms 1.2v/ms 1.2v/ms +3.3 v 1.35 A +1.1 v 1.35 A Vout = 0.8*((R75/R80)+1) = 1.10 v Vout = 0.8*((R61/R66)+1) = 3.28 v Vout = 0.8*((R76/R81)+1) = 1.51 v Core Power 3.3V 1_5V Current 1.5V 1.2v/ms +2.5v 1.1 A Vout = 0.8*((R60/R62)+1) = 2.52 v 2.5V 0.45 v drop at 500 mA max SERDES VCCHTX 1.1V Power +1.1 v 500 mA SERDES VCCA 1.1V Power +1.1 v 500 mA 1_1V Current GLOBAL POWER TEST POINTS All the mounting holes needs to be connected to ground 12V 12V 3V3 3V3 3V3 2V5 VCC_CORE 3V3 1V5 3V3 12V_EXT 12V 12V 12V 12V 12V 12V 1V5 3V3 2V5 VCC_CORE VCCA 12V VCCHTX 12V_EXT 12V 5V 5V VCCIO8 3V3 2V5 VCCIO1 3V3 2V5 VCCIO3 3V3 2V5 CN1_VCC 2V5 3V3 VCCIO0 VCCIO4 3V3 2V5 12V 5V 5V 1V5 5V 3V3 2V5 12V VCC_CORE VCCHTX VCCA VCCHTX VCCA VCCIO2 3V3 2V5 CN2_VCC DDDaaateee: Siiizeee SSchheeemaaatic RRReev o f SShhheeeeet TTTiiitttlllee LLLaaattiiceee SSSeeemicooonnnddduuucttooorrr AAAppppppliicaaatiiiooonns EEmaaaiil: [email protected] BBoooarrrddd RRReeev PPrrrooojjeeect FFrriddaay,,, 1166---DDDeecc---11166 CCC 00...1 99 44 PPooowwweerrr RRReegguullaaatttoorrr innttteeefffaacee EECCPPP55 VVIIIPP PPPrrroocceesssoorr BBBooaaarrdd BBB VCCHTX 1 L26 4.7uH R63 51k C55 100pF 25V C50 10pF 50V C277 1uF 25V R67 51k R87 10K 3V3 1 R78 63.4K R88 110K C49 10pF 50V C60 10uF 16V GND1 1 R81 10K C41 22uF 6.3V C36 330pF 50V TP10 C257 47uF Q5 MMBT2222A 2 1 C54 22uF 6.3V U7 FUSE 1 1 2 2 L5 4.7uH TP5 1000pF C32 25V L7 4.7uH C48 330pF 50V C276 100pF 31.6K25V D10 1N4448W 2 1 TP12 D14 Green 1 32 R231 536K VCCA 1 R545 2k2 ThruHole R66 10K R557 10K SW2 PWR 1 3 2 R556 30.1K R62 10K R91 110K TP8 C278 33pF 2V5 1 C38 22uF 6.3V 220nF C44 16V D16 Green 1 32 TH2 ThruHole L28 60ohms 2.3A 1 2 R550 680R 1000pF C47 25V R65 51k R232 100K R57 0 C37 10pF 50V C34 10pF 50V R547 2k2 TH1 TH3 TH4 ThruHole J5 CON3 1 2 3 C27 0.1uF 25V L6 4.7uH C258 470pF U9 LT3508EUF FB2 18 VC2 19 PG2 20 RT/SYNC 22 SHDN 21 FB1 1 TRACK/SS1 2 BOOST1 7 SW1 8 VIN1 9 VC1 24 VIN2 10 PG1 23 SW2 11 BOOST2 12 TRACK/SS2 17 GND5 25 GND6 13 GND7 14 GND4 6 GND3 5 GND2 4 GND1 3 GND8 15 GND9 16 J55 Tri-Con 2V5 1 VCCIO2 2 3V3 3 1V2 4 C58 22uF 6.3V U11 LT3085 OUT_1 1 OUT_2 2 SET 3 IN_7 5 IN_8 6 VCtrl 4 Pad 7 C28 0.1uF 25V L27 60ohms 2.3A 1 2 R230 34K R549 2k2 R73 10K D12 DFLS220L 1 2 ThruHole J7 Tri-Con 2V5 1 VCCIO0 2 3V3 3 1V2 4 D19 Green 1 32 C67 10uF 16V C53 22uF 6.3V R70 0 100E R56 DNI C279 47pF D23 Green 1 2 LT3680 U54 LT3680 Manufacturer = Linear PART_NUMBER = LT3680EDD#PBF BD 1 BOOST 2 SW 3 VIN 4 RUN_SS 5 SYNC 6 PG 7 FB 8 VC 9 RT 10 EPAD 11 C40 22uF 6.3V R64 34K U10 LT3085 OUT_1 1 OUT_2 2 SET 3 IN_7 5 IN_8 6 VCtrl 4 Pad 7 C29 10uF 35V D20 Green 1 32 C51 330pF 50V R59 0 R75 3.83K D11 1N4448W 2 1 C259 0.47uF R72 0 1000pF C33 25V D13 DFLS220L 1 2 J6 CON3 1 2 3 1000pF C46 25V 220nF C30 16V C275 100pF 21.5K25V Q2 MMBT2222A 2 1 R544 2k2 1K R509 C66 1uF 25V C70 100nF 16V D9 DFLS220L 1 2 L4 4.7uH Q6 MMBT2222A 2 1 TP7 R58 51k C256 10uF R74 10K D15 Green 1 2 D18 Green 1 32 C26 10uF 35V C52 100pF 25V D17 Green 1 2 TP6 C56 22uF 6.3V 220nF C45 16V D7 1N4448W 2 1 R76 8.87K R92 10K C43 10uF 35V C42 22uF 6.3V TP11 R60 220nF C31 16V 12V 1 R546 2k2 R61 R77 34.8K GND4 1 Q3 MMBT2222A 2 1 1V5 1 D8 DFLS220L 1 2 TP9 J9 CON3 1 2 3 R558 10K R80 10K R86 10K C35 330pF 50V C59 1uF 25V D22 0.3VF MBRA340T3G 2 1 GND5 1 R548 2k2 VCC_CORE 1 D6 1N4448W 2 1 5V 1 C63 100nF 16V Q4 MMBT2222A 2 1 GND2 1 J51 CON3 1 2 3 C57 22uF 6.3V C39 22uF 6.3V U8 LT3508EUF FB2 18 VC2 19 PG2 20 RT/SYNC 22 SHDN 21 FB1 1 TRACK/SS1 2 BOOST1 7 SW1 8 VIN1 9 VC1 24 VIN2 10 PG1 23 SW2 11 BOOST2 12 TRACK/SS2 17 GND5 25 GND6 13 GND7 14 GND4 6 GND3 5 GND2 4 GND1 3 GND8 15 GND9 16 D5 V12P10 2 3 1 J4 PJ-051A 1 2 3

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 FPGA-EB-02001-1.2 Figure A.4. MIPI and GPIO Connector Interface 5 5 4 4 3 3 2 2 1 1 D D C C B B A A NOTE : PLACE X2 NEAR U17 NOTE : R119 SHUOULD BE PLACED NEAR X2 OSCILLATOR NOTE : PLACE NEAR U17 NOTE : PLACE NEAR U17 NOTE : PLACE NEAR U17 NOTE : PLACE NEAR U17 NOTE : PLACE ALL De-Coupling near U17 RS RS RP RP LP_P LP_N D/C_N D/C_P NOTE : MIPI TX Resistors Placement bt dont use comman pad RS and RP NOTE : PLACE NEAR U17 SLVS_0P SLVS_0N UP_GPIO1 UP_GPIO2 SLVS_1P SLVS_1N SLVS_2P SLVS_2N LVDS_D0P LVDS_D0N SLVS_3P SLVS_3N LDI_RX_D3_P LDI_RX_D3_N PANASONIC_B1P PANASONIC_B1N LVDS_D2P LVDS_D2N PANASONIC_B0P PANASONIC_B0N LVDS_D1P LVDS_D1N LDI_RX_D2_N LP_MIPITX_CLKP CLKN LP_MIPITX_CLKN CLKP MIPITX_CLKP MIPITX_CLKN LP_MIPITX_DATA0P DATA0N LP_MIPITX_DATA0N DATA0P MIPITX_DATA0P MIPITX_DATA0N LP_MIPITX_DATA1P DATA1N LP_MIPITX_DATA1N DATA1P MIPITX_DATA1P MIPITX_DATA1N LP_MIPITX_DATA2P DATA2N LP_MIPITX_DATA2N DATA2P MIPITX_DATA2P MIPITX_DATA2N LP_MIPITX_DATA3P DATA3N LP_MIPITX_DATA3N DATA3P MIPITX_DATA3P MIPITX_DATA3N DW_GPIO47 DW_GPIO48 HDRXP0_D0CH0 HDRXN0_D0CH0 HDRXP0_D0CH1 HDRXN0_D0CH1 HDRXN0_D1CH1 HDRXP0_D1CH1 HDRXN0_D1CH0 HDRXP0_D1CH0 UP_GPIO17 UP_GPIO18 UP_GPIO19 UP_GPIO20 UP_GPIO21 UP_GPIO22 UP_GPIO26 UP_GPIO27 UP_GPIO28 UP_GPIO29 UP_GPIO25 UP_GPIO30 UP_GPIO39 UP_GPIO40 UP_GPIO41 UP_GPIO42 UP_GPIO43 UP_GPIO44 UP_CDONE UP_CRESETB UP_SPISO UP_SISPI UP_MCLK UP_CSSPIN FTDI_TCK FTDI_TDO FTDI_TDI FTDI_TMS MIPITX_CLKP MIPITX_CLKN MIPITX_DATA0P MIPITX_DATA0N MIPITX_DATA1P MIPITX_DATA1N MIPITX_DATA2P MIPITX_DATA2N MIPITX_DATA3P MIPITX_DATA3N HDTXN0_D0CH1 HDTXP0_D0CH1 HDTXN0_D0CH0 HDTXP0_D0CH0 HDTXN0_D1CH0 HDTXP0_D1CH0 HDTXN0_D1CH1 HDTXP0_D1CH1 FTDI_TCK FTDI_TDO FTDI_TDI FTDI_TMS SCL SDA DW_GPIO6 DW_GPIO5 DW_GPIO8 DW_GPIO7 DW_GPIO12 DW_GPIO11 DW_GPIO16 DW_GPIO15 DW_GPIO22 DW_GPIO21 DW_GPIO20 DW_GPIO19 DW_GPIO18 DW_GPIO17 DW_GPIO29 DW_GPIO28 DW_GPIO27 DW_GPIO30 DW_GPIO33 DW_GPIO36 DIR_GPIO1 DIR_GPIO3 DIR_GPIO5 DIR_GPIO3 DIR_GPIO4 DIR_GPIO1 DW_GPIO49 DW_GPIO50 DW_GPIO51 SCL SDA CLK_INT CLK_INT DW_GPIO46 DW_GPIO47 DW_GPIO48 DW_GPIO49 SLVS_0P SLVS_0N SLVS_1P SLVS_1N SLVS_2P SLVS_2N SLVS_3P SLVS_3N PANASONIC_B1P PANASONIC_B1N PANASONIC_B0P PANASONIC_B0N SLVS_CP SLVS_CN LP_MIPITX_CLKP LP_MIPITX_CLKN UP_GPIO9 UP_GPIO10 LDI_RX_D2_P LDI_RX_D2_N UP_GPIO33 UP_GPIO34 LDI_RX_D0_P LDI_RX_D0_N LDI_RX_D1_P LDI_RX_D1_N UP_GPIO32 UP_GPIO31 UP_GPIO37 UP_GPIO38 UP_GPIO45 DW_GPIO40 DW_GPIO41 DW_GPIO39 DW_GPIO42 DW_GPIO43 UP_GPIO43 UP_GPIO44 UP_GPIO49 UP_GPIO48 UP_GPIO45 SLVS_CP SLVS_CN DW_GPIO4 DW_GPIO3 DATA0N DATA1P DATA0P LDI_TX_CK_N DATA1N LDI_TX_CK_P CLKN CLKP DATA2P DATA2N DATA3P DATA3N DW_GPIO5 DW_GPIO6 DW_GPIO7 DW_GPIO8 DW_GPIO18 DW_GPIO19 UP_GPIO25 UP_GPIO26 UP_GPIO27 UP_GPIO30 UP_GPIO31 UP_GPIO32 UP_GPIO33 UP_GPIO34 UP_GPIO17 UP_GPIO29 UP_GPIO28 UP_GPIO40 UP_GPIO37 UP_GPIO38 UP_GPIO39 UP_GPIO18 UP_GPIO19 UP_GPIO20 UP_GPIO21 UP_GPIO22 LDI_RX_D1_N LDI_RX_D0_P LP_MIPITX_DATA0P LP_MIPITX_DATA1P LP_MIPITX_DATA1N LP_MIPITX_DATA2P LP_MIPITX_DATA2N LP_MIPITX_DATA0N LP_MIPITX_DATA3P LP_MIPITX_DATA3N DW_GPIO39 DW_GPIO40 DW_GPIO41 DW_GPIO42 DW_GPIO1 DW_GPIO2 DW_GPIO11 DW_GPIO12 LDI_TX_D3_N DW_GPIO15 DW_GPIO16 DW_GPIO17 DW_GPIO27 DW_GPIO28 DW_GPIO29 DW_GPIO33 LDI_TX_D0_P DW_GPIO20 DW_GPIO21 DW_GPIO22 DW_GPIO23 DW_GPIO24 DW_GPIO25 DW_GPIO26 DW_GPIO43 DW_GPIO45 DW_GPIO44 LVDS_D3P LVDS_D3N UP_GPIO48 UP_GPIO49 LVDS_D2N DW_GPIO50 DW_GPIO51 DW_GPIO46 DW_GPIO47 DW_GPIO49 DW_GPIO48 DW_GPIO50 UP_GPIO42 UP_GPIO41 UP_GPIO44 UP_GPIO43 UP_GPIO45 UP_GPIO48 UP_GPIO49 UP_GPIO50 LVDS_CP LVDS_CN LVDS_D3P LVDS_D3N LVDS_D0P LVDS_D0N LVDS_D1P LVDS_D1N LVDS_D2P LVDS_D2N LVDS_D3P LVDS_D3N LVDS_CP LVDS_CN LDI_RX_D3_N UP_GPIO2 LDI_RX_D3_P UP_GPIO1 LVDS_D1P LVDS_D1N LVDS_CP LVDS_CN LVDS_D0P LVDS_D0N LVDS_D2P UP_GPIO50 DW_GPIO51 LDI_TX_D0_N LDI_TX_D1_P LDI_TX_D1_N DW_GPIO36 DW_GPIO30 LDI_TX_D2_P LDI_TX_D2_N LDI_TX_D3_P LDI_RX_D0_N LDI_RX_D1_P LDI_RX_D2_P LDI_RX_D1_P LDI_RX_D1_N LDI_RX_D2_P LDI_RX_D2_N LDI_RX_D3_P LDI_RX_D3_N LDI_RX_D0_P LDI_RX_D0_N UP_GPIO9 UP_GPIO10 LDI_TX_D0_P LDI_TX_D0_N LDI_TX_D3_P LDI_TX_D3_N DW_GPIO3 DW_GPIO4 DW_GPIO2 DW_GPIO1 LDI_TX_D1_P LDI_TX_D1_N LDI_TX_D2_P LDI_TX_D2_N DW_GPIO24 DW_GPIO23 DW_GPIO25 DW_GPIO26 LDI_TX_CK_P LDI_TX_CK_N DW_GPIO44 DW_GPIO45 VCCIO2 VCCIO2 5V VCCIO1 VCCIO1 VCCIO3 VCCIO1 3V3 2V5 3V3 2V5 12V VCCIO0 VCCIO0 3V3 3V3 2V5 2V5 VCCIO1 2V5 3V3 VCCIO0 VCCIO3 VCCIO1 VCCIO0 VCCHTX HDRXP0_D0CH0 {7} HDRXN0_D0CH0 {7} HDRXP0_D0CH1 {7} HDRXN0_D0CH1 {7} HDRXP0_D1CH0 {7} HDRXN0_D1CH0 {7} HDRXP0_D1CH1 {7} HDRXN0_D1CH1 {7} {3} UP_CDONE DIR_G{P3I}O4 UP_CRESETB {3} UP_MCLK {3} UP_SISPI {3} UP_SPISO {3} UP_CSSPIN HDTXP0_D0CH0 {7} HDTXN0_D0CH0 {7} HDTXP0_D0CH1 {7} HDTXN0_D0CH1 {7} HDTXP0_D1CH1 {7} HDTXN0_D1CH1 {7} HDTXP0_D1CH0 {7} HDTXN0_D1CH0 {7} {3,7} SCL {3,7} SDA {3} FTDI_TDO DIR_GPIO5{3,7} FTDI_TMS {3,7} FTDI_TCK {3} FTDI_TDI SLVS_0P {9} SLVS_0N {9} PANASONIC_B0P {9} PANASONIC_B0N {9} SLVS_3P {9} SLVS_3N {9} SLVS_2P {9} SLVS_2N {9} PANASONIC_B1P {9} PANASONIC_B1N {9} SLVS_1P {9} SLVS_1N {9} {9} SIGNAL_TRIGGER {9} RESET_BAR {9} OUTPUT_EN_BAR {9} STANDBY {9} SADDR {9} SDCLK {9} SDATA {9} HISPI_RESETN {3} ECP_SCLK {3} ECP_MOSI {3} ECP_MISO {3} FPGA_CSN {3} DW_DONE {3} DW_INITN SLVS_CP {9} SLVS_CN {9} {7} 156MHz_EN {7} ECP5_PLL ECP5_PLL_VREF {7} {7} SW2 {7} SW1 {7} SW4 {7} SW3 {7} SW6 {7} SW5 {7} SW8 {7} SW7 GSRN {3,5} GSRN {3,5} SLVS_4P {9} SLVS_4N {9} SLVS_5P {9} SLVS_5N {9} SLVS_6P {9} SLVS_6N {9} SLVS_7P {9} SLVS_7N {9} SLVS_8P {9} SLVS_8N {9} SLVS_9P {9} SLVS_9N {9} {9} DOUT4 {9} DOUT6 {9} DOUT9 {9} DOUT11 {9} OSC_EN {9} EXTCLK_FPGA {9} PIXCLK {9} FRAME_VALID {9} LINE_VALID {9} VDDIO_RP {9} VDDIO_RH {9} HISPI_SCLK {9} RESERVED {9} HISPI_SDA DDDaaateee: Siiizeee Schhheemaaatiic RReeev ooo f SSheeeeet TTiiittllleee LLLaaattiiicceee Seeemiiicooonnnddduuucctooorrr AApppplllicaaatiiiooons EEmaaaiiilll:: tteeechhhsuuuppppppooorrrt@LLLaaattiiiceesem mi.cooom BBBoooaarrddd RRReeev PPrrrooojjjeeect FFriddaay, 111666-DDDeecc-166 CCC 00.11 9 55 MIPPPIII && GPPIO CCCoonnnneectoorr I/FFF EECCCPP55 VVVIPPP PProoocceessoor BBBooaaardd B C91 100nF 16V J11 CONN RCPT 30x2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 R94 0 R148 4.7k DNI R55D1NI 100E DNI R121 0E C89 100nF 16V C77 1uF 25V 49.9E R137 DNI R555 100E R126 0E R149 4.7k DNI R465 100E DNI 49.9E R127 DNI R578 100E DNI R470 100E DNI R135 0E C90 100nF 16V C76 100nF 16V R140 49.9E DNI R151 4.7k DNI R552 100E DNI R505 220E C75 100nF 16V 49.9E R124 DNI J12 CONN RCPT 30x2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 R123 49.9E DNI R150 4.7k DNI R579 100E DNI R128 49.9E DNI R504 10K R553 100E DNI R152 4.7k DNI R106 0 R119 0 R110 4.7k DNI R580 100E DNI R130 0E R139 0E LFE5UM-85F-BG756 U17A VCCIO0 K16 VCCIO0 K15 VCCIO0 K14 VCCIO0 K12 PT11A D7 PT11B C7 PT13A B7 PT13B A7 PT15A F8 PT15B E8 PT18A D8 PT18B C8 PT20A B8 PT20B A8 PT22A F9 PT22B D9 PT24A C9 PT24B A9 PT27A F10 PT27B E10 PT29A D10 PT29B C10 PT31A B10 PT31B A10 PT33A F11 PT33B E11 PT36A D11 PT36B C11 PT38A B11 PT38B A11 PT40A F13 PT40B D13 PT42A C13 PT42B A13 PT45A F14 PT45B E14 PT47A D14 PT47B C14 PT49A B14 PT49B A14 PT4A/ ULC_GPLL1T_IN B3 PT4B/ ULC_GPLL1C_IN B4 PT51A F15 PT51B D15 PT54A C15 PT54B A15 PT56A F16 PT56B E16 PT58A D16 PT58B C16 PT60A/ GR_PCLK0_1 B16 PT60B/ GR_PCLK0_0 A16 PT63A/ PCLKT0_1 A17 PT63B/ PCLKC0_1 B17 PT65A/ PCLKT0_0 C17 PT65B/ PCLKC0_0 D17 PT6A A2 PT6B A3 PT9A A4 PT9B A5 R111 4.7k DNI C74 100nF 16V R466 100E DNI R554 100E DNI C87 100nF 16V 49.9E R129 DNI R108 0 R464 100E DNI R581 100E DNI R506 220E R122 0E R113 4.7k DNI R125 0E J10 CONN RCPT 30x2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 J13 CONN RCPT 30x2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 R132 49.9E DNI C88 1uF 25V C84 1uF 25V R112 4.7k DNI R471 100E DNI C78 100nF 10V C83 100nF 16V R134 0E C85 100nF 16V R469 100E DNI C73 100nF 16V C86 100nF 16V C82 100nF 16V LFE5UM-85F-BG756 U17B VCCIO1 K21 VCCIO1 K19 VCCIO1 K18 VCCIO1 K17 PT101A A24 PT101B C24 PT103A D24 PT103B F24 PT105A A25 PT105B B25 PT107A C25 PT107B D25 PT110A E25 PT110B F25 PT112A A26 PT112B B26 PT114A C26 PT114B D26 PT116A A28 PT116B A29 PT119A A30 PT119B A31 PT121A/ URC_GPLL1T_IN B29 PT121B/URC_GPLL1C_IN B30 PT69A/ PCLKT1_1 E17 PT69B/ PCLKC1_1 F17 PT71A/ PCLKT1_0 A18 PT71B/ PCLKC1_0 C18 PT74A/ GR_PCLK1_0 D18 PT74B/ GR_PCLK1_1 F18 PT76A A19 PT76B B19 PT78A C19 PT78B D19 PT80A E19 PT80B F19 PT83A A20 PT83B C20 PT85A D20 PT85B F20 PT87A A22 PT87B B22 PT89A C22 PT89B D22 PT92A E22 PT92B F22 PT94A A23 PT94B B23 PT96A C23 PT96B D23 PT98A E23 PT98B F23 KC2520B27.0000C2GE00 X2 GND 2 VDD 4 STDBY# 1 OUT 3 49.9E R133 DNI R114 4.7k DNI C81 100nF 16V R467 100E DNI R131 0E R117 100K R136 49.9E DNI LFE5UM-85F-BG756 U17D VCCIO3 U23 VCCIO3 V23 VCCIO3 W23 VCCIO3 AA23 PR47A/ PCLKT3_1/S3_OUT P28 PR47B /PCLKC3_1 P29 PR47C / PCLKT3_0/S4_IN R26 PR47D/ PCLKC3_0 T26 PR50A/ GR_PCLK3_0 R27 PR50B T27 PR50C/ GR_PCLK3_1 U27 PR50D U26 PR53A R29 PR53B T28 PR53C T29 PR53D U28 PR56A/ S4_OUT U29 PR56B/ VREF1_3 V29 PR56C/ S5_IN V27 PR56D V26 PR59A P31 PR59B P30 PR59C R30 PR59D T30 PR62A N32 PR62B P32 PR62C U31 PR62D U30 PR65A R32 PR65B T31 PR65C W30 PR65D Y30 PR68A T32 PR68B U32 PR68C V32 PR68D W32 PR71A Y26 PR71B Y27 PR71C Y28 PR71D W28 PR74A Y29 PR74B W29 PR74C AB26 PR74D AC27 PR77A AB28 PR77B AB27 PR77C AC26 PR77D AD26 PR80A AD27 PR80B AE27 PR80C AE28 PR80D AE29 PR83A/ S5_OUT AB30 PR83B/ S6_IN AB29 PR83C AC28 PR83D AD29 PR86A/ S6_OUT W31 PR86B/ S7_IN Y32 PR86C AD30 PR86D AE30 PR89A AC30 PR89B AB31 PR89C/ LRC_GPLL0T_MFGOUT2 AC31 PR89D/ LRC_GPLL0C_MFGOUT2 AE31 PR92A/ LRC_GPLL0T_MFGOUT1 AB32 PR92B/ LRC_GPLL0C_MFGOUT1 AC32 PR92C/ LRC_GPLL0T_IN AD32 PR92D/ LRC_GPLL0C_IN/S7_OUT AE32 C92 1uF 25V LFE5UM-85F-BG756 U17C VCCIO2 M23 VCCIO2 P23 VCCIO2 R23 VCCIO2 T23 PR11A/ URC_GPLL0T_IN C28 PR11B/ URC_GPLL0C_IN/S0_IN D28 PR11C/ URC_GPLL0T_MFGOUT2 C29 PR11D/ URC_GPLL0C_MFGOUT2 C30 PR14A/ S0_OUT D29 PR14B/ S1_IN E29 PR14C F29 PR14D F28 PR17A/ URC_GPLL0T_MFGOUT1 B32 PR17B/ URC_GPLL0C_MFGOUT1 C31 PR17C D30 PR17D D31 PR20A F30 PR20B E30 PR20C C32 PR20D D32 PR23A F31 PR23B E32 PR23C F32 PR23D H32 PR26A H31 PR26B H30 PR26C J30 PR26D K30 PR29A K31 PR29B J32 PR29C K32 PR29D L32 PR32A L31 PR32B L30 PR32C J29 PR32D K29 PR35A/ S1_OUT H27 PR35B/S2_IN H28 PR35C/ VREF1_2 J26 PR35D J27 PR38A K27 PR38B K26 PR38C K28 PR38D L29 PR41A/ GR_PCLK2_1 N30 PR41B N29 PR41C/ GR_PCLK2_0 L26 PR41D L27 PR44A/ PCLKT2_1/S2_OUT N27 PR44B/ PCLKC2_1 N26 PR44C/ PCLKT2_0/S3_IN P27 PR44D/ PCLKC2_0 P26 R93 0 R138 0E

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 25 Figure A.5. DDR3 Interface 5 5 4 4 3 3 2 2 1 1 D D C C B B A A ALL Memory controller buses, clocks, and control traces must be 50 Ohm Transmission lines PLACE CLOSE TO MEMORY CHIP for all traces Place Address/Control Termination Resistors as close as possible to Memory Chip U7 VTT X1 needs to be matched length U17 Pin MEMORY DEVICE TERMINATION for ADDRESS/ CONTROL SIGNALS X1 X2 Termination at end of line Memory NOTE : PLACE VDD1,VDDQ1 De-Caps near U12 NOTE : PLACE VDD1,VDDQ1 De-Caps near U19 Place close to FPGA DDR3_DQ1 DDR3_DQ4 DDR3_DQ2 DDR3_DQ0 DDR3_DQ5 DDR3_DQ7 DDR3_DQ3 DDR3_DM1 DDR3_A5 DDR3_A3 DDR3_A0 DDR3_A8 DDR3_A4 DDR3_A1 DDR3_A7 DDR3_A6 DDR3_A2 DDR3_A9 DDR3_A10 DDR3_A12 DDR3_A11 DDR3_CS0# DDR3_DQ9 DDR3_DQ12 DDR3_DQ14 DDR3_DQ10 DDR3_DQ8 DDR3_DQ13 DDR3_DQ15 DDR3_DQ11 DDR3_ODT0 DDR3_RAS# DDR3_WE# DDR3_CE0 DDR3_K0# DDR3_BA0 DDR3_BA1 DDR3_RST# DDR3_DQS0# DDR3_DQS1# DDR3_DQS1 DDR3_DQS0 DDR3_BA2 DDR3_DQ6 ZQ0 DDR3_DM0 DDR3_CAS# DDR3_K0 DDR3_A3 DDR3_K0 DDR3_K0# DDR3_BA2 DDR3_A12 DDR3_BA1 DDR3_RAS# DDR3_A8 DDR3_A5 DDR3_A2 DDR3_A11 DDR3_A4 DDR3_A0 DDR3_A10 DDR3_CAS# DDR3_A9 DDR3_A1 DDR3_A6 DDR3_ODT0 DDR3_BA0 DDR3_WE# DDR3_CE0 DDR3_CS0# MEM_VREF DDR3_VREF R16M7EM_VREF ECP5_VR0EEF ECP5_VREF DDR3_VREF DDR3_SD0 DDR3_A13 MEM_VREF DDR3_DQ17 DDR3_DQ20 DDR3_DQ18 DDR3_DQ16 DDR3_DQ21 DDR3_DQ23 DDR3_DQ19 DDR3_DM3 DDR3_A5 DDR3_A3 DDR3_A0 DDR3_A8 DDR3_A4 DDR3_A1 DDR3_A7 DDR3_A6 DDR3_A2 DDR3_A9 DDR3_A10 DDR3_A12 DDR3_A11 DDR3_CS0# DDR3_DQ25 DDR3_DQ28 DDR3_DQ30 DDR3_DQ26 DDR3_DQ24 DDR3_DQ29 DDR3_DQ31 DDR3_DQ27 DDR3_ODT0 DDR3_RAS# DDR3_WE# DDR3_CE1 DDR3_K1# DDR3_BA0 DDR3_BA1 DDR3_RST# DDR3_DQS2# DDR3_DQS3# DDR3_DQS3 DDR3_DQS2 DDR3_BA2 DDR3_DQ22 ZQ1 DDR3_DM2 DDR3_CAS# DDR3_K1 DDR3_A13 DDR3_DQ4 DDR3_DQ0 DDR3_DQ3 DDR3_DQ7 DDR3_DQ2 DDR3_DQ6 DDR3_DQ1 DDR3_DQ5 DDR3_DQ19 DDR3_DQ23 DDR3_DQ16 DDR3_DQ18 DDR3_DQ17 DDR3_DQ22 DDR3_DQ21 DDR3_DQ20 DDR3_DQ9 DDR3_DQ10 DDR3_DQ13 DDR3_DQ8 DDR3_DQ14 DDR3_DQ11 DDR3_DQ15 DDR3_DQ12 DDR3_DQ29 DDR3_DQ31 DDR3_DQ26 DDR3_DQ28 DDR3_DQ27 DDR3_DQ30 DDR3_DQ24 DDR3_DQ25 DDR3_DQS0# DDR3_DQS0 DDR3_DQS2# DDR3_DQS2 DDR3_DQS1# DDR3_DQS1 DDR3_DQS3 DDR3_DQS3# DDR3_RST# DDR3_RAS# DDR3_WE# DDR3_CE0 DDR3_CE1 DDR3_K1# DDR3_K1 DDR3_K0# DDR3_K0 DDR3_CS0# DDR3_CS1# DDR3_DM0 DDR3_DM2 DDR3_DM1 DDR3_DM3 DDR3_BA2 DDR3_ODT1 DDR3_BA0 DDR3_CAS# DDR3_A12 DDR3_ODT0 DDR3_A7 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A1 DDR3_BA1 DDR3_A9 DDR3_A6 DDR3_A0 DDR3_A5 DDR3_A8 DDR3_A11 DDR3_A10 DDR3_A13 ECP5_VREF DDR3_K1 DDR3_K1# DDR3_CE1 DDR3_A7 DDR3_VS 100MHZp 100MHZn 100MHZp 100MHZn 100MHZp 100MHZn DDR3_VTT 1V5 DDR3_VDD1 1V5 DDR3_VDDQ1 1V5 1V5 DDR3_VDD2 DDR3_VDDQ2 1V5 1V5 2V5 1V5 1V5 1V5 1V5 DDR3_VDD2 1V5 DDR3_VDDQ2 DDR3_VDD1 DDR3_VDDQ1 DDR3_VTT DDR3_VTT 1V5 1V5 DDR3_VTT 2V5 1V5 2V5 Daatee: Siiizeee SSchheemaattiiic Reev oo f SShheeeeet TTiiitttllleee LLaaattiiicee Seemiiicoonndduuctoorr Appppplliicaaatiiioonns EEmaaiiilll: [email protected] BBoaardd RReev PProoojjjeectt FFrrriiidddaay,,, 11166---Deec---1116 C 00...111 99 66 DDDRR333 IIInnnttteeerrrfffaaccee EECCP55 VIIIP PPrrrooceessoorrr Booaarrrdd BB LFE5UM-85F-BG756 U17G VCCIO7 M10 VCCIO7 P10 VCCIO7 R10 VCCIO7 T10 PL11A/ ULC_GPLL0T_IN C5 PL11B/ ULC_GPLL0C_IN D5 PL11C/ ULC_GPLL0T_MFGOUT2 C4 PL11D/ ULC_GPLL0C_MFGOUT2 C3 PL14A/ ULC_GPLL0T_MFGOUT1 D4 PL14B/ ULC_GPLL0C_MFGOUT1 E4 PL14C F4 PL14D F5 PL17A B1 PL17B C2 PL17C D3 PL17D D2 PL20A F3 PL20B E3 PL20C C1 PL20D D1 PL23A F2 PL23B E1 PL23C F1 PL23D H1 PL26A H2 PL26B H3 PL26C J3 PL26D K3 PL29A K2 PL29B J1 PL29C K1 PL29D L1 PL32A L2 PL32B L3 PL32C J4 PL32D K4 PL35A H6 PL35B H5 PL35C/VREF1_7 J7 PL35D J6 PL38A K6 PL38B K7 PL38C K5 PL38D L4 PL41A/GR_PCLK7_1 N3 PL41B N4 PL41C/GR_PCLK7_0 L7 PL41D L6 PL44A/PCLKT7_1 N6 PL44B/PCLKC7_1 N7 PL44C/PCLKT7_0 P6 PL44D/PCLKC7_0 P7 L14 60ohms 2.3A 1 2 C130 100nF 16V R486 49.9E C220 22uF 6.3V R521 49.9E R527 49.9E R483 49.9E ddr3-96bga U12A VDD B2 VDD D9 VDD K2 VDD K8 VDD G7 VDD N1 VDD N9 VDD R1 VDD R9 VDDQ A1 VDDQ A8 VDDQ C1 VSS A9 VSS B3 VSS E1 VSS G8 VSS J2 VSS J8 VSS M1 VSS M9 VSS P1 VSS P9 VSS T1 VSS T9 VSSQ B1 VSSQ B9 VSSQ D1 VSSQ D8 VSSQ E8 VREFCA M8 VDDQ C9 VDDQ E9 VDDQ F1 VDDQ H9 VREFDQ H1 VSSQ F9 VSSQ G1 VSSQ G9 VDDQ D2 VDDQ H2 VSSQ E2 R165 0E C227 10nF 25V C125 10nF 25V R514 49.9E R162 49.9E C124 1uF 16V ddr3-96bga U12B DQ0 E3 DQ1 F7 DQ2 F2 DQ3 F8 DQ4 H3 DQ5 H8 DQ6 G2 DQ7 H7 A0 N3 A1 P7 A2 P3 A3 N2 A4 P8 A5 P2 A6 R8 A7 R2 A8 T8 A9 R3 A10/AP L7 A11 R7 A12/BC# N7 BA0 M2 BA1 N8 CAS# K3 CK J7 CK# K7 CKE K9 CS# L2 LDM E7 LDQS F3 LDQS# G3 ODT K1 RAS# J3 RST# T2 WE# L3 ZQ L8 NC_J1 J1 NC_L1 L1 NC_J9 J9 NC_L9 L9 NC_T3/A13 T3 NC_T7 T7 NC_M7 M7 DQ8 D7 DQ9 C3 DQ10 C8 DQ11 C2 DQ12 A7 DQ13 A2 DQ14 B8 DQ15 A3 UDM D3 UDQS C7 UDQS# B7 BA2 M3 C108 10nF 25V C142 100nF 16V R522 49.9E R158 240E C221 22uF 6.3V C133 100nF 16V R484 49.9E 0E DNI C121 1uF 16V ddr3-96bga U19B DQ0 E3 DQ1 F7 DQ2 F2 DQ3 F8 DQ4 H3 DQ5 H8 DQ6 G2 DQ7 H7 A0 N3 A1 P7 A2 P3 A3 N2 A4 P8 A5 P2 A6 R8 A7 R2 A8 T8 A9 R3 A10/AP L7 A11 R7 A12/BC# N7 BA0 M2 BA1 N8 CAS# K3 CK J7 CK# K7 CKE K9 CS# L2 LDM E7 LDQS F3 LDQS# G3 ODT K1 RAS# J3 RST# T2 WE# L3 ZQ L8 NC_J1 J1 NC_L1 L1 NC_J9 J9 NC_L9 L9 NC_T3/A13 T3 NC_T7 T7 NC_M7 M7 DQ8 D7 DQ9 C3 DQ10 C8 DQ11 C2 DQ12 A7 DQ13 A2 DQ14 B8 DQ15 A3 UDM D3 UDQS C7 UDQS# B7 BA2 M3 C95 10nF 25V R172 DNI R515 49.9E LFE5UM-85F-BG756 U17F VCCIO6 U10 VCCIO6 V10 VCCIO6 W10 VCCIO6 AA10 PL47A/ PCLKT6_1 P5 PL47B/ PCLKC6_1 P4 PL47C/ PCLKT6_0 R7 PL47D/ PCLKC6_0 T7 PL50A/ GR_PCLK6_0 R6 PL50B T6 PL50C/ GR_PCLK6_1 U6 PL50D U7 PL53A R4 PL53B T5 PL53C T4 PL53D U5 PL56A U4 PL56B/ VREF1_6 V4 PL56C V6 PL56D V7 PL59A P2 PL59B P3 PL59C R3 PL59D T3 PL62A N1 PL62B P1 PL62C U2 PL62D U3 PL65A R1 PL65B T2 PL65C W3 PL65D Y3 PL68A T1 PL68B U1 PL68C V1 PL68D W1 PL71A Y7 PL71B Y6 PL71C Y5 PL71D W5 PL74A Y4 PL74B W4 PL74C AB7 PL74D AC6 PL77A AB5 PL77B AB6 PL77C AC7 PL77D AD7 PL80A AD6 PL80B AE6 PL80C AE5 PL80D AE4 PL83A AB3 PL83B AB4 PL83C/ D15/IO15 AC5 PL83D/ D14/IO14 AD4 PL86A/ D13/IO13 W2 PL86B/ D12/IO12 Y1 PL86C/ D11/IO11 AD3 PL86D/ D10/IO10 AE3 PL89A/ LLC_GPLL0T_MFGOUT2 AC3 PL89B/ LLC_GPLL0C_MFGOUT2 AB2 PL89C/ D9/IO9 AC2 PL89D/ D8/IO8 AE2 PL92A/ LLC_GPLL0T_MFGOUT1 AB1 PL92B/ LLC_GPLL0C_MFGOUT1 AC1 PL92C/ LLC_GPLL0T_IN AD1 PL92D/ LLC_GPLL0C_IN AE1 C136 10nF 25V C228 10nF 25V C107 100nF 16V C129 10nF 25V C99 100nF 16V R164 49.9E R523 49.9E C264 1uF 25V R161 49.9E C103 100nF 16V R516 49.9E C122 10uF 16V C262 1uF 25V C96 100nF 16V C222 1uF 16V C109 100nF 16V C94 100nF 16V R524 49.9E C229 10nF 25V C101 100nF 16V R166 4.7k C140 10nF 25V R160 49.9E R517 49.9E C97 100nF 16V R171 0E DNI C120 47uF 10V R472 240E C118 100nF 16V C139 100nF 16V R525 49.9E C230 10nF 25V C134 10nF 25V R510 49.9E C223 10nF 25V C143 10nF 25V C239 10nF 25V C98 100nF 16V R118 100E R159 49.9E C119 10nF 25V C128 100nF 16V C123 22uF 6.3V R169 0E C231 100nF 16V C263 1uF 25V X5 100_00MHz_LVDS Q_N 5 Q 4 VCC 6 GND 3 EN 1 NC 2 C266 1uF 25V R511 49.9E C111 100nF 16V C115 22uF 6.3V C281 100nF 16V C232 100nF 16V C102 10nF 25V C116 1uF 16V C127 10nF 25V C260 1uF 25V C233 100nF 16V C131 100nF 16V C112 1uF 16V C132 10nF 25V TP25 C141 100nF 16V C224 100nF 16V R512 49.9E C138 10nF 25V C100 100nF 16V C234 100nF 16V C282 10nF 25V TP26 R518 49.9E C137 100nF 16V R513 49.9E R170 0E L23 60ohms 2.3A 1 2 C135 100nF 16V C261 1uF 25V C235 100nF 16V C104 10nF 25V ddr3-96bga U19A VDD B2 VDD D9 VDD K2 VDD K8 VDD G7 VDD N1 VDD N9 VDD R1 VDD R9 VDDQ A1 VDDQ A8 VDDQ C1 VSS A9 VSS B3 VSS E1 VSS G8 VSS J2 VSS J8 VSS M1 VSS M9 VSS P1 VSS P9 VSS T1 VSS T9 VSSQ B1 VSSQ B9 VSSQ D1 VSSQ D8 VSSQ E8 VREFCA M8 VDDQ C9 VDDQ E9 VDDQ F1 VDDQ H9 VREFDQ H1 VSSQ F9 VSSQ G1 VSSQ G9 VDDQ D2 VDDQ H2 VSSQ E2 L22 60ohms 2.3A 1 2 R519 49.9E R560 10K C114 47uF 10V C225 10nF 25V C105 100nF 16V C126 100nF 16V C93 10nF 25V C265 1uF 25V C110 10nF 25V L13 60ohms 2.3A 1 2 C236 100nF 16V C117 100nF 16V C219 1uF 16V L29 60ohms 2.3A 1 2 R526 49.9E R520 49.9E C113 100nF 16V R163 49.9E C226 10nF 25V U13 LP2998-SO8 GND 1 SD 2 VSENSE 3 VREF 4 VDDQ 5 AVIN 6 PVIN 7 VTT 8 EPAD 9 C106 10nF 25V R168 0E DNI

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 FPGA-EB-02001-1.2 Figure A.6. SERDES Interface 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Place all the resistors in the top side HDRXN0_D0CH1 {5} NOTE : PLACE AC-Caps near U17 Symmetrically NOTE : PLACE AC-Caps near U17 Symmetri NOTE : PLACE X4 near U53 RightAngle 5X2 NOTE : USE 90 degree Header and place near board edge REFCLKP_D1 REFCLKN_D1 HDRXN0_D0CH0 HDRXP0_D0CH0 HDRXP0_D0CH1 REFCLKP_D0 REFCLKN_D0 HDRXN0_D1CH1 HDRXP0_D1CH1 HDRXN0_D1CH0 HDRXP0_D1CH0 REFCLKN_D0 ECP5_PLL ECP5_PLL_VREF ISPCLOCK_TDI ISPCLOCK_TDO FTDI_TMS FTDI_TCK REFCLKP_D1 REFCLKN_D1 156MHz 156MHz_VREF REFCLKP_D0 156MHz_VREF 156MHz_EN 156MHz LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 HEADER6 HEADER7 HEADER8 HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 HEADER6 HEADER7 HEADER8 HDTXP0_D1CH0 HDTXN0_D1CH0 HDTXP0_D1CH1 HDTXN0_D1CH1 HDTXN0_D0CH1 HDTXP0_D0CH1 HDTXN0_D0CH0 AK9 C271 HDTXP0_D0CH0 REF_SEL REF_SEL VCCHTX VCCA VCCA VCCHTX VCCIO1 VCCIO1 3V3 3V3 3V3 VCCIO4 3V3 3V3 VCCO VCCO VCCIO4 VCCIO4 VCCIO4 3V3 HDRXP0_D0CH0 {5} HDRXN0_D0CH0 {5} HDRXP0_D1CH0 {5} HDRXN0_D1CH0 {5} HDRXP0_D1CH1 {5} cHaDllRyXN0_D1CH1 {5} {5} SW1 {5} SW2 {5} SW3 {5} SW4 {5} SW5 {5} SW6 {5} SW7 {5} SW8 {3,5} FTDI_TMS {3,5} FTDI_TCK {3} ispCLOCK_TDI {3} ispCLOCK_TDO 156MHz_EN {5} {5} ECP5_PLL {5} ECP5_PLL_VREF {3,5} SCL {3,5} SDA UART_RX {3} UART_TX {3} HDTXP0_D1CH1 {5} HDTXP0_D1CH0 {5} HDTXN0_D1CH1 {5} HDTXN0_D1CH0 {5} HDTXP0_D0CH0 {5} HDTXN0_D0CH0 {5} HDTXP0_D0CH1 {5} HDTXN0_D0CH1 {5} Daate:: Size SSSchem matiiic Reev of SSShheett Tiiittlllee Lattiiicee SSSem m miiiconduuctorrr AAAppllliiicaatttiiioons EEEm m maaiiilll:: teechsuppooorrrt@Lattiiicceseeem mii.com m BBooarrd Reev FFFrrridayyy, 166---Decc---16 BBB 0.1 9 7 SSSEEERDEEESSS Inteeerrrffacce PPPrrroojjjectt EEECPP5 VVVIIPPP PPPrrroccesssorrr BBBoarrrd BBB R532 680R C268 100nF 16V L16 60ohms 2.3A 1 2 J54 CON3 1 2 3 L25 60ohms 2.3A 1 2 R179 4.7k R494 4.7k L18 60ohms 2.3A 1 2 C243 100nF 16V U53 ispCLOCK5406D DI USER3 45 USER2 46 USER1 47 USER0 48 VCCJ 37 TDO 38 TMS 39 TCK 40 TDI 41 RESETb 42 VCCO_0 33 BANK_0P 35 BANK_0N 34 GNDO_0 36 VCCO_1 32 GNDO_1 29 BANK_1P 31 BANK_1N 30 VCCO_2 25 GNDO_2 28 BANK_2P 27 BANK_2N 26 VCCO_3 12 GNDO_3 9 BANK_3P 10 BANK_3N 11 VCCO_4 5 GNDO_4 8 BANK_4P 6 BANK_4N 7 VCCO_5 4 GNDO_5 1 BANK_5P 2 BANK_5N 3 REFAP 16 REFAN 15 REFAVTT 14 REFBP 19 REFBN 18 REFBVTT 17 RREF 24 FBKP 22 FBKN 21 FBKVTT 20 GNDD 43 GNDA 13 VCCD 44 VCCA 23 DIE_PAD 49 D28 Green 1 2 C253 1uF 25V C249 1uF 25V J14 2 4 6 8 10 1 3 5 7 9 R180 4.7k AK18C267 100nF 16V C240 100nF 16V R496 0 R529 680R R533 680R C269 100nF 16V C151 100nF 16V D25 Green 1 2 C241 10nF 25V D29 Green 1 2 C245 100nF 16V R508 470E C150 1uF 16V C270 100nF 16V C254 100nF 16V C251 100nF 16V L24 60ohms 2.3A 1 2 C152 10nF 25V C252 10nF 25V C144 1uF 16V C255 10nF 25V L17 60ohms 2.3A 1 2 R530 680R LFE5UM-85F-BG756 U17E VCCIO4 AB23 VCCIO4 AC23 PB101A AK32 PB101B AJ32 PB103A AM30 PB103B AL30 PB105A AK31 PB105B AJ31 PB107A AM31 PB107B AL32 PB110A AG28 PB110B AG29 PB112A AJ28 PB112B AH28 PB114A AH30 PB114B AG30 PB116A AK29 PB116B AK30 PB119A AH32 PB119B AG32 PB121A AJ29 PB121B AJ30 PB96A AM28 PB96B AM29 PB98A AL28 PB98B AK28 R534 680R C145 100nF 16V D26 Green 1 2 X4 156.25MHz_LVCMOS VCC 4 GND 2 OUT 3 OE 1 R173 4.7k LFE5UM-85F-BG756 U17I VCCHTX0_D0CH0 AC13 VCCHRX0_D0CH0 AC14 VCCHRX1_D0CH1 AC15 VCCHTX1_D0CH1 AC16 VCCHTX0_D1CH0 AC17 VCCHRX0_D1CH0 AC18 VCCHRX1_D1CH1 AC19 VCCHTX1_D1CH1 AC20 HDRXP0_D0CH0 AM8 HDRXN0_D0CH0 AM9 HDRXP0_D1CH0 AM17 HDRXN0_D1CH0 AM18 HDRXP0_D0CH1 AM11 HDRXN0_D0CH1 HDRXN0_D0CH1 HDRXP0_D0CH1 {5} AM12 HDRXP0_D1CH1 AM20 HDRXN0_D1CH1 AM21 HDTXP0_D0CH0 HDTXN0_D0CH0 HDTXP0_D1CH0 HDTXN0_D1CH0 AK19 HDTXP0_D0CH1 AK12 HDTXN0_D0CH1 AK13 HDTXP0_D1CH1 AK21 HDTXN0_D1CH1 AK22 REFCLKP_D0 AM14 REFCLKN_D0 AM15 REFCLKP_D1 AM23 REFCLKN_D1 AM24 D30 Green 1 2 C248 1uF 25V C146 10nF 25V R531 680R R495 0 100nF 16V R561 1K R174 4.7k R535 680R L15 60ohms 2.3A 1 2 C148 100nF 16V D27 Green 1 2 C272 AK10 100nF 16V R562 4.7k R175 4.7k D31 Green 1 2 R502 220E R500 0 C154 100nF 16V C147 1uF 16V R507 680R R176 4.7k C273 100nF 16V C153 1uF 16V R528 680R D21 blue 1 2 R177 4.7k C149 10nF 25V C274 100nF 16V R501 0 R503 220E D24 Green 1 2 C155 10nF 25V R178 4.7k C242 100nF 16V SW3 SW DIP-8 MFG P/N = 97C08SRT

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 27 Figure A.7. ECP5 Decoupling 5 5 4 4 3 3 2 2 1 1 D D C C B B A A NOTE : PLACE All the De-caps near respective power pins VCCA VCCA VCC_AUXA1 2V5 VCC_AUXA0 2V5 VCC_AUXA1 VCC_AUXA0 VCC_AUX VCCA VCCA VCC_CORE VCC_CORE VCC_CORE VCC_AUX 2V5 Daatttee::: SSSiizeee SSchheem maaatttiiic Reev oo ff SSheeeettt Tittleee LLaattttttiiicee SSSeem m miiicoonndduuctttoorrr AAAppppplliicaatttiiioonns EEm m maaiiilll::: ttteechhsuupppppoorrrttt@ @LLLaattttttiiicceseeem m mii...coom m m BBooaarrrddd RRev PPrrrooojjjeeccttt FFrrriidddaaay, 111666---DDDeec---1166 CCC 00..11 99 8 EEECCPPP55 DDDeeecoouuppiiinnngg EEECCPPP555 VVVIPPP PPPrrrooceessoorrr BBBoooaarrrddd BB LFE5UM-85F-BG756 U17K VCC M21 VCC N21 VCC P21 VCC R21 VCC T21 VCC U21 VCC V21 VCC W21 VCC Y21 VCC AA21 VCC M20 VCC AA20 VCC M19 VCC AA19 VCC M18 VCC AA18 VCC M17 VCC AA17 VCC M16 VCC AA16 VCC M15 VCC AA15 VCC M14 VCC AA14 VCC M13 VCC AA13 VCC M12 VCC N12 VCC P12 VCC R12 VCC T12 VCC U12 VCC V12 VCC W12 VCC Y12 VCC AA12 VCCA1 AJ18 VCCA1 AJ19 VCCA1 AH19 VCCA1 AG19 VCCA1 AJ21 VCCA1 AJ22 VCCA1 AH22 VCCA1 AG22 VCCA1 AF22 VCCA0 AJ9 VCCA0 AH9 VCCA0 AG9 VCCA0 AJ10 VCCA0 AJ12 VCCA0 AH12 VCCA0 AG12 VCCA0 AJ13 VCCAUX Y10 VCCAUX N10 VCCAUX AC11 VCCAUX K13 VCCAUX K20 VCCAUX AC22 VCCAUX Y23 VCCAUX N23 VCCAUXA1 AJ24 VCCAUXA1 AJ25 VCCAUXA0 AJ15 VCCAUXA0 AJ16 C188 100nF 16V C186 1uF 25V C193 100nF 16V L21 60ohms 2.3A 1 2 C159 100nF 16V LFE5UM-85F-BG756 U17L NC1 AG31 NC2 V30 NC3 H29 NC4 AC29 NC5 L28 NC6 W27 NC7 E26 NC8 AE26 NC9 G24 NC10 AG24 NC11 G23 NC12 G22 NC13 G19 NC14 G18 NC15 G17 NC16 G16 NC17 G15 NC18 G14 NC19 G11 NC20 G10 NC21 G9 NC22 E7 NC23 AE7 NC24 W6 NC25 L5 NC26 H4 NC27 AC4 NC28 V3 NC29 AG2 RESERVED1 AK24 RESERVED2 AK25 RESERVED3 AK15 RESERVED4 AK16 L19 60ohms 2.3A 1 2 L20 60ohms 2.3A 1 2 C194 10nF 25V C176 10uF 16V C166 100nF 16V C191 1uF 25V C208 10nF 25V C174 100nF 16V C204 100nF 16V C181 100nF 16V C195 100nF 16V C189 10nF 25V C211 100nF 16V C206 100nF 16V C168 10nF 25V C169 100nF 16V C197 10nF 25V C163 10uF 16V C183 100nF 16V C212 10nF 25V C190 100nF 16V C196 100nF 16V C203 10uF 16V C175 1uF 25V C162 1uF 25V C213 100nF 16V C158 100nF 16V C177 100nF 16V C207 100nF 16V C178 10nF 25V C215 10nF 25V C164 100nF 16V C161 10nF 25V C198 100nF 16V C218 10uF 16V C179 100nF 16V C165 10nF 25V C184 100nF 16V C214 100nF 16V C160 100nF 16V LFE5UM-85F-BG756 U17J GND V17 GND U17 GND T17 GND R17 GND P17 GND N17 GND L17 GND AB18 GND Y18 GND W18 GND V18 GND U18 GND T18 GND R18 GND P18 GND N18 GND L18 GND E18 GND B18 GND AB19 GND Y19 GND W19 GND V19 GND U19 GND T19 GND R19 GND P19 GND N19 GND L19 GND AB20 GND Y20 GND W20 GND V20 GND U20 GND T20 GND R20 GND P20 GND N20 GND L20 GND E20 GND B20 GND AC21 GND AB21 GND L21 GND AB22 GND AA22 GND Y22 GND W22 GND V22 GND U22 GND T22 GND R22 GND P22 GND N22 GND M22 GND L22 GND K22 GND L23 GND K23 GND E24 GND B24 GND AD28 GND V28 GND R28 GND N28 GND J28 GND E28 GND B28 GND AL29 GND AH29 GND AL31 GND AH31 GND AD31 GND Y31 GND V31 GND R31 GND N31 GND J31 GND E31 GND B31 GND Y16 GND W16 GND V16 GND U16 GND T16 GND R16 GND P16 GND N16 GND L16 GND AB17 GND Y17 GND W17 GND P14 GND N14 GND L14 GND AB15 GND Y15 GND W15 GND V15 GND U15 GND T15 GND R15 GND P15 GND N15 GND L15 GND E15 GND B15 GND AB16 GND R14 GND T14 GND U14 GND V14 GND W14 GND Y14 GND AB14 GND B13 GND E13 GND L13 GND N13 GND P13 GND R13 GND T13 GND U13 GND V13 GND W13 GND Y13 GND AB11 GND L12 GND AB12 GND AC12 GND K11 GND L11 GND M11 GND N11 GND P11 GND R11 GND T11 GND U11 GND V11 GND W11 GND Y11 GND AA11 GND AB13 GND K10 GND L10 GND B9 GND E9 GND B5 GND E5 GND J5 GND N5 GND R5 GND V5 GND AD5 GND AH5 GND AL5 GND B2 GND E2 GND J2 GND N2 GND R2 GND V2 GND Y2 GND AD2 GND AH2 GND AL2 GNDA AM7 GNDA AL7 GNDA AK7 GNDA AJ7 GNDA AH7 GNDA AL8 GNDA AK8 GNDA AJ8 GNDA AH8 GNDA AL9 GNDA AL11 GNDA AK11 GNDA AJ11 GNDA AH11 GNDA AG11 GNDA AF11 GNDA AL12 GNDA AF12 GNDA AL14 GNDA AK14 GNDA AJ14 GNDA AH14 GNDA AG14 GNDA AF14 GNDA AL15 GNDA AH15 GNDA AG15 GNDA AF15 GNDA AH16 GNDA AG16 GNDA AF16 GNDA AL17 GNDA AK17 GNDA AJ17 GNDA AH17 GNDA AG17 GNDA AF17 GNDA AL18 GNDA AF19 GNDA AL20 GNDA AK20 GNDA AJ20 GNDA AH20 GNDA AG20 GNDA AF20 GNDA AL21 GNDA AL23 GNDA AK23 GNDA AJ23 GNDA AH23 GNDA AG23 GNDA AF23 GNDA AL24 GNDA AH24 GNDA AH25 GNDA AM26 GNDA AL26 GNDA AK26 GNDA AJ26 GNDA AH26 C187 10uF 16V C182 10nF 25V C201 100nF 16V C209 100nF 16V C173 10nF 25V C216 100nF 16V C167 100nF 16V C172 100nF 16V C185 10nF 25V C202 1uF 25V C205 10nF 25V C171 10uF 16V C192 10uF 16V C200 10nF 25V C199 100nF 16V C156 100nF 16V C210 100nF 16V C157 10nF 25V C180 100nF 16V C170 1uF 25V C217 1uF 25V

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 FPGA-EB-02001-1.2 Figure A.8. HISPI/CSI2 Connector 5 5 4 4 3 3 2 2 1 1 D D C C B B A A TOP - HIGH SPI to SENSOR 1 CONNECTOR 1 TOP - PARALLEL UP to SENSOR1 CONNECTOR 1 NOTE : PLACE NEAR U17 NOTE : PLACE NEAR U17 RESET_BAR OUTPUT_EN_BAR STANDBY SIGNAL_TRIGGER SADDR SLVS_4N SLVS_4P SLVS_5P SLVS_5N FRAME_VALID DOUT4 DOUT9 SLVS_4P SLVS_4N SLVS_5P SLVS_5N FRAME_VALID DOUT4 STANDBY OUTPUT_EN_BAR RESET_BAR SIGNAL_TRIGGER SADDR DOUT9 5V GND GND 5V GND 5V GND 5V 5V GND 5V GND CN2_VCC CN2_VCC CN2_VCC CN1_VCC CN1_VCC CN1_VCC {5} SIGNAL_TRIGGER {5} RESET_BAR {5} OUTPUT_EN_BAR {5} STANDBY {5} EXTCLK_FPGA SADDR {5} SDCLK {5} SDATA {5} SLVS_CN {5} SLVS_CP {5} PANASONIC_B0N {5} PANASONIC_B0P {5} SLVS_0N {5} SLVS_0P {5} {5} SLVS_3N {5} SLVS_3P {5} PANASONIC_B1N {5} PANASONIC_B1P {5} SLVS_2N {5} SLVS_2P {5} SLVS_1N {5} SLVS_1P {5} SLVS_4N {5} SLVS_4P SLVS_5N {5} SLVS_5P {5} VDDIO_RP {5} HISPI_RESETN {5} HISPI_SCLK {5} HISPI_SDA {5} RESERVED {5} VDDIO_RH {5} PIXCLK {5} FRAME_VALID {5} OSC_EN {5} {5} LINE_VALID {5} SLVS_7N {5} SLVS_7P {5} SLVS_6N {5} SLVS_6P SLVS_8N {5} SLVS_8P {5} SLVS_9N {5} SLVS_9P {5} {5} DOUT6 {5} DOUT11 DOUT4 {5} DOUT9 {5} DDDattte:: Sizee SSSchemattiic RRRev o ff SSheeett Titttllee Laattttttice SSSem micconduucttorrr AAApplicatttioonnns EEEm mail::: [email protected] BBBoarrd RRRevv Frrriday,,, 166--DDDec---16 BBB 0..1 9 9 HHHIIISSSPPPIII///CCSSSIII2 CConnneecttoorrr PPPrrroojecttt EEECCCPPP5 VVVIIIPPP PPPrrroceessoorr BBBoarrrd BBB R563 0 R457 0 C286 1uF 25V R458 0 R575 100E DNI HRS-DF12A-(3.0)-40D*-0.5V** CN2 DF12B_-40DS-0.5V_RECEPTACLE PART_NUMBER = DF12B(4.0)-40DS-0.5V Manufacturer = HIROSE PIN1 1 PIN2 2 PIN3 3 PIN4 4 PIN5 5 PIN6 6 PIN7 7 PIN8 8 PIN9 9 PIN10 10 PIN11 11 PIN12 12 PIN13 13 PIN14 14 PIN15 15 PIN16 16 PIN17 17 PIN18 18 PIN19 19 PIN20 20 PIN21 21 PIN22 22 PIN23 23 PIN24 24 PIN25 25 PIN26 26 PIN27 27 PIN28 28 PIN29 29 PIN30 30 PIN31 31 PIN32 32 PIN33 33 PIN34 34 PIN35 35 PIN36 36 PIN37 37 PIN38 38 PIN39 39 PIN40 40 SHIELD_1 SHIELD1 SHIELD_2 SHIELD2 R459 0 R582 0 R576 100E DNI R568 0 R566 0 R460 0 R583 0 R567 0 R577 100E DNI R584 0 R570 100E DNI R585 0 R571 100E DNI HRS-DF12A(3.0)-40D*-0.5V** CN1 DF12B(4.0)-40DP-0.5V_HEADER PART_NUMBER = DF12B(4.0)-40DP-0.5V Manufacturer = HIROSE PIN1 1 PIN2 2 PIN3 3 PIN4 4 PIN5 5 PIN6 6 PIN7 7 PIN8 8 PIN9 9 PIN10 10 PIN11 11 PIN12 12 PIN13 13 PIN14 14 PIN15 15 PIN16 16 PIN17 17 PIN18 18 PIN19 19 PIN20 20 PIN21 21 PIN22 22 PIN23 23 PIN24 24 PIN25 25 PIN26 26 PIN27 27 PIN28 28 PIN29 29 PIN30 30 PIN31 31 PIN32 32 PIN33 33 PIN34 34 PIN35 35 PIN36 36 PIN37 37 PIN38 38 PIN39 39 PIN40 40 SHIELD_1 SHIELD1 SHIELD_2 SHIELD2 R461 0 R569 0 R586 0 R564 0 R462 0 C283 100nF 16V R565 0 R463 0 C285 100nF 16V C284 1uF 25V R587 0 R456 0 R574 100E DNI

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 29 Appendix B. ECP5 VIP Processor Board Bill of Materials Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 1 CN1 1 DF12B(4.0)- 40DP- 0.5V_HEADER HRS- DF12B- HEADER — DF12B(4.0)- 40DP-0.5V Hirose CONN HEADER 40POS 4 mm SMD 0.5 mm 2 CN2 1 DF12B_-40DS- 0.5V_RECEPTA CLE HRS- DF12B- RECEPTACL E-CENTER — DF12B(4.0)- 40DS-0.5V Hirose CONN RECEPT 40POS 0.5 mm GOLD SMD 3 C1, C3 2 4u7 C0603 — 8850121060 05 Wurth CAP CER 4.7 µF 6.3 V X5R 0603 4 C2, C5, C7, C24, C25, C73, C74, C75, C76, C78, C81, C82, C83, C85, C86, C87, C89, C90, C91, C94, C96, C97, C98, C99, C100, C101, C103, C105, C107, C109, C111, C113, C117, C118, C126, C128, C130, C131, C133, C135, C137, C139, C141, C142, C145, C148, C151, C154, C156, C158, C159, C160, C164, C166, C167, C169, C172, C174, C177, C179, C180, C181, C183, C184, C188, C190, C193, C195, C196, C198, C199, C201, C204, C206, C207, C209, C210, C211, C213, C214, C216, C224, C231, C232, C233, C234, C235, C236, C237, C238, C240, C242, C243, C245, C251, C254, C281, C283, C285 99 100nF C0201 — CC0201KRX5 R7BB104 Yageo CAP CER 0.1 µF 16 V X5R 0201 5 C4, C10, C11, C14, C15, C16, C17, C18, C19, C20, C21 11 0.1uF C0201 — CC0201KRX5 R7BB104 Yageo CAP CER 0.1 µF 16 V X5R 0201 6 C6, C8, C23, C280 4 0.1uF C0402 — 8850122050 37 Wurth CAP CER 0.1 µF 16 V X7R 0402 7 C9 1 10uF C0603 — LMK107BJ10 6MALTD Taiyo Yuden CAP CER 10 µF 10 V X5R 20% 0603 8 C12, C13 2 18pF C0402 — C0402C180K 3GACTU Kemet CAP CER 18 pF 25 V C0G 0402 9 C26, C29, C43 3 10uF C6032 — TRJC106K03 5RRJ AVX Tantalum Capacitors - Solid SMD 10 µF ±10% 35V

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 FPGA-EB-02001-1.2 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 10 C27, C28 2 0.1uF C0603 — 8850122060 71 Wurth CAP CER 0.1 µF 25 V X7R 0603 11 C30, C31, C44, C45 4 220nF C0402 — 8850121050 17 Wurth CAP CER 0.22 µF 16 V X5R 0402 12 C32, C33, C46, C47 4 1000pF C0402 — 8850122050 44 Wurth CAP CER 1000 pF 25 V X7R 0402 13 C34, C37, C49, C50 4 10pF C0402 — 8850120050 55 Wurth CAP CER 10 pF 50 V NP0 0402 14 C35, C36, C48, C51 4 330pF C0402 — 8850122050 58 Wurth CAP CER 330 pF 50 V X7R 0402 15 C38, C39, C40, C41, C42, C53, C54, C56, C57, C58, C115, C123, C220, C221 14 22uF C0805 — 8850121070 05 Wurth CAP CER 22 µF 6.3 V X5R 0805 16 C52, C55, C275, C276 4 100pF C0402 — 8850120050 46 Wurth CAP CER 100 pF 25 V NP0 0402 17 C59, C66, C77, C84, C88, C92, C162, C170, C175, C186, C191, C202, C217, C248, C249, C253, C260, C261, C262, C263, C264, C265, C266, C277, C284, C286 26 1uF C1206 — THJA105K02 5RJN AVX Tantalum Capacitors - Solid SMD 25 V 1 µF 10% 18 C60, C67, C122, C163, C171, C176, C187, C192, C203, C218 10 10uF C1210 — THJB106K01 6SJN AVX Tantalum Capacitors - Solid SMD 16 V 10 µF 10% 19 C63, C70 2 100nF C0402 — 8850122050 37 Wurth CAP CER 0.1 µF 16 V X7R 0402 20 C93, C95, C102, C104, C106, C108, C110, C119, C125, C127, C129, C132, C134, C136, C138, C140, C143, C146, C149, C152, C155, C157, C161, C165, C168, C173, C178, C182, C185, C189, C194, C197, C200, C205, C208, C212, C215, C223, C225, C226, C227, C228, C229, C230, C239, C241, C252, C255, C282 49 10nF C0201 — GRM033R61 E103KA12D Murata CAP CER 10000 pF 25 V X5R 0201 21 C112, C116, C121, C124, C144, C147, C150, C153, C219, C222 10 1uF C0805 — 8850122070 51 Wurth CAP CER 1 µF 16 V X7R 0805 22 C114, C120 2 47uF CASEB — T491B476K0 10AT KEMET CAP TANT 47 µF 10 V 10% 1411 23 C256 1 10uF C0603 — CL10A106M A8NRNC Samsung CAP CER 10 µF 25 V 20% X5R 0603

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 31 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 24 C257 1 47uF C0805 — C2012X5R1 A476M125A C TDK CAP CER 47 µF 10 V 20% X5R 0805 25 C258 1 470pF C0603 — 8850120060 42 Wurth Electronics Multilayer Ceramic Capacitors MLCC - SMD/SMT WCAP-CSGP 470 pF 0603 5% 25 V MLCC 26 C259 1 0.47uF C0402 — CL05A474KA 5NNNC Samsung CAP CER 0.47 µF 25 V 10% X5R 0402 27 C267, C268, C269, C270, C271, C272, C273, C274 8 100nF C0201 — CC0201KRX5 R7BB104 Yageo 0.10 µF 16 V Ceramic Capacitor X5R 0201 (0603 Metric) 0.024" L x 0.012" W (0.60 mm x 0.30 mm) 28 C278 1 33pF C0603 — 8850120060 54 Wurth Electronics Multilayer Ceramic Capacitors MLCC - SMD/SMT WCAP-CSGP 33 pF 0603 5% 50 V MLCC 29 C279 1 47pF C0402 — 8850120050 59 Wurth Electronics Multilayer Ceramic Capacitors MLCC - SMD/SMT WCAP-CSGP 47 pF 0402 5% 50 V MLCC 30 C287, C288, C289, C290 4 18pF C0402 DNL C0402C180K 3GACTU Kemet CAP CER 18 pF 25 V C0G 0402 31 D1, D3, D4, D21 4 blue led_0603 — 150060BS75 000 Wurth LED BLUE CLEAR 0603 SMD 32 D2, D14, D15, D16, D17, D18, D19, D20, D23, D24, D25, D26, D27, D28, D29, D30, D31 17 Green led_0603 — 150060VS75 000 Wurth LED GREEN CLEAR 0603 SMD 33 D5 1 V12P10 V12P10 — V12P10- M3/86A Vishay Intertechno- logies Diode Schottky 100 V 12A 3-Pin(2+Tab) SMPC T/R 34 D6, D7, D10, D11 4 1N4448W 1N4448W — 1N4448WT Fairchild Semiconductor Diode Small Signal Switching 75 V 2-Pin SOD-523F T/R 35 D8, D9, D12, D13 4 DFLS220L DFLS220L — DFLS220L-7 Diodes Incorporated Diode Schottky 20 V 2 A POWERDI123

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 FPGA-EB-02001-1.2 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 36 D22 1 0.3VF MBRA340T 3G — MBRA340T3 G On Semiconductor Diode Schottky 40 V 3 A SMA 37 GND1, GND2, GND4, GND5, 5V, 12V, 1V5, 2V5, 3V3, VCC_CORE, VCCHTX, VCCA 12 TP_S_40_63 tp_s_40_63 DNL — — Square test point, 40 mil inner diameter, 63 mil outer diameter 38 J1 1 header_1x8 hdr_amp_8 7220_8_1x 8_100 — 6130081112 1 Wurth 8 Positions Header, Unshrouded Connector 0.100" (2.54 mm) Through Hole Gold 39 J2 1 SKT_MINIUSB _B_RA skt_minius b_b_ra — 6510051612 1 Wurth CONN COM Type-B Mini USB SMD 5P 40 J3 1 HEADER 3X2 HDR3X2 — 6130062112 1 Wurth 6 Positions Header, Unshrouded Connector 0.100" (2.54 mm) Through Hole Gold 41 J4 1 PJ-051A PJ_051A — PJ-051A CUI Inc. DC Power Connectors Power Jacks 42 J5, J6, J9, J51 4 CON3 HDR1X3 — 6130031112 1 Wurth 3 Positions Header, Unshrouded Connector 0.100" (2.54 mm) Through Hole Gold 43 J7, J55 2 Tri-Con TriCon Regular 100mil header — — General 100 mils header 44 J10, J11 2 CONN RCPT 30x2 ERM5-030- 050-L-DV- K-TR — ERM5-030- 05.0-L-DV-K- TR Samtec Inc. Conn High Speed Edge Rate Terminal Strip HDR 60 POS 0.5 mm Solder ST SMD T/R - 45 J12, J13 2 CONN RCPT 30x2 ERF5-030- 070-L-DV- K-TR — ERF5-030- 07.0-L-DV-K- TR Samtec Inc. Conn High Speed Edge Rate Terminal Strip HDR 60 POS 0.5 mm Solder ST SMD T/R - 46 J14 1 RightAngle 5X2 90122- 0925 — 90122-0925 Molex 10 Positions Header, Unshrouded, Breakaway Connector 0.100" (2.54 mm) Through Hole, Right Angle Gold

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 33 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 47 J50 1 HEADER 3X2 HDR-3X2 — 6130062112 1 Wurth 6 Positions Header, Unshrouded Connector 0.100" (2.54 mm) Through Hole Gold 48 J52, J53, J54 3 CON3 HDR_1X3_ 100MIL — 6130031112 1 Wurth 3 Positions Header, Unshrouded Connector 0.100" (2.54 mm) Through Hole Gold 49 L1, L2, L3 3 600ohm 500mA FB0603 — 742792651 Wurth FERRITE BEAD 600 Ω 0603 1LN 50 L4, L5, L6, L7 4 4.7uH SPD62R — SPD62R- 472M API Delevan Inc. FIXED IND 4.7 µH 2 A 150 MΩ SMD 51 L13, L14, L15, L16, L17, L18, L19, L20, L21, L22, L23, L24, L25, L29 14 60ohms 2.3A FB0603 — 742792602 Wurth FERRITE BEAD 60 Ω 0603 1LN 52 L26 1 4.7uH 744373460 47 — 7443734604 7 Wurth FIXED IND 4.7 µH 3.8 A 40 MΩ SMD 53 L27, L28 2 60ohms 2.3A FB0603 — MPZ1608Y6 00B TDK EMI Filter Beads, Chips & Arrays 60 Ω Power 54 Q1 1 2N2222 MMBT2222 ALT-1 — MMBT2222 ALT1G On Semiconductor Trans GP BJT NPN 40 V 0.6 A Automotive 3-Pin SOT-23 T/R 55 Q2, Q3, Q4, Q5, Q6 5 MMBT2222A SM_SOT23- 3 — MMBT2222 A,215 NXP USA Inc. TRANS NPN 40 V 0.6 A SOT23 56 R1, R2, R3, R5, R6, R38, R47, R48, R49, R51, R53, R54, R166, R173, R174, R175, R176, R177, R178, R179, R180, R479, R480, R482, R494, R537, R562 27 4.7k R0402 — ERJ- 2RKF4701X Panasonic RES SMD 4.7K Ω 1% 1/10 W 0402 57 R4, R57, R59, R70, R72 5 0 R0603 — RC0603JR- 070RL Yageo Res 1/10 W 0.0 Ω 5% 0603 58 R7, R8, R9, R10, R12, R19, R20, R28, R93, R94, R106, R108, R119, R456, R457, R458, R459, R460, R461, R462, R463, R495, R496, R500, R501, R539, R540, R542, R543, R563, R564, R565, R566, R567, R568, R569, R582, R583, R584, R585, R586, R587 42 0 R0402 — ERJ- 2GE0R00X Panasonic RES SMD 0.0 Ω JUMPER 1/10 W 0402 59 R11 1 0 R0402 DNL ERJ- 2GE0R00X Panasonic RES SMD 0.0 Ω JUMPER 1/10 W 0402

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 FPGA-EB-02001-1.2 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 60 R14, R25, R538, R544, R545, R546, R547, R548, R549 9 2k2 R0402 — ERJ- 2RKF2201X Panasonic RES SMD 2.2K Ω 1% 1/10 W 0402 61 R15 1 12k R0402 — ERJ- 2RKF1202X Panasonic RES SMD 12K Ω 1% 1/10 W 0402 62 R16, R17, R18, R29, R43, R44, R45, R46, R62, R66, R80, R81, R504, R557, R558, R560 16 10K R0402 — ERJ- 2GEJ103X Panasonic RES SMD 10K Ω 5% 1/10 W 0402 63 R26, R27, R50, R52, R507, R528, R529, R530, R531, R532, R533, R534, R535, R550 14 680R R0402 — RMCF0402J T680R Stackpole Electronics Inc. RES 680 Ω 1/16 W 5% 0402 64 R30, R31, R32, R509, R559, R561 6 1K R0402 — RMCF0402J T1K00 Stackpole Electronics Inc. RES 1K Ω 1/16 W 5% 0402 65 R33 1 33E R0603 — ERJ- 3GEYJ330V Panasonic Thick Film Resistors 0603 33 Ω 5% AEC-Q200 66 R56 1 100E R0603 DNL CRCW06031 00RFKEAHP Vishay/Dale Thick Film Resistors - SMD 1/4 W 100 Ω 1% 100 ppm High Power 67 R58, R63, R65, R67 4 51k RLP-100 — TNPW04025 1K0BEED Vishay/Dale Thin Film Resistors 51K Ω 0.1% 25 ppm 68 R60 1 21.5K R0402 — ERJ- 2RKF2152X Panasonic RES SMD 21.5K Ω 1% 1/10 W 0402 69 R61 1 31.6K R0402 — ERJ- 2RKF3162X Panasonic RES SMD 31.6K Ω 1% 1/10 W 0402 70 R64 1 34K R0402 — ERJ- 2RKF3402X Panasonic RES SMD 34K Ω 1% 1/10 W 0402 71 R73, R74, R86, R87, R92 5 10K R0402 — ERJ- 2GEJ103X Panasonic RES SMD 10K Ω 5% 1/10 W 0402 72 R75 1 3.83K R0402 — ERJ- 2RKF3831X Panasonic RES SMD 3.83K Ω 1% 1/10 W 0402 73 R76 1 8.87K R0402 — ERJ- 2RKF8871X Panasonic RES SMD 8.87K Ω 1% 1/10 W 0402 74 R77 1 34.8K R0402 — ERJ- 2RKF3482X Panasonic RES 34.8K Ω 1/10 W 1% 0402 SMD 75 R78 1 63.4K R0402 — ERJ- 2RKF6342X Panasonic RES 63.4K Ω 1/10 W 1% 0402 SMD 76 R88, R91 2 110K R0402 — ERJ- 2RKF1103X Panasonic RES SMD 110K Ω 0.1% 1/10 W 0402

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 35 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 77 R110, R111, R112, R113, R114, R148, R149, R150, R151, R152 10 4.7k R0402 DNL ERJ- 2RKF4701X Panasonic RES SMD 4.7K Ω 1% 1/10 W 0402 78 R117 1 100K R0402 — RMCF0402J T100K Stackpole Electronics Inc. RES 100K Ω 1/16 W 5% 0402 79 R118 1 100E R0402 — TNPW04021 00RBEED Vishay Thin Film Resistors - SMD 100 Ω .1% 25ppm 80 R121, R122 2 0E R0402 — ERJ- 2GE0R00X Panasonic RES SMD 0.0 Ω JUMPER 1/10 W 0402 81 R123, R124, R127, R128, R129, R132, R133, R136, R137, R140 10 49.9E R0402 DNL CRCW04024 9R9FKED Vishay Dale Thick Film Resistors - SMD 1/16 W 49.9 Ω 1% 82 R125, R126, R130, R131, R134, R135, R138, R139 8 0E R0402 — ERJ- 2GE0R00X Panasonic RES SMD 0.0 Ω Jumper 1/10 W 0402 83 R158, R472 2 240E R0402 — ERJ- 2RKF2400X Panasonic RES SMD 240 Ω 1% 1/10 W 0402 84 R159, R160, R161, R162, R163, R164, R483, R484, R486, R510, R511, R512, R513, R514, R515, R516,R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527 27 49.9E R0402 — CRCW04024 9R9FKED Vishay Dale Thick Film Resistors - SMD 1/16 W 49.9 Ω 1% 85 R165, R169, R170 3 0E R0402 — ERJ- 2GE0R00X Panasonic RES SMD 0.0 Ω Jumper 1/10 W 0402 86 R167, R168, R171, R172 4 0E R0402 DNL ERJ- 2GE0R00X Panasonic RES SMD 0.0 Ω Jumper 1/10 W 0402 87 R230 1 34K R0402 — ERJ- 2RKF3402X Panasonic RES 34K Ω 1/10 W 1% 0402 SMD 88 R231 1 536K R0402 — ERJ- 2RKF5363X Panasonic Electronic Components RES 536K Ω 1/10 W 1% 0402 SMD 89 R232 1 100K R0402 — ERJ- 2RKF1003X Panasonic Electronic Components RES 100K Ω 1/10 W 1% 0402 SMD 90 R464, R465, R466, R467, R469, R470, R471, R551, R552, R553, R554, R555, R570, R571, R574, R575, R576, R577, R578, R579, R580, R581 22 100E R0402 DNL TNPW04021 00RBEED Vishay Thin Film Resistors - SMD 100 Ω 0.1% 25 ppm 91 R474, R475, R477 3 0 R0603 — ERJ- 3GEY0R00V Panasonic Thick Film Resistors - SMD 0603 Zero Ω

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 FPGA-EB-02001-1.2 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 92 R481 1 1k R0402 — RMCF0402J T1K00 Stackpole Electronics Inc. RES SMD 1K Ω 5% 1/16 W 0402 93 R502, R503, R505, R506 4 220E R0402 — ERJ- 2RKF2200X Panasonic RES SMD 220 Ω 1% 1/10 W 0402 94 R508 1 470E R0402 — CRCW04024 70RFKED Vishay Thick Film Resistors - SMD 1/16 W 470 Ω 1% 100 ppm 95 R556 1 30.1K R0402 — ERJ- 2RKF3012X Panasonic RES 30.1K Ω 1/10 W 1% 0402 SMD 96 SW1, SW4 2 SYS_RST 4psmd_ switch — 4341530178 35 Wurth SWITCH TACTILE SPST- NO 0.05 A 12 V 97 SW2 1 PWR 450301014 042_switch — 4503010140 42 Wurth Slide Switch SPDT Through Hole 98 SW3 1 SW DIP-8 CTS_218-8 Alternate PN : 218- 8LPST 97C08SRT Grayhill Inc. Dip Switch SPST 8 Position Surface Mount Slide (Standard) Actuator 25 mA 24 VDC 99 TH1, TH2, TH3, TH4 4 ThruHole MTG125 DNL — — — 100 TP1, TP2, TP3, TP17, TP18, TP25, TP26 7 20mil_SMD 20mil_SMD DNL — — — 101 TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12 8 TestPoint TP50 DNL — — — 102 U1 1 ATSHA204A ATSHA204 A — ATSHA204A- MAHDA-T Atmel Corporation IC CRYPTO 4.5 KB I2C 8UDFN 103 U2 1 FT2232HL tqfp64_0p5 _12p2x12p 2_h1p6 — FT2232HL FTDI USB to UART / FIFO 104 U3 1 M24M01 M24M01 — M24M01- RMN6P STMicroelectr onics EEPROM Serial-I2C 1 Mbit 128K x 8 2.5 V/3.3 V/5 V 8-Pin SO N 105 U4 1 93LC56-SO8 so8_50_ 244 — 93LC56C- I/SN Microchip IC EEPROM 2 KBIT 3 MHz 8SOIC 106 U7 1 FUSE 0154004DR T — 0154004.DR T Littelfuse Surface Mount Fuses Fuseblock with fuse 4 A OMNI BLOK 154T 107 U8, U9 2 LT3508EUF LT3508EUF — LT3508EUF# PBF Linear Technology IC REG BUCK ADJ 1.4 A DL 24QFN

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02001-1.2 37 Item Reference Qty Part PCB Footprint Comments Part Number Manufacturer Description 108 U10, U11 2 LT3085 LT3085E_6 DFN — LT3085EDCB #PBF Linear Technology IC REG LDO ADJ 0.5 A 6DFN 109 U12, U19 2 ddr3-96bga MT41J64M 16TW-093 — MT41J64M1 6TW-093 Micron IC DDR3 SDRAM 1 Gbit FBGA 110 U13 1 LP2998-SO8 RLP-300 — LP2998MR/ NOPB Texas Instruments Termination Regulator 2.2 V to 5.5 V 8-Pin HSOP EP Tube 111 U17 1 ECP5UM-85F- BG756 LFE5UM- 85F- 7BG756I — LFE5UM- 85F- 7BG756I Lattice Semiconductor Corporation IC FPGA 84K LUT 1.1 V 756CABGA IND 112 U52 1 N25Q128A13E SE40E N25Q128_ SO8W Assembly Option A S25FL132K0 XMFI011 Cypress IC FLASH 32 Mbit 108 MHz 8SOIC Assembly Option B N25Q128A1 3ESE40E Micron IC FLASH 128 Mbit 108 MHz 8SO 113 U53 1 ispCLOCK5406 D ISPCLOCK5 406D — ispCLOCK54 06D Lattice Semiconductor Corporation ispClock Manager 114 U54 1 LT3680 LT3680_10 QFN — LT3680EDD# PBF Linear 5 V Step down converter 115 X1 1 12MHZ crystal_4p_ 3p2x2p5 — 7M- 12.000MAAJ -T TXC CRYSTAL 12.0000 MHz 18 pF SMD 116 X2 1 KC2520B27.00 00C2GE00 27MHZ_OS C — KC2520B27. 0000C2GE0 0 AVX/Kyocera Standard Clock Oscillators 27 MHz 2.5 V 2.5x2.0 mm SMD 117 X4 1 156.25MHz_L VCMOS SiT8256AC — SiT8256AC- 23-33E - 156.250000 Y SiTime 125 MHz CMOS MEMS (Silicon) Oscillator Surface Mount 2.25 V ~ 3.6 V 35 mA Enable/Disable 118 X5 1 100_00MHz_L VDS DSC1123CI 5 — DSC1123CI5 -100.0000 Microchip Technology/ Micrel 100 MHz LVDS MEMS (Silicon) Oscillator Surface Mount 2.25 V ~ 3.6 V 32 mA Enable/Disable 119 ECP5 Video Processor Board REVB PCB 1 — — — 305-PD-16- 1002 Pactron —

Evaluation Board User Guide © 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 FPGA-EB-02001-1.2 Revision History Date Version Change Summary June 2017 1.2 Updated Ordering Information section. May 2017 1.1 Updated board pictures to Rev B:  Figure 1.1. Top View of ECP5 VIP Processor Board and its Key Components  Figure 1.2. Bottom View of ECP5 VIP Processor Board April 2017 1.0 Initial release.