Texas Instruments TMS320x2833 series Reference Manual

Interrupts Reference Guide Literature Number: SPRUFB0C September 2007–Revised May 2009

1.1 Flash and OTP Memory................................................................................................... 16 1.1.1 Flash Memory...................................................................................................... 16 1.1.2 OTP Memory....................................................................................................... 16 1.2 Flash and OTP Power Modes ............................................................................................ 16 1.2.1 Flash and OTP Performance ................................................................................... 18 1.2.2 Flash Pipeline Mode .............................................................................................. 18 1.2.3 Reserved Locations Within Flash and OTP ................................................................... 19 1.2.4 Procedure to Change the Flash Configuration Registers.................................................... 20 1.3 Flash and OTP Registers ................................................................................................. 21 2 Code Security Module (CSM) ..................................................................................... 27 2.1 Functional Description..................................................................................................... 28 2.2 CSM Impact on Other On-Chip Resources............................................................................. 30 2.3 Incorporating Code Security in User Applications ..................................................................... 31 2.3.1 Environments That Require Security Unlocking .............................................................. 32 2.3.2 Password Match Flow ........................................................................................... 33 2.3.3 Unsecuring Considerations for Devices With/Without Code Security...................................... 34 2.4 Do's and Don'ts to Protect Security Logic............................................................................... 36 2.4.1 Do's ................................................................................................................. 36 2.4.2 Don'ts .............................................................................................................. 36 2.5 CSM Features - Summary ................................................................................................ 36 3 Clocking .................................................................................................................. 37 3.1 Clocking and System Control............................................................................................. 38 3.2 OSC and PLL Block........................................................................................................ 45 3.2.1 PLL-Based Clock Module ........................................................................................ 45 3.2.2 Main Oscillator Fail Detection.................................................................................... 46 3.2.3 XCLKOUT Generation............................................................................................ 48 3.2.4 PLL Control (PLLCR) Register .................................................................................. 49 3.2.5 PLL Control, Status and XCLKOUT Register Descriptions.................................................. 51 3.2.6 External Reference Oscillator Clock Option ................................................................... 52 3.3 Low-Power Modes Block.................................................................................................. 53 3.4 Watchdog Block ............................................................................................................ 55 3.4.1 Servicing The Watchdog Timer.................................................................................. 56 3.4.2 Watchdog Reset or Watchdog Interrupt Mode ................................................................ 56 3.4.3 Watchdog Operation in Low Power Modes.................................................................... 57 3.4.4 Emulation Considerations........................................................................................ 57 3.4.5 Watchdog Registers .............................................................................................. 58 3.5 32-Bit CPU Timers 0/1/2 .................................................................................................. 60 4 General-Purpose Input/Output (GPIO) ......................................................................... 65 SPRUFB0C–September 2007–Revised May 2009 Contents 3 Submit Documentation Feedback

4.2 Configuration Overview.................................................................................................... 71 4.3 Digital General Purpose I/O Control ..................................................................................... 72 4.4 Input Qualification .......................................................................................................... 74 4.4.1 No Synchronization (asynchronous input) ..................................................................... 74 4.4.2 Synchronization to SYSCLKOUT Only......................................................................... 74 4.4.3 Qualification Using a Sampling Window ....................................................................... 74 4.5 GPIO and Peripheral Multiplexing (MUX)............................................................................... 78 4.6 Register Bit Definitions .................................................................................................... 83 5 Peripheral Frames ................................................................................................... 109 5.1 Peripheral Frame Registers ............................................................................................. 110 5.2 EALLOW-Protected Registers .......................................................................................... 112 5.3 Device Emulation Registers............................................................................................. 116 5.4 Write-Followed-by-Read Protection .................................................................................... 118 6 Peripheral Interrupt Expansion (PIE) ......................................................................... 121 6.1 Overview of the PIE Controller.......................................................................................... 122 6.1.1 Interrupt Operation Sequence.................................................................................. 122 6.2 Vector Table Mapping.................................................................................................... 125 6.3 Interrupt Sources.......................................................................................................... 127 6.3.1 Procedure for Handling Multiplexed Interrupts............................................................... 129 6.3.2 Procedures for Enabling And Disabling Multiplexed Peripheral Interrupts............................... 130 6.3.3 Flow of a Multiplexed Interrupt Request From a Peripheral to the CPU ................................. 131 6.3.4 The PIE Vector Table ........................................................................................... 132 6.4 PIE Configuration Registers............................................................................................. 139 6.5 PIE Interrupt Registers................................................................................................... 140 6.5.1 PIE Interrupt Flag Registers.................................................................................... 141 6.5.2 PIE Interrupt Enable Registers................................................................................. 141 6.5.3 CPU Interrupt Flag Register (IFR)............................................................................. 142 6.5.4 Interrupt Enable Register (IER) and Debug Interrupt Enable Register (DBGIER) ...................... 144 6.6 External Interrupt Control Registers ................................................................................... 148 A Revision History ..................................................................................................... 151 Contents 4 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

1-1 Flash Power Mode State Diagram....................................................................................... 17 1-2 Flash Pipeline............................................................................................................... 19 1-3 Flash Configuration Access Flow Diagram ............................................................................. 20 1-4 Flash Options Register (FOPT) .......................................................................................... 22 1-5 Flash Power Register (FPWR) ........................................................................................... 22 1-6 Flash Status Register (FSTATUS)....................................................................................... 23 1-7 Flash Standby Wait Register (FSTDBYWAIT) ......................................................................... 24 1-8 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) .................................................. 24 1-9 Flash Wait-State Register (FBANKWAIT) .............................................................................. 25 1-10 OTP Wait-State Register (FOTPWAIT) ................................................................................. 26 2-1 CSM Status and Control Register (CSMSCR) ......................................................................... 32 2-2 Password Match Flow (PMF) ............................................................................................ 33 3-1 Clock and Reset Domains ................................................................................................ 38 3-2 Peripheral Clock Control 0 Register (PCLKCR0) ...................................................................... 39 3-3 Peripheral Clock Control 1 Register (PCLKCR1) ..................................................................... 40 3-4 Peripheral Clock Control 3 Register (PCLKCR3) ...................................................................... 43 3-5 High-Speed Peripheral Clock Prescaler (HISPCP) Register ......................................................... 44 3-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP)......................................................... 44 3-7 OSC and PLL Block........................................................................................................ 45 3-8 Oscillator Fail-Detection Logic Diagram................................................................................. 46 3-9 XCLKOUT Generation..................................................................................................... 48 3-10 PLLCR Change Procedure Flow Chart.................................................................................. 50 3-11 PLLCR Register Layout ................................................................................................... 51 3-12 PLL Status Register (PLLSTS)........................................................................................... 51 3-13 Low Power Mode Control 0 Register (LPMCR0)....................................................................... 54 3-14 Watchdog Module.......................................................................................................... 55 3-15 System Control and Status Register (SCSR) .......................................................................... 58 3-16 Watchdog Counter Register (WDCNTR)................................................................................ 59 3-17 Watchdog Reset Key Register (WDKEY)............................................................................... 59 3-18 Watchdog Control Register (WDCR) .................................................................................... 59 3-19 CPU-Timers................................................................................................................. 60 3-20 CPU-Timer Interrupts Signals and Output Signal...................................................................... 61 3-21 TIMERxTIM Register (x = 0, 1, 2)........................................................................................ 62 3-22 TIMERxTIMH Register (x = 0, 1, 2)...................................................................................... 62 3-23 TIMERxPRD Register (x = 0, 1, 2)....................................................................................... 62 3-24 TIMERxPRDH Register (x = 0, 1, 2)..................................................................................... 62 3-25 TIMERxTCR Register (x = 0, 1, 2)....................................................................................... 63 3-26 TIMERxTPR Register (x = 0, 1, 2)....................................................................................... 64 3-27 TIMERxTPRH Register (x = 0, 1, 2) .................................................................................... 64 4-1 GPIO0 to GPIO27 Multiplexing Diagram................................................................................ 66 4-2 GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 67 4-3 GPIO32, GPIO33 Multiplexing Diagram................................................................................. 68 4-4 GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) .................... 69 4-5 GPIO64 to GPIO79 Multiplexing Diagram (Minimal GPIOs Without Qualification)................................ 70 4-6 Input Qualification Using a Sampling Window.......................................................................... 74 4-7 Input Qualifier Clock Cycles .............................................................................................. 77 4-8 GPIO Port A MUX 1 (GPAMUX1) Register............................................................................. 83 4-9 GPIO Port A MUX 2 (GPAMUX2) Register............................................................................. 85 4-10 GPIO Port B MUX 1 (GPBMUX1) Register............................................................................. 87 4-11 GPIO Port B MUX 2 (GPBMUX2) Register............................................................................. 89 4-12 GPIO Port C MUX 1 (GPCMUX1) Register............................................................................. 91 4-13 GPIO Port C MUX 2 (GPCMUX2) Register............................................................................. 92 SPRUFB0C–September 2007–Revised May 2009 List of Figures 5 Submit Documentation Feedback

4-15 GPIO Port B Qualification Control (GPBCTRL) Register ............................................................ 95 4-16 GPIO Port A Qualification Select 1 (GPAQSEL1) Register........................................................... 96 4-17 GPIO Port A Qualification Select 2 (GPAQSEL2) Register........................................................... 96 4-18 GPIO Port B Qualification Select 1 (GPBQSEL1) Register........................................................... 97 4-19 GPIO Port B Qualification Select 2 (GPBQSEL2) Register........................................................... 97 4-20 GPIO Port A Direction (GPADIR) Register ............................................................................. 98 4-21 GPIO Port B Direction (GPBDIR) Register ............................................................................. 98 4-22 GPIO Port C Direction (GPCDIR) Register ............................................................................ 99 4-23 GPIO Port A Pullup Disable (GPAPUD) Registers .................................................................. 100 4-24 GPIO Port B Pullup Disable (GPBPUD) Registers .................................................................. 100 4-25 GPIO Port C Pullup Disable (GPCPUD) Registers .................................................................. 101 4-26 GPIO Port A Data (GPADAT) Register ............................................................................... 101 4-27 GPIO Port B Data (GPBDAT) Register ............................................................................... 102 4-28 GPIO Port C Data (GPCDAT) Register ............................................................................... 103 4-29 GPIO Port A Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers ....................... 104 4-30 GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers ....................... 105 4-31 GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers ...................... 106 4-32 GPIO XINTn, XNMI Interrupt Select (GPIOXINTnSEL, GPIOXNMISEL) Registers ............................. 107 4-33 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register................................................ 108 5-1 Device Configuration (DEVICECNF) Register ........................................................................ 116 5-2 Part ID Register........................................................................................................... 117 5-3 CLASSID Register........................................................................................................ 117 5-4 REVID Register ........................................................................................................... 117 6-1 Overview: Multiplexing of Interrupts Using the PIE Block ........................................................... 122 6-2 Typical PIE/CPU Interrupt Response - INTx.y........................................................................ 124 6-3 Reset Flow Diagram...................................................................................................... 126 6-4 PIE Interrupt Sources and External Interrupts XINT1/XINT2 ....................................................... 127 6-5 PIE Interrupt Sources and External Interrupts (XINT3 – XINT7) ................................................... 128 6-6 Multiplexed Interrupt Request Flow Diagram ......................................................................... 131 6-7 PIECTRL Register (Address CE0) ..................................................................................... 140 6-8 PIE Interrupt Acknowledge Register (PIEACK) Register (Address CE1) ......................................... 140 6-9 PIEIFRx Register (x = 1 to 12).......................................................................................... 141 6-10 PIEIERx Register (x = 1 to 12).......................................................................................... 141 6-11 Interrupt Flag Register (IFR) — CPU Register ....................................................................... 143 6-12 Interrupt Enable Register (IER) — CPU Register .................................................................... 145 6-13 Debug Interrupt Enable Register (DBGIER) — CPU Register ..................................................... 146 6-14 External Interrupt n Control Register (XINTnCR) .................................................................... 148 6-15 External NMI Interrupt Control Register (XNMICR) — Address 7077h............................................ 148 6-16 External Interrupt 1 Counter (XINT1CTR) (Address 7078h) ........................................................ 149 6-17 External Interrupt 2 Counter (XINT2CTR) (Address 7079h) ........................................................ 149 6-18 External NMI Interrupt Counter (XNMICTR) (Address 707Fh) ..................................................... 150 List of Figures 6 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

1-1 Flash/OTP Configuration Registers...................................................................................... 21 1-2 Flash Options Register (FOPT) Field Descriptions .................................................................... 22 1-3 Flash Power Register (FPWR) Field Descriptions..................................................................... 22 1-4 Flash Status Register (FSTATUS) Field Descriptions................................................................. 23 1-5 Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions ................................................... 24 1-6 Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions............................. 24 1-7 Flash Wait-State Register (FBANKWAIT) Field Descriptions ........................................................ 25 1-8 OTP Wait-State Register (FOTPWAIT) Field Descriptions ........................................................... 26 2-1 Security Levels ............................................................................................................. 28 2-2 Resources Affected by the CSM ......................................................................................... 30 2-3 Resources Not Affected by the CSM .................................................................................... 30 2-4 Code Security Module (CSM) Registers ................................................................................ 31 2-5 CSM Status and Control Register (CSMSCR) Field Descriptions................................................... 32 3-1 PLL, Clocking, Watchdog, and Low-Power Mode Registers ........................................................ 39 3-2 Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions................................................ 39 3-3 Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions ............................................... 41 3-4 Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions................................................ 43 3-5 High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions.............................................. 44 3-6 Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions................................... 44 3-7 Possible PLL Configuration Modes ...................................................................................... 46 3-8 PLLCR Bit Descriptions ................................................................................................... 51 3-9 PLL Status Register (PLLSTS) Field Descriptions..................................................................... 51 3-10 Low-Power Mode Summary .............................................................................................. 53 3-11 Low Power Modes ......................................................................................................... 53 3-12 Low Power Mode Control 0 Register (LPMCR0) Field Descriptions ................................................ 54 3-13 Example Watchdog Key Sequences..................................................................................... 56 3-14 System Control and Status Register (SCSR) Field Descriptions .................................................... 58 3-15 Watchdog Counter Register (WDCNTR) Field Descriptions ......................................................... 59 3-16 Watchdog Reset Key Register (WDKEY) Field Descriptions......................................................... 59 3-17 Watchdog Control Register (WDCR) Field Descriptions.............................................................. 59 3-18 CPU-Timers 0, 1, 2 Configuration and Control Registers............................................................. 61 3-19 TIMERxTIM Register Field Descriptions ................................................................................ 62 3-20 TIMERxTIMH Register Field Descriptions .............................................................................. 62 3-21 TIMERxPRD Register Field Descriptions ............................................................................... 62 3-22 TIMERxPRDH Register Field Descriptions ............................................................................. 63 3-23 TIMERxTCR Register Field Descriptions ............................................................................... 63 3-24 TIMERxTPR Register Field Descriptions ............................................................................... 64 3-25 TIMERxTPRH Register Field Descriptions.............................................................................. 64 4-1 GPIO Control Registers ................................................................................................... 71 4-2 GPIO Interrupt and Low Power Mode Select Registers............................................................... 71 4-3 GPIO Data Registers ...................................................................................................... 73 4-4 Sampling Period............................................................................................................ 75 4-5 Sampling Frequency....................................................................................................... 75 4-6 Case 1: Three-Sample Sampling Window Width ...................................................................... 76 4-7 Case 2: Six-Sample Sampling Window Width.......................................................................... 76 4-8 Default State of Peripheral Input ......................................................................................... 79 4-9 GPIOA MUX ................................................................................................................ 80 4-10 GPIOB MUX ................................................................................................................ 81 4-11 GPIOC MUX ................................................................................................................ 82 SPRUFB0C–September 2007–Revised May 2009 List of Tables 7 Submit Documentation Feedback

4-13 GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions....................................................... 85 4-14 GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions....................................................... 87 4-15 GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions....................................................... 89 4-16 GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions ...................................................... 91 4-17 GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions ...................................................... 92 4-18 GPIO Port A Qualification Control (GPACTRL) Register Field Descriptions....................................... 94 4-19 GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions....................................... 95 4-20 GPIO Port A Qualification Select 1 (GPAQSEL1) Register Field Descriptions .................................... 96 4-21 GPIO Port A Qualification Select 2 (GPAQSEL2) Register Field Descriptions .................................... 96 4-22 GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions .................................... 97 4-23 GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions .................................... 97 4-24 GPIO Port A Direction (GPADIR) Register Field Descriptions ....................................................... 98 4-25 GPIO Port B Direction (GPBDIR) Register Field Descriptions ....................................................... 99 4-26 GPIO Port C Direction (GPCDIR) Register Field Descriptions....................................................... 99 4-27 GPIO Port A Internal Pullup Disable (GPAPUD) Register Field Descriptions .................................... 100 4-28 GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions .................................... 100 4-29 GPIO Port C Internal Pullup Disable (GPCPUD) Register Field Descriptions.................................... 101 4-30 GPIO Port A Data (GPADAT) Register Field Descriptions.......................................................... 102 4-31 GPIO Port B Data (GPBDAT) Register Field Descriptions.......................................................... 102 4-32 GPIO Port C Data (GPCDAT) Register Field Descriptions ......................................................... 103 4-33 GPIO Port A Set (GPASET) Register Field Descriptions............................................................ 104 4-34 GPIO Port A Clear (GPACLEAR) Register Field Descriptions ..................................................... 104 4-35 GPIO Port A Toggle (GPATOGGLE) Register Field Descriptions ................................................. 104 4-36 GPIO Port B Set (GPBSET) Register Field Descriptions............................................................ 105 4-37 GPIO Port B Clear (GPBCLEAR) Register Field Descriptions ..................................................... 105 4-38 GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions ................................................. 105 4-39 GPIO Port C Set (GPCSET) Register Field Descriptions ........................................................... 106 4-40 GPIO Port C Clear (GPCCLEAR) Register Field Descriptions ..................................................... 106 4-41 GPIO Port C Toggle (GPCTOGGLE) Register Field Descriptions ................................................. 106 4-42 GPIO XINTn Interrupt Select (GPIOXINTnSEL) Register Field Descriptions..................................... 107 4-43 XINT1/XINT2 Interrupt Select and Configuration Registers......................................................... 107 4-44 GPIO XINT3 - XINT7 Interrupt Select (GPIOXINTnSEL) Register Field Descriptions .......................... 107 4-45 XINT3 - XINT7 Interrupt Select and Configuration Registers....................................................... 107 4-46 GPIO XNMI Interrupt Select (GPIOXNMISEL) Register Field Descriptions ...................................... 108 4-47 GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register Field Descriptions.......................... 108 5-1 Peripheral Frame 0 Registers .......................................................................................... 110 5-2 Peripheral Frame 1 Registers........................................................................................... 110 5-3 Peripheral Frame 2 Registers........................................................................................... 111 5-4 Peripheral Frame 3 Registers........................................................................................... 111 5-5 Access to EALLOW-Protected Registers.............................................................................. 112 5-6 EALLOW-Protected Device Emulation Registers..................................................................... 112 5-7 EALLOW-Protected Flash/OTP Configuration Registers............................................................ 112 5-8 EALLOW-Protected Code Security Module (CSM) Registers ...................................................... 113 5-9 EALLOW-Protected PIE Vector Table ................................................................................. 113 5-10 EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................... 114 5-11 EALLOW-Protected GPIO MUX Registers ........................................................................... 114 5-12 EALLOW-Protected eCAN Registers .................................................................................. 115 5-13 EALLOW-Protected ePWM1 - ePWM6 Registers.................................................................... 115 5-14 XINTF Registers ......................................................................................................... 115 5-15 Device Emulation Registers............................................................................................. 116 8 List of Tables SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

5-17 PARTID Register Field Descriptions ................................................................................... 117 5-18 CLASSID Register Description.......................................................................................... 117 5-19 REVID Register Field Descriptions..................................................................................... 118 5-20 PROTSTART and PROTRANGE Registers........................................................................... 118 5-21 PROTSTART Valid Values ............................................................................................. 118 5-22 PROTRANGE Valid Values ............................................................................................. 119 6-1 Enabling Interrupt......................................................................................................... 124 6-2 Interrupt Vector Table Mapping ........................................................................................ 125 6-3 Vector Table Mapping After Reset Operation ........................................................................ 125 6-4 PIE MUXed Peripheral Interrupt Vector Table........................................................................ 133 6-5 PIE Vector Table.......................................................................................................... 134 6-6 PIE Configuration and Control Registers.............................................................................. 139 6-7 PIECTRL Register Address Field Descriptions....................................................................... 140 6-8 PIE Interrupt Acknowledge Register (PIEACK) Field Descriptions................................................. 140 6-9 PIEIFRx Register Field Descriptions................................................................................... 141 6-10 PIEIERx Register (x = 1 to 12) Field Descriptions ................................................................... 142 6-11 Interrupt Flag Register (IFR) — CPU Register Field Descriptions ................................................. 143 6-12 Interrupt Enable Register (IER) — CPU Register Field Descriptions.............................................. 145 6-13 Debug Interrupt Enable Register (DBGIER) — CPU Register Field Descriptions ............................... 146 6-14 External Interrupt n Control Register (XINTnCR) Field Descriptions .............................................. 148 6-15 External NMI Interrupt Control Register (XNMICR) Field Descriptions............................................ 148 6-16 XNMICR Register Settings and Interrupt Sources ................................................................... 149 6-17 External Interrupt 1 Counter (XINT1CTR) Field Descriptions....................................................... 149 6-18 External Interrupt 2 Counter (XINT2CTR) Field Descriptions....................................................... 150 6-19 External NMI Interrupt Counter (XNMICTR) Field Descriptions .................................................... 150 A-1 Changes Made in This Revision........................................................................................ 151 SPRUFB0C–September 2007–Revised May 2009 List of Tables 9 Submit Documentation Feedback

Read This First About This Manual This reference guide is applicable for the systems control and interrupts found on the TMS320F2833x/TMS320F2823x Delfino digital signal controllers (DSCs). This guide describes how various 2833x/2823x DSC system controls and interrupts work. It includes information on the: • Flash and one-time programmable (OTP) memories • Code security module (CSM), which is a security feature incorporated in TMS320C28x™ devices. • Clocking mechanisms including the oscillator, PLL, XCLKOUT, watchdog module, and the low-power modes. In addition, the 32-bit CPU-Timers are also described. • GPIO multiplexing (MUX) registers used to select the operation of shared pins on the device. • Accessing the peripheral frames to write to and read from various peripheral registers on the device. • Interrupt sources both external and the peripheral interrupt expansion (PIE) block that multiplexes numerous interrupt sources into a smaller set of interrupt inputs. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the following number is 40 hexadecimal (decimal 64): 40h or 0x40. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documentation From Texas Instruments The following books describe the 2833x and related support tools that are available on the TI website: Data Manual and Errata— SPRS439— TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 Digital Signal Controllers (DSCs) Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the F2833x/2823x devices. SPRZ272— TMS320F28335, F28334, F28332, TMS320F28235, F28234, F28232 Digital Signal Controllers (DSCs) Silicon Errata describes the advisories and usage notes for different versions of silicon. CPU User's Guides— SPRU430 —TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. SPRUEO2 —TMS320C28x Floating Point Unit and Instruction Set Reference Guide describes the floating-point unit and includes the instructions for the FPU. Peripheral Guides— SPRUFB0C–September 2007–Revised May 2009 Read This First 11 Submit Documentation Feedback

www.ti.com SPRU566 —TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUFB0 —TMS320x2833x, 2823x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2833x and 2823x digital signal controllers (DSCs). SPRU812 —TMS320x2833x, 2823x Analog-to-Digital Converter (ADC) Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. SPRU949 —TMS320x2833x, 2823x DSC External Interface (XINTF) Reference Guide describes the XINTF, which is a nonmultiplexed asynchronous bus, as it is used on the 2833x and 2823x devices. SPRU963 —TMS320x2833x, 2823x Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. SPRUFB7 —TMS320x2833x, 2823x Multichannel Buffered Serial Port (McBSP) Reference Guide describes the McBSP available on the 2833x and 2823x devices. The McBSPs allow direct interface between a DSP and other devices in a system. SPRUFB8 —TMS320x2833x, 2823x Direct Memory Access (DMA) Module Reference Guide describes the DMA on the 2833x and 2823x devices. SPRUG04 —TMS320x2833x, 2823x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion. SPRUG02 —TMS320x2833x, 2823x High-Resolution Pulse Width Modulator (HRPWM) Reference Guide describes the operation of the high-resolution extension to the pulse width modulator (HRPWM). SPRUFG4 —TMS320x2833x, 2823x Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers. SPRUG05 —TMS320x2833x, 2823x Enhanced Quadrature Encoder Pulse (eQEP) Module Reference Guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high-performance motion and position control systems. It includes the module description and registers. SPRUEU1 —TMS320x2833x, 2823x Enhanced Controller Area Network (eCAN) Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments. SPRUFZ5 —TMS320x2833x, 2823x Serial Communications Interface (SCI) Reference Guide describes the SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. SPRUEU3 —TMS320x2833x, 2823x DSC Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. SPRUG03 — TMS320x2833x, 2823x Inter-Integrated Circuit (I2C) Module Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module. Tools Guides— 12 Read This First SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

SPRU513 —TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514 —TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 — TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core. SPRU625 —TMS320C28x DSP/BIOS 5.32 Application Programming Interface (API) Reference Guide describes development using DSP/BIOS. Trademarks TMS320C28x, C28x, Code Composer Studio are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. SPRUFB0C–September 2007–Revised May 2009 Read This First 13 Submit Documentation Feedback

Flash and OTP Memory Blocks This chapter describes the proper sequence to configure the wait states and operating mode of flash and one-time programmable (OTP) memories. It also includes information on flash and OTP power modes and how to improve flash performance by enabling the flash pipeline mode. Topic .................................................................................................. Page 1.1 Flash and OTP Memory.............................................................. 16 1.2 Flash and OTP Power Modes...................................................... 16 1.3 Flash and OTP Registers ........................................................... 21 SPRUFB0C–September 2007–Revised May 2009 Flash and OTP Memory Blocks 15 Submit Documentation Feedback

1.1.1 Flash Memory 1.1.2 OTP Memory 1.2 Flash and OTP Power Modes Flash and OTP Memory www.ti.com This section describes how to configure flash and one-time programmable (OTP) memory. The on-chip flash is uniformly mapped in both program and data memory space. This flash memory is always enabled and features: • Multiple sectors The minimum amount of flash memory that can be erased is a sector. Having multiple sectors provides the option of leaving some sectors programmed and only erasing specific sectors. • Code security The flash is protected by the Code Security Module (CSM). By programming a password into the flash, the user can prevent access to the flash by unauthorized persons. See Chapter 2 for information in using the Code Security Module. • Low power modes To save power when the flash is not in use, two levels of low power modes are available. See Section 1.2 for more information on the available flash power modes. • Configurable wait states Configurable wait states can be adjusted based on CPU frequency to give the best performance for a given execution speed. • Enhanced performance A flash pipeline mode is provided to improve performance of linear code execution. The 1K x 16 block of one-time programmable (OTP) memory is uniformly mapped in both program and data memory space. Thus, the OTP can be used to program data or code. This block, unlike flash, can be programmed only one time and cannot be erased. The following operating states apply to the flash and OTP memory: • Reset or Sleep State This is the state after a device reset. In this state, the bank and pump are in a sleep state (lowest power). When the flash is in the sleep state, a CPU data read or opcode fetch to the flash or OTP memory map area will automatically initiate a change in power modes to the standby state and then to the active state. During this transition time to the active state, the CPU will automatically be stalled. Once the transition to the active state is completed, the CPU access will complete as normal. • Standby State In this state, the bank and pump are in standby power mode state. This state uses more power then the sleep state, but takes a shorter time to transition to the active or read state. When the flash is in the standby state, a CPU data read or opcode fetch to the flash or OTP memory map area will automatically initiate a change in power modes to the active state. During this transition time to the active state, the CPU will automatically be stalled. Once the flash/OTP has reached the active state, the CPU access will complete as normal. • Active or Read State In this state, the bank and pump are in active power mode state (highest power). The CPU read or fetch access wait states to the flash/OTP memory map area is controlled by the FBANKWAIT and FOTPWAIT registers. A prefetch mechanism called flash pipeline can also be enabled to improve fetch performance for linear code execution. 16 Flash and OTP Memory Blocks SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

PWR=0,1 PWR=0,0 PWR=0,0 PWR=1,1 or access to the Flash/OTP PWR=0,1 PWR=1,1 or access to the Flash/OTP Reset www.ti.com Flash and OTP Power Modes Note: During the boot process, the Boot ROM performs a dummy read of the Code Security Module (CSM) password locations located in the flash. This read is performed to unlock a new or erased device that has no password stored in it so that flash programming or loading of code into CSM protected SARAM can be performed. On devices with a password stored, this read has no affect and the CSM remains locked (see Chapter 2 for information on the CSM). One effect of this read is that the flash will transition from the sleep (reset) state to the active state. The flash/OTP bank and pump are always in the same power mode. See Figure 1-1 for a graphic depiction of the available power states. You can change the current flash/OTP memory power state as follows: • To move to a lower power state Change the PWR mode bits from a higher power mode to a lower power mode. This change instantaneously moves the flash/OTP bank to the lower power state. This register should be accessed only by code running outside the flash/OTP memory. • To move to a higher power state To move from a lower power state to a higher power state, there are two options. 1. Change the FPWR register from a lower state to a higher state. This access brings the flash/OTP memory to the higher state. 2. Access the flash or OTP memory by a read access or program opcode fetch access. This access automatically brings the flash/OTP memory to the active state. There is a delay when moving from a lower power state to a higher one. See Figure 1-1. This delay is required to allow the flash to stabilize at the higher power mode. If any access to the flash/OTP memory occurs during this delay the CPU automatically stalls until the delay is complete. Figure 1-1. Flash Power Mode State Diagram SPRUFB0C–September 2007–Revised May 2009 Flash and OTP Memory Blocks 17 Submit Documentation Feedback

1.2.2 Flash Pipeline Mode Flash and OTP Power Modes www.ti.com The duration of the delay is determined by the FSTDBYWAIT and FACTIVEWAIT registers. Moving from the sleep state to a standby state is delayed by a count determined by the FSTDBYWAIT register. Moving from the standby state to the active state is delayed by a count determined by the FACTIVEWAIT register. Moving from the sleep mode (lowest power) to the active mode (highest power) is delayed by FSTDBYWAIT + FACTIVEWAIT. These registers should be left in their default state. CPU read or data fetch operations to the flash/OTP can take one of the following forms: • 32-bit instruction fetch • 16-bit or 32-bit data space read • 16-bit program space read Once flash is in the active power state, then a read or fetch access to the bank memory map area can be classified as a flash access or an OTP access. The main flash array is organized into rows and columns. The rows contain 2048 bits of information. Accesses to flash and OTP are one of three types: 1. Flash Memory Random Access The first access to a 2048 bit row is considered a random access. 2. Flash Memory Paged Access While the first access to a row is considered a random access, subsequent accesses within the same row are termed paged accesses. The number of wait states for both a random and a paged access can be configured by programming the FBANKWAIT register. The number of wait states used by a random access is controlled by the RANDWAIT bits and the number of wait states used by a paged access is controlled by the PAGEWAIT bits. The FBANKWAIT register defaults to a worst-case wait state count and, thus, needs to be initialized for the appropriate number of wait states to improve performance based on the CPU clock rate and the access time of the flash. The flash supports 0-wait accesses when the PAGEWAIT bits are set to zero. This assumes that the CPU speed is low enough to accommodate the access time. To determine the random and paged access time requirements, refer to the Data Manual for your particular device. 3. OTP Access Read or fetch accesses to the OTP are controlled by the OTPWAIT bits in the FOTPWAIT register. Accesses to the OTP take longer than the flash and there is no paged mode. To determine OTP access time requirements, see the data manual for your particular device. Some other points to keep in mind when working with flash: • CPU writes to the flash or OTP memory map area are ignored. They complete in a single cycle. • When the Code Security Module (CSM) is secured, reads to the flash/OTP memory map area from outside the secure zone take the same number of cycles as a normal access. However, the read operation returns a zero. • Reads of the CSM password locations are hardwired for 16 wait-states. The PAGEWAIT and RANDOMWAIT bits have no effect on these locations. See Chapter 2 for more information on the CSM. Flash memory is typically used to store application code. During code execution, instructions are fetched from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code that resides in sequential addresses makes up the majority of the application code and is referred to as linear code. To improve the performance of linear code execution, a flash pipeline mode has been implemented. The flash pipeline feature is disabled by default. Setting the ENPIPE bit in the FOPT register enables this mode. The flash pipeline mode is independent of the CPU pipeline. 18 Flash and OTP Memory Blocks SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Instruction Fetch (64 bits) Flash or OTP Read 16 bits Flash and OTP Instruction buffer 64-bit Buffer 64-bit Buffer 1.2.3 Reserved Locations Within Flash and OTP www.ti.com Flash and OTP Power Modes An instruction fetch from the flash or OTP reads out 64 bits per access. The starting address of the access from flash is automatically aligned to a 64-bit boundary such that the instruction location is within the 64 bits to be fetched. With flash pipeline mode enabled (see Figure 1-2), the 64 bits read from the instruction fetch are stored in a 64-bit wide by 2-level deep instruction pre-fetch buffer. The contents of this pre-fetch buffer are then sent to the CPU for processing as required. Up to two 32-bit instructions or up to four 16-bit instructions can reside within a single 64-bit access. The majority of C28x instructions are 16 bits, so for every 64-bit instruction fetch from the flash bank it is likely that there are up to four instructions in the pre-fetch buffer ready to process through the CPU. During the time it takes to process these instructions, the flash pipeline automatically initiates another access to the flash bank to pre-fetch the next 64 bits. In this manner, the flash pipeline mode works in the background to keep the instruction pre-fetch buffers as full as possible. Using this technique, the overall efficiency of sequential code execution from flash or OTP is improved significantly. Figure 1-2. Flash Pipeline The flash pipeline pre-fetch is aborted only on a PC discontinuity caused by executing an instruction such as a branch, BANZ, call, or loop. When this occurs, the pre-fetch is aborted and the contents of the pre-fetch buffer are flushed. There are two possible scenarios when this occurs: 1. If the destination address is within the flash or OTP, the pre-fetch aborts and then resumes at the destination address. 2. If the destination address is outside of the flash and OTP, the pre-fetch is aborted and begins again only when a branch is made back into the flash or OTP. The flash pipeline pre-fetch mechanism only applies to instruction fetches from program space. Data reads from data memory and from program memory do not utilize the pre-fetch buffer capability and thus bypass the pre-fetch buffer. For example, instructions such as MAC, DMAC, and PREAD read a data value from program memory. When this read happens, the pre-fetch buffer is bypassed but the buffer is not flushed. If an instruction pre-fetch is already in progress when a data read operation is initiated, then the data read will be stalled until the pre-fetch completes. When allocating code and data to flash and OTP memory, keep the following in mind: 1. Address locations 0x33 FFF6 and 0x33 FFF7 are reserved for an "entry into flash" branch instruction. When the "boot to flash" boot option is used, the boot ROM will jump to address 0x33 FFF6. If you program a branch instruction here that will then re-direct code execution to the entry point of the application. SPRUFB0C–September 2007–Revised May 2009 Flash and OTP Memory Blocks 19 Submit Documentation Feedback

Wait eight cycles to let the write instructions propagate through the CPU pipeline. This must be done before the return-from-function call is made. Write instructions to FOPT, FBANKWAIT, etc. The function that changes the configuration cannot execute from the Flash or OTP. Branch or call is required to properly flush the CPU pipeline before the configuration change. Wait 8 cycles (8 NOPs) Return to calling function Continue execution SARAM, Flash, or OTP Flash configuration change Do not execute from Flash/OTP SARAM Begin Flash configuration change SARAM, Flash, OTP Branch or call to configuration code Flash and OTP Power Modes www.ti.com 2. For code security operation, all addresses between 0x33 FF80 and 0x33 FFF5 cannot be used for program code or data, but must be programmed to 0x0000 when the Code Security Password is programmed. If security is not a concern, addresses 0x33 FF80 through 0x33 FFF5 may be used for code or data. See Chapter 2 for information in using the Code Security Module. 3. Addresses from 0x33 FFF0 to 0x33 FFF5 are reserved for data variables and should not contain program code. During flash configuration, no accesses to the flash or OTP can be in progress. This includes instructions still in the CPU pipeline, data reads, and instruction pre-fetch operations. To be sure that no access takes place during the configuration change, you should follow the procedure shown in Figure 1-3 for any code that modifies the FOPT, FPWR, FBANKWAIT, or FOTPWAIT registers. Figure 1-3. Flash Configuration Access Flow Diagram 20 Flash and OTP Memory Blocks SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

www.ti.com Flash and OTP Registers The flash and OTP memory can be configured by the registers shown in Table 1-1. The configuration registers are all EALLOW protected. The bit descriptions are in Figure 1-4 through Figure 1-10. Table 1-1. Flash/OTP Configuration Registers Name(1)(2) Address Size (x16) Description Bit Description FOPT 0x0A80 1 Flash Option Register Figure 1-4 Reserved 0x0A81 1 Reserved FPWR 0x0A82 1 Flash Power Modes Register Figure 1-5 FSTATUS 0x0A83 1 Status Register Figure 1-6 FSTDBYWAIT (3) 0x0A84 1 Flash Sleep To Standby Wait Register Figure 1-7 FACTIVEWAIT (3) 0x0A85 1 Flash Standby To Active Wait Register Figure 1-8 FBANKWAIT 0x0A86 1 Flash Read Access Wait State Register Figure 1-9 FOTPWAIT 0x0A87 1 OTP Read Access Wait State Register Figure 1-10 (1) These registers are EALLOW protected. See Section 5.2 for information. (2) These registers are protected by the Code Security Module (CSM). See Chapter 2 for more information. (3) These registers should be left in their default state. Note: The flash configuration registers should not be written to by code that is running from OTP or flash memory or while an access to flash or OTP may be in progress. All register accesses to the flash registers should be made from code executing outside of flash/OTP memory and an access should not be attempted until all activity on the flash/OTP has completed. No hardware is included to protect against this. To summarize, you can read the flash registers from code executing in flash/OTP; however, do not write to the registers. CPU write access to the flash configuration registers can be enabled only by executing the EALLOW instruction. Write access is disabled when the EDIS instruction is executed. This protects the registers from spurious accesses. Read access is always available. The registers can be accessed through the JTAG port without the need to execute EALLOW. See Section 5.2 for information on EALLOW protection. These registers support both 16-bit and 32-bit accesses. SPRUFB0C–September 2007–Revised May 2009 Flash and OTP Memory Blocks 21 Submit Documentation Feedback

www.ti.com Figure 1-4. Flash Options Register (FOPT) 15 1 0 Reserved ENPIPE R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-2. Flash Options Register (FOPT) Field Descriptions Bit Field Value Description (1)(2)(3) 15-1 Reserved 0 ENPIPE Enable Flash Pipeline Mode Bit. Flash pipeline mode is active when this bit is set. The pipeline mode improves performance of instruction fetches by pre-fetching instructions. See Section 1.2.2 for more information. When pipeline mode is enabled, the flash wait states (paged and random) must be greater than zero. On flash devices, ENPIPE affects fetches from flash and OTP. 0 Flash Pipeline mode is not active. (default) 1 Flash Pipeline mode is active. (1) This register is EALLOW protected. See Section 5.2 for more information. (2) This register is protected by the Code Security Module (CSM). See Chapter 2 for more information. (3) When writing to this register, follow the procedure described in Section 1.2.4. Figure 1-5. Flash Power Register (FPWR) 15 2 1 0 Reserved PWR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-3. Flash Power Register (FPWR) Field Descriptions Bit Field Value Description (1)(2) 15-2 Reserved 1-0 PWR Flash Power Mode Bits. Writing to these bits changes the current power mode of the flash bank and pump. See section Section 1.2 for more information on changing the flash bank power mode. 00 Pump and bank sleep (lowest power) 01 Pump and bank standby 10 Reserved (no effect) 11 Pump and bank active (highest power) (1) This register is EALLOW protected. See Section 5.2 for more information. (2) This register is protected by the Code Security Module (CSM). See Chapter 2 for more information. Flash and OTP Memory Blocks 22 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Figure 1-6. Flash Status Register (FSTATUS) 15 9 8 Reserved 3VSTAT R-0 R/W1C-0 7 4 3 2 1 0 Reserved ACTIVEWAITS STDBYWAITS PWRS R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset Table 1-4. Flash Status Register (FSTATUS) Field Descriptions Bit Field Value Description (1)(2) 15-9 Reserved Reserved 8 3VSTAT Flash Voltage (VDD3VFL) Status Latch Bit. When set, this bit indicates that the 3VSTAT signal from the pump module went to a high level. This signal indicates that the flash 3.3-V supply went out of the allowable range. 0 Writes of 0 are ignored. 1 When this bit reads 1, it indicates that the flash 3.3-V supply went out of the allowable range. Clear this bit by writing a 1. 7-4 Reserved Reserved 3 ACTIVEWAITS Bank and Pump Standby To Active Wait Counter Status Bit. This bit indicates whether the respective wait counter is timing out an access. 0 The counter is not counting. 1 The counter is counting. 2 STDBYWAITS Bank and Pump Sleep To Standby Wait Counter Status Bit. This bit indicates whether the respective wait counter is timing out an access. 0 The counter is not counting. 1 The counter is counting. 1-0 PWRS Power Modes Status Bits. These bits indicate which power mode the flash/OTP is currently in. The PWRS bits are set to the new power mode only after the appropriate timing delays have expired. 00 Pump and bank in sleep mode (lowest power) 01 Pump and bank in standby mode 10 Reserved 11 Pump and bank active and in read mode (highest power) (1) This register is EALLOW protected. See Section 5.2 for more information. (2) This register is protected by the Code Security Module (CSM). See Chapter 2 for more information. SPRUFB0C–September 2007–Revised May 2009 Flash and OTP Memory Blocks 23 Submit Documentation Feedback

www.ti.com Figure 1-7. Flash Standby Wait Register (FSTDBYWAIT) 15 9 8 0 Reserved STDBYWAIT R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-5. Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions Bit Field Value Description (1)(2) 15-9 Reserved 0 Reserved 8-0 STDBYWAIT This register should be left in its default state. Bank and Pump Sleep To Standby Wait Count. 111111111 511 SYSCLKOUT cycles (default) (1) This register is EALLOW protected. See Section 5.2 for more information. (2) This register is protected by the Code Security Module (CSM). See Chapter 2 for more information. Figure 1-8. Flash Standby to Active Wait Counter Register (FACTIVEWAIT) 7 9 8 0 Reserved ACTIVEWAIT R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-6. Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions Bits Field Value Description (1)(2) 15-9 Reserved 0 Reserved 8-0 ACTIVEWAIT This register should be left in its default state. Bank and Pump Standby To Active Wait Count: 111111111 511 SYSCLKOUT cycles (default) (1) This register is EALLOW protected. See Section 5.2 for more information. (2) This register is protected by the Code Security Module (CSM). See Chapter 2 for more information. Flash and OTP Memory Blocks 24 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Figure 1-9. Flash Wait-State Register (FBANKWAIT) 15 12 11 8 7 4 3 0 Reserved PAGEWAIT Reserved RANDWAIT R-0 R/W-1 R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-7. Flash Wait-State Register (FBANKWAIT) Field Descriptions Bits Field Value Description (1)(2)(3) 15-12 Reserved Reserved 11-8 PAGEWAIT Flash Paged Read Wait States. These register bits specify the number of wait states for a paged read operation in CPU clock cycles (0..15 SYSCLKOUT cycles) to the flash bank. See Section 1.2.1 for more information. See the device-specific data manual for the minimum time required for a PAGED flash access. You must set RANDWAIT to a value greater than or equal to the PAGEWAIT setting. No hardware is provided to detect a PAGEWAIT value that is greater then RANDWAIT. 0000 Illegal value. PAGEWAIT must be set greater then 0. 0001 One wait state per paged flash access or a total of two SYSCLKOUT cycles per access. 0010 Two wait states per paged flash access or a total of three SYSCLKOUT cycles per access. 0011 Three wait states per paged flash access or a total of four SYSCLKOUT cycles per access. . . . . . . 1111 15 wait states per paged flash access or a total of 16 SYSCLKOUT cycles per access. (default) 7-4 Reserved Reserved 3-0 RANDWAIT Flash Random Read Wait States. These register bits specify the number of wait states for a random read operation in CPU clock cycles (1..15 SYSCLKOUT cycles) to the flash bank. See Section 1.2.1 for more information. See the device-specific data manual for the minimum time required for a RANDOM flash access. RANDWAIT must be set greater than 0. That is, at least 1 random wait state must be used. In addition, you must set RANDWAIT to a value greater than or equal to the PAGEWAIT setting. The device will not detect and correct a PAGEWAIT value that is greater then RANDWAIT. 0000 Illegal value. RANDWAIT must be set greater then 0. 0001 One wait state per random flash access or a total of two SYSCLKOUT cycles per access. 0010 Two wait states per random flash access or a total of three SYSCLKOUT cycles per access. 0011 Three wait states per random flash access or a total of four SYSCLKOUT cycles per access. . . . . . . 1111 15 wait states per random flash access or a total of 16 SYSCLKOUT cycles per access. (default) (1) This register is EALLOW protected. See Section 5.2 for more information. (2) This register is protected by the Code Security Module (CSM). See Chapter 2 for more information. (3) When writing to this register, follow the procedure described in Section 1.2.4. SPRUFB0C–September 2007–Revised May 2009 Flash and OTP Memory Blocks 25 Submit Documentation Feedback

www.ti.com Figure 1-10. OTP Wait-State Register (FOTPWAIT) 15 5 4 0 Reserved OTPWAIT R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-8. OTP Wait-State Register (FOTPWAIT) Field Descriptions Bit(s) Field Value Description (1)(2)(3) 15-5 Reserved 0 Reserved 4-0 OTPWAIT OTP Read Wait States. These register bits specify the number of wait states for a read operation in CPU clock cycles (1..31 SYSCLKOUT cycles) to the OTP. See CPU Read Or Fetch Access From flash/OTP section for details. There is no PAGE mode in the OTP. OTPWAIT must be set greater than 0. That is, a minimum of 1 wait state must be used. See the device-specific data manual for the minimum time required for an OTP access. 00000 Illegal value. OTPWAIT must be set to 1 or greater. 00001 One wait state will be used each OTP access for a total of two SYSCLKOUT cycles per access. 00010 Two wait states will be used for each OTP access for a total of three SYSCLKOUT cycles per access. 00011 Three wait states will be used for each OTP access for a total of four SYSCLKOUT cycles per access. . . . . . . 11111 31 wait states will be used for an OTP access for a total of 32 SYSCLKOUT cycles per access. (1) This register is EALLOW protected. See Section 5.2 for more information. (2) This register is protected by the Code Security Module (CSM). See Chapter 2 for more information. (3) When writing to this register, follow the procedure described in Section 1.2.4. 26 Flash and OTP Memory Blocks SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Code Security Module (CSM) The code security module (CSM) is a security feature incorporated in 28x devices. It prevents access/visibility to on-chip memory to unauthorized persons—i.e., it prevents duplication/reverse engineering of proprietary code. The word secure means access to on-chip memory is protected. The word unsecure means access to on-chip secure memory is not protected — i.e., the contents of the memory could be read by any means (through a debugging tool such as Code Composer Studio™, for example). Topic .................................................................................................. Page 2.1 Functional Description............................................................... 28 2.2 CSM Impact on Other On-Chip Resources ................................... 30 2.3 Incorporating Code Security in User Applications......................... 31 2.4 Do's and Don'ts to Protect Security Logic.................................... 36 2.5 CSM Features - Summary........................................................... 36 SPRUFB0C–September 2007–Revised May 2009 Code Security Module (CSM) 27 Submit Documentation Feedback

CPU execution. When a read occurs to a protected memory location, the read returns a zero value and CPU execution continues with the next instruction. This, in effect, blocks read and write access to various memories through the JTAG port or external peripherals. Security is defined with respect to the access of on-chip memory and prevents unauthorized copying of proprietary code or data. The device is secure when CPU access to the on-chip secure memory locations is restricted. When secure, two levels of protection are possible, depending on where the program counter is currently pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked (i.e., through the emulator). This allows secure code to access secure data. Conversely, if code is running from nonsecure memory, all accesses to secure memories are blocked. User code can dynamically jump in and out of secure memory, thereby allowing secure function calls from nonsecure memory. Similarly, interrupt service routines can be placed in secure memory, even if the main program loop is run from nonsecure memory. Security is protected by a password of 128-bits of data (eight 16-bit words) that is used to secure or unsecure the device. This password is stored at the end of flash in 8 words referred to as the password locations. The device is unsecured by executing the password match flow (PMF), described Section 2.3.2. Table 2-1 shows the levels of security. Table 2-1. Security Levels PMF Executed Operating Mode Program Fetch Security Description With Correct Location Password? No Secure Outside secure memory Only instruction fetches by the CPU are allowed to secure memory. In other words, code can still be executed, but not read No Secure Inside secure memory CPU has full access. JTAG port cannot read the secured memory contents. Yes Not Secure Anywhere Full access for CPU and JTAG port to secure memory The password is stored in code security password locations (PWL) in flash memory (0x33 FFF8 - 0x33 FFFF). These locations store the password predetermined by the system designer. If the password locations have all 128 bits as ones, the device is labeled unsecure. Since new flash devices have erased flash (all ones), only a read of the password locations is required to bring the device into unsecure mode. If the password locations have all 128 bits as zeros, the device is secure, regardless of the contents of the KEY registers. Do not use all zeros as a password or reset the device during an erase of the flash. Resetting the device during an erase routine can result in either an all zero or unknown password. If a device is reset when the password locations are all zeros, the device cannot be unlocked by the password match flow described in Section 2.3.2. Using a password of all zeros will seriously limit your ability to debug secure code or reprogram the flash. Note: If a device is reset while the password locations are all zero or an unknown value, the device will be permanently locked unless a method to run the flash erase routine from secure SARAM is embedded into the flash or OTP. Care must be taken when implementing this procedure to avoid introducing a security hole. User accessible registers (eight 16-bit words) that are used to unsecure the device are referred to as key registers. These registers are mapped in the memory space at addresses 0x00 0AE0 - 0x00 0AE7 and are EALLOW protected. 28 Code Security Module (CSM) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, L0, L1, L2 or L3 memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory reads, you must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value does not need to match. When initially debugging a device with the password locations in flash programmed (i.e., secured), the emulator takes some time to take control of the CPU. During this time, the CPU will start running and may execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will trip and cause the emulator connection to be cut. Two solutions to this problem exist: 1. The first is to use the Wait-In-Reset emulation mode, which will hold the device in reset until the emulator takes control. The emulator must support this mode for this option. 2. The second option is to use the “Branch to check boot mode” boot option. This will sit in a loop and continuously poll the boot mode select pins. You can select this boot mode and then exit this mode once the emulator is connected by re-mapping the PC to another address or by changing the boot mode selection pin to the desired boot mode. Note: Reserved Flash Locations When Using Code Security For code security operation, all addresses between 0x33 FF80 and 0x33 FFF5 cannot be used as program code or data, but must be programmed to 0x0000 when the Code Security Password is programmed. If security is not a concern, addresses 0x33 FF80 through 0x33 FFF5 may be used for code or data. The 128-bit password (at 0x33 FFF8 - 0x33 FFFF) must not be programmed to zeros. Doing so would permanently lock the device. Addresses 0x33 FFF0 through 0x33 FFF5 are reserved for data variables and should not contain program code. Disclaimer: Code Security Module Disclaimer The Code Security Module ("CSM") included on this device was designed to password protect the data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI's published specifications for the warranty period applicable for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. SPRUFB0C–September 2007–Revised May 2009 Code Security Module (CSM) 29 Submit Documentation Feedback

CSM Impact on Other On-Chip Resources www.ti.com The CSM affects access to the on-chip resources listed in Table 2-2: Table 2-2. Resources Affected by the CSM Address Block 0x00 0A80 - 0x00 0A87 Flash Configuration Registers 0x00 8000 - 0x00 8FFF L0 SARAM (4K X 16) 0x00 9000 - 0x00 9FFF L1 SARAM (4K X 16) 0x00 A000 - 0x00 AFFF L2 SARAM (4K X 16) 0x00 B000 - 0x00 BFFF L3 SARAM (4K X 16) 0x30 0000 - 0x33 FFFF Flash (64K X 16, 32 X 16, or 16 X 16) 0x38 0000 - 0x38 03FF TI One-Time Programmable (OTP)(1) (1K X 16) 0x38 0400 - 0x38 07FF User One-Time Programmable (OTP) (1K X 16) 0x3F 8000 - 0x3F 8FFF L0 SARAM (4K X 16), mirror 0x3F 9000 - 0x3F 9FFF L1 SARAM (4K X 16), mirror 0x3F A000 - 0x3F AFFF L2 SARAM (4K X 16), mirror 0x3F B000 - 0x3F BFFF L3 SARAM (4K X 16), mirror (1) Not affected by ECSL The Code Security Module has no impact whatsoever on the following on-chip resources: • Single-access RAM (SARAM) blocks not designated as secure - These memory blocks can be freely accessed and code run from them, whether the device is in secure or unsecure mode. • Boot ROM contents - Visibility to the boot ROM contents is not impacted by the CSM. • On-chip peripheral registers - The peripheral registers can be initialized by code running from on-chip or off-chip memory, whether the device is in secure or unsecure mode. • PIE Vector Table - Vector tables can be read and written regardless of whether the device is in secure or unsecure mode. Table 2-2 and Table 2-3 show which on-chip resources are affected (or are not affected) by the CSM. Table 2-3. Resources Not Affected by the CSM Address Block 0x00 0000 - 0x00 03FF M0 SARAM (1K X 16) 0x00 0400 - 0x00 07FF M1 SARAM (1K X16) 0x00 0800 - 0x00 0CFF Peripheral Frame 0 (2K X 16) 0x00 0D00 - 0x00 0FFF PIE Vector RAM (256 X 16) 0x00 6000 - 0x00 6FFF Peripheral Frame 1 (4K X 16) 0x00 7000 - 0x00 7FFF Peripheral Frame 2 (4K X 16) 0x00 C000 - 0x00 CFFF L4 SARAM (4K X 16) 0x00 D000 - 0x00 DFFF L5 SARAM (4K X 16) 0x00 E000 - 0x00 EFFF L6 SARAM (4K X 16) 0x00 F000 - 0x00 FFFF L7 SARAM (4K X 16) 0x3F F000 - 0x3F FFFF Boot ROM (4K X 16) To summarize, it is possible to load code onto the unprotected on-chip program SARAM shown in Table 2-3 via the JTAG connector without any impact from the Code Security Module. The code can be debugged and the peripheral registers initialized, independent of whether the device is in secure or unsecure mode. Code Security Module (CSM) 30 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

www.ti.com Incorporating Code Security in User Applications Code security is typically not required in the development phase of a project; however, security is needed once a robust code is developed. Before such a code is programmed in the flash memory, a password should be chosen to secure the device. Once a password is in place, the device is secured (i.e., programming a password at the appropriate locations and either performing a device reset or setting the FORCESEC bit (CSMSCR.15) is the action that secures the device). From that time on, access to debug the contents of secure memory by any means (via JTAG, code running off external/on-chip memory etc.) requires the supply of a valid password. A password is not needed to run the code out of secure memory (such as in a typical end-customer usage); however, access to secure memory contents for debug purpose requires a password. Table 2-4. Code Security Module (CSM) Registers Memory Address Register Name Reset Values Register Description KEY Registers 0x00 - 0AE0 KEY0(1) 0xFFFF Low word of the 128-bit KEY register 0x00 - 0AE1 KEY1(1) 0xFFFF Second word of the 128-bit KEY register 0x00 - 0AE2 KEY2(1) 0xFFFF Third word of the 128-bit KEY register 0x00 - 0AE3 KEY3(1) 0xFFFF Fourth word of the 128-bit key 0x00 - 0AE4 KEY4(1) 0xFFFF Fifth word of the 128-bit key 0x00 - 0AE5 KEY5(1) 0xFFFF Sixth word of the 128-bit key 0x00 - 0AE6 KEY6(1) 0xFFFF Seventh word of the 128-bit key 0x00 - 0AE7 KEY7(1) 0xFFFF High word of the 128-bit KEY register 0x00 - 0AEF CSMSCR(1) 0x005F CSM status and control register Password Locations (PWL) in Flash Memory - Reserved for the CSM password only 0x33 - FFF8 PWL0 User defined Low word of the 128-bit password 0x33 - FFF9 PWL1 User defined Second word of the 128-bit password 0x33 - FFFA PWL2 User defined Third word of the 128-bit password 0x33 - FFFB PWL3 User defined Fourth word of the 128-bit password 0x33 - FFFC PWL4 User defined Fifth word of the 128-bit password 0x33 - FFFD PWL5 User defined Sixth word of the 128-bit password 0x33 - FFFE PWL6 User defined Seventh word of the 128-bit password 0x33 - FFFF PWL7 User defined High word of the 128-bit password (1) These registers are EALLOW protected. Refer to Section 5.2 for more information. SPRUFB0C–September 2007–Revised May 2009 Code Security Module (CSM) 31 Submit Documentation Feedback

Incorporating Code Security in User Applications www.ti.com Figure 2-1. CSM Status and Control Register (CSMSCR) 15 14 7 6 1 0 FORCESEC Reserved Reserved SECURE R/W-1 R-0 R-10111 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 2-5. CSM Status and Control Register (CSMSCR) Field Descriptions Bits Field Value Description (1) 15 FORCESEC Writing a 1 clears the KEY registers and secures the device. 0 A read always returns a zero. 1 Clears the KEY registers and secures the device. The password match flow described in Section 2.3.2 must be followed to unsecure the device again. 14-1 Reserved Reserved 0 SECURE Read-only bit that reflects the security state of the device. 0 Device is unsecure (CSM unlocked). 1 Device is secure (CSM locked). (1) This register is EALLOW protected. Refer to Section 5.2 for more information. Following are the typical situations under which unsecuring can be required: • Code development using debuggers (such as Code Composer Studio™). This is the most common environment during the design phase of a product. • Flash programming using TI's flash utilities such as Code Composer Studio™ F28xx On-Chip Flash Programmer plug-in. Flash programming is common during code development and testing. Once the user supplies the necessary password, the flash utilities disable the security logic before attempting to program the flash. The flash utilities can disable the code security logic in new devices without any authorization, since new devices come with an erased flash. However, reprogramming devices (that already contain a custom password) require the password to be supplied to the flash utilities in order to unlock the device to enable programming. In custom programming solutions that use the flash API supplied by TI unlocking the CSM can be avoided by executing the flash programming algorithms from secure memory. • Custom environment defined by the application In addition to the above, access to secure memory contents can be required in situations such as: • Using the on-chip bootloader to load code or data into secure SARAM or to erase/program the flash. • Executing code from on-chip unsecure memory and requiring access to secure memory for lookup table. This is not a suggested operating condition as supplying the password from external code could compromise code security. The unsecuring sequence is identical in all the above situations. This sequence is referred to as the password match flow (PMF) for simplicity. Figure 2-2 explains the sequence of operation that is required every time the user attempts to unsecure a device. A code example is listed for clarity. 32 Code Security Module (CSM) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Start Yes No Yes No Device�unsecure User�can�access on-chip�secure memory Device�permanently�secured CPU�access�is�limited. Device�cannot�be�debugged or�reprogrammed. Do�dummy�read�of�PWL 0x33�FFF8 − 0x33�FFFF KEY�registers�=�all�ones Correct password? Are�PWL�= all�Fs? Are�PWL�= all�zeros? Device�secure�after reset�or�runtime No Yes Write�the�password�to KEY�registers 0x00�0AE0 0x00�0AE7 (A) − www.ti.com Incorporating Code Security in User Applications Password match flow (PMF) is essentially a sequence of eight dummy reads from password locations (PWL) followed by eight writes to KEY registers. Figure 2-2 shows how the PMF helps to initialize the security logic registers and disable security logic. Figure 2-2. Password Match Flow (PMF) A The KEY registers are EALLOW protected. SPRUFB0C–September 2007–Revised May 2009 Code Security Module (CSM) 33 Submit Documentation Feedback

Incorporating Code Security in User Applications www.ti.com Case 1 and Case 2 provide unsecuring considerations for devices with and without code security. Case 1: Device With Code Security A device with code security should have a predetermined password stored in the password locations (0x33 FFF8 - 0x33 FFFF in memory). In addition, locations 0x33 FF80 - 0x33 FFF5 should be programmed with all 0x0000 and not used for program and/or data storage. The following are steps to unsecure this device: 1. Perform a dummy read of the password locations. 2. Write the password into the KEY registers (locations 0x00 0AE0 - 0x00 0AE7 in memory). 3. If the password is correct, the device becomes unsecure; otherwise, it stays secure. Case 2: Device Without Code Security A device without code security should have 0x FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF (128 bits of all ones) stored in the password locations. The following are steps to use this device: 1. At reset, the CSM will lock memory regions protected by the CSM. 2. Perform a dummy read of the password locations. 3. Since the password is all ones, this alone will unlock all memory regions. Secure memory is fully accessible immediately after this operation is completed. Note: Even if a device is not protected with a password (all password locations all ones), the CSM will lock at reset. Thus, a dummy read operation must still be performed on these devices prior to reading, writing, or programming secure memory if the code performing the access is executing from outside of the CSM protected memory region. The Boot ROM code does this dummy read for convenience. 34 Code Security Module (CSM) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

2.3.3.2 C Code Example to Resecure www.ti.com Incorporating Code Security in User Applications volatile int *CSM = (volatile int *)0x000AE0; //CSM register file volatile int *PWL = (volatile int *)0x0033FFF8; //Password location volatile int tmp; int I; // Read the 128-bits of the password locations (PWL) // in flash at address 0x33 FFF8 - 0x33 FFFF // If the device is secure, then the values read will // not actually be loaded into the temp variable, so // this is called a dummy read. for (I=0; i<8; I++) tmp = *PWL++; // If the password locations (PWL) are all = ones (0xFFFF), // then the device will now be unsecure. If the password // is not all ones (0xFFFF), then the code below is required // to unsecure the CSM. // Write the 128-bit password to the KEY registers // If this password matches that stored in the // PWL then the CSM will become unsecure. If it does not // match, then the device will remain secure. // An example password of: // 0x11112222333344445555666677778888 is used. asm(" EALLOW"); // Key registers are EALLOW protected *CSM++ = 0x1111; // Register KEY0 at 0xAE0 *CSM++ = 0x2222; // Register KEY1 at 0xAE1 *CSM++ = 0x3333; // Register KEY2 at 0xAE2 *CSM++ = 0x4444; // Register KEY3 at 0xAE3 *CSM++ = 0x5555; // Register KEY4 at 0xAE4 *CSM++ = 0x6666; // Register KEY5 at 0xAE5 *CSM++ = 0x7777; // Register KEY6 at 0xAE6 *CSM++ = 0x8888; // Register KEY7 at 0xAE7 asm(" EDIS"); volatile int *CSMSCR = 0x00AEF; //CSMSCR register //Set FORCESEC bit asm(" EALLOW"); //CSMSCR register is EALLOW protected. *CSMSCR = 0x8000; asm("EDIS"); SPRUFB0C–September 2007–Revised May 2009 Code Security Module (CSM) 35 Submit Documentation Feedback

2.4.1 Do's 2.4.2 Don'ts 2.5 CSM Features - Summary Do's and Don'ts to Protect Security Logic www.ti.com • To keep the debug and code development phase simple, use the device in the unsecure mode; i.e., use all 128 bits as ones in the password locations (or use a password that is easy to remember). Use a password after the development phase when the code is frozen. • Recheck the password stored in the password locations before programming the COFF file using flash utilities. • The flow of code execution can freely toggle back and forth between secure memory and unsecure memory without compromising security. To access data variables located in secure memory when the device is secured, code execution must currently be running from secure memory. • Program locations 0x33 FF80 - 0x33 FFF5 with 0x0000 when using the CSM. • If code security is desired, do not embed the password in your application anywhere other than in the password locations or security can be compromised. • Do not use 128 bits of all zeros as the password. This automatically secures the device, regardless of the contents of the KEY register. The device is not debuggable nor reprogrammable. • Do not pull a reset during an erase operation on the flash array. This can leave either zeros or an unknown value in the password locations. If the password locations are all zero during a reset, the device will always be secure, regardless of the contents of the KEY register. • Do not use locations 0x33 FF80 - 0x33 FFF5 to store program and/or data. These locations should be programmed to 0x0000 when using the CSM. 1. The flash is secured after a reset until the password match flow described in Section 2.3.2 is executed. 2. The standard way of running code out of the flash is to program the flash with the code and power up the DSP. Since instruction fetches are always allowed from secure memory, regardless of the state of the CSM, the code functions correctly even without executing the password match flow. 3. Secure memory cannot be modified by code executing from unsecure memory while the device is secured. 4. Secure memory cannot be read from any code running from unsecure memory while the device is secured. 5. Secure memory cannot be read or written to by the debugger (i.e., Code Composer Studio™) at any time that the device is secured. 6. Complete access to secure memory from both the CPU code and the debugger is granted while the device is unsecured. Code Security Module (CSM) 36 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Clocking This section describes the oscillator, PLL and clocking mechanisms, the watchdog function, and the low-power modes. Topic .................................................................................................. Page 3.1 Clocking and System Control..................................................... 38 3.2 OSC and PLL Block................................................................... 45 3.3 Low-Power Modes Block............................................................ 53 3.4 Watchdog Block........................................................................ 55 3.5 32-Bit CPU Timers 0/1/2 ............................................................. 60 SPRUFB0C–September 2007–Revised May 2009 Clocking 37 Submit Documentation Feedback

ePWM1/../6,�HRPWM1/../6, eCAP1/../6,�eQEP1/2 Peripheral Registers Bridge Clock�Enables I/O Peripheral Registers Clock�Enables I/O eCAN-A/B /2 Peripheral Registers Clock�Enables I/O SPI-A,�SCI-A/B/C LOSPCP LSPCLK System Control Register Bridge SYSCLKOUT Memory�Bus C28x�Core GPIO Mux Clock�Enables Peripheral Registers I/O McBSP-A/B LOSPCP LSPCLK Clock�Enables Bridge HISPCP HSPCLK DMA Bus Result Registers Bridge 12-Bit ADC ADC Registers 16�Channels DMA Clock�Enables Peripheral�Bus CLKIN I2C-A Clock�Enables Clocking and System Control www.ti.com Figure 3-1 shows the various clock and reset domains. The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-1. Figure 3-1. Clock and Reset Domains A CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Clocking 38 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 3-1. PLL, Clocking, Watchdog, and Low-Power Mode Registers Name Address Size Description(1) Bit Description (x16) PLLSTS (2) 0x7011 1 PLL Status Register Figure 3-12 HISPCP 0x701A 1 High-Speed Peripheral Clock (HSPCLK) Prescaler Register Figure 3-5 LOSPCP 0x701B 1 Low-Speed Peripheral Clock (LSPCLK) Prescaler Register Figure 3-6 PCLKCR0 0x701C 1 Peripheral Clock Control Register 0 Figure 3-2 PCLKCR1 0x701D 1 Peripheral Clock Control Register 1 Figure 3-3 LPMCR0 0x701E 1 Low Power Mode Control Register 0 Figure 3-6 PCLKCR3 0x7020 1 Peripheral Clock Control Register 3 Figure 3-4 PLLCR (2) 0x7021 1 PLL Control Register Figure 3-11 SCSR 0x7022 1 System Control & Status Register Figure 3-15 WDCNTR 0x7023 1 Watchdog Counter Register. Figure 3-16 WDKEY 0x7025 1 Watchdog Reset Key Register Figure 3-17 WDCR 0x7029 1 Watchdog Control Register Figure 3-18 (1) All of the registers in this table are EALLOW protected. See Section 5.2 for more information. (2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to a known state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic have no effect. The PCLKCR0/1/3 registers enable/disable clocks to the various peripheral modules. There is a 2-SYSCLKOUT cycle delay from when a write to the PCLKCR0/1/3 registers occurs to when the action is valid. This delay must be taken into account before attempting to access the peripheral configuration registers. Due to the peripheral-GPIO MUXing, all peripherals cannot be used at the same time. While it is possible to turn on the clocks to all the peripherals at the same time, such a configuration is not useful. If this is done, the current drawn will be more than required. To avoid this, only enable the clocks required by the application. Figure 3-2. Peripheral Clock Control 0 Register (PCLKCR0) 15 14 13 12 11 10 9 8 ECANBENCLK ECANAENCLK MCBSPBENCLK MCBSPAENCLK SCIBENCLK SCIAENCLK Reserved SPIAENCLK R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 7 6 5 4 3 2 1 0 Reserved SCICENCLK I2CAENCLK ADCENCLK TBCLKSYNC Reserved R-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-2. Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions Bit Field Valu Description (1) e 15 ECANBENCLK ECAN-B Clock enable 0 The eCAN-B module is not clocked. (default) (2) 1 The eCAN-B module is clocked (SYSCLKOUT/2). 14 ECANAENCLK ECAN-A clock enable 0 The eCAN-A module is not clocked. (default) (2) 1 The eCAN-A module is clocked (SYSCLKOUT/2). 13 MCBSPBENCLK McBSP-B Clock Enable. This bit is reserved on devices without the McBSP-B module.(3) 0 The McBSP-B module is not clocked. (default) 1 The McBSP-B module is clocked by the low-speed clock (LSPCLK). (1) This register is EALLOW protected. See Section 5.2 for more information. (2) If a peripheral block is not used, the clock to that peripheral can be turned off to minimize power consumption. (3) On devices without a particular peripheral, the clock selection bit is reserved. On these devices, the bit should not be written to with a 1. SPRUFB0C–September 2007–Revised May 2009 Clocking 39 Submit Documentation Feedback

www.ti.com Table 3-2. Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions (continued) Bit Field Valu Description (1) e 12 MCBSPAENCLK McBSP-A Clock Enable 0 The McBSP-A module is not clocked. (default) 1 The McBSP-A module is clocked by the low-speed clock (LSPCLK). 11 SCIBENCLK SCI-B clock enable 0 SCI-B module is not clocked. (default) (2) 1 The SCI-B module is clocked by the low-speed clock (LSPCLK). 10 SCIAENCLK SCI-A clock enable 0 The SCI-A module is not clocked. (default) (2) 1 The SCI-A module is clocked by the low-speed clock (LSPCLK). 9 Reserved 0 Reserved 8 SPIAENCLK SPI-A clock enable 0 The SPI-A module is not clocked. (default) (2) 1 The SPI-A module is clocked by the low-speed clock (LSPCLK). 7:6 Reserved 0 Reserved 5 SCICENCLK SCI-C clock enable. This bit is reserved on devices without the SCI-C module.(3) 0 The SCI-C module is not clocked. (default) 1 The SCI-C module is clocked by the low-speed clock (LSPCLK). 4 I2CAENCLK I2C clock enable 0 The I2C module is not clocked. (default) (2) 1 The I2C module is clocked by SYSCLKOUT. 3 ADCENCLK ADC clock enable 0 The ADC is not clocked. (default) (2) 1 The ADC module is clocked by the high-speed clock (HSPCLK) 2 TBCLKSYNC ePWM Module Time Base Clock (TBCLK) Sync: Allows the user to globally synchronize all enabled ePWM modules to the time base clock (TBCLK): 0 The TBCLK (Time Base Clock) within each enabled ePWM module is stopped. (default). If, however, the ePWM clock enable bit is set in the PCLKCR1 register, then the ePWM module will still be clocked by SYSCLKOUT even if TBCLKSYNC is 0. 1 All enabled ePWM module clocks are started with the first rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The proper procedure for enabling ePWM clocks is as follows: • Enable ePWM module clocks in the PCLKCR1 register. • Set TBCLKSYNC to 0. • Configure prescaler values and ePWM modes. • Set TBCLKSYNC to 1. 1-0 Reserved Reserved Figure 3-3. Peripheral Clock Control 1 Register (PCLKCR1) 15 14 13 12 11 10 9 8 EQEP2ENCLK EQEP1ENCLK ECAP6ENCLK ECAP5ENCLK ECAP4ENCLK ECAP3ENCLK ECAP2ENCLK ECAP1ENCLK R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 Reserved EPWM6ENCLK EPWM5ENCLK EPWM4ENCLK EPWM3ENCLK EPWM2ENCLK EPWM1ENCLK R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Clocking 40 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 3-3. Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions Bits Field Value Description (1) 15 EQEP2ENCLK eQEP2 clock enable 0 The eQEP2 module is not clocked. (default) (2) 1 The eQEP2 module is clocked by the system clock (SYSCLKOUT). 14 EQEP1ENCLK eQEP1 clock enable 0 The eQEP1 module is not clocked. (default) (2) 1 The eQEP1 module is clocked by the system clock (SYSCLKOUT). 14 EQEP1ENCLK eQEP1 clock enable 0 The eQEP1 module is not clocked. (default) (2) 1 The eQEP1 module is clocked by the system clock (SYSCLKOUT). 13-9 Reserved 13 ECAP6ENCLK eCAP6 clock enable. This bit is reserved on devices without the eCAP6 module. 0 The eCAP6 module is not clocked. (default) 1 The eCAP6 module is clocked by the system clock (SYSCLKOUT). 12 ECAP5ENCLK eCAP5 clock enable. This bit is reserved on devices without the eCAP5 module. 0 The eCAP5 module is not clocked. (default) 1 The eCAP5 module is clocked by the system clock (SYSCLKOUT). 11 ECAP4ENCLK eCAP4 clock enable 0 The eCAP4 module is not clocked. (default) (2) 1 The eCAP4 module is clocked by the system clock (SYSCLKOUT). 10 ECAP3ENCLK eCAP3 clock enable 0 The eCAP3 module is not clocked. (default) (2) 1 The eCAP3 module is clocked by the system clock (SYSCLKOUT). 9 ECAP2ENCLK eCAP2 clock enable 0 The eCAP2 module is not clocked. (default) (2) 1 The eCAP2 module is clocked by the system clock (SYSCLKOUT). 8 ECAP1ENCLK eCAP1 clock enable 0 The eCAP1 module is not clocked. (default) (2) 1 The eCAP1 module is clocked by the system clock (SYSCLKOUT). 7:6 Reserved 0 Reserved 5 EPWM6ENCLK ePWM6 clock enable (3) 0 The ePWM6 module is not clocked. (default) (2) 1 The ePWM6 module is clocked by the system clock (SYSCLKOUT). 4 EPWM5ENCLK ePWM5 clock enable (3) 0 The ePWM5 module is not clocked. (default) (2) 1 The ePWM5 module is clocked by the system clock (SYSCLKOUT). 3 EPWM4ENCLK ePWM4 clock enable. (3) 0 The ePWM4 module is not clocked. (default) (2) 1 The ePWM4 module is clocked by the system clock (SYSCLKOUT). 2 EPWM3ENCLK ePWM3 clock enable. (3) 0 The ePWM3 module is not clocked. (default) (2) 1 The ePWM3 module is clocked by the system clock (SYSCLKOUT). 1 EPWM2ENCLK ePWM2 clock enable. (3) 0 The ePWM2 module is not clocked. (default) (2) 1 The ePWM2 module is clocked by the system clock (SYSCLKOUT). (1) This register is EALLOW protected. See Section 5.2 for more information. (2) If a peripheral block is not used, the clock to that peripheral can be turned off to minimize power consumption. (3) To start the ePWM Time-base clock (TBCLK) within the ePWM modules, the TBCLKSYNC bit in PCLKCR0 must also be set. SPRUFB0C–September 2007–Revised May 2009 Clocking 41 Submit Documentation Feedback

www.ti.com Table 3-3. Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions (continued) Bits Field Value Description (1) 0 EPWM1ENCLK ePWM1 clock enable. (3) 0 The ePWM1 module is not clocked. (default) (2) 1 The ePWM1 module is clocked by the system clock (SYSCLKOUT). Clocking 42 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Figure 3-4. Peripheral Clock Control 3 Register (PCLKCR3) 15 14 13 12 11 10 9 8 Reserved GPIOINENCLK XINTFENCLK DMAENCLK CPUTIMER2ENCLK CPUTIMER1ENCLK CPUTIMER0ENCLK R-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 7 0 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-4. Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions Bit Field Value Description 15:`14 Reserved Reserved 13 GPIOINENCLK GPIO Input Clock Enable 0 The GPIO module is not clocked. 1 The GPIO module is clocked. 12 XINTFENCLK External Interface (XINTF) Clock Enable 0 The external memory interface is not clocked. 1 The external memory interface is clocked. 11 DMAENCLK DMA Clock Enable 0 The DMA module is not clocked. 1 The DMA module is clocked. 10 CPUTIMER2ENCLK CPU Timer 2 Clock Enable 0 The CPU Timer 2 is not clocked. 1 The CPU Timer 2 is clocked. 9 CPUTIMER1ENCLK CPU Timer 1 Clock Enable 0 The CPU Timer 1 is not clocked. 1 The CPU Timer 1 is clocked. 8 CPUTIMER0ENCLK CPU Timer 0 Clock Enable 0 The CPU Timer 0 is not clocked. 1 The CPU Timer 0 is clocked. 7:0 Reserved Reserved The high speed peripheral and low speed peripheral clock prescale (HISPCP and LOSPCP) registers are used to configure the high- and low-speed peripheral clocks, respectively. See Figure 3-5 for the HISPCP bit layout and Figure 3-6 for the LOSPCP layout. SPRUFB0C–September 2007–Revised May 2009 Clocking 43 Submit Documentation Feedback

www.ti.com Figure 3-5. High-Speed Peripheral Clock Prescaler (HISPCP) Register 15 3 2 0 Reserved HSPCLK R-0 R/W-001 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-5. High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions Bits Field Value Description (1) 15-3 Reserved Reserved 2-0 HSPCLK These bits configure the high-speed peripheral clock (HSPCLK) rate relative to SYSCLKOUT: If HISPCP(2) ≠ 0, HSPCLK = SYSCLKOUT/(HISPCP X 2) If HISPCP = 0, HSPCLK = SYSCLKOUT 000 High speed clock = SYSCLKOUT/1 001 High speed clock = SYSCLKOUT/2 (reset default) 010 High speed clock = SYSCLKOUT/4 011 High speed clock = SYSCLKOUT/6 100 High speed clock = SYSCLKOUT/8 101 High speed clock = SYSCLKOUT/10 110 High speed clock = SYSCLKOUT/12 111 High speed clock = SYSCLKOUT/14 (1) This register is EALLOW protected. See Section 5.2 for more information. (2) HISPCP in this equation denotes the value of bits 2:0 in the HISPCP register. Figure 3-6. Low-Speed Peripheral Clock Prescaler Register (LOSPCP) 15 3 2 0 Reserved LSPCLK R-0 R/W-010 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-6. Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions Bits Field Value Description (1) 15-3 Reserved Reserved 2-0 LSPCLK These bits configure the low-speed peripheral clock (LSPCLK) rate relative to SYSCLKOUT: If LOSPCP(2) ≠ 0, then LSPCLK = SYSCLKOUT/(LOSPCP X 2) If LOSPCP = 0, then LSPCLK = SYSCLKOUT 000 Low speed clock = SYSCLKOUT/1 001 Low speed clock= SYSCLKOUT/2 010 Low speed clock= SYSCLKOUT/4 (reset default) 011 Low speed clock= SYSCLKOUT/6 100 Low speed clock= SYSCLKOUT/8 101 Low speed clock= SYSCLKOUT/10 110 Low speed clock= SYSCLKOUT/12 111 Low speed clock= SYSCLKOUT/14 (1) This register is EALLOW protected. See Section 5.2 for more information. (2) LOSPCP in this equation denotes the value of bits 2:0 in the LOSPCP register. Clocking 44 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

3.2.1 PLL-Based Clock Module X1 XCLKIN (3.3-V�clock�input from�external oscillator) On-chip oscillator X2 PLLSTS[OSCOFF] OSCCLK PLL VCOCLK 4-bit�Multiplier�PLLCR[DIV] OSCCLK�or VCOCLK CLKIN OSCCLK 0 PLLSTS[PLLOFF] n n ≠ 0 PLLSTS[DIVSEL] /1 /2 /4 External Crystal�or Resonator To CPU www.ti.com OSC and PLL Block The on-chip oscillator and phase-locked loop (PLL) block provides the clocking signals for the device, as well as control for low-power mode (LPM) entry. The 2833x, 2823x devices have an on-chip, PLL-based clock module. The PLL has a 4-bit ratio control to select different CPU clock rates. Figure 3-7 shows the OSC and PLL block. Figure 3-7. OSC and PLL Block The PLL-based clock module provides two modes of operation: • Crystal/Resonator Operation: The on-chip oscillator enables the use of an external crystal/resonator to be attached to the device to provide the time base to the device. The crystal/resonator is connected to the X1/X2 pins and XCLKIN is tied low. • External clock source operation: If the on-chip oscillator is not used, this mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on either the X1 or the XCLKIN pin. Option 1: External clock on the XCLKIN pin: When using XCLKIN as the external clock source, you must tie X1 low and leave X2 disconnected. In this case, an external oscillator clock is connected to the XCLKIN pin, which allows for a 3.3-V clock source to be used. Option 2: External clock on the X1 pin: When using X1 as the clock source, you must tie XCLKIN low and leave X2 disconnected. In this case, an external oscillator clock is connected to the X1 pin, which allows for a 1.8-V clock source to be used. The OSC circuit enables attachment of a crystal using the X1 and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the XCLKIN pin, the X2 pin is left unconnected, and the X1 pin is tied low. See the TMS320F28335, TMS320F28334, TMS28332, TMS320F28235, TMS320F28234, TMS28232 Digital Signal Controllers (DSCs) Data Manual (literature number SPRS439). The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) does not exceed 300 MHz. SPRUFB0C–September 2007–Revised May 2009 Clocking 45 Submit Documentation Feedback

VCOCLK counter (13�bits) Clear Res Clear OSCCLK Clear (7�bits) counter Res Clear Ovf Clk XRS PLL Clk Ovf Off Clear OSCCLK Clock switch logic VCOCLK C28x CPU Missing clock reset PLLCLK /1, /2 or /4 PLLSTS reg PLLCR reg C28x CPU OSC and PLL Block www.ti.com Table 3-7. Possible PLL Configuration Modes PLL Mode Remarks PLLSTS[DIVSEL](1) SYSCLKOUT PLL Off Invoked by the user setting the PLLOFF bit in the PLLSTS register. The 0, 1 OSCCLK/4 PLL block is disabled in this mode. This can be useful to reduce system 2 OSCCLK/2 noise and for low power operation. The PLLCR register must first be set 3 OSCCLK/1 to 0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is derived directly from the input clock on either X1/X2, X1 or XCLKIN. PLL Bypass PLL Bypass is the default PLL configuration upon power-up or after an 0, 1 OSCCLK/4 external reset (XRS). This mode is selected when the PLLCR register is 2 OSCCLK/2 set to 0x0000 or while the PLL locks to a new frequency after the 3 OSCCLK/1 PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. PLL Enabled Achieved by writing a non-zero value n into the PLLCR register. Upon 0, 1 OSCCLK*n/4 writing to the PLLCR, the device will switch to PLL Bypass mode until 2 OSCCLK*n/2 the PLL locks. (1) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. See Figure 3-10. Due to vibrations, it is possible for the external clock source to the DSP to become detached and fail to clock the device. When the PLL is not disabled, the main oscillator fail logic allows the device to detect this condition and default to a known state as described in this section. Two counters are used to monitor the presence of the OSCCLK signal as shown in Figure 3-8. The first counter is incremented by the OSCCLK signal itself either from the X1/X2 or XCLKIN input. When the PLL is not turned off, the second counter is incremented by the VCOCLK coming out of the PLL block. These counters are configured such that when the 7-bit OSCCLK counter overflows, it clears the 13-bit VCOCLK counter. In normal operating mode, as long as OSCCLK is present, the VCOCLK counter will never overflow. Figure 3-8. Oscillator Fail-Detection Logic Diagram 46 Clocking SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

If the OSCCLK input signal is missing, then the PLL will output a default "limp mode" frequency and the VCOCLK counter will continue to increment. Since the OSCCLK signal is missing, the OSCCLK counter will not increment and, therefore, the VCOCLK counter is not periodically cleared. Eventually, the VCOCLK counter overflows and, if required, the device switches the CLKIN input to the CPU to the limp mode output frequency of the PLL. When the VCOCLK counter overflows, the missing clock detection logic resets the CPU, peripherals, and other device logic. The reset generated is known as a missing clock detect logic reset (MCLKRES). The MCLKRES is an internal reset only. The external XRS pin of the device is not pulled low by MCLKRES and the PLLCR and PLLSTS registers are not reset. In addition to resetting the device, the missing oscillator logic sets the PLLSTS[MCLKSTS] register bit. When the MCLKCSTS bit is 1, this indicates that the missing oscillator detect logic reset the part and that the CPU is now running either at or one-half of the limp mode frequency. Software should check the PLLSTS[MCLKSTS] bit after a reset to determine if the device was reset by MCLKRES due to a missing clock condition. If MCLKSTS is set, then the firmware should take the action appropriate for the system such as a system shutdown. The missing clock status can be cleared by writing a 1 to the PLLSTS[MCLKCLR] bit. This will reset the missing clock detection circuits and counters. If OSCCLK is still missing after writing to the MCLKCLR bit, then the VCOCLK counter again overflows and the process will repeat. Note: Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the DSP will be held in reset should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory and the VDD3VFL rail. The following precautions and limitations should be kept in mind: • Use the proper procedure when changing the PLL Control Register. Always follow the procedure outlined in Figure 3-10 when modifying the PLLCR register. • Do not write to the PLLCR register when the device is operating in limp mode. When writing to the PLLCR register, the device switches to the CPU's CLKIN input to OSCCLK/2. When operating after limp mode has been detected, OSCCLK may not be present and the clocks to the system will stop. Always check that the PLLSTS[MCLKSTS] bit = 0 before writing to the PLLCR register as described in Figure 3-10. • The watchdog is not functional without an external clock. The watchdog is not functional and cannot generate a reset when OSCCLK is not present. No special hardware has been added to switch the watchdog to the limp mode clock should OSCCLK become missing. • Limp mode may not work from power up. The PLL may not generate a limp mode clock if OSCCLK is missing from power-up. Only if OSCCLK is initially present will a limp mode clock be generated by the PLL. • Do not enter HALT low power mode when the device is operating in limp mode. If you try to enter HALT mode when the device is already operating in limp mode then the device may not properly enter HALT. The device may instead enter STANDBY mode or may hang and you may not be able to exit HALT mode. For this reason, always check that the PLLSTS[MCLKSTS] bit = 0 before entering HALT mode. SPRUFB0C–September 2007–Revised May 2009 Clocking 47 Submit Documentation Feedback

www.ti.com The following list describes the behavior of the missing clock detect logic in various operating modes: • PLL by-pass mode When the PLL control register is set to 0x0000, the PLL is by-passed. Depending on the state of the PLLSTS[DIVSEL] bit, OSCCLK, OSCCLK/2, or OSCCLK/4 is connected directly to the CPU's input clock, CLKIN. If the OSCCLK is detected as missing, the device will automatically switch to the PLL, set the missing clock detect status bit, and generate a missing clock reset. The device will now run at the PLL limp mode frequency or one-half of the PLL limp mode frequency. • PLL enabled mode When the PLL control register is non-zero (PLLCR = n, where n ≠ 0x0000), the PLL is enabled. In this mode, OSCCLK*n, OSCCLK*n/2, or OSCCLK*n/4 is connected to CLKIN of the CPU. If OSCCLK is detected as missing, the missing clock detect status bit will be set and the device will generate a missing clock reset. The device will now run at one-half of the PLL limp mode frequency. • STANDBY low power mode In this mode, the CLKIN to the CPU is stopped. If a missing input clock is detected, the missing clock status bit will be set and the device will generate a missing clock reset. If the PLL is in by-pass mode when this occurs, then one-half of the PLL limp frequency will automatically be routed to the CPU. The device will now run at the PLL limp mode frequency or at one-half or one-fourth of the PLL limp mode frequency, depending on the state of the PLLSTS[DIVSEL] bit. • HALT low power mode In HALT low power mode, all of the clocks to the device are turned off. When the device comes out of HALT mode, the oscillator and PLL will power up. The counters that are used to detect a missing input clock (VCOCLK and OSCCLK) will be enabled only after this power-up has completed. If VCOCLK counter overflows, the missing clock detect status bit will be set and the device will generate a missing clock reset. If the PLL is in by-pass mode when the overflow occurs, then one-half of the PLL limp frequency will automatically be routed to the CPU. The device will now run at the PLL limp mode frequency or at one-half or one-fourth of the PLL limp mode frequency depending on the state of the PLLSTS[DIVSEL] bit. The XCLKOUT signal is directly derived from the system clock SYSCLKOUT as shown in Figure 3-9. XCLKOUT can be either equal to, one-half, or one-fourth of SYSCLKOUT. By default, at power-up, XCLKOUT = SYSCLKOUT/4 or XCLKOUT = OSCCLK/16. Figure 3-9. XCLKOUT Generation The XCLKOUT signal is active when reset is active. Since XCLKOUT should reflect SYSCLKOUT/4 when reset is low, you can monitor this signal to detect if the device is being properly clocked during debug. There is no internal pullup or pulldown on the XCLKOUT pin. If XCLKOUT is not being used, it can be turned off by setting the CLKOFF bit to 1 in the XINTCNF2 register. Clocking 48 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

www.ti.com OSC and PLL Block The PLLCR register is used to change the PLL multiplier of the device. Before writing to the PLLCR register, the following requirements must be met: • The PLLSTS[DIVSEL] bit must be 0 (CLKIN divide by 4 enabled). Change PLLSTS[DIVSEL] to 1 only after the PLL has completed locking, i.e., after PLLSTS[PLLLOCKS] = 1. • The device must not be operating in "limp mode". That is, the PLLSTS[MCLKSTS] bit must be 0. When the CPU writes to the PLLCR[DIV] bits, the PLL logic switches the CPU clock (CLKIN) to OSCCLK/2. Once the PLL is stable and has locked at the new specified frequency, the PLL switches CLKIN to the new value as shown in Table 3-8. When this happens, the PLLLOCKS bit in the PLLSTS register is set, indicating that the PLL has finished locking and the device is now running at the new frequency. User software can monitor the PLLLOCKS bit to determine when the PLL has completed locking. Once PLLSTS[PLLLOCKS] = 1, DIVSEL can be changed. Follow the procedure in Figure 3-10 any time you are writing to the PLLCR register. SPRUFB0C–September 2007–Revised May 2009 Clocking 49 Submit Documentation Feedback

www.ti.com Figure 3-10. PLLCR Change Procedure Flow Chart 50 Clocking SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

www.ti.com OSC and PLL Block The DIV field in the PLLCR register controls whether the PLL is bypassed or not and sets the PLL clocking ratio when it is not bypassed. PLL bypass is the default mode after reset. Do not write to the DIV field if the PLLSTS[DIVSEL] bit is 10 or 01, or if the PLL is operating in limp mode as indicated by the PLLSTS[MCLKSTS] bit being set. See the procedure for changing the PLLCR described in Figure 3-10. Figure 3-11. PLLCR Register Layout 15 4 3 0 Reserved DIV R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-8. PLLCR Bit Descriptions(1) SYSCLKOUT (CLKIN)(2) PLLCR[DIV] Value(3) PLLSTS[DIVSEL] = 0 or 1 PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3 0000 (PLL bypass) OSCCLK/4 (Default) OSCCLK/2 OSCCLK 0001 (OSCCLK * 1)/4 (OSCCLK*1)/2 – 0010 (OSCCLK * 2)/4 (OSCCLK*2)/2 – 0011 (OSCCLK * 3)/4 (OSCCLK*3)/2 – 0100 (OSCCLK * 4)/4 (OSCCLK*4)/2 – 0101 (OSCCLK * 5)/4 (OSCCLK*5)/2 – 0110 (OSCCLK * 6)/4 (OSCCLK*6)/2 – 0111 (OSCCLK * 7)/4 (OSCCLK*7)/2 – 1000 (OSCCLK * 8)/4 (OSCCLK*8)/2 – 1001 (OSCCLK * 9)/4 (OSCCLK*9)/2 – 1010 (OSCCLK * 10)/4 (OSCCLK*10)/2 – 1011 - 1111 Reserved Reserved Reserved (1) This register is EALLOW protected. See Section 5.2 for more information. (2) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. See Figure 3-10. (3) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic have no effect. Figure 3-12. PLL Status Register (PLLSTS) 15 9 8 Reserved DIVSEL R-0 R/W-0 7 6 5 4 3 2 1 0 DIVSEL MCLKOFF OSCOFF MCLKCLR MCLKSTS PLLOFF Reserved PLLLOCKS R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R-0 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-9. PLL Status Register (PLLSTS) Field Descriptions Bits Field Value Description (1)(2) 15-9 Reserved Reserved 8:7 DIVSEL Divide Select: This bit selects between /4, /2, and /1 for CLKIN to the CPU. The configuration of the DIVSEL bit is as follows: (1) This register is reset to its default state only by the XRS signal or a watchdog reset. It is not reset by a missing clock or debugger reset. (2) This register is EALLOW protected. See Section 5.2 for more information. SPRUFB0C–September 2007–Revised May 2009 Clocking 51 Submit Documentation Feedback

OSC and PLL Block www.ti.com Table 3-9. PLL Status Register (PLLSTS) Field Descriptions (continued) Bits Field Value Description (1)(2) 00 Select Divide By 8 for CLKIN 00, 01 Select Divide By 4 for CLKIN 10 Select Divide By 2 for CLKIN 11 Select Divide By 1 for CLKIN. (This mode can be used only when PLL is off or bypassed.) 6 MCLKOFF Missing clock-detect off bit 0 Main oscillator fail-detect logic is enabled. (default) 1 Main oscillator fail-detect logic is disabled and the PLL will not issue a limp-mode clock. Use this mode when code must not be affected by the detection circuit. For example, if external clocks are turned off. 5 OSCOFF Oscillator Clock Off Bit 0 The OSCCLK signal from X1, X1/X2 or XCLKIN is fed to the PLL block. (default) 1 The OSCCLK signal from X1, X1/X2 or XCLKIN is not fed to the PLL block. This does not shut down the internal oscillator. The OSCOFF bit is used for testing the missing clock detection logic. When the OSCOFF bit is set, do not enter HALT or STANDBY modes or write to PLLCR as these operations can result in unpredictable behavior. When the OSCOFF bit is set, the behavior of the watchdog is different depending on which input clock source (X1, X1/X2 or XCLKIN) is being used: • X1 or X1/X2: The watchdog is not functional. • XCLKIN: The watchdog is functional and should be disabled before setting OSCOFF. 4 MCLKCLR Missing Clock Clear Bit. 0 Writing a 0 has no effect. This bit always reads 0. 1 Forces the missing clock detection circuits to be cleared and reset. If OSCCLK is still missing, the detection circuit will again generate a reset to the system, set the missing clock status bit (MCLKSTS), and the CPU will be powered by the PLL operating at a "limp mode" frequency. 3 MCLKSTS Missing Clock Status Bit. Check the status of this bit after a reset to determine whether a missing oscillator condition was detected. Under normal conditions, this bit should be 0. Writes to this bit are ignored. This bit will be cleared by writing to the MCLKCLR bit or by forcing an external reset. 0 Indicates normal operation. A missing clock condition has not been detected. 1 Indicates that OSCCLK was detected as missing. The main oscillator fail detect logic has reset the device and the CPU is now clocked by the PLL operating at the limp mode frequency. 2 PLLOFF PLL Off Bit. This bit turns off the PLL. This is useful for system noise testing. This mode must only be used when the PLLCR register is set to 0x0000. 0 PLL On (default) 1 PLL Off. While the PLLOFF bit is set the PLL module will be kept powered down. The device must be in PLL bypass mode (PLLCR = 0x0000) before writing a 1 to PLLOFF. While the PLL is turned off (PLLOFF = 1), do not write a non-zero value to the PLLCR. The STANDBY and HALT low power modes will work as expected when PLLOFF = 1. After waking up from HALT or STANDBY the PLL module will remain powered down. 1 Reserved Reserved 0 PLLLOCKS PLL Lock Status Bit. 0 Indicates that the PLLCR register has been written to and the PLL is currently locking. The CPU is clocked by OSCCLK/2 until the PLL locks. 1 Indicates that the PLL has finished locking and is now stable. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values to provide proper start-up and stability over the entire operating range. Clocking 52 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

www.ti.com Low-Power Modes Block Table 3-10 summarizes the various modes. The various low-power modes operate as shown in Table 3-11. See the TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 Digital Signal Controllers (DSCs) Data Manual (literature number SPRS439) for exact timing for entering and exiting the low power modes. Table 3-10. Low-Power Mode Summary Mode LPMCR0[1:0] OSCCLK CLKIN SYSCLKOUT Exit(1) IDLE 00 On On On(2) XRS, Watchdog interrupt, Any enabled interrupt STANDBY 01 On Off Off XRS, (watchdog still running) Watchdog interrupt, GPIO Port A signal, Debugger(3) HALT 1X Off Off Off XRS, (oscillator and PLL turned off, GPIO Port A Signal, watchdog not functional) Debugger(3) (1) The Exit column lists which signals or under what conditions the low power mode is exited. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode is not exited and the device goes back into the indicated low power mode. (2) The IDLE mode on the 28x behaves differently than on the 24x/240x. On the 28x, the clock output from the CPU (SYSCLKOUT) is still functional while on the 24x/240x the clock is turned off. (3) On the 28x, the JTAG port can still function even if the clock to the CPU (CLKIN) is turned off. Table 3-11. Low Power Modes Mode Description IDLE This mode is exited by any enabled interrupt or an NMI. The LPM block itself performs no tasks during this Mode: mode. STANDBY If the LPM bits in the LPMCR0 register are set to 01, the device enters STANDBY mode when the IDLE Mode: instruction is executed. In STANDBY mode the clock input to the CPU (CLKIN) is disabled, which disables all clocks derived from SYSCLKOUT. The oscillator and PLL and watchdog will still function. Before entering the STANDBY mode, you should perform the following tasks: • Enable the WAKEINT interrupt in the PIE module. This interrupt is connected to both the watchdog and the low power mode module interrupt. • If desired, specify one of the GPIO port A signals to wake the device in the GPIOLPMSEL register. The GPIOLPMSEL register is part of the GPIO module. In addition to the selected GPIO signal, the XRS input and the watchdog interrupt, if enabled in the LPMCR0 register, can wake the device from the STANDBY mode. • Select the input qualification in the LPMCR0 register for the signal that will wake the device. When the selected external signal goes low, it must remain low a number of OSCCLK cycles as specified by the qualification period in the LPMCR0 register. If the signal should be sampled high during this time, the qualification will restart. At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt is latched in the PIE block. The CPU then responds to the WAKEINT interrupt if it is enabled. SPRUFB0C–September 2007–Revised May 2009 Clocking 53 Submit Documentation Feedback

www.ti.com Table 3-11. Low Power Modes (continued) Mode Description HALT If the LPM bits in the LPMCR0 register are set to 1x, the device enters the HALT mode when the IDLE Mode: instruction is executed. In HALT mode all of the device clocks, including the PLL and oscillator, are shut down. Before entering the HALT mode, you should perform the following tasks: • Enable the WAKEINT interrupt in the PIE module (PIEIER1.8 = 1). This interrupt is connected to both the watchdog and the Low-Power-Mode module interrupt. • Specify one of the GPIO port A signals to wake the device in the GPIOLPMSEL register. The GPIOLPMSEL register is part of the GPIO module. In addition to the selected GPIO signal, the XRS input can also wake the device from the HALT mode • Disable all interrupts with the possible exception of the HALT mode wakeup interrupt. The interrupts can be re-enabled after the device is brought out of HALT mode. • For device to exit HALT mode properly, the following conditions must be met: Bit 7 (INT1.8) of PIEIER1 register should be 1. Bit 0 (INT1) of IER register must be 1. • If the above conditions are met, – WAKE_INT ISR will be executed first, followed by the instruction(s) after IDLE, if INTM = 0. – WAKE_INT ISR will not be executed and instruction(s) after IDLE will be executed, if INTM = 1. Do not enter HALT low power mode when the device is operating in limp mode (PLLSTS[MCLKSTS] = 1). If you try to enter HALT mode when the device is already operating in limp mode then the device may not properly enter HALT. The device may instead enter STANDBY mode or may hang and you may not be able to exit HALT mode. For this reason, always check that the PLLSTS[MCLKSTS] bit = 0 before entering HALT mode. When the selected external signal goes low, it is fed asynchronously to the LPM block. The oscillator is turned on and begins to power up. You must hold the signal low long enough for the oscillator to complete power up. Once the oscillator has stabilized, the PLL lock sequence is initiated. Once the PLL has locked, it feeds the CLKIN to the CPU at which time the CPU responds to the WAKEINT interrupt if enabled. The low-power modes are controlled by the LPMCR0 register (Figure 3-13). Figure 3-13. Low Power Mode Control 0 Register (LPMCR0) 15 14 8 7 2 1 0 WDINTE Reserved QUALSTDBY LPM R/W-0 R-0 R/W-1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-12. Low Power Mode Control 0 Register (LPMCR0) Field Descriptions Bits Field Value Description (1) 15 WDINTE Watchdog interrupt enable 0 The watchdog interrupt is not allowed to wake the device from STANDBY. (default) The watchdog is allowed to wake the device from STANDBY. The watchdog interrupt must also 1 be enabled in the SCSR Register. 14-8 Reserved Reserved 7-2 QUALSTDBY Select number of OSCCLK clock cycles to qualify the selected GPIO inputs that wake the device from STANDBY mode. This qualification is only used when in STANDBY mode. The GPIO signals that can wake the device from STANDBY are specified in the GPIOLPMSEL register. 000000 2 OSCCLKs (default) 000001 3 OSCCLKs . . . . . . 111111 65 OSCCLKs (1) This register is EALLOW protected. See Section 5.2 for more information. Clocking 54 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Key Detector XRS Core-reset WDRST(A) Internal Pullup www.ti.com Watchdog Block Table 3-12. Low Power Mode Control 0 Register (LPMCR0) Field Descriptions (continued) Bits Field Value Description (1) 1-0 LPM(2) These bits set the low power mode for the device. 00 Set the low power mode to IDLE (default) 01 Set the low power mode to STANDBY 10 Set the low power mode to HALT (3) 11 Set the low power mode to HALT (3) (2) The low power mode bits (LPM) only take effect when the IDLE instruction is executed. Therefore, you must set the LPM bits to the appropriate mode before executing the IDLE instruction. (3) If you try to enter HALT mode when the device is already operating in limp mode then the device may not properly enter HALT. The device may instead enter STANDBY mode or may hang and you may not be able to exit HALT mode. For this reason, always check that the PLLSTS[MCLKSTS] bit = 0 before entering HALT mode. The watchdog module generates an output pulse, 512 oscillator-clocks (OSCCLK) wide whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user can either disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which resets the watchdog counter. Figure 3-14 shows the various functional blocks within the watchdog module. Figure 3-14. Watchdog Module A The WDRST and XRS signals are driven low for 512 OSCCLK cycles when a watchdog reset occurs. Likewise, if the watchdog interrupt is enabled, the WDINT signal will be driven low for 512 OSCCLK cycles when an interrupt occurs. Watchdog is not functional and cannot generate a reset when OSCCLK is not present. SPRUFB0C–September 2007–Revised May 2009 Clocking 55 Submit Documentation Feedback

3.4.2 Watchdog Reset or Watchdog Interrupt Mode Watchdog Block www.ti.com The WDCNTR is reset when the proper sequence is written to the WDKEY register before the 8-bit watchdog counter (WDCNTR) overflows. The WDCNTR is reset-enabled when a value of 0x55 is written to the WDKEY. When the next value written to the WDKEY register is 0xAA then the WDCNTR is reset. Any value written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55 and 0xAA values can be written to the WDKEY without causing a system reset; only a write of 0x55 followed by a write of 0xAA to the WDKEY resets the WDCNTR. Table 3-13. Example Watchdog Key Sequences Step Value Written to WDKEY Result 1 0xAA No action 2 0xAA No action 3 0x55 WDCNTR is enabled to be reset if next value is 0xAA. 4 0x55 WDCNTR is enabled to be reset if next value is 0xAA. 5 0x55 WDCNTR is enabled to be reset if next value is 0xAA. 6 0xAA WDCNTR is reset. 7 0xAA No action 8 0x55 WDCNTR is enabled to be reset if next value is 0xAA. 9 0xAA WDCNTR is reset. 10 0x55 WDCNTR is enabled to be reset if next value is 0xAA. 11 0x32 Improper value written to WDKEY. No action, WDCNTR no longer enabled to be reset by next 0xAA. 12 0xAA No action due to previous invalid value. 13 0x55 WDCNTR is enabled to be reset if next value is 0xAA. 14 0xAA WDCNTR is reset. Step 3 in Table 3-13 is the first action that enables the WDCNTR to be reset. The WDCNTR is not actually reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR. Step 10 again re-enables the WDCNTR ro be reset. Writing the wrong key value to the WDKEY in step 11 causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now has no effect. If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to the WDCR[WDCHK] bits will reset the device and set the watchdog flag (WDFLAG) in the WDCR register. After a reset, the program can read the state of this flag to determine the source of the reset. After reset, the WDFLAG should be cleared by software to allow the source of subsequent resets to be determined. Watchdog resets are not prevented when the flag is set. The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an interrupt (WDINT) if the watchdog counter reaches its maximum value. The behavior of each condition is described below: • Reset mode: If the watchdog is configured to reset the device, then the WDRST signal will pull the device reset (XRS) pin low for 512 OSCCLK cycles when the watchdog counter reaches its maximum value. • Interrupt mode: If the watchdog is configured to assert an interrupt, then the WDINT signal will be driven low for 512 OSCCLK cycles, causing the WAKEINT interrupt in the PIE to be taken if it is enabled in the PIE module. The watchdog interrupt is edge triggered on the falling edge of WDINT. Thus, if the WAKEINT interrupt is re-enabled before WDINT goes inactive, you will not immediately get another interrupt. The next WAKEINT interrupt will occur at the next watchdog timeout. If the watchdog is re-configured from interrupt mode to reset mode while WDINT is still active low, then the device will reset immediately. The WDINTS bit in the SCSR register can be read to determine the current state of the WDINT signal before reconfiguring the watchdog to reset mode. Clocking 56 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

3.4.4 Emulation Considerations www.ti.com Watchdog Block In STANDBY mode, all of the clocks to the peripherals are turned off on the device. The only peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock (OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM) block so that it can be used to wake the device from STANDBY low power mode (if enabled). See the Low Power Modes Block section of the device data manual for details. In IDLE mode, the watchdog interrupt (WDINT) signal can generate an interrupt to the CPU to take the CPU out of IDLE mode. The watchdog is connected to the WAKEINT interrupt in the PIE. Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low power mode condition, then make sure that the WDINT signal goes back high again before attempting to go back into the IDLE or STANDBY mode. The WDINT signal will be held low for 512 OSCCLK cycles when the watchdog interrupt is generated. You can determine the current state of WDINT by reading the watchdog interrupt status bit (WDINTS) bit in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles. In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and, therefore, so is the watchdog. The watchdog module behaves as follows under various debug conditions: CPU Suspended: When the CPU is suspended, the watchdog clock (WDCLK) is suspended Run-Free Mode: When the CPU is placed in run-free mode, then the watchdog module resumes operation as normal. Real-Time Single-Step When the CPU is in real-time single-step mode, the watchdog clock Mode: (WDCLK) is suspended. The watchdog remains suspended even within real-time interrupts. Real-Time Run-Free When the CPU is in real-time run-free mode, the watchdog operates as Mode: normal. SPRUFB0C–September 2007–Revised May 2009 Clocking 57 Submit Documentation Feedback

interrupt enable/disable bit. Figure 3-15 describes the bit functions of the SCSR register. Figure 3-15. System Control and Status Register (SCSR) 15 8 Reserved R-0 7 3 2 1 0 Reserved WDINTS WDENINT WDOVERRIDE R-0 R-1 R/W-0 R/W1C-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-14. System Control and Status Register (SCSR) Field Descriptions Bit Field Value Description (1) 15-3 Reserved 2 WDINTS Watchdog interrupt status bit. WDINTS reflects the current state of the WDINT signal from the watchdog block. WDINTS follows the state of WDINT by two SYSCLKOUT cycles. If the watchdog interrupt is used to wake the device from IDLE or STANDBY low power mode, use this bit to make sure WDINT is not active before attempting to go back into IDLE or STANDBY mode. 0 Watchdog interrupt signal (WDINT) is active. 1 Watchdog interrupt signal (WDINT) is not active. 1 WDENINT Watchdog interrupt enable. 0 The watchdog reset (WDRST) output signal is enabled and the watchdog interrupt (WDINT) output signal is disabled. This is the default state on reset (XRS). When the watchdog interrupt occurs the WDRST signal will stay low for 512 OSCCLK cycles. If the WDENINT bit is cleared while WDINT is low, a reset will immediately occur. The WDINTS bit can be read to determine the state of the WDINT signal. 1 The WDRST output signal is disabled and the WDINT output signal is enabled. When the watchdog interrupt occurs, the WDINTsignal will stay low for 512 OSCCLK cycles. If the watchdog interrupt is used to wake the device from IDLE or STANDBY low power mode, use the WDINTS bit to make sure WDINT is not active before attempting to go back into IDLE or STANDBY mode. 0 WDOVERRIDE Watchdog override 0 Writing a 0 has no effect. If this bit is cleared, it remains in this state until a reset occurs. The current state of this bit is readable by the user. 1 You can change the state of the watchdog disable (WDDIS) bit in the watchdog control (WDCR) register. If the WDOVERRIDE bit is cleared by writing a 1, you cannot modify the WDDIS bit. (1) This register is EALLOW protected. See Section 5.2 for more information. Clocking 58 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

15 8 7 0 Reserved WDCNTR R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-15. Watchdog Counter Register (WDCNTR) Field Descriptions Bits Field Description 15-8 Reserved Reserved 7-0 WDCNTR These bits contain the current value of the WD counter. The 8-bit counter continually increments at the watchdog clock (WDCLK), rate. If the counter overflows, then the watchdog initiates a reset. If the WDKEY register is written with a valid combination, then the counter is reset to zero. The watchdog clock rate is configured in the WDCR register. Figure 3-17. Watchdog Reset Key Register (WDKEY) 15 8 7 0 Reserved WDKEY R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-16. Watchdog Reset Key Register (WDKEY) Field Descriptions Bits Field Value Description (1) 15-8 Reserved Reserved 7-0 WDKEY Refer to Table 3-13 for examples of different WDKEY write sequences. 0x55 + 0xAA Writing 0x55 followed by 0xAA to WDKEY causes the WDCNTR bits to be cleared. Other value Writing any value other than 0x55 or 0xAA causes no action to be generated. If any value other than 0xAA is written after 0x55, then the sequence must restart with 0x55. Reads from WDKEY return the value of the WDCR register. (1) This register is EALLOW protected. See Section 5.2 for more information. Figure 3-18. Watchdog Control Register (WDCR) 15 8 Reserved 7 6 5 3 2 0 WDFLAG WDDIS WDCHK WDPS R/W1C-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-17. Watchdog Control Register (WDCR) Field Descriptions Bits Field Value Description (1) 15-8 Reserved Reserved 7 WDFLAG Watchdog reset status flag bit 0 The reset was caused either by the XRS pin or because of power-up. The bit remains latched until you write a 1 to clear the condition. Writes of 0 are ignored. 1 Indicates a watchdog reset (WDRST) generated the reset condition. . (1) This register is EALLOW protected. See Section 5.2 for more information. SPRUFB0C–September 2007–Revised May 2009 Clocking 59 Submit Documentation Feedback

Borrow Reset Timer reload SYSCLKOUT TCR.4 (Timer start status) TINT 16-bit timer divide-down TDDRH:TDDR 32-bit timer period PRDH:PRD 32-bit counter TIMH:TIM 16-bit prescale counter PSCH:PSC Borrow 32-Bit CPU Timers 0/1/2 www.ti.com Table 3-17. Watchdog Control Register (WDCR) Field Descriptions (continued) Bits Field Value Description (1) 6 WDDIS Watchdog disable. On reset, the watchdog module is enabled. 0 Enables the watchdog module. WDDIS can be modified only if the WDOVERRIDE bit in the SCSR register is set to 1. (default) 1 Disables the watchdog module. 5-3 WDCHK Watchdog check. 0,0,0 You must ALWAYS write 1,0,1 to these bits whenever a write to this register is performed unless the intent is to reset the device via software. other If the watchdog is enabled, then writing any other value causes an immediate device reset or watchdog interrupt to be taken. These three bits always read back as zero (0, 0, 0). This feature can be used to generate a software reset of the DSP. 2-0 WDPS Watchdog pre-scale. These bits configure the watchdog counter clock (WDCLK) rate relative to OSCCLK/512: 000 WDCLK = OSCCLK/512/1 (default) 001 WDCLK = OSCCLK/512/1 010 WDCLK = OSCCLK/512/2 011 WDCLK = OSCCLK/512/4 100 WDCLK = OSCCLK/512/8 101 WDCLK = OSCCLK/512/16 110 WDCLK = OSCCLK/512/32 111 WDCLK = OSCCLK/512/64 When the XRS line is low, the WDFLAG bit is forced low. The WDFLAG bit is only set if a rising edge on WDRST signal is detected (after synch and an 8192 SYSCLKOUT cycle delay) and the XRS signal is high. If the XRS signal is low when WDRST goes high, then the WDFLAG bit remains at 0. In a typical application, the WDRST signal connects to the XRS input. Hence to distinguish between a watchdog reset and an external device reset, an external reset must be longer in duration then the watchdog pulse. This section describes the three 32-bit CPU-timers (Figure 3-19) (TIMER0/1/2). CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for DSP-BIOS. If the application is not using DSP-BIOS, then Timer 2 can be used in the application. The CPU-timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 3-20. Figure 3-19. CPU-Timers 60 Clocking SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Figure 3-20. CPU-Timer Interrupts Signals and Output Signal A The timer registers are connected to the Memory Bus of the 28x processor. B The timing of the timers is synchronized to SYSCLKOUT of the processor clock. The general operation of the CPU-timer is as follows: The 32-bit counter register TIMH:TIM is loaded with the value in the period register PRDH:PRD. The counter register decrements at the SYSCLKOUT rate of the 28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 3-18 are used to configure the timers. Table 3-18. CPU-Timers 0, 1, 2 Configuration and Control Registers Name Address Size (x16) Description Bit Description TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter Register Figure 3-21 TIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register High Figure 3-22 TIMER0PRD 0x0C02 1 CPU-Timer 0, Period Register Figure 3-23 TIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register High Figure 3-24 TIMER0TCR 0x0C04 1 CPU-Timer 0, Control Register Figure 3-25 Reserved 0x0C05 1 TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale Register Figure 3-26 TIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register High Figure 3-27 TIMER1TIM 0x0C08 1 CPU-Timer 1, Counter Register Figure 3-21 TIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register High Figure 3-22 TIMER1PRD 0x0C0A 1 CPU-Timer 1, Period Register Figure 3-23 TIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register High Figure 3-24 TIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Register Figure 3-25 Reserved 0x0C0D 1 TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale Register Figure 3-26 TIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register High Figure 3-27 TIMER2TIM 0x0C10 1 CPU-Timer 2, Counter Register Figure 3-21 TIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register High Figure 3-22 TIMER2PRD 0x0C12 1 CPU-Timer 2, Period Register Figure 3-23 TIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register High Figure 3-24 TIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register Figure 3-25 Reserved 0x0C15 1 TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale Register Figure 3-26 TIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High Figure 3-27 SPRUFB0C–September 2007–Revised May 2009 Clocking 61 Submit Documentation Feedback

www.ti.com Figure 3-21. TIMERxTIM Register (x = 0, 1, 2) 15 0 TIM R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-19. TIMERxTIM Register Field Descriptions Bits Field Description 15-0 TIM CPU-Timer Counter Registers (TIMH:TIM): The TIM register holds the low 16 bits of the current 32-bit count of the timer. The TIMH register holds the high 16 bits of the current 32-bit count of the timer. The TIMH:TIM decrements by one every (TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer prescale divide-down value. When the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD registers. The timer interrupt (TINT) signal is generated. Figure 3-22. TIMERxTIMH Register (x = 0, 1, 2) 15 0 TIMH R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-20. TIMERxTIMH Register Field Descriptions Bits Field Description 15-0 TIMH See description for TIMERxTIM. Figure 3-23. TIMERxPRD Register (x = 0, 1, 2) 15 0 PRD R/W-0xFFFF LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-21. TIMERxPRD Register Field Descriptions Bits Field Description 15-0 PRD CPU-Timer Period Registers (PRDH:PRD): The PRD register holds the low 16 bits of the 32-bit period. The PRDH register holds the high 16 bits of the 32-bit period. When the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD registers, at the start of the next timer input clock cycle (the output of the prescaler). The PRDH:PRD contents are also loaded into the TIMH:TIM when you set the timer reload bit (TRB) in the Timer Control Register (TCR). Figure 3-24. TIMERxPRDH Register (x = 0, 1, 2) 15 0 PRDH R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Clocking 62 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 3-22. TIMERxPRDH Register Field Descriptions Bits Field Description 15-0 PRDH See description for TIMERxPRD Figure 3-25. TIMERxTCR Register (x = 0, 1, 2) 15 14 13 12 11 10 9 8 TIF TIE Reserved FREE SOFT Reserved R/W-0 R/W-0 R-0 R/W-0 R/W-0 R-0 7 6 5 4 3 0 Reserved TRB TSS Reserved R-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-23. TIMERxTCR Register Field Descriptions Bits Field Value Description 15 TIF CPU-Timer Interrupt Flag. 0 The CPU-Timer has not decremented to zero. Writes of 0 are ignored. 1 This flag gets set when the CPU-timer decrements to zero. Writing a 1 to this bit clears the flag. 14 TIE CPU-Timer Interrupt Enable. 0 The CPU-Timer interrupt is disabled. 1 The CPU-Timer interrupt is enabled. If the timer decrements to zero, and TIE is set, the timer asserts its interrupt request. 13-12 Reserved Reserved 11-10 FREE CPU-Timer Emulation Modes: These bits are special emulation bits that determine the SOFT state of the timer when a breakpoint is encountered in the high-level language debugger. If the FREE bit is set to 1, then, upon a software breakpoint, the timer continues to run (that is, free runs). In this case, SOFT is a don't care. But if FREE is 0, then SOFT takes effect. In this case, if SOFT = 0, the timer halts the next time the TIMH:TIM decrements. If the SOFT bit is 1, then the timer halts when the TIMH:TIM has decremented to zero. FREE SOFT CPU-Timer Emulation Mode 0 0 Stop after the next decrement of the TIMH:TIM (hard stop) 0 1 Stop after the TIMH:TIM decrements to 0 (soft stop) 1 0 Free run 1 1 Free run In the SOFT STOP mode, the timer generates an interrupt before shutting down (since reaching 0 is the interrupt causing condition). 9-6 Reserved Reserved 5 TRB CPU-Timer Reload bit. 0 The TRB bit is always read as zero. Writes of 0 are ignored. 1 When you write a 1 to TRB, the TIMH:TIM is loaded with the value in the PRDH:PRD, and the prescaler counter (PSCH:PSC) is loaded with the value in the timer divide-down register (TDDRH:TDDR). 4 TSS CPU-Timer stop status bit. TSS is a 1-bit flag that stops or starts the CPU-timer. 0 Reads of 0 indicate the CPU-timer is running. To start or restart the CPU-timer, set TSS to 0. At reset, TSS is cleared to 0 and the CPU-timer immediately starts. 1 Reads of 1 indicate that the CPU-timer is stopped. To stop the CPU-timer, set TSS to 1. SPRUFB0C–September 2007–Revised May 2009 Clocking 63 Submit Documentation Feedback

www.ti.com Table 3-23. TIMERxTCR Register Field Descriptions (continued) Bits Field Value Description 3-0 Reserved Reserved Figure 3-26. TIMERxTPR Register (x = 0, 1, 2) 15 8 7 0 PSC TDDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-24. TIMERxTPR Register Field Descriptions Bits Field Description 15-8 PSC CPU-Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer clock source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one. One timer clock (output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and the timer counter register (TIMH:TIM) decrements by one. The PSCH:PSC is also reloaded whenever the timer reload bit (TRB) is set by software. The PSCH:PSC can be checked by reading the register, but it cannot be set directly. It must get its value from the timer divide-down register (TDDRH:TDDR). At reset, the PSCH:PSC is set to 0. 7-0 TDDR CPU-Timer Divide-Down. Every (TDDRH:TDDR + 1) timer clock source cycles, the timer counter register (TIMH:TIM) decrements by one. At reset, the TDDRH:TDDR bits are cleared to 0. To increase the overall timer count by an integer factor, write this factor minus one to the TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value is 0, one timer clock source cycle later, the contents of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit (TRB) is set by software. Figure 3-27. TIMERxTPRH Register (x = 0, 1, 2) 15 8 7 0 PSCH TDDRH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-25. TIMERxTPRH Register Field Descriptions Bits Field Description 15-8 PSCH See description of TIMERxTPR. 7-0 TDDRH See description of TIMERxTPR. 64 Clocking SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

General-Purpose Input/Output (GPIO) The GPIO multiplexing (MUX) registers are used to select the operation of shared pins. The pins are named by their general purpose I/O name (i.e., GPIO0 - GPIO87). These pins can be individually selected to operate as digital I/O, referred to as GPIO, or connected to one of up to three peripheral I/O signals (via the GPxMUXn registers). If selected for digital I/O mode, registers are provided to configure the pin direction (via the GPxDIR registers). You can also qualify the input signals to remove unwanted noise (via the GPxQSELn, GPACTRL, and GPBCTRL registers). Topic .................................................................................................. Page 4.1 GPIO Module Overview.............................................................. 66 4.2 Configuration Overview ............................................................. 71 4.3 Digital General Purpose I/O Control ............................................ 72 4.4 Input Qualification..................................................................... 74 4.5 GPIO and Peripheral Multiplexing (MUX)...................................... 78 4.6 Register Bit Definitions.............................................................. 83 SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 65 Submit Documentation Feedback

GPADAT (latch) GPACLEAR, GPATOGGLE GPAQSEL 1/2 Qual GPAMUX1/2 SYSCLKOUT High impedance output control GPIO0 to GPIO27 Pins PU XRS Sync Low�power modes�block GPIOx.async GPADIR (latch) 01 11 01 GPACTRL 2 2 10 Peripheral�1�input N/C (default�on�reset) (default�on�reset) GPIOx_OUT GPIOx_DIR GPAPUD 0 = enable�PU 1 = disable�PU (disabled�after�reset) async (async�disable when�low) 11 10 Peripheral�2�input Peripheral�3�input Peripheral�1�output GPASET, (default on�reset) 3�samples 6�samples 00 00 XRS (default�on�reset) 01 11 10 00 01 11 10 00 0�=�input,�1�=�output GPIO�XINT1SEL GPIO�XINT2SEL GPIOXNMISEL External interrupt MUX PIE GPADAT (read) GPIOLPMSEL LPMCR0 Peripheral�2�output Peripheral�3�output Peripheral�1�output�enable Peripheral�2�output�enable Peripheral�3�output�enable GPIO Module Overview www.ti.com Up to three independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to individual pin bit-I/O capability. There are three 32-bit I/O ports. Port A consists of GPIO0-GPIO31, port B consists of GPIO32-GPIO63, and port C consists of GPIO64-87. Figure 4-1 shows the basic modes of operation for the GPIO module. Figure 4-1. GPIO0 to GPIO27 Multiplexing Diagram A GPxDAT latch/read are accessed at the same memory location. 66 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Sync Low�Power Modes�Block GPIOx.async GPADIR (latch) 01 11 01 01 0x 1x 01 GPACTRL 2 2 10 Perpheral�1�input N/C (default�on�reset) (default�on�reset) GPIOx_OUT GPIOx_DIR GPAPUD 0 = enable�PU 1 = disable�PU (disabled�after�reset) async (async�disable when�low) 0x 1x 11 10 XINTF�Output�Signals XZCS6,�XA19,�XA18,�XA17 1 N/C N/C Perpheral�1�output Perpheral�1�ouput�enable GPASET (default�on�reset) 3�samples 6�samples LPMCR0 GPIOLPMSEL 00 00 00 00 XRS Default�at�Reset External interrupt MUX GPIO�XINT2SEL GPIOXNMISEL GPIO�XINT1SEL PIE GPADAT (read) www.ti.com GPIO Module Overview Figure 4-2. GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) A The shaded area is disabled in the above GPIOs when the GPIOINENCLK bit is cleared to 0 in the PCLKCR3 register and the respective pin is configured as an output. This is to reduce power consumption when a pin is configured as an output. Clearing the GPIOINCLK bit will reset the sync and qualification logic so no residual value is left. B The input qualification circuit is not reset when modes are changed (such as changing from output to input mode). Any state will get flushed by the circuit eventually. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 67 Submit Documentation Feedback

Sync GPBDIR (latch) 01 11 01 GPBCTRL 2 2 10 Perpheral�1�input N/C (default�on�reset) GPIO32/33_OUT (default�on�reset) GPBPUD 0 = enable�PU 1 = disable�PU (disabled�after�reset) async (async�disable when�low) 0x 1x 11 10 Peripheral�2�input Peripheral�3�input GPBSET (default�on�reset) 3�samples 6�samples 00 00 XRS Default�at�Reset External interrupt MUX GPIO�XINT6SEL GPIO�XINT7SEL GPIO�XINT5SEL GPIO�XINT4SEL GPIO�XINT3SEL PIE GPBDAT (read) 01 Perpheral�1�output 11 10 Peripheral�2�output Peripheral�3�output 00 01 11 10 Peripheral�2�output�enable Peripheral�3�output�enable 00 SDAA/SCLA (I2C�output�enable) SDAA/SCLA (I2C�data�out) GPIO32/33-DIR GPIO Module Overview www.ti.com Figure 4-3. GPIO32, GPIO33 Multiplexing Diagram A The GPIOINENCLK bit in the PCLKCR3 register does not affect the above GPIOs (I2C pins) since the pins are bi-directional. B The input qualification circuit is not reset when modes are changed (such as changing from output to input mode). Any state will get flushed by the circuit eventually. General-Purpose Input/Output (GPIO) 68 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Sync XINT Input�Signals (XREADY,�XD31:16_IN) GPBDIR (latch) 01 11 01 01 0x 1x 01 GPBCTRL 2 2 10 Perpheral�1�input N/C (default�on�reset) (default�on�reset) GPIOx_OUT GPIOx_DIR GPBPUD 0 = enable�PU 1 = disable�PU (disabled�after�reset) async (async�disable when�low) 0x 1x 11 10 XINTF�Output�Signals (XR/ , , , , /XA0, XA7.1,�XD31:16_OUT) W��XZCS0��XZCS7 XWE0��XWE1 N/C N/C Peripheral�1�output Peripheral�1�output�enable GPBSET (default�on�reset) 3�samples 6�samples 00 00 00 00 XRS Default�at�Reset XINTF�Output�Enables (XD_OE�or�1) External interrupt MUX GPIO�XINT6SEL GPIO�XINT7SEL GPIO�XINT5SEL GPIO�XINT4SEL GPIO�XINT3SEL PIE GPBDAT (read) High- Impedance Output Control www.ti.com GPIO Module Overview Figure 4-4. GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged) A The shaded area is disabled in the above GPIOs when the GPIOINENCLK bit is cleared to "0" in the PCLKCR3 register and the respective pin is configured as an output. This is to reduce power consumption when a pin is configured as an output. Clearing the GPIOINCLK bit will reset the sync and qualification logic so no residual value is left. B The input qualification circuit is not reset when modes are changed (such as changing from output to input mode). Any state will get flushed by the circuit eventually. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 69 Submit Documentation Feedback

www.ti.com Figure 4-5. GPIO64 to GPIO79 Multiplexing Diagram (Minimal GPIOs Without Qualification) 70 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

sources are all controlled by the GPIO configuration control registers. In addition, you can assign pins to wake the device from the HALT and STANDBY low power modes and enable/disable internal pullup resistors. Table 4-1 and Table 4-2 list the registers that are used to configure the GPIO pins to match the system requirements. Table 4-1. GPIO Control Registers Name (1) Address Size (x16) Register Description Bit Description GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0-GPIO31) Figure 4-14 GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0-GPIO15) Figure 4-16 GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16-GPIO31) Figure 4-17 GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0-GPIO15) Figure 4-8 GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16-GPIO31) Figure 4-9 GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0-GPIO31) Figure 4-20 GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0-GPIO31) Figure 4-23 GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32-GPIO63) Figure 4-15 GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32-GPIO47) Figure 4-18 GPBQSEL2 0x6F94 2 GPIO B Qualifier Select 2 Register (GPIO48 - GPIO63) Figure 4-19 GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32-GPIO47) Figure 4-10 GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO48-GPIO63) Figure 4-11 GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32-GPIO63) Figure 4-21 GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32-GPIO63) Figure 4-24 GPCMUX1 0x6FA6 2 GPIO C MUX 1 Register (GPIO64-GPIO79) Figure 4-12 GPCMUX2 0x6FA8 2 GPIO C MUX 2 Register (GPIO80-GPIO87) Figure 4-13 GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64-GPIO87) Figure 4-22 GPCPUD 0x6FAC 2 GPIO C Pull Up Disable Register (GPIO64-GPIO87) Figure 4-25 (1) The registers in this table are EALLOW protected. See Section 5.2 for more information. Table 4-2. GPIO Interrupt and Low Power Mode Select Registers Size Name (1) Address Register Description Bit Description (x16) GPIOXINT1SEL 0x6FE0 1 XINT1 Source Select Register (GPIO0-GPIO31) Figure 4-32 GPIOXINT2SEL 0x6FE1 1 XINT2 Source Select Register (GPIO0-GPIO31) Figure 4-32 GPIOXNMISEL 0x6FE2 1 XNMI Source Select Register (GPIO0-GPIO31) Figure 4-32 GPIOXINT3SEL 0x6FE3 1 XINT3 Source Select Register (GPIO32 - GPIO63) Table 4-44 GPIOXINT4SEL 0x6FE4 1 XINT4 Source Select Register (GPIO32 - GPIO63) Table 4-44 GPIOXINT5SEL 0x6FE5 1 XINT5 Source Select Register (GPIO32 - GPIO63) Table 4-44 GPIOXINT6SEL 0x6FE6 1 XINT6 Source Select Register (GPIO32 - GPIO63) Table 4-44 GPIOXINT7SEL 0x6FE7 1 XINT7 Source Select Register (GPIO32 - GPIO63) Table 4-44 GPIOLPMSEL 0x6FE8 1 LPM wakeup Source Select Register (GPIO0-GPIO31) Figure 4-33 (1) The registers in this table are EALLOW protected. See Section 5.2 for more information. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 71 Submit Documentation Feedback

Digital General Purpose I/O Control www.ti.com To plan configuration of the GPIO module, consider the following steps: Step 1. Plan the device pin-out: Through a pin multiplexing scheme, a lot of flexibility is provided for assigning functionality to the GPIO-capable pins. Before getting started, look at the peripheral options available for each pin, and plan pin-out for your specific system. Will the pin be used as a general purpose input or output (GPIO) or as one of up to three available peripheral functions? Knowing this information will help determine how to further configure the pin. Step 2. Enable or disable internal pullup resistors: To enable or disable the internal pullup resistors, write to the respective bits in the GPIO pullup disable (GPAPUD, GPBPUD, and GPCPUD) registers. For pins that can function as ePWM output pins (GPIO0-GPIO11), the internal pullup resistors are disabled by default. All other GPIO-capable pins have the pullup enabled by default. Step 3. Select input qualification: If the pin will be used as an input, specify the required input qualification, if any. The input qualification is specified in the GPACTRL, GPBCTRL, GPAQSEL1, GPAQSEL2, GPBQSEL1, and GPBQSEL2 registers. By default, all of the input signals are synchronized to SYSCLKOUT only. Step 4. Select the pin function: Configure the GPxMUXn registers such that the pin is a GPIO or one of three available peripheral functions. By default, all GPIO-capable pins are configured at reset as general purpose input pins. Step 5. For digital general purpose I/O, select the direction of the pin: If the pin is configured as an GPIO, specify the direction of the pin as either input or output in the GPADIR, GPBDIR, and GPCDIR registers. By default, all GPIO pins are inputs. To change the pin from input to output, first load the output latch with the value to be driven by writing the appropriate value to the GPxCLEAR, GPxSET, or GPxTOGGLE registers. Once the output latch is loaded, change the pin direction from input to output via the GPxDIR registers. The output latch for all pins is cleared at reset. Step 6. Select low power mode wake-up sources: Specify which pins, if any, will be able to wake the device from HALT and STANDBY low power modes. The pins are specified in the GPIOLPMSEL register. Step 7. Select external interrupt sources: Specify the source for the XINT1 - XINT7, and XNMI interrupts. For each interrupt you can specify one of the port A signals (for XINT1/2/3) or port B signals (XINT4/5/6/7) as the source. This is done by specifying the source in the GPIOXINTnSEL, and GPIOXNMISEL registers. The polarity of the interrupts can be configured in the XINTnCR, and the XNMICR registers as described in Section 6.6. Note: There is a 2-SYSCLKOUT cycle delay from when a write to configuration registers such as GPxMUXn and GPxQSELn occurs to when the action is valid For pins that are configured as GPIO you can change the values on the pins by using the registers in Table 4-3. 72 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-3. GPIO Data Registers Name Address Size (x16) Register Description Bit Description GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0-GPIO31) Figure 4-26 GPASET 0x6FC2 2 GPIO A Set Register (GPIO0-GPIO31) Figure 4-29 GPACLEAR 0x6FC4 2 GPIO A Clear Register (GPIO0-GPIO31) Figure 4-29 GPATOGGLE 0x6FC6 2 GPIO A Toggle Register (GPIO0-GPIO31) Figure 4-29 GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32-GPIO63) Figure 4-27 GPBSET 0x6FCA 2 GPIO B Set Register (GPIO32-GPIO63) Figure 4-30 GPBCLEAR 0x6FCC 2 GPIO B Clear Register (GPIO32-GPIO63) Figure 4-30 GPBTOGGLE 0x6FCE 2 GPIO B Toggle Register (GPIO32-GPIO63) Figure 4-30 GPCDAT 0x6FD0 2 GPIO C Data Register (GPIO64 - GPIO87) Figure 4-28 GPCSET 0x6FD2 2 GPIO C Set Register (GPIO64 - GPIO87) Figure 4-31 GPCCLEAR 0x6FD4 2 GPIO C Clear Register (GPIO64 - GPIO87) Figure 4-31 GPCTOGGLE 0x6FD6 2 GPIO C Toggle Register (GPIO64 - GPIO87) Figure 4-31 • GPxDAT Registers Each I/O port has one data register. Each bit in the data register corresponds to one GPIO pin. No matter how the pin is configured (GPIO or peripheral function), the corresponding bit in the data register reflects the current state of the pin after qualification. Writing to the GPxDAT register clears or sets the corresponding output latch and if the pin is enabled as a general purpose output (GPIO output) the pin will also be driven either low or high. If the pin is not configured as a GPIO output then the value will be latched, but the pin will not be driven. Only if the pin is later configured as a GPIO output, will the latched value be driven onto the pin. When using the GPxDAT register to change the level of an output pin, you should be cautious not to accidentally change the level of another pin. For example, if you mean to change the output latch level of GPIOA0 by writing to the GPADAT register bit 0, using a read-modify-write instruction. The problem can occur if another I/O port A signal changes level between the read and the write stage of the instruction. You can also change the state of that output latch. You can avoid this scenario by using the GPxSET, GPxCLEAR, and GPxTOGGLE registers to load the output latch instead. • GPxSET Registers The set registers are used to drive specified GPIO pins high without disturbing other pins. Each I/O port has one set register and each bit corresponds to one GPIO pin. The set registers always read back 0. If the corresponding pin is configured as an output, then writing a 1 to that bit in the set register will set the output latch high and the corresponding pin will be driven high. If the pin is not configured as a GPIO output, then the value will be latched but the pin will not be driven. Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin. Writing a 0 to any bit in the set registers has no effect. • GPxCLEAR Registers The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O port has one clear register. The clear registers always read back 0. If the corresponding pin is configured as a general purpose output, then writing a 1 to the corresponding bit in the clear register will clear the output latch and the pin will be driven low. If the pin is not configured as a GPIO output, then the value will be latched but the pin will not be driven. Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin. Writing a 0 to any bit in the clear registers has no effect. • GPxTOGGLE Registers The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other pins. Each I/O port has one toggle register. The toggle registers always read back 0. If the corresponding pin is configured as an output, then writing a 1 to that bit in the toggle register flips the output latch and pulls the corresponding pin in the opposite direction. That is, if the output pin is driven low, then writing a 1 to the corresponding bit in the toggle register will pull the pin high. Likewise, if the output pin is high, then writing a 1 to the corresponding bit in the toggle register will pull the pin low. If the pin is not configured as a GPIO output, then the value will be latched but the pin will not be driven. Only if the pin is later configured as a GPIO output will the latched value will be driven onto the pin. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 73 Submit Documentation Feedback

4.4.2 Synchronization to SYSCLKOUT Only 4.4.3 Qualification Using a Sampling Window GPxCTRL Reg SYNC SYSCLKOUT Qualification Input Signal Qualified By 3 or 6 Samples GPIOx Time between samples GPxQSEL1/2 Number of Samples Input Qualification www.ti.com Writing a 0 to any bit in the toggle registers has no effect. The input qualification scheme has been designed to be very flexible. You can select the type of input qualification for each GPIO pin by configuring the GPAQSEL1, GPAQSEL2, GPBQSEL1 and GPBQSEL2 registers. In the case of a GPIO input pin, the qualification can be specified as only synchronize to SYSCLKOUT or qualification by a sampling window. For pins that are configured as peripheral inputs, the input can also be asynchronous in addition to synchronized to SYSCLKOUT or qualified by a sampling window. The remainder of this section describes the options available. This mode is used for peripherals where input synchronization is not required or the peripheral itself performs the synchronization. Examples include communication ports SCI, SPI, eCAN, and I2C. In addition, it may be desirable to have the ePWM trip zone (TZ1-TZ6) signals function independent of the presence of SYSCLKOUT. The asynchronous option is not valid if the pin is used as a general purpose digital input pin (GPIO). If the pin is configured as a GPIO input and the asynchronous option is selected then the qualification defaults to synchronization to SYSCLKOUT as described in Section 4.4.2. This is the default qualification mode of all the pins at reset. In this mode, the input signal is only synchronized to the system clock (SYSCLKOUT). Because the incoming signal is asynchronous, it can take up to a SYSCLKOUT period of delay in order for the input to the DSP to be changed. No further qualification is performed on the signal. In this mode, the signal is first synchronized to the system clock (SYSCLKOUT) and then qualified by a specified number of cycles before the input is allowed to change. Figure 4-6 and Figure 4-7 show how the input qualification is performed to eliminate unwanted noise. Two parameters are specified by the user for this type of qualification: 1) the sampling period, or how often the signal is sampled, and 2) the number of samples to be taken. Figure 4-6. Input Qualification Using a Sampling Window 74 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

To qualify the signal, the input signal is sampled at a regular period. The sampling period is specified by the user and determines the time duration between samples, or how often the signal will be sampled, relative to the CPU clock (SYSCLKOUT). The sampling period is specified by the qualification period (QUALPRDn) bits in the GPxCTRL register. The sampling period is configurable in groups of 8 input signals. For example, GPIO0 to GPIO7 use GPACTRL[QUALPRD0] setting and GPIO8 to GPIO15 use GPACTRL[QUALPRD1]. Table 4-4 and Table 4-5 show the relationship between the sampling period or sampling frequency and the GPxCTRL[QUALPRDn] setting. Table 4-4. Sampling Period Sampling Period If GPxCTRL[QUALPRDn] = 0 1 × TSYSCLKOUT If GPxCTRL[QUALPRDn] ≠ 0 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT Where TSYSCLKOUT is the period in time of SYSCLKOUT Table 4-5. Sampling Frequency Sampling Frequency If GPxCTRL[QUALPRDn] = 0 fSYSCLKOUT If GPxCTRL[QUALPRDn] ≠ 0 fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn]) Where fSYSCLKOUT is the frequency of SYSCLKOUT From these equations, the minimum and maximum time between samples can be calculated for a given SYSCLKOUT frequency: Example: Maximum Sampling Frequency: If GPxCTRL[QUALPRDn] = 0 then the sampling frequency is fSYSCLKOUT If, for example, fSYSCLKOUT = 150 MHz then the signal will be sampled at 150 MHz or one sample every ns. Example: Minimum Sampling Frequency: If GPxCTRL[QUALPRDn] = 0xFF (i.e. 255) then the sampling frequency is fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn]) If, for example, fSYSCLKOUT = 150 MHz then the signal will be sampled at 150 MHz × 1 ÷ (2 × 255) or one sample every 3.4 µs. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 75 Submit Documentation Feedback

The number of times the signal is sampled is either 3 samples or 6 samples as specified in the qualification selection (GPAQSEL1, GPAQSEL2, GPBQSEL1, and GPBQSEL2) registers. When 3 or 6 consecutive cycles are the same, then the input change will be passed through to the DSP. Total Sampling Window Width: The sampling window is the time during which the input signal will be sampled as shown in Figure 4-7. By using the equation for the sampling period along with the number of samples to be taken, the total width of the window can be determined. For the input qualifier to detect a change in the input, the level of the signal must be stable for the duration of the sampling window width or longer. The number of sampling periods within the window is always one less then the number of samples taken. For a thee-sample window, the sampling window width is 2 sampling periods wide where the sampling period is defined in Table 4-4. Likewise, for a six-sample window, the sampling window width is 5 sampling periods wide. Table 4-6 and Table 4-7 show the calculations that can be used to determine the total sampling window width based on GPxCTRL[QUALPRDn] and the number of samples taken. Table 4-6. Case 1: Three-Sample Sampling Window Width Total Sampling Window Width If GPxCTRL[QUALPRDn] = 0 2 × TSYSCLKOUT If GPxCTRL[QUALPRDn] ≠ 0 2 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT Where TSYSCLKOUT is the period in time of SYSCLKOUT Table 4-7. Case 2: Six-Sample Sampling Window Width Total Sampling Window Width If GPxCTRL[QUALPRDn] = 0 5 × TSYSCLKOUT If GPxCTRL[QUALPRDn] ≠ 0 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT Where TSYSCLKOUT is the period in time of SYSCLKOUT Note: The external signal change is asynchronous with respect to both the sampling period and SYSCLKOUT. Due to the asynchronous nature of the external signal, the input should be held stable for a time greater than the sampling window width to make sure the logic detects a change in the signal. The extra time required can be up to an additional sampling period + TSYSCLKOUT. The required duration for an input signal to be stable for the qualification logic to detect a change is described in the device specific data manual. General-Purpose Input/Output (GPIO) 76 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

(SYSCLKOUT/2) (SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)) (A) GPxQSELn = 1,0 (6 samples) Sampling Period determined by GPxCTRL[QUALPRD](B) A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value “n”, the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled). B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins. C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. (D) tw(SP) tw(IQSW) www.ti.com Input Qualification Example Qualification Window: For the example shown in Figure 4-7, the input qualification has been configured as follows: • GPxQSEL1/2 = 1,0. This indicates a six-sample qualification. • GPxCTRL[QUALPRDn] = 1. The sampling period is tw(SP) = 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT. This configuration results in the following: • The width of the sampling window is: . tw(IQSW) = 5 × tw(SP) = 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT or 5 × 2 × TSYSCLKOUT • If, for example, TSYSCLKOUT = 6.67 ns, then the duration of the sampling window is: tw(IQSW) = 5 × 2 × 6.67 ns = 67 ns. • To account for the asynchronous nature of the input relative to the sampling period and SYSCLKOUT, up to an additional sampling period, tw(SP), + TSYSCLKOUT may be required to detect a change in the input signal. For this example: tw(SP) + TSYSCLKOUT = 13.34 ns + 6.67 ns = 20 ns • In Figure 4-7, the glitch (A) is shorter then the qualification window and will be ignored by the input qualifier. Figure 4-7. Input Qualifier Clock Cycles SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 77 Submit Documentation Feedback

GPIO and Peripheral Multiplexing (MUX) www.ti.com Up to three different peripheral functions are multiplexed along with a general input/output (GPIO) function per pin. This allows you to pick and choose a peripheral mix that will work best for the particular application. Table 4-9, Table 4-10, and Table 4-11 show an overview of the possible multiplexing combinations sorted by GPIO pin. The second column indicates the I/O name of the pin on the device. Since the I/O name is unique, it is the best way to identify a particular pin. Therefore, the register descriptions in this section only refer to the GPIO name of a particular pin. The MUX register and particular bits that control the selection for each pin are indicated in the first column. For example, the multiplexing for the GPIO7 pin is controlled by writing to GPAMUX[15:14]. By writing to these bits, the pin is configured as either GPIO7, or one of up to three peripheral functions. The GPIO7 pin can be configured as follows: GPAMUX1[15:14] Bit Setting Pin Functionality Selected If GPAMUX1[15:14] = 0,0 Pin configured as GPIO7 If GPAMUX1[15:14] = 0,1 Pin configured as EPWM4B (O) If GPAMUX1[15:14] = 1,0 Pin configured as MCLKRA (I/O) If GPAMUX1[15:14] = 1,1 Pin configured as ECAP2 (I/O) All devices in the 2833x, 2823x family have the same multiplexing scheme. The only difference is that if a peripheral is not available on a particular device, that MUX selection is reserved on that device and should not be used. Note: If you should select a reserved GPIO MUX configuration that is not mapped to a peripheral, the state of the pin will be undefined and the pin may be driven. Reserved configurations are for future expansion and should not be selected. In the device MUX tables (Table 4-9, Table 4-10, and Table 4-11) these options are indicated as "Reserved". Some peripherals can be assigned to more than one pin via the MUX registers. For example, the CAP1 function can be assigned to either the GPIO5 or GPIO24 pin, depending on individual system requirements as shown below: Pin Assigned to CAP1 MUX Configuration Choice 1 GPIO5 GPAMUX1[11:10] = 1,1 or Choice 2 GPIO24 GPAMUX2[17:16] = 0,1 If no pin is configured as an input to a peripheral, or if more than one pin is configured as an input for the same peripheral, then the input to the peripheral will either default to a 0 or a 1 as shown in Table 4-8. For example, if ECAP1 were assigned to both GPIO5 and GPIO24, the input to the eCAP1 peripheral would default to a high state as shown in Table 4-8 and the input would not be connected to GPIO5 or GPIO24. 78 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-8. Default State of Peripheral Input Peripheral Input Description Default Input (1) TZ1-TZ6 Trip zone 1-6 1 EPWMSYNCI ePWM Synch Input 0 ECAPn eCAP input 1 EQEPnA eQEP input 1 EQEPnI eQEP index 1 EQEPnS eQEP strobe 1 SPICLKx SPI clock 1 SPISTEx SPI transmit enable 0 SPISIMOx SPI Slave-in, master-out 1 SPISOMIx SPI Slave-out, master-in 1 SCIRXDx SCI receive 1 CANRXx CAN receive 1 SDAA I2C data 1 SCLA1 I2C clock 1 (1) This value will be assigned to the peripheral input if more then one pin has been assigned to the peripheral function in the GPxMUX1/2 registers or if no pin has been assigned. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 79 Submit Documentation Feedback

www.ti.com Table 4-9. GPIOA MUX Default at Reset Primary I/O Function Peripheral Selection Peripheral Selection 2 Peripheral Selection 3 GPAMUX1 Register (GPAMUX1 bits = 00) (GPAMUX1 bits = 01) (GPAMUX1 bits = 10) (GPAMUX1 bits = 11) Bits 1-0 GPIO0 EPWM1A (O) Reserved(1) Reserved(1) 3-2 GPIO1 EPWM1B (O) ECAP6 (I/O) MFSRB (I/O)(1) 5-4 GPIO2 EPWM2A (O) Reserved(1) Reserved(1) 7-6 GPIO3 EPWM2B (O) ECAP5 (I/O) MCLKRB (I/O)(1) 9-8 GPIO4 EPWM3A (O) Reserved(1) Reserved(1) 11-10 GPIO5 EPWM3B (O) MFSRA (I/O) ECAP1 (I/O) 13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O) 15-14 GPIO7 EPWM4B (O) MCLKRA (I/O) ECAP2 (I/O) 17-16 GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O) 19-18 GPIO9 EPWM5B (O) SCITXDB (O) ECAP3 (I/O) 21-20 GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O) 23-22 GPIO11 EPWM6B (O) SCIRXDB (I) ECAP4 (I/O) 25-24 GPIO12 TZ1 (I) CANTXB (O) MDXB (O) 27-26 GPIO13 TZ2 (I) CANRXB (I) MDRB (I) 29-28 GPIO14 TZ3/XHOLD (I) SCITXDB (O) MCLKXB (I/O) 31-30 GPIO15 TZ4/XHOLDA (O) SCIRXDB (I) MFSXB (I/O) GPAMUX2 Register (GPAMUX2 bits = 00) (GPAMUX2 bits = 01) (GPAMUX2 bits = 10) (GPAMUX2 bits = 11) Bits 1-0 GPIO16 SPISIMOA (I/O) CANTXB (O) TZ5 (I) 3-2 GPIO17 SPISOMIA (I/O) CANRXB (I) TZ6 (I) 5-4 GPIO18 SPICLKA (I/O) SCITXDB (O) CANRXA (I) 7-6 GPIO19 SPISTEA (I/O) SCIRXDB (I) CANTXA (O) 9-8 GPIO20 EQEP1A (I) MDXA (O) CANTXB (O) 11-10 GPIO21 EQEP1B (I) MDRA (I) CANRXB (I) 13-12 GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) 15-14 GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I) 17-16 GPIO24 ECAP1 (I/O) EQEP2A (I) MDXB (O) 19-18 GPIO25 ECAP2 (I/O) EQEP2B (I) MDRB (I) 21-20 GPIO26 ECAP3 (I/O) EQEP2I (I/O) MCLKXB (I/O) 23-22 GPIO27 ECAP4 (I/O) EQEP2S (I/O) MFSXB (I/O) 25-24 GPIO28 SCIRXDA (I) XZCS6 (O) XZCS6 (O) 27-26 GPIO29 SCITXDA (O) XA19 (O) XA19 (O) 29-28 GPIO30 CANRXA (I) XA18 (O) XA18 (O) 31-30 GPIO31 CANTXA (O) XA17 (O) XA17 (O) (1) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. General-Purpose Input/Output (GPIO) 80 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-10. GPIOB MUX Default at Reset Primary I/O Function Peripheral Selection 1 Peripheral Selection 2 Peripheral Selection 3 GPBMUX1 Register (GPBMUX1 bits = 00) (GPBMUX1 bits = 01) (GPBMUX1 bits = 10) (GPBMUX1 bits = 11) Bits 1,0 GPIO32 (I/O) SDAA (I/OC) EPWMSYNCI (I) ADCSOCAO (O) 3,2 GPIO33 (I/O) SCLA (I/OC) EPWMSYNCO (O) ADCSOCBO (O) 5,4 GPIO34 (I/O) ECAP1 (I/O) XREADY (I) XREADY (I) 7,6 GPIO35 (I/O) SCITXDA (O) XR/W (O) XR/W (O) 9,8 GPIO36 (I/O) SCIRXDA (I) XZCS0 (O) XZCS0 (O) 11,10 GPIO37 (I/O) ECAP2 (I/O) XZCS7 (O) XZCS7 (O) 13,12 GPIO38 (I/O) Reserved XWE0 (O) XWE0 (O) 15,14 GPIO39 (I/O) Reserved XA16 (O) XA16 (O) 17,16 GPIO40 (I/O) Reserved XA0/XWE1 (O) XA0/XWE1 (O) 19,18 GPIO41 (I/O) Reserved XA1 (O) XA1 (O) 21,20 GPIO42 (I/O) Reserved XA2 (O) XA2 (O) 23,22 GPIO43 (I/O) Reserved XA3 (O) XA3 (O) 25,24 GPIO44 (I/O) Reserved XA4 (O) XA4 (O) 27,26 GPIO45 (I/O) Reserved XA5 (O) XA5 (O) 29,28 GPIO46 (I/O) Reserved XA6 (O) XA6 (O) 31,30 GPIO47 (I/O) Reserved XA7 (O) XA7 (O) GPBMUX2 Register (GPBMUX2 bits = 00) (GPBMUX2 bits = 01) (GPBMUX2 bits = 10 or 11) Bits 1,0 GPIO48 (I/O) ECAP5 (I/O) XD31 (I/O) 3,2 GPIO49 (I/O) ECAP6 (I/O) XD30 (I/O) 5,4 GPIO50 (I/O) EQEP1A (I) XD29 (I/O) 7,6 GPIO51 (I/O) EQEP1B (I) XD28 (I/O) 9,8 GPIO52 (I/O) EQEP1S (I/O) XD27 (I/O) 11,10 GPIO53 (I/O) EQEP1I (I/O) XD26 (I/O) 13,12 GPIO54 (I/O) SPISIMOA (I/O) XD25 (I/O) 15,14 GPIO55 (I/O) SPISOMIA (I/O) XD24 (I/O) 17,16 GPIO56 (I/O) SPICLKA (I/O) XD23 (I/O) 19,18 GPIO57 (I/O) SPISTEA (I/O) XD22 (I/O) 21,20 GPIO58 (I/O) MCLKRA (I/O) XD21 (I/O) 23,22 GPIO59 (I/O) MFSRA (I/O) XD20 (I/O) 25,24 GPIO60 (I/O) MCLKRB (I/O) XD19 (I/O) 27,26 GPIO61 (I/O) MFSRB (I/O) XD18 (I/O) 29,28 GPIO62 (I/O) SCIRXDC (I) XD17 (I/O) 31,30 GPIO63 (I/O) SCITXDC (O) XD16 (I/O) SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 81 Submit Documentation Feedback

www.ti.com Table 4-11. GPIOC MUX Default at Reset Primary I/O Function Peripheral Selection 2 or 3 GPCMUX1 Register Bits (GPCMUX1 bits = 00 or 01) (GPCMUX1 bits = 10 or 11) 1,0 GPIO64 (I/O) XD15 (I/O) 3,2 GPIO65 (I/O) XD14 (I/O) 5,4 GPIO66 (I/O) XD13 (I/O) 7,6 GPIO67 (I/O) XD12 (I/O) 9,8 GPIO68 (I/O) XD11 (I/O) 11,10 GPIO69 (I/O) XD10 (I/O) 13,12 GPIO70 (I/O) XD9 (I/O) 15,14 GPIO71 (I/O) XD8 (I/O) 17,16 GPIO72 (I/O) XD7 (I/O) 19,18 GPIO73 (I/O) XD6 (I/O) 21,20 GPIO74 (I/O) XD5 (I/O) 23,22 GPIO75 (I/O) XD4 (I/O) 25,24 GPIO76 (I/O) XD3 (I/O) 27,26 GPIO77 (I/O) XD2 (I/O) 29,28 GPIO78 (I/O) XD1 (I/O) 31,30 GPIO79 (I/O) XD0 (I/O) GPCMUX2 Register Bits GPCMUX2 bits = 00 or 01 GPCMUX2 bits = 10 or 11 1,0 GPIO80 (I/O) XA8 (O) 3,2 GPIO81 (I/O) XA9 (O) 5,4 GPIO82 (I/O) XA10 (O) 7,6 GPIO83 (I/O) XA11 (O) 9,8 GPIO84 (I/O) XA12 (O) 11,10 GPIO85 (I/O) XA13 (O) 13,12 GPIO86 (I/O) XA14 (O) 15,14 GPIO87 (I/O) XA15 (O) 16 – 31 Reserved Reserved General-Purpose Input/Output (GPIO) 82 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

www.ti.com Register Bit Definitions Figure 4-8. GPIO Port A MUX 1 (GPAMUX1) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND- R/W = Read/Write; R = Read only; -n = value after reset Table 4-12. GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions Bits Field Value Description (1) 31-30 GPIO15 Configure the GPIO15 pin as: 00 GPIO15 - General purpose input/output 15 (default) (I/O) 01 TZ4 - Trip Zone 4 (I) or XHOLDA (O). The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). 10 SCIRXDB - SCI-B receive. (I) 11 MFSXB - McBSP-B transmit frame synch (I/O) This option is reserved on devices that do not have a McBSP-B port. (2) 29-28 GPIO14 Configure the GPIO14 pin as: 00 GPIO14 - General purpose I/O 14 (default) (I/O) 01 TZ3 - Trip zone 3 or XHOLD (I). XHOLD, when active (low), requests the external memory interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I) 10 SCITXDB - SCI-B transmit (O) 11 MCLKXB - McBSP-B transmit clock (I/O) This option is reserved on devices that do not have a McBSP-B port. (2) 27-26 GPIO13 Configure the GPIO13 pin as: 00 GPIO13 - General purpose I/O 13 (default) (I/O) 01 TZ2 - Trip zone 2 (I) 10 CANRXB - eCAN-B receive. (I) 11 MDRB - McBSP-B Data Receive (I) This option is reserved on devices that do not have a McBSP-B port. (2) 25-24 GPIO12 Configure the GPIO12 pin as: 00 GPIO12 - General purpose I/O 12 (default) (I/O) 01 TZ1 - Trip zone 1 (I) 10 CANTXB - eCAN-B transmit. (O) 11 MDXB - McBSP-B, Data transmit (O) This option is reserved on devices that do not have a McBSP-B port. (2) (1) This register is EALLOW protected. See Section 5.2 for more information. (2) If reserved configurations are selected, then the state of the pin will be undefined and the pin may be driven. These selections are reserved for future expansion and should not be used. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 83 Submit Documentation Feedback

www.ti.com Table 4-12. GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions (continued) Bits Field Value Description (1) 23-22 GPIO11 Configure the GPIO11 pin as: 00 GPIO11 - General purpose I/O 11 (default) (I/O) 01 EPWM6B - ePWM 6 output B (O) 10 SCIRXDB - SCI-B receive (I) 11 ECAP4 - eCAP4. (I/O) 21-20 GPIO10 Configure the GPIO10 pin as: 00 GPIO10 - General purpose I/O 10 (default) (I/O) 01 EPWM6A - ePWM6 output A (O) 10 CANRXB - eCAN-B receive (I) 11 ADCSOCBO - ADC Start of conversion B (O) 19-18 GPIO9 Configure the GPIO9 pin as: 00 GPIO9 - General purpose I/O 9 (default) (I/O) 01 EPWM5B - ePWM5 output B 10 SCITXDB - SCI-B transmit (O) 11 ECAP3 - eCAP3 (I/O) 17-16 GPIO8 Configure the GPIO8 pin as: 00 GPIO8 - General purpose I/O 8 (default) (I/O) 01 EPWM5A - ePWM5 output A (O) 10 CANTXB - eCAN-B transmit (O) 11 ADCSOCAO - ADC Start of conversion A 15-14 GPIO7 Configure the GPIO7 pin as: 00 GPIO7 - General purpose I/O 7 (default) (I/O) 01 EPWM4B - ePWM4 output B (O) 10 MCLKRA - McBSP-A Receive clock (I/O) 11 ECAP2 - eCAP2 (I/O) 13-12 GPIO6 Configure the GPIO6 pin as: 00 GPIO6 - General purpose I/O 6 (default) 01 EPWM4A - ePWM4 output A (O) 10 EPWMSYNCI - ePWM Synch-in (I) 11 EPWMSYNCO - ePWM Synch-out (O) 11-10 GPIO5 Configure the GPIO5 pin as: 00 GPIO5 - General purpose I/O 5 (default) (I/O) 01 EPWM3B - ePWM3 output B 10 MFSRA - McBSP-A Receive frame synch (I/O) 11 ECAP1 - eCAP1 (I/O) 9-8 GPIO4 Configure the GPIO4 pin as: 00 GPIO4 - General purpose I/O 4 (default) (I/O) 01 EPWM3A - ePWM3 output A (O) 10 Reserved. (2) 11 Reserved. (2) 7-6 GPIO3 Configure the GPIO3 pin as: 00 GPIO3 - General purpose I/O 3 (default) (I/O) 01 EPWM2B - ePWM2 output B (O) 10 ECAP5 - eCAP5 (I/O) 11 MCLKRB - McBSP-B receive clock (I/O) 84 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-12. GPIO Port A Multiplexing 1 (GPAMUX1) Register Field Descriptions (continued) Bits Field Value Description (1) 5-4 GPIO2 Configure the GPIO2 pin as: 00 GPIO2 (I/O) General purpose I/O 2 (default) (I/O) 01 EPWM2A - ePWM2 output A (O) 10 Reserved. (2) 11 Reserved. (2) 3-2 GPIO1 Configure the GPIO1 pin as: 00 GPIO1 - General purpose I/O 1 (default) (I/O) 01 EPWM1B - ePWM1 output B (O) 10 ECAP6 - eCAP6 (I/O) 11 MFSRB - McBSP-B Receive Frame Synch (I/O) 1-0 GPIO0 Configure the GPIO0 pin as: 00 GPIO0 - General purpose I/O 0 (default) (I/O) 01 EPWM1A - ePWM1 output A (O) 10 Reserved. (2) 11 Reserved. (2) Figure 4-9. GPIO Port A MUX 2 (GPAMUX2) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO31 GPIO30 GPIO29 GPIO128 GPIO27 GPIO26 GPIO25 GPIO24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-13. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions Bits Field Value Description (1) 31-30 GPIO31 Configure the GPIO31 pin as: 00 GPIO31 - General purpose I/O 31 (default) (I/O) 01 CANTXA - eCAN-A transmit (O) 10 or 11 XA17 - External interface address line 17 (O) 29-28 GPIO30 Configure the GPIO30 pin as: 00 GPIO30 (I/O) General purpose I/O 30 (default) (I/O) 01 CANRXA - eCAN-A receive (I) 10 or 11 XA18 - External interface address line 18 27-26 GPIO29 Configure the GPIO29 pin as: 00 GPIO29 (I/O) General purpose I/O 29 (default) (I/O) 01 SCITXDA - SCI-A transmit. (O) 10 or 11 XA19 - External Interface address line 19 (O) 25-24 GPIO28 Configure the GPIO28 pin as: 00 GPIO28 (I/O) General purpose I/O 28 (default) (I/O) 01 SCIRXDA - SCI-A receive (I) 10 or 11 XZCS6 - External interface zone 6 chip select (O) (1) This register is EALLOW protected. See Section 5.2 for more information. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 85 Submit Documentation Feedback

www.ti.com Table 4-13. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions (continued) Bits Field Value Description (1) 23-22 GPIO27 Configure the GPIO27 pin as: 00 GPIO27 - General purpose I/O 27 (default) (I/O) 01 ECAP4 - eCAP4. (I/O) 10 EQEP2S - eQEP2 strobe (I/O) 11 MFSXB - McBSP-B Transmit Frame Synch (I/O) 21-20 GPIO26 Configure the GPIO26 pin as: 00 GPIO26 - General purpose I/O 26 (default) (I/O) 01 ECAP3 - eCAP3. (I/O) 10 EQEP2I - eQEP2 index. (I/O) 11 MCLKXB - McBSP-B Transmit Clock (I/O) 19-18 GPIO25 Configure the GPIO25 pin as: 00 GPIO25 - General purpose I/O 25 (default) (I/O) 01 ECAP2 - eCAP2 (I/O) 10 EQEP2B - eQEP2 input B (I) 11 MDRB - McBSP-B data receive (O) 17-16 GPIO24 Configure the GPIO24 pin as: 00 GPIO24 - General purpose I/O 24 (default) (I/O) 01 ECAP1 - eCAP1 (I/O) 10 EQEP2A - eQEP2 input A. (I) 11 MDXB - McBSP-B data transmit (O) 15-14 GPIO23 Configure the GPIO23 pin as: 00 GPIO23 - General purpose I/O 23 (default) (I/O) 01 EQEP1I - eQEP1 index (I/O) 10 MFSXA - McBSP-A transmit frame synch (I/O) 11 SCIRXDB - SCI-B receive (I/O) 13-12 GPIO22 Configure the GPIO22 pin as: 00 GPIO22 - General purpose I/O 22 (default) (I/O) 01 EQEP1S - eQEP1 strobe (I/O) 10 MCLKXA - McBSP-A transmit clock (I/O) 11 SCITXDB - SCI-B transmit (O) 11-10 GPIO21 Configure the GPIO21 pin as: 00 GPIO21 - General purpose I/O 21 (default) (I/O) 01 EQEP1B - eQEP1 input B (I) 10 MDRA - McBSP-A data receive (I) 11 CANRXB - eCAN-B receive (I) 9-8 GPIO20 Configure the GPIO20 pin as: 00 GPIO20 - General purpose I/O 22 (default) (I/O) 01 EQEP1A - eQEP1 input A (I) 10 MDXA - McBSP-A data transmit (O) 11 CANTXB - eCAN-B transmit (O) 7-6 GPIO19 Configure the GPIO19 pin as: 00 GPIO19 - General purpose I/O 19 (default) (I/O) 01 SPISTEA - SPI-A slave transmit enable (I/O) 10 SCIRXDB - SCI-B receive (I) 11 CANTXA - eCAN-A Transmit (O) 86 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-13. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions (continued) Bits Field Value Description (1) 5-4 GPIO18 Configure the GPIO18 pin as: 00 GPIO18 - General purpose I/O 18 (default) (I/O) 01 SPICLKA - SPI-A clock (I/O) 10 SCITXDB - SCI-B transmit. (O) 11 CANRXA - eCAN-A Receive (I) 3-2 GPIO17 Configure the GPIO17 pin as: 00 GPIO17 - General purpose I/O 17 (default) (I/O) 01 SPISOMIA - SPI-A slave-out, master-in (I/O) 10 CANRXB eCAN-B receive (I) 11 TZ6 - Trip zone 6 (I) 1-0 GPIO16 Configure the GPIO16 pin as: 00 GPIO16 - General purpose I/O 16 (default) (I/O) 01 SPISIMOA - SPI-A slave-in, master-out (I/O), 10 CANTXB - eCAN-B transmit. (O) 11 TZ5 - Trip zone 5 (I) Figure 4-10. GPIO Port B MUX 1 (GPBMUX1) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-14. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions Bit Field Value Description 31:30 GPIO47 Configure this pin as: 00 GPIO 47 - general purpose I/O 47 (default) 01 Reserved 10 or XA7 - External interface (XINTF) address line 7 (O) 11 29:28 GPIO46 Configure this pin as: 00 GPIO 46 - general purpose I/O 46 (default) 01 Reserved 10 or XA6 - External interface (XINTF) address line 6 (O) 11 27:26 GPIO45 Configure this pin as: 00 GPIO 45 - general purpose I/O 45 (default) 01 Reserved 10 or XA5 - External interface (XINTF) address line 5 (O) 11 SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 87 Submit Documentation Feedback

www.ti.com Table 4-14. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions (continued) Bit Field Value Description 25:24 GPIO44 Configure this pin: 00 GPIO 44 - general purpose I/O 44 (default) 01 Reserved 10 or XA4 - External interface (XINTF) address line 4 (O) 11 23:22 GPIO43 Configure this pin as: 00 GPIO 43 - general purpose I/O 43 (default) 01 Reserved 10 or XA3 - External interface (XINTF) address line 3 (O) 11 21:20 GPIO42 Configure this pin as: 00 GPIO 42 - general purpose I/O 42 (default) 01 Reserved 10 or XA2 - External interface (XINTF) address line 2 (O) 11 19:18 GPIO41 Configure this pin as: 00 GPIO 41 - general purpose I/O 41 (default) 01 Reserved 10 or XA1 - External interface (XINTF) address line 1 (O) 11 17:16 GPIO40 Configure this pin as: 00 GPIO 40 - general purpose I/O 40 (default) 01 Reserved 10 or XA0/XWE1 - External interface (XINTF) address line 1 or external interface write enable strobe 1 11 (O) 15:14 GPIO39 Configure this pin as: 00 GPIO 39 - general purpose I/O 39 (default) 01 Reserved 10 or XA16 - External interface (XINTF) address line 16 (O) 11 13:12 GPIO38 Configure this pin as: 00 GPIO 38 - general purpose I/O 38 (default) 01 Reserved 10 or XWE0 - External interface write enable strobe 0 11 11:10 GPIO37 Configure this pin as: 00 GPIO 37 - general purpose I/O 37 (default) 01 ECAP2 - Enhanced capture input/output 2 (I/O) 10 or XZCS7 - External interface zone 7 chip select (O) 11 9:8 GPIO36 Configure this pin as: 00 GPIO 36 - general purpose I/O 36 (default) 01 SCIRXDA - SCI-A receive data (I) 10 or XZCS0 - External interface zone 0 chip select (O) 11 7:6 GPIO35 Configure this pin as: 00 GPIO 35 - general purpose I/O 35 (default) 01 SCITXDA - SCI-A transmit data (O) 10 or XR/W - Read Not Write Strobe. Normally held high. When low, XR/W indicates write cycle is active; 11 when high, XR/W indicates read cycle is active. 88 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-14. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions (continued) Bit Field Value Description 5:4 GPIO34 Configure this pin as: 00 GPIO 34 - general purpose I/O 34 (default) 01 ECAPI - Enhanced capture input/output 1 (I/O) 10 or XREADY - External interface ready signal 11 3:2 GPIO33 Configure this pin as: 00 GPIO 33 - general purpose I/O 33 (default) 01 SCLA - I2C clock open drain bidirectional port (I/O) 10 EPWMSYNCO - External ePWM sync pulse output (O) 11 ADCSOCBO - ADC start-of-conversion B (O) 1:0 GPIO32 Configure this pin as: 00 GPIO 32 - general purpose I/O 32 (default) 01 SDAA - I2C data open drain bidirectional port (I/O) 10 EPWMSYNCI - External ePWM sync pulse input (I) 11 ADCSOCAO - ADC start-of-conversion A (O) Figure 4-11. GPIO Port B MUX 2 (GPBMUX2) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-15. GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions Bit Field Value Description 31:30 GPIO63 Configure this pin as: 00 GPIO 63 - general purpose I/O 63 (default) 01 GPIO 63 - general purpose I/O 63 (default) 10 or XD16 - External interface data line 16 (I/O) 11 29:28 GPIO62 Configure this pin as: 00 GPIO 62 - general purpose I/O 62 (default) 01 SCIRXDC - SCI-C receive data (I) 10 or XD17 - External interface data line 17 (I/O) 11 27:26 GPIO61 Configure this pin as: 00 GPIO 61 - general purpose I/O 61 (default) 01 MFSRB - McBSP-B receive frame synch (I/O) 10 or XD18 - External interface data line 18 (I/O) 11 25:24 GPIO60 Configure this pin as: 00 GPIO 60 - general purpose I/O 60 (default) 01 MCLKRB - McBSP-B receive clock (I/O) 10 or XD19 - External interface data line 19 (I/O) 11 SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 89 Submit Documentation Feedback

www.ti.com Table 4-15. GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions (continued) Bit Field Value Description 23:22 GPIO59 Configure this pin as: 00 GPIO 59 - general purpose I/O 59 (default) 01 MFSRA - McBSP-A receive frame synch (I/O) 10 or XD20 - External interface data line 20 (I/O) 11 21:20 GPIO58 Configure this pin as: 00 GPIO 58 - general purpose I/O 58 (default) 01 MCLKRA - McBSP-A receive clock (I/O) 10 or XD21 - External interface data line 21 (I/O) 11 19:18 GPIO57 Configure this pin as: 00 GPIO 57 - general purpose I/O 57 (default) 01 SPISTEA - SPI-A slave transmit enable (I/O) 10 or XD22 - External interface data line 22 (I/O) 11 17:16 GPIO56 Configure this pin as: 00 GPIO 56 - general purpose I/O 56 (default) 01 SPICLKA - SPI-A clock input/output (I/O) 10 or XD23 - External interface data line 23 (I/O) 11 15:14 GPIO55 Configure this pin as: 00 GPIO 55 - general purpose I/O 55 (default) 01 SPISOMIA - SPI-A slave out, master in (I/O) 10 or XD24 - External interface data line 24 (I/O) 11 13:12 GPIO54 Configure this pin as: 00 GPIO 54 - general purpose I/O 54 (default) 01 SPISIMOA - SPI slave in, master out (I/O) 10 or XD25 - External interface data line 25 (I/O) 11 11:10 GPIO53 Configure this pin as: 00 GPIO 53 - general purpose I/O 53 (default) 01 EQEP1I - Enhanced QEP1 index (I/O) 10 or XD26 - External interface data line 26 (I/O) 11 9:8 GPIO52 Configure this pin as: 00 GPIO 52 - general purpose I/O 52 (default) 01 EQEP1S - Enhanced QEP1 strobe (I/O) 10 or XD27External interface data line 27 (I/O) 11 7:6 GPIO51 Configure this pin as: 00 GPIO 51 - general purpose I/O 51 (default) 01 EQEP1B - Enhanced QEP1 input B (I) 10 or XD28 - External interface data line 28 (I/O) 11 5:4 GPIO50 Configure this pin as: 00 GPIO 50 - general purpose I/O 50 (default) 01 EQEP1A - Enhanced QEP1 input A (I) 10 or XD29 - External interface data line 29 (I/O) 11 90 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-15. GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions (continued) Bit Field Value Description 3:2 GPIO49 Configure this pin as: 00 GPIO 49 - general purpose I/O 49 (default) 01 ECAP6 - Enhanced Capture input/output 6 (I/O) 10 or XD30 - External interface data line 30 (I/O) 11 1:0 GPIO48 Configure this pin as: 00 GPIO 48 - general purpose I/O 48 (default) 01 ECAP5 - Enhanced Capture input/output 5 (I/O) 10 or XD31 - External interface data line 31 (I/O) 11 Figure 4-12. GPIO Port C MUX 1 (GPCMUX1) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-16. GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions Bit Field Value Description 31:30 GPIO79 Configure this pin as: 00 or 01 GPIO 79 - general purpose I/O 79 (default) 10 or 11 XD0 - External interface data line 0 (O) 29:28 GPIO78 Configure this pin as: 00 or 01 GPIO 78 - general purpose I/O 78 (default) 10 or 11 XD1 - External interface data line 1 (O) 27:26 GPIO77 Configure this pin as: 00 or 01 GPIO 77 - general purpose I/O 77 (default) 10 or 11 XD2 - External interface data line 2 (O) 25:24 GPIO76 Configure this pin as: 00 or 01 GPIO 76 - general purpose I/O 76 (default) 10 or 11 XD3 - External interface data line 3 (O) 23:22 GPIO75 Configure this pin as: 00 or 01 GPIO 75 - general purpose I/O 75 (default) 10 or 11 XD4 - External interface data line 4 (O) 21:20 GPIO74 Configure this pin as: 00 or 01 GPIO 74 - general purpose I/O 74 (default) 10 or 11 XD5 - External interface data line 5(O) 19:18 GPIO73 Configure this pin as: 00 or 01 GPIO 73 - general purpose I/O 73 (default) 10 or 11 XD6 - External interface data line 6 (O) 17:16 GPIO72 Configure this pin as: 00 or 01 GPIO 72 - general purpose I/O 72 (default) 10 or 11 XD7 - External interface data line 7 (O) SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 91 Submit Documentation Feedback

www.ti.com Table 4-16. GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions (continued) Bit Field Value Description 15:14 GPIO71 Configure this pin as: 00 or 01 GPIO 71 - general purpose I/O 71 (default) 10 or 11 XD8 - External interface data line 8 (O) 13:12 GPIO70 Configure this pin as: 00 or 01 GPIO 70 - general purpose I/O 70 (default) 10 or 11 XD9 - External interface data line 9 (O) 11:10 GPIO69 Configure this pin as: 00 or 01 GPIO 69 - general purpose I/O 69 (default) 10 or 11 XD10 - External interface data line 10 (O) 9:8 GPIO68 Configure this pin as: 00 or 01 GPIO 68 - general purpose I/O 68 (default) 10 or 11 XD11 - External interface data line 11 (O) 7:6 GPIO67 Configure this pin as: 00 or 01 GPIO 67 - general purpose I/O 67 (default) 10 or 11 XD12 - External interface data line 12 (O) 5:4 GPIO66 Configure this pin as: 00 or 01 GPIO 66 - general purpose I/O 66 (default) 10 or 11 XD13 - External interface data line 13 (O) 3:2 GPIO65 Configure this pin as: 00 or 01 GPIO 65 - general purpose I/O 65 (default) 10 or 11 XD14 - External interface data line 14 (O) 1:0 GPIO64 Configure this pin as: 00 or 01 GPIO 64 - general purpose I/O 64 (default) 10 or 11 XD15 - External interface data line 15 (O) Figure 4-13. GPIO Port C MUX 2 (GPCMUX2) Register 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-17. GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions Bit Field Value Description 31:16 Reserved 15:14 GPIO87 Configure this pin as: 00 or GPIO 87 - general purpose I/O 87 (default) 01 10 or XA15 - External interface address line 15 (O) 11 92 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-17. GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions (continued) Bit Field Value Description 13:12 GPIO86 Configure this pin as: 00 or GPIO 86 - general purpose I/O 86 (default) 01 10 or XA14 - External interface address line 14 (O) 11 11:10 GPIO85 Configure this pin as: 00 or GPIO 85 - general purpose I/O 85 (default) 01 10 or XA13 - External interface address line 13 (O) 11 9:8 GPIO84 Configure this pin as: 00 or GPIO 84 - general purpose I/O 84 (default) 01 10 or XA12 - External interface address line 12 (O) 11 7:6 GPIO83 Configure this pin as: 00 or GPIO 83 - general purpose I/O 83 (default) 01 10 or XA11 - External interface address line 11 (O) 11 5:4 GPIO82 Configure this pin as: 00 or GPIO 82 - general purpose I/O 82 (default) 01 10 or XA10 - External interface address line 10 (O) 11 3:2 GPIO81 Configure this pin as: 00 or GPIO 81 - general purpose I/O 81 (default) 01 10 or XA9 - External interface address line 9 (O) 11 1:0 GPIO80 Configure this pin as: 00 or GPIO 80 - general purpose I/O 80(default) 01 10 or XA8 - External interface address line 8 (O) 11 SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 93 Submit Documentation Feedback

www.ti.com Figure 4-14. GPIO Port A Qualification Control (GPACTRL) Register 31 24 23 16 QUALPRD3 QUALPRD2 R/W-0 R/W-0 15 8 7 0 QUALPRD1 QUALPRD0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The GPxCTRL registers specify the sampling period for input pins when configured for input qualification using a window of 3 or 6 samples. The sampling period is the amount of time between qualification samples relative to the period of SYSCLKOUT. The number of samples is specified in the GPxQSELn registers. Table 4-18. GPIO Port A Qualification Control (GPACTRL) Register Field Descriptions Bits Field Value Description (1) 31-24 QUALPRD3 Specifies the sampling period for pins GPIO24 to GPIO31. 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT 23-16 QUALPRD2 Specifies the sampling period for pins GPIO16 to GPIO23. 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT 15-8 QUALPRD1 Specifies the sampling period for pins GPIO8 to GPIO15. 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT 7-0 QUALPRD0 Specifies the sampling period for pins GPIO0 to GPIO7. 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT (1) This register is EALLOW protected. See Section 5.2 for more information. (2) TSYSCLKOUT indicates the period of SYSCLKOUT. General-Purpose Input/Output (GPIO) 94 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Figure 4-15. GPIO Port B Qualification Control (GPBCTRL) Register 31 24 23 16 QUALPRD3 QUALPRD2 R/W-0 R/W-0 15 8 7 0 QUALPRD1 QUALPRD0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-19. GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions Bits Field Value Description (1) 31-24 QUALPRD3 Specifies the sampling period for pins GPIO56 to GPIO63 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT 23-16 QUALPRD2 Specifies the sampling period for pins GPIO48 to GPIO55 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT 15-8 QUALPRD1 Specifies the sampling period for pins GPIO40 to GPIO47 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT 7-0 QUALPRD0 Specifies the sampling period for pins GPIO32 to GPIO39 0x00 Sampling Period = TSYSCLKOUT (2) 0x01 Sampling Period = 2 × TSYSCLKOUT 0x02 Sampling Period = 4 × TSYSCLKOUT . . . . . . 0xFF Sampling Period = 510 × TSYSCLKOUT (1) This register is EALLOW protected. See Section 5.2 for more information. (2) TSYSCLKOUT indicates the period of SYSCLKOUT. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 95 Submit Documentation Feedback

www.ti.com Figure 4-16. GPIO Port A Qualification Select 1 (GPAQSEL1) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-20. GPIO Port A Qualification Select 1 (GPAQSEL1) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO15-GPIO0 Select input qualification type for GPIO0 to GPIO15. The input qualification of each GPIO input is controlled by two bits as shown in Figure 4-16. 00 Synchronize to SYSCLKOUT only. Valid for both peripheral and GPIO pins. 01 Qualification using 3 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 10 Qualification using 6 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 11 Asynchronous. (no synchronization or qualification). This option applies to pins configured as peripherals only. If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. (1) This register is EALLOW protected. See Section 5.2 for more information. Figure 4-17. GPIO Port A Qualification Select 2 (GPAQSEL2) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-21. GPIO Port A Qualification Select 2 (GPAQSEL2) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO31-GPIO16 Select input qualification type for GPIO16 to GPIO31. The input qualification of each GPIO input is controlled by two bits as shown in Figure 4-17. 00 Synchronize to SYSCLKOUT only. Valid for both peripheral and GPIO pins. 01 Qualification using 3 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 10 Qualification using 6 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 11 Asynchronous. (no synchronization or qualification). This option applies to pins configured as peripherals only. If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. (1) This register is EALLOW protected. See Section 5.2 for more information. 96 General-Purpose Input/Output (GPIO) SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Figure 4-18. GPIO Port B Qualification Select 1 (GPBQSEL1) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-22. GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO47-GPIO32 Select input qualification type for GPIO32 to GPIO47. The input qualification of each GPIO input is controlled by two bits as shown in Figure 4-16. 00 Synchronize to SYSCLKOUT only. Valid for both peripheral and GPIO pins. 01 Qualification using 3 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 10 Qualification using 6 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 11 Asynchronous. (no synchronization or qualification). This option applies to pins configured as peripherals only. If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. (1) This register is EALLOW protected. See Section 5.2 for more information. Figure 4-19. GPIO Port B Qualification Select 2 (GPBQSEL2) Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-23. GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO63-GPIO48 Select input qualification type for GPIO48 to GPIO63. The input qualification of each GPIO input is controlled by two bits as shown in Figure 4-17. 00 Synchronize to SYSCLKOUT only. Valid for both peripheral and GPIO pins. 01 Qualification using 3 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 10 Qualification using 6 samples. Valid for pins configured as GPIO or a peripheral function. The time between samples is specified in the GPACTRL register. 11 Asynchronous. (no synchronization or qualification). This option applies to pins configured as peripherals only. If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. (1) This register is EALLOW protected. See Section 5.2 for more information. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 97 Submit Documentation Feedback

www.ti.com The GPADIR and GPBDIR registers control the direction of the pins when they are configured as a GPIO in the appropriate MUX register. The direction register has no effect on pins configured as peripheral functions. Figure 4-20. GPIO Port A Direction (GPADIR) Register 31 30 29 28 27 26 25 24 GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23 22 21 20 19 18 17 16 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-24. GPIO Port A Direction (GPADIR) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO31-GPIO0 Controls direction of GPIO Port A pins when the specified pin is configured as a GPIO in the appropriate GPAMUX1 or GPAMUX2 register. 0 Configures the GPIO pin as an input. (default) 1 Configures the GPIO pin as an output The value currently in the GPADAT output latch is driven on the pin. To initialize the GPADAT latch prior to changing the pin from an input to an output, use the GPASET, GPACLEAR, and GPATOGGLE registers. (1) This register is EALLOW protected. See Section 5.2 for more information. Figure 4-21. GPIO Port B Direction (GPBDIR) Register 31 30 29 28 27 26 25 24 GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23 22 21 20 19 18 17 16 GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) 98 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback

Table 4-25. GPIO Port B Direction (GPBDIR) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO63-GPIO32 Controls direction of GPIO pin when GPIO mode is selected. Reading the register returns the current value of the register setting 0 Configures the GPIO pin as an input. (default) 1 Configures the GPIO pin as an output (1) This register is EALLOW protected. See Section 5.2 for more information. Figure 4-22. GPIO Port C Direction (GPCDIR) Register 31 24 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23 22 21 20 19 18 17 16 GPIO87 GPIO86 GPIO85 GPIO84 GPIO83 GPIO82 GPIO81 GPIO80 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 GPIO79 GPIO78 GPIO77 GPIO76 GPIO75 GPIO74 GPIO73 GPIO72 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-26. GPIO Port C Direction (GPCDIR) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO87-GPIO64 Controls direction of GPIO pin when GPIO mode is selected. Reading the register returns the current value of the register setting 0 Configures the GPIO pin as an input. (default) 1 Configures the GPIO pin as an output (1) This register is EALLOW protected. See Section 5.2 for more information. The pullup disable (GPxPUD) registers allow you to specify which pins should have an internal pullup resister enabled. The internal pullups on the pins that can be configured as ePWM outputs(GPIO0-GPIO11) are all disabled asynchronously when the external reset signal (XRS) is low. The internal pullups on all other pins are enabled on reset. When coming out of reset, the pullups remain in their default state until you enable or disable them selectively in software by writing to this register. The pullup configuration applies both to pins configured as I/O and those configured as peripheral functions. SPRUFB0C–September 2007–Revised May 2009 General-Purpose Input/Output (GPIO) 99 Submit Documentation Feedback

www.ti.com Figure 4-23. GPIO Port A Pullup Disable (GPAPUD) Registers 31 30 29 28 27 26 25 24 GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23 22 21 20 19 18 17 16 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 7 6 5 4 3 2 1 0 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-27. GPIO Port A Internal Pullup Disable (GPAPUD) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO31-GPIO0 Configure the internal pullup resister on the selected GPIO Port A pin. Each GPIO pin corresponds to one bit in this register. 0 Enable the internal pullup on the specified pin. (default for GPIO12-GPIO31) 1 Disable the internal pullup on the specified pin. (default for GPIO0-GPIO11) (1) This register is EALLOW protected. See Section 5.2 for more information. Figure 4-24. GPIO Port B Pullup Disable (GPBPUD) Registers 31 30 29 28 27 26 25 24 GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 23 22 21 20 19 18 17 16 GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-28. GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions Bits Field Value Description (1) 31-0 GPIO63- Configure the internal pullup resister on the selected GPIO Port B pin. Each GPIO pin GPIO32 corresponds to one bit in this register. 0 Enable the internal pullup on the specified pin. (default) 1 Disable the internal pullup on the specified pin. (1) This register is EALLOW protected. See Section 5.2 for more information. General-Purpose Input/Output (GPIO) 100 SPRUFB0C–September 2007–Revised May 2009 Submit Documentation Feedback