Philips ISP1301 Operation & User’s Manual

Eval Kit User’s Guide February 2003 We welcome your feedback. Send it to [email protected]. Philips Semiconductors - Asia Product Innovation Centre Visit www.semiconductors.philips.com/buses/usb or www.flexiusb.com User’s Guide Rev. 1.0 Revision History: Version Date Descriptions Author 1.0 Feb 2003 First release David Wang

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 2 of 18 This is a legal agreement between you (either an individual or an entity) and Philips Semiconductors. By accepting this product, you indicate your agreement to the disclaimer specified as follows: DISCLAIMER PRODUCT IS DEEMED ACCEPTED BY RECIPIENT. THE PRODUCT IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, PHILIPS SEMICONDUCTORS FURTHER DISCLAIMS ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANT ABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE PRODUCT AND DOCUMENTATION REMAINS WITH THE RECIPIENT. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, IN NO EVENT SHALL PHILIPS SEMICONDUCTORS OR ITS SUPPLIERS BE LIABLE FOR ANY CONSEQUENTIAL, INCIDENTAL, DIRECT, INDIRECT, SPECIAL, PUNITIVE, OR OTHER DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OUT OF THIS AGREEMENT OR THE USE OF OR INABILITY TO USE THE PRODUCT, EVEN IF PHILIPS SEMICONDUCTORS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 3 of 18 CONTENTS 1. INTRODUCTION ...............................................................................................................................5 2. SYSTEM REQUIREMENTS................................................................................................................5 3. CONFIGURATIONS AND SETTINGS............................................................................................6 3.1. POWER REQUIREMENTS......................................................................................................................................................6 3.2. I 2C MASTER SELECTION ......................................................................................................................................................6 3.3. USB INTERFACE..................................................................................................................................................................7 3.4. AUDIO INTERFACE..............................................................................................................................................................7 3.5. RESET ...................................................................................................................................................................................7 4. LOCATION OF MAJOR COMPONENTS .......................................................................................7 5. TEST PROGRAM 1301.EXE ..............................................................................................................8 5.1. INTRODUCTION..................................................................................................................................................................8 5.2. RUNNING THE TEST PROGRAM..........................................................................................................................................9 5.3. USING MENUS......................................................................................................................................................................9 5.3.1. Choose I2C slave address for ISP1301..................................................................................................................................9 5.3.2. Reset all registers .........................................................................................................................................................................9 5.3.3. List all registers ..........................................................................................................................................................................10 5.3.4. Read/Write register..................................................................................................................................................................10 5.3.5. Select Mode of Operation.......................................................................................................................................................11 5.3.6. Enable/Disable charge-pump.................................................................................................................................................11 6. HARDWARE DESCRIPTION..........................................................................................................12 6.1. BLOCK DIAGRAM ..............................................................................................................................................................12 6.2. FUNCTIONAL DESCRIPTION.............................................................................................................................................12 6.2.1. PCF8584 I 2C-bus controller....................................................................................................................................................12 6.2.2. PC parallel to I 2C converter ....................................................................................................................................................12 6.2.3. HC, DC and OTG core logic interface connector.............................................................................................................12 6.2.4. Power manager..........................................................................................................................................................................13 6.2.5. Audio interface...........................................................................................................................................................................13 7. CONNECTOR PIN INFORMATION..............................................................................................13 7.1. DB-25 PC PARALLEL PORT CONNECTOR (J10) PIN ASSIGNMENT...............................................................................13 7.2. 8-BIT MICROPROCESSOR INTERFACE 20 X 2 HEADER (J13) PIN ASSIGNMENT.............................................................13 7.3. USB OTG CONTROLLER INTERFACE 8 X 2 HEADER (J8 AND J3) PIN ASSIGNMENT.................................................13 8. SCHEMATICS OF THE EVALUATION BOARD .........................................................................14 9. BILL OF MATERIALS.......................................................................................................................17 10. REFERENCES ....................................................................................................................................18

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 4 of 18 TABLES Table 3-1: +5.0 V power selection.......................................................................................................................................................................... 6 Table 3-2: VBAT and VIO selection.............................................................................................................................................................................. 6 Table 3-3: I 2C master selection................................................................................................................................................................................ 6 Table 7-1: DB-25 PC parallel port connector (J10) pin assignment..............................................................................................................13 Table 7-2: 8-bit microprocessor-interface 20 x 2 header (J13) pin assignment [1].......................................................................................13 Table 7-3: OTG Controller interface J8 pin assignment..................................................................................................................................14 Table 7-4: OTG Controller interface J3 pin assignment..................................................................................................................................14 Table 9-1: BOM of the ISP1301 evaluation board.............................................................................................................................................17 FIGURES Figure 1-1: ISP1301 evaluation board PCB layout ............................................................................................................................................... 5 Figure 4-1: Location of major components........................................................................................................................................................... 8 Figure 5-1: Test program main menu..................................................................................................................................................................... 9 Figure 5-2: List all registers screen display..........................................................................................................................................................10 Figure 5-3: Read/Write register screen display..................................................................................................................................................11 Figure 5-4: Select Mode of Operation screen display.......................................................................................................................................11 Figure 6-1: Block diagram of the ISP1301 evaluation board............................................................................................................................12 Microsoft and Windows are registered trademarks of Microsoft Corp. Intel is a registered trademark of Intel, Inc. The names of actual companies and products mentioned herein may be the trademarks of their respective owners. All other names, products, and trademarks are the property of their respective owners.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 5 of 18 1. Introduction The ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. It integrates a USB full-speed and low-speed transceiver, and other analog components to fully support OTG functionality. The ISP1301 is ideal for use in portable electronics devices, such as mobile phones, personal digital assistants (PDAs), digital still cameras, and digital audio players. The ISP1301 acts as a physical layer to interface with any USB OTG Controller. The ISP1301 evaluation board is designed to evaluate the functions of the ISP1301 chip. The main components on the board are: the ISP1301 (in HVQFN24 package), I 2C master, USB mini-AB connector, analog audio interface, and USB OTG controller interface. The operation mode of the ISP1301 can be configured through the I 2C interface. The OTG status and control registers in the ISP1301 can also be accessed through the I 2C interface. To verify the functions of the ISP1301 by using the DOS test program that is provided with the evaluation kit, connect the ISP1301 evaluation board to the parallel port of a PC. To fully verify the functions of the ISP1301, a USB OTG controller is used to connect to the ISP1301 board through the defined interface connector. Figure 1-1: ISP1301 evaluation board PCB layout 2. System requirements An x86 PC with DB-25 parallel port is required. The test program runs on DOS (or the command line in Microsoft ® Windows ® 98). In the BIOS setting, select port address 378H for the onboard parallel port. The test program is compiled using Turbo ® C++ 3.0.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 6 of 18 3. Configurations and settings 3.1. Power requirements By default, the ISP1301 board is powered by a +5.0 V power supply through the DC jack (J12, inner +). The +5.0 V power can also be supplied from the USB Type-B connector (J4). However, when J4 is connected to a USB port on the PC, leave the USB mini-AB connector (J9) unconnected. If an external microprocessor is used to control the I 2C controller chip PCF8584 (U4), the +5.0 V power can also be supplied from pin 16 and pin 18 of the microprocessor connector (J13). When the +5.0 V power is correctly applied to the board, LED2 (green) will turn ON. Table 3-1: +5.0 V power selection Jumper Descriptions JP6 Short 1(UP5V) and 2 (+5V): +5.0 V from the microprocessor interface (pin 16 or 18 of J13) Short 3 (H_VBUS) and 4 (+5V): +5.0 V from the VBUS line of the USB connector (pin 1 of J4) Short 5 (EXT5V) and 6 (+5V): +5.0 V from the DC jack (J12, inner +) [default] The power supply (VBAT pin) for the ISP1301 can be provided either from the onboard +3.3 V source or from the OTG Controller interface (pin 2 of J3). Similarly, the power supply for the VIO (called VDD_LGC in the ISP1301 datasheet) pin of the ISP1301 can be provided either from the onboard +3.3 V source or from the OTG Controller interface (pin 2 of J8). Table 3-2: VBAT and VIO selection Jumper Descriptions JP2 Short: VBAT from the onboard +3.3 V source [default] Open: VBAT from the pin 2 of J3 JP5 Short: VIO from the onboard +3.3 V source [default] Open: VIO from the pin 2 of J8 3.2. I 2C master selection The I 2C master controller can be supplied from any one of three sources: • PC parallel port (software I 2C master) • Philips I 2C controller chip PCF8584 (hardware I 2C master) • External I 2C master that is connected to the I 2C header J11. Table 3-3: I 2C master selection Jumper Descriptions JP3 Short 1 (SDA_8584) and 2 (SDA5V): SDA from PCF8584 Short 2 (SDA5V) and 3 (SDA_PC): SDA from PC parallel port [default] Open: SDA from I 2C connector (pin 4 of J11) JP4 Short 1 (SCL_8584) and 2 (SCL5V): SCL from PCF8584 Short 2 (SCL5V) and 3 (SCL_PC): SCL from PC parallel port [default] Open: SCA from I 2C connector (pin 3 of J11) Note: SCL and SDA come from the same I 2C master.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 7 of 18 3.3. USB interface There are three USB connectors on the ISP1301 evaluation board. • If an OTG Controller is connected to the ISP1301, the USB port functions as an OTG dual-role device and only the mini-AB connector (J5) will be used. • If a Host Controller is connected to the ISP1301, the USB port functions as a host and only the Type-A connector (J1) will be used. • If a Device Controller is connected to the ISP1301, the USB port functions as a device and only the Type- B connector (J4) will be used. You can use all the three ports at the same time. If you have a system that consists of a USB host port and a separate device port, then the host port can be connected to J4 and the device port can be connected to J1 using the standard USB cable. In such a case, the ISP1301 provides only OTG functions to the system; the transceiver function of the ISP1301 is not used. 3.4. Audio interface The ISP1301 evaluation board has an interface to support an analog audio carkit application. Connect: • The audio carkit to the mini-AB connector (J9) on the board; • The audio input line signal to the SPK LINE IN socket (J6) on the board; • The audio output line signalto the MIC LINE OUT socket (J7) on the board. 3.5. Reset For a hardware reset to the ISP1301, press the manual reset switch (SW1). The reset pulse (active LOW) can also come from the OTG Controller interface (pin 8 of J3). 4. Location of major components Figure 4-1 shows the location of major components on the evaluation board.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 8 of 18 J13 U1 J9 J3 J1 J4 J10 J8 U4 J11 J6 J7 J 5 J 2 J12 JP6 JP4 JP3 JP1 JP5 JP2 ISP1301 EVALUATION BOARD REV 1.0 SW1 Figure 4-1: Location of major components 5. Test program 1301.EXE 5.1. Introduction A DOS test program “1301.exe” is provided to help you verify the functions of the ISP1301 chip. The program uses the PC parallel port to access the ISP1301 registers through the I 2C interface. The program simulates software I 2C master at the hardware abstraction layer (HAL). The test program can do the following: • Set the I 2C slave address for the ISP1301 based on the hardware setting of the ADR pin • Reset all registers to their default values • Display the current value of all registers on your PC screen • Write any value to a writable register • Set the mode of operation of the ISP1301 (such as, USB function and suspend mode, transparent I 2C mode, transparent general-purpose buffer mode, and global power-down mode) • Enable or disable the charge pump of the ISP1301.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 9 of 18 5.2. Running the test program If your PC boots to pure DOS, run the test program on the command line. If your PC boots to Microsoft Windows 98, open an MS-DOS window and run the test program. It is recommended that you boot the PC to pure DOS. To run the test program, type 1301 1 and press the Enter key at the command prompt. Note: In the BIOS setting of the PC, the I/O address for the onboard parallel port is 378H. 5.3. Using menus After the program has been launched, the main menu will appear on the screen. See Figure 5-1. Figure 5-1: Test program main menu In the main menu screen, selecting any item 1–6 will perform the desired action. If you wish to exit the program, press the Esc key. The following sections describe the menu items. 5.3.1. Choose I2C slave address for ISP1301 The program will prompt you to enter your choice based on the hardware setting of the ADR pin. • If ADR is HIGH, select 1. The slave address for the ISP1301 will become 0x5A. • If ADR is LOW, select 0. The slave address for the ISP1301 will become 0x58. Make sure that choices are done correctly; otherwise, other operations may fail. If you set the ISP1301 to the transparent I 2C mode and choose a slave address value other than the value set here, you must set it back to the original slave address when you revert to the direct I 2C mode. 5.3.2. Reset all registers On selecting this option, the program will set all the registers—excluding the read-only registers—to their default values and display these values on your PC screen. 1 In this document, items that you type or click are indicated in bold.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 10 of 18 5.3.3. List all registers On selecting this option, the program will display all the 22 registers on the screen. See Figure 5-2. Figure 5-2: List all registers screen display 5.3.4. Read/Write register The program will display the current value of all registers and prompt you to write to a specific register. On selecting item 4 from the main menu, the program will display the screen given in Figure 5-3. The program will prompt you to type the address of the register whose value you want to change. On entering the address of the register and pressing Enter, the program will prompt you to enter the new value that you want to assign. If you want to return to the main menu, type FF at the command prompt.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 11 of 18 Figure 5-3: Read/Write register screen display 5.3.5. Select Mode of Operation You can select the mode of operation of the ISP1301 by selecting item 5 from the main menu. A submenu will appear on the screen. See Figure 5-4. The possible choices include the USB functional mode (four data encoding and decoding methods), transparent I 2C mode, transparent buffer mode, USB suspend mode, and global power- down mode. Note: If the ISP1301 Engineering Sample 1 (ES1) (that is, the chip whose version register reads 0x0100, or the chip package is marked ####AX) is mounted on the evaluation board, software cannot wake up the chip, if set to the global power-down mode. Only a hardware reset can wake up the chip. Figure 5-4: Select Mode of Operation screen display 5.3.6. Enable/Disable charge-pump If the charge pump in the ISP1301 is disabled, selecting menu item 6 will enable the charge pump. If the charge pump is enabled, selecting menu item 6 will disable it.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 12 of 18 6. Hardware description 6.1. Block diagram Figure 6-1 shows the block diagram of the ISP1301 evaluation board. ISP1301 OTG TRANSCEIVER AUDIO INTERFACE (L/R SPEAKER LINE IN, MIC PRE-AMP OUT) PC PARALLEL-TO-I2C CONVERTER PCF8584 I2C-BUS CONTROLLER POW ER MANAGER ISA PARALLEL DP, DM, ID, VBUS I2C-BUS (SCL, SDA, ADR, INT) DP, DM, ID VBUS HC, DC and OTG CORE LOGIC INTERFACE CONNECTOR (to the ISP1362 FPGA or Phone FPGA) CORE INTERFACE (OE, VP, VM, RCV, SPEED, SUSPEND, RESET, VDD_LGC) FPGA INTERFACE VBAT mini-AB Receptacle Vext 4-PIN I2C HEADER Figure 6-1: Block diagram of the ISP1301 evaluation board 6.2. Functional description A brief description of each function module is given in the following sections. 6.2.1. PCF8584 I 2C-bus controller This block provides functions of the I 2C-bus to the 8-bit parallel-bus converter. It can connect to the Philips ISP1362 or ISP1161x ISA interface board, or any other generic 8-bit microprocessor interface through a 40-wire IDE cable. The PC or other microprocessor can service the interrupt from the ISP1301 and access the registers of the ISP1301 through this interface. 6.2.2. PC parallel to I 2C converter This interface provides an alternative method to access the ISP1301 I 2C interface through the PC. The PC needs to emulate software I 2C master to access the ISP1301 I 2C slave. 6.2.3. HC, DC and OTG core logic interface connector This interface provides connection to a Host Controller (HC), Device Controller (DC) or On-The-Go (OTG) core logic. This interface is used during OTG system-level evaluation or during compliance testing.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 13 of 18 6.2.4. Power manager This block includes the 5.0 V-to-3.3 V regulator and power source selection. 6.2.5. Audio interface This block provides stereo audio line IN interface and microphone (with pre-amp) OUT interface. Its main purpose is to demonstrate the carkit application (play audio or voice with carkit). 7. Connector pin information 7.1. DB-25 PC parallel port connector (J10) pin assignment J10 is used to connect to the PC parallel port through the DB-25 printer cable. Table 7-1 shows its pin assignment. Table 7-1: DB-25 PC parallel port connector (J10) pin assignment Pin no Printer port signal ISP1301 evaluation board signal 9 D7 SDAOUT# 11 S7# SDAIN# 15 S3 SCLIN 17 C3# SCLOUT# 10,13,18–25 — GND 1–8,12,14,16, — No connection 7.2. 8-bit microprocessor interface 20 x 2 header (J13) pin assignment J13 is used to connect to a generic 8-bit parallel bus microprocessor controller. The bus uses the Intel ® mode. Required signals include D0–D7, A0, WR_N, RD_N, CS_N, INT1 and INT2. Table 7-2 shows the pin assignment for J13. Note: We use a 20 x 2 header to make it compatible with the Philips ISP1362 and ISP1161x ISA interface boards. Table 7-2: 8-bit microprocessor-interface 20 x 2 header (J13) pin assignment [1] Pin no Pin name Pin no Pin name Pin no Pin name Pin no Pin name 1 GND 11 n. c. 21 D7 31 D2 2 n. c. 12 +3.3 V 22 INT2 32 n. c. 3 n. c. 13 n. c. 23 D6 33 D1 4 CHRG_EN 14 n. c. 24 INT1 34 WR_N 5 n. c. 15 n. c. 25 D5 35 D0 6 n. c. 16 +5.0 V 26 n. c. 36 RD_N 7 n. c. 17 n. c. 27 D4 37 n. c. 8 n. c. 18 +5.0 V 28 n. c. 38 CS_N 9 n. c. 19 GND 29 D3 39 A0 10 +3.3 V 20 n. c. 30 n. c. 40 n. c. [1] n. c.—Denotes no connection. Note: An external OTG Controller system can use the CHRG_EN signal to enable or disable +5.0 V from the VBUS line of the mini-AB connector to pin 2 of J2. This is useful when an analog audio carkit is attached and the carkit can charge the external battery. 7.3. USB OTG Controller interface 8 x 2 header (J8 and J3) pin assignment Header connectors J8 and J3 are used to connect the ISP1301 to the OTG Controller core. J8 includes the USB Serial Interface Engine (SIE) signals—DAT_VP, SE0_VM, RCV and OE_TP_INT_N—and I 2C signals—SDA, SCL and INT_N. J3 also includes other signals that may be used by selected OTG Controller.

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 14 of 18 Table 7-3: OTG Controller interface J8 pin assignment Pin no Pin name Pin no Pin name 1 GND 9 GND 2 VIO 10 OE_TP_INT_N 3 GND 11 GND 4 INT_N 12 DAT_VP 5 GND 13 GND 6 SDA 14 SE0_VM 7 GND 15 GND 8 SCL 16 RCV Table 7-4: OTG Controller interface J3 pin assignment Pin no Pin name Pin no Pin name 1 GND 9 GND 2 VBAT 10 SPEED 3 GND 11 GND 4 n. c. 12 SUSPEND 5 GND 13 GND 6 ADR 14 VM 7 GND 15 GND 8 RESET_N 16 VP 8. Schematics of the evaluation board

C11 0.1uF C10 0.1uF C1 0.1uF C14 22pF C15 22pF C12 28nF C13 120nF 1 2 JP1 JUMPER SW1 SW-PB + C6 4.7uF16V + C4 4.7uF16V + C3 4.7uF16V ISP1301 EVALUATION BOARD A +C16 4.7uF16V R6 10K R7 10K R8 10K R9 10K R10 10K VIO VBAT VIO R15 10K + C17 1uF VIO PAD 1 TP1 VBUS PAD 1 TP3 ID PAD 1 TP2 D- PAD 1 TP4 D+ R11 100R R12 100R C7 220nF C8 220nF C9 220nF R16 100R A 1 B 2 C 3 J6 PHONEJACK STEREO(SPK LINE IN) J7 PHONEJACK(MIC LINE OUT) VBUS D- D+ ID 1 4 7 8 5 6 2 3 Q1 PHP125 R4 0 R3 10K C5 0.1uF CHRG_EN 3 2 1 D1 STZ5.6N VBUS 1 D- 2 D+ 3 GND 4 CHASSIS 5 J1 USB A-RECEPTACLE VBUS 1 D- 2 D+ 3 GND 4 CHASSIS 5 J4 USB B-RECEPTACLE H_VBUS D- D+ +5V + C2 10uF16V R1 0 R2 0 ADR SDA SCL RESET_N INT_N SPEED SUSPEND OE_TP_INT_N VM VP RCV SE0_VM DAT_VP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J3 HEADER 8X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J8 HEADER 8X2 ADR SDA SCL RESET_N INT_N SPEED SUSPEND OE_TP_INT_N VM VP RCV SE0_VM DAT_VP VIO VBAT ISP1301 PORT V1.0 1/2 LOUT LIN_L LIN_R VBUS D- D+ ID GND SHIELD 1 2 3 4 5 6 J5 HEADER 6 SHIELD LED1 5.0V R5 4.7K NOT INSTALL LOUT LIN_L LIN_R GND 5VOUT VBUS VBUS 5VOUT 1 2 3 4 5 6 J2 HEADER 6 GND D_VBUS C50 0.1uF

ISP1301 EVALUATION BOARD V1.0 2/2 +5V C51 0.1uF C53 0.1uF C52 0.1uF +5V +5V +5V

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 17 of 18 9. Bill of Materials Table 9-1: BOM of the ISP1301 evaluation board Part Type Quantity Designator Footprint 18pF +80%/-20% 3 C29, C30, C31 0805 22pF ±10% 2 C14, C15 0805 28nF ±10% 1 C12 0805 120nF ±10% 1 C13 0805 220nF ±10% 3 C7, C8, C9 0805 0.1uF+80%/-20% 11 C1, C5, C10, C11, C19, C21, C22, C23, C24, C26, C28 0805 1uF+80%/-20% 1 C17 1206 4.7uF16V 4 C3, C4, C6, C16 RB.1/.2 10uF16V 5 C2, C18, C20, C25, C27 RB.1/.2 0R 3 R1, R2, R4 0805 33R ±%1 2 R13, R14 0805 100R 3 R11, R12, R16 0805 3.3K 4 R20, R21, R22, R23 0805 4.7K 2 R5, R24 0805 10K 10 R3, R6, R7, R8, R9, R10, R15, R17, R18, R19 0805 12MHz OSC_HALF 1 Y1 XTAL-CTX ISP1301 1 U1 HVQFN24 74HCT05 1 U2 SOP14 74HCT04 1 U3 SOP14 PCF8584 I2C CONTROLLER 1 U4 DIP20 PHP125 P-MOSFET POWER MOS 1 Q1 SO8 ZVN4206 N-MOSFET 2 Q2, Q3 TO92 LM1117DT33 3.3V REGULATOR 1 Q4 TO252 STZ5.6N ESD DIODE 1 D1 SOT346 LED 2 LED1, LED2 Thru'hole DB25 (MALE) 1 J10 Thru'hole HEADER 3 2 JP3, JP4 Thru'hole HEADER 4 1 J11 Thru'hole HEADER 3X2 1 JP6 Thru'hole HEADER 6 2 J2, J5 Thru'hole HEADER 8X2 2 J3, J8 Thru'hole HEADER20X2 1 J13 Thru'hole JUMPER 3 JP1, JP2, JP5 Thru'hole PHONEJACK (MIC LINE OUT) 1 J7 PHONEJACK PHONEJACK STEREO (SPK LINE IN) 1 J6 PHONEJACK STEREO POWER JACK 1 J12 DC JACK SW-PB 1 SW1 SW-TACT USB A-RECEPTACLE 1 J1 USB A USB B-RECEPTACLE 1 J4 USB B USB mini-AB RECEPTACLE 1 J9 USB mini-AB

UM10028_1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. User’s Guide Rev. 1.0—February 2003 18 of 18 10. References • ISP1301 USB On-The-Go Transceiver datasheet • Universal Serial Bus Specification Rev. 2.0 • On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0 • ISP1301 Errata