DEC VR14 Operation & User’s Manual

monitor user's manual EK-VR14-0P-005 digital equipment corporation:. maynard. massachusetts

2nd Printing (Rev) June 1971 3rd Printing (Rev) June 1972 4th Printing (Rev) January 1973 5th Printing, July 1973 2nd Edition, December 1973 7th Printing, November 1974 Copyright © 1971,1972, 1973, 1974 by Digital Equipment Corporation The material in this manual is for infonnational purposes and is subject to change without notice. Digital Equipment Corporation assumes no respon- sibility for any errors which may appear in this manual. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC FLIP CHIP DIGITAL PDP FOCAL COMPUTER LAB

SPECIFICATIONS ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1 BLOCK DIAGRAM DESCRIPTION ............................. 1-3 OPERATION INSTALLATION ...................................... 2-1 FRONT PANEL CONTROLS ................................ 2-1 REAR PANEL CONNECTORS ............................... 2-2 INTERNAL CONTROLS .................................. 2-2 INPUT SIGNAL REQUIREMENTS ............................. 2-2 THEORY OF OPERATION X- AND Y- DEFLECTION CIRCUITS .......................... " 3-1 PLUS AND MINUS LOW VOLTAGE REGULATED SUPPLY ............... 3-5 CRT ELECTRODE VOLTAGES ............................. " 3-6 HIGH VOLTAGE POWER SUPPLY ............................. 3-6 W682 AND W684 INTENSITY CIRCUITS ......................... 3-10 LIGHT PEN AMPLIFICATION ............................... 3-13 375 Light Pen ..................................... 3-14 MAINTENANCE PREVENTIVE MAINTENANCE .............................. 4-1 TROUBLESHOOTING ................................... 4-1 No Picture ....................................... 4-1 Faulty Picture ..................................... 4-5 ASSEMBLY REPLACEMENT INSTRUCTIONS ...................... 4-5 Deflection Heat Sink Removal ............................. 4-5 7007165 Power Regulator Assembly Removal ........ . . . . . . . . . . . .. 4-7 Regulator Heat Sink Removal ............................. 4-9 Yoke and CRT Removal ................................ 4-9 High Voltage Supply Removal ............................. 4-11 ENGINEERING DRAWINGS POWER SUPPLY TROUBLESHOOTING DEFLECTION AMPLIFIER TROUBLESHOOTING A225 REPAIR iii

VRI4L/VRI7L Block Diagram Input Power Jumper ..... Locations of Internal Controls X and Y Deflection Circuit . . G836 Circuit Board, Part of the 7007165 Power Regulator Assembly Intensity Amplifier W682, Circuit Schematic W684 Intensity Control ........... . G838 Circuit Diagram ............ . VRI4L/VRI7L Brightness and Contrast Control Ligh t Pen Amplifier ........ . Light Pen Pulse Timing, G840 Module VRI4/VRI7 Interior View .... . Deflection Heat Sink Removal .. . 7007165 Power Regulator Assembly 7007165 Removal ..... Regulator Heat Sink Removal TABLES VR14 and VR17 Configurations . J 17 Rear Connector Pin Assignments J18 Rear Connector Pin Assignments Control Settings ........ . Brightness Control ....... . VRI4/VRI7 Voltage Check Points VR14 Engineering Drawings VR17 Engineering Drawings ... Title iv Page 1-4 1-5 2-1 2-6 3-3 3-7 3-9 3-10 3-11 3-12 3-13 3-14 4-3 4-6 4-7 4-8 . 4-10 Page 1-1 2-3 2-5 2-7 3-12 4-2 5-1 5-1

by qualified service personnel only. High voltages are present within the unit and, under certain conditions, are potentially dangerous. All electrical safety precautions must be observed. Inherent implosion protection is employed in the CRT design; however, the tube may be damaged if it is subjected to rough treatment or dropped while being removed from or installed in the display. Exercise caution during these operations.

display monitors that require only analog X- and Y-position information and an intensity input, to generate sharp, bright displays. The VR14 and VR17 are electrically identical. The VR17, however, has a larger display screen (17 inches diagonal) than the VR14 (12 inches diagonal). This necessitates a correspondingly larger enclosure, and a CRT support bracket for the VR17. Except for the CRT itself, both VR14 and VR17 are composed of fully solid state circuits, utilizing high-speed magnetic deflection to enhance brightness and resolution. The inputs for the X- and Y - deflection may be balanced or single ended, bipolar or offset, and positive- or negative-going without any modification to the VR14/VR17. The VR14 and VR17 come in several configurations, listed in Table 1-1. Table 1-1 VR14 and VR17 Configurations Designation Mounting Power Light Pen Option VR14-0 Rack 115V No VR14-A Rack 230 V No VR14-B Rack 100V No VR14-C Table 115V No VR14-D Table 230 V No VR14-E Table 100V No VR14-LC Table 115 V Yes VR14-LD Table 230 V Yes VR17-LC Table 115 V Yes VR17-LD Table 230V Yes The VR14 versions without the light pen option contain a W682 Intensity Control Circuit Board and a G838 Fault Protection Circuit Board, as well as a front panel CHANNEL switch which operates with the W682 board. In CHAPTER 1 GENERAL INFORMATION 1-1 this variation, intensity pulses may be time multiplexed or gated by a separate input to allow the screen to be timeshared by two inputs. The VR14/VR17 versions with the light pen option (VR14-LC, VR14-LD, VR17-LC, VR17-LD) do not have this timesharing capability nor channel selectivity. They contain a W684 Intensity Control Circuit Board in place of the W682, and a G840 Light Pen Amplifier in place of the G838. The G840 circuit board, however, contains the fault protection circuitry of the G838 board. 1.2 SPECIFICATIONS VR14/VR17 specifications are as follows: Physical: Height Width Depth Weight Viewable VR14 10-1/2 in. (267 mm) 19 in. (483 mm) 17 in. (432 mm) 75 lb (34 kg) VR17 15 in. (381 mm) 21-1/2 in. (546 mm) 27 in. (686 mm) 85 lb (39 kg) Area 6-3/4 in. X 9 in. 8-1/4 in. X 11 in. (171.45 X 228.6 mm) (210 X 280 mm) VR14 and VR17 Spot Size: < 20 mils inside the usable screen area at a brightness of 30 fL Jitter: < ±1 /2 spot diameter Repeatability: < ± 1 spot diameter (Repeatability is the deviation from the nominal loca- tion of any given spot)

change for each ±1 % line voltage variation Temperature Range: 0° to 50° C (operating) Relative Humidity: 10% to 90% (noncondensing) Brightness: ~ 30 fL for VRI4, ~ 25 fL for VRI7; measured using a shrinking raster technique Linearity: Maximum deviation of any straight line is ~ 1 % of the line length, measured perpendicular to a best-fit straight line. Deflection Method: Magnetic (70° diagonal deflection angle) Focus Method: Electros ta tic High Voltage: 10.5 kV dc nominal (voltage proportional to input line voltage). Supply is self-contained and equipped with a bleeder resistor. Shielding: CRT is fully enclosed in a magnetic shield. Overload Protection: Unit is protected against fan failure or air blockage by thermal cutouts. Power supply and amplifiers are current limited. Phosphor protection is provided against fault conditions. Deflection Amplifier a. Deflection amplifiers are dc coupled and are capable of sustaining a full screen ac or dc deflection at environmental extremes. b. Input Specifications: 1. Inputs are differential. 2. Differential input impedance,S kQ minimum. 3. Input sensitivity, 500 mY/inch maximum (200 m V linch with resistor change) 1-2 4. Common mode rejection ratio, 40 dB 5. Maximum operating input, ±6 V. (Maximum oper- ating input is the sum of the common mode input and the differential input.) 6. Input offset not to exceed ±1/2 peak-to-peak input signal. 7. Maximum nonoperating input, ±50 V c. Full screen deflection and settling time to within ±1 spot diameter, ~ 18 }J.S. d. Small signal settling time to within 1/2 spot diameter, ~1 }J.s for a 0.1 inch deflection e. Small signal linear slew rate, ~ 0.4 inch/l }J.S f. Velocity error coefficient, 500 ns maximum (average ramp delay between input and output) Z-Axis (on VR14 without Light Pen Option) a. Z-Input - A negative transition from ~ +2.4 V, but not exceeding +8 V, to ~ +0.8 V, but not more negative than -4 V, in ~ 20 ns, causes an unblanking pulse at the CRT cathode from approximately +62 V to ground with a duration of ~ 200 ns at the 50 percent points. Delay between the 50 percent point of the negative input transition to the 50 percent point of the output pulse is less than 100 ns. Driver must sink 4 rnA. b. Z-Direct - A positive-going pulse not exceeding 65 V, but at least 45 V in height and not exceeding 10 }J.S, but at least 1 }J.S in duration, unblanks the CRT to a viewable intensity. This signal is ac coupled to the CRT grid. c." Channel Select - With the Channel Select Switch in the Channell position, a positive level of greater than +2.4 V, but not exceeding +8 V, enables the Z-input circuit. A level of less than +0.8 V, but not more negative than -4 V, disables the circuit. With the switch in the Channel 2 position, a positive level disables the Z-circuit; a negative level enables it. Placing the switch in the Channel 1 & 2 position disables this input.

and VR17L)] a. Z-Input - This is a TTL logic signal. When a TTL low, it un blanks the CRT by causing the cathode voltage to change from approximately +62 V to ground. The CRT will remain unblanked as long as the Z-input is at a logic low. b. Intensity 0, 1, 2 - These three signals, together with" the brightness control, generate a voltage of from - 80 V to 0 V on the CRT grid 1, to determine image brightness. The combination of the three intensity signals asserts one of eight possible analog voltages, which in turn is ANDed with the output of the brightness control to generate a grid voltage in the 0 to - 80 V range. Thus, there are eight intensity levels at each of the infinite positions of the brightness control. Power a. All power supplies necessary for operation of the unit are self-contained. b. Input Requirements Voltage: (Selectable by tap changes) 100 V ± 10% 115 V ± 10% 230 V ± 10% Frequency - 50-60 Hz Power - ::;:;;;; 500 W Current - ::;:;;;; 5 A Type - Single Phase 1.3 BLOCK DIAGRAM DESCRIPTION Figure I-I is the functional block diagram of the VR14 without the light pen option. The X- and Y - position signals are connected to their respective A225 Deflection Ampli- fier Circuit Boards. The A225s boost the input signal to a level sufficient to drive the power transistors, while also providing gain and position controls. In turn, the power transistors drive the deflection yoke that positions the electron beam on the screen. The yoke currents are then passed through a 0.5 n resistor that converts the yoke currents back into voltages that are used as feedback for each A225 deflection amplifier. This feedback allows the A225 to produce an exact current replica in the yoke of the input signals. The intensity input is applied to the W682 circuit board that converts this input to a 60 V pulse which drives the cathode. The cathode pulse is negative going; this pulse turns on the electron beam, creating a spot on the screen. 1-3 The W682 accepts a gating input that allows the intensity pulse to be time-multiplexed between two input sources. The G838 Fault Protection Board disables the intensity circuit in the event of a ±22 V failure. This prevents the phosphor screen from burning, as there would be no deflection under these conditions. Line power is passed through a fuse, an on-off switch, and then through one normally closed thermal cutout switch. The switch is located on the +22 V regulator heat sink, and in the event of a fan failure or excessive temperature on the heat sink, VRI4/VRI7 input power will be shut off until it cools down. The line power is then connected to the power transformer, the high voltage power supply, and the fans. The high voltage supply converts the input line voltage to 10.5 kV that is connected to the CRT anode. The power transformer has three basic secondaries: a 6.3 V for fila- ment, a 70/150 for CRT electrodes, and a 72 V center tapped for deflection. The 72 Vac is rectified and filtered to provide ±43 Vdc unregulated. This ±43 Vdc is regulated with circuits on the G836 board, along with four power transistors on the regulator heat sink assembly. The regulated output is ±22 Vdc and is distributed to the deflection amplifiers. The 70/150 ac is rectified and filtered on the G836 to generate ±80 V dc and +400 V dc. The -80 Vdc is used for the brightness potentiometer which is tied to the grid. One side of the brightness control is connected to another potentiometer on the G836 which can adjust the maximum brightness range of the brightness potentiometer. The +400 Vdc is supplied directly to grid 2 and also to one side of the focus potentiometer on the G836 board. The wiper of the focus potentiometer goes directly to the focus electrode on the CRT. Figure 1-2 is a block diagram of the VRI4L and VRI7L, i.e., VRI4/VRI7 with the light pen option. Note that the G840 Light Pen Amplifier replaces the G838 Fault Protec- tion Circuit Board. The G840 contains the G838 circuitry as well as an amplifier to detect and shape pdse outputs from the light pen. The output of the light pen amplifier is brought out of the VRI4L/VRI7L through pin 19 of the 24-contact amphenol connector (117) at the rear of the display monitor. Note that in the VRI4L and VRI7L, the W684 intensity control replaces the W682. The W684 allows an intensity pulse to the cathode whose duration is equal to that of the Z intensify signal. The W684 circuitry also modifies the grid I bias voltage, thereby allowing eight intensity levels for a particular setting of the front panel brightness control. All other circuits represented in Figure 1-2 are identical to those represented in Figure I-I.

FROM THERMAL CUTOUT 115VAC~ 115VAC POWER TRANSFORMER 115 VAC UNIT POWER RECTIFIERS + FILTER CAP. CHANNEL 1>---------------~~~----~ CHANNEL 2»--------~o Z INTENSITY >--------------.... +22V -22V POWER SUPPLY a REGULATOR BOARD G836 +80V X FEEDBACK X INPUT >-------------t THERMAL CUTOUT ~-------+ +22V ~------+ -22V ~------+ FOCUS X POWER TRANSISTOR y Y INPUT >---------1" ~~~tl~~~~N ~_---I" PO~ER A225 RANSISTOR 115VAC HIGH VOLTAGE POWER SUPPLY 10.500VDC ANODE 0.5 J'l. .?"'I---~+-~- CURRENT SAMPLE +20V -20V ~t GAIN Y IpOSITIONI r;;;l---< 115 L.:.::.J----< VAC 0.5.n. CURRENT SAMPLE Y FEEDBACK CP-0758 Figure 1-1 Block Diagram ofVR14 Without Light Pen Option

115VAC POWER TRANSFORMER 115 VAC UNIT POWER RECTIFIERS + FILTER CAP. INTENSITY 0'>--------------....., l~tt~~IH 1 >-__________ ----I~L---__, POWER SUPPLY a REGULATOR BOARD GS36 THERMAL CUTOUT ~------+ +22V ~------+ -22V r-------. FOCUS ~------++400V ~------+ +SOV ~--------+ -SOY r--~-'---......L.----1 DEFLECTION YOKE 115VAC HIGH VOLTAGE POWER SUPPLY 10,500VDC ANODE INTENSITY OUT C>-------------~ ~--__=_------:---==::;j~~-~.i:~==~ LIGHT PEN INPUT +22V -22V LIGHT PEN PULSE -x INPUT >------~ +YINPUT>------~~ -Y INPUT>----------~ Y FEEDBACK Figure 1-2 VR14L/VR17L Block Diagram 0.5.n. ,2>----+--iI-+- CURRENT X POWER TRANSISTOR Y POWER RANSISTOR +22V -22V r;;:;l---< 115 L..::J----< VAC SAMPLE 0.5 J), CURRENT SAMPLE cp- 0760

by 10-1/2 inch (l0-7/16 inch) rack-mounted unit or as a table-top model (without chassis slides) with its own decorator cover. 'The VR17 comes only in a table-top model. The VR14/VR17 can operate from a power line frequency between 47 and 63 Hz. The input line voltage, however, is specified by a letter designation after the VR14/VR17 (O,C is 115 V; A,D is 230 V; and B,E is 100 V). The VR14/VRI7 can operate with any of the three input line voltages simply by changing the jumpers and interconnections on TB 1 and TB2 (Figure 2-1 and drawing D-CS-7007084-0-1 ). Equipment cooling is the most important VR14/VR17 installation requirement. Fans draw air from the bottom of the unit; therefore, at least 1 inch of free air space must be provided below the bottom chassis. The table-top model keeps the bottom 1 inch above the table surface. In the rack-mounted unit, if equipment is mounted immediately below the VR14, as long as there is open area under the VR14 fans (a screen is acceptable; a solid plate closer than 1 inch is not), proper cooling can occur. The same requirements apply, on the rack-mounted unit, to the area immediately above the unit. The table-top model has a solid top cover. The cooling air exits from the rear of the unit. Therefore, at least 2 inches of free space must be provided immediately behind the unit. (Do not push the VRI4/VRI7 flush against a wall or solid vertical surface that would cut off air circulation.) NOTE Before applying power to the VR14/VR17, ensure that the position potentiometers are set for the particular input signals being used. Because of the universal nature of allowable input signals, the deflection amplifiers may be driven into saturation far off screen by position settings. Leaving the deflection amplifiers satu- rated way off screen continuously may cause damage. See Paragraph 2.S and Table 2-2 for proper settings. 2-1 Interchange Orange with Red (from Transformer) TBl TBl 1 (2) 3 4 5 @ TBl CHAPTER 2 OPERATION 115 Vac TB2 1 ~ __ ~ju_m~p_er ____ ~~ 3 4 5 ~ __ ~ju_m~p_er ____ ~@ 230 Vac TB2 1 ~ jum 3 per 4 5 ® 100 Vac TB2 jumper 4 5 jumper ® Interchange White with Gray (from Transformer) Figure 2-1 Input Power Jumper 2.2 FRONT PANEL CONTROLS The on/off, brightness control, and the channel select control (not applicable to VRI4L/VRI7L) are located on the front panel. The on/off switch turns on input power to the VRI4/VRI7 when the knob is rotated clockwise from the maximum counterclockwise off position. Turning the knob clockwise also increases the brightness of the dis-

before information appears on the screen while the CRT filament warms up. In an operating system, it is recom- mended that power be left on the display even when it is not in continuous use so that the filament warmup delays do not occur. The channel select switch on VR14s without the light pen option works in conjunction with the channel select signal applied at the rear connector. When not using the dual- channel feature, the select switch should be in the 1 & 2 position. When using the dual-channel system, points on the screen will be intensified from Z-intensity inputs only when the channel select signal at the rear connector is high and the channel select switch is in the Channell position. If the channel select input signal goes low while the select switch is at 1, intensification ceases. On the other hand, the Channel 2 position works in the opposite manner. If the channel select input signal is low and the select switch is at 2, Z-intensification signals will intensify on the screen. Thus, if a group of information points is to be separated from another group, separation can be achieved by having group 1 intensification pulses occur only when the Z-select line is high, and group 2 intensification pulses occur only when the Z-select line is low. Channel select position 1 & 2 overrides the select input signal and displays every intensifi- cation pulse of both channels at once. To observe only Channel 1 information, select Channel 1 and all Channel 2 signals are locked out. By selecting Channel 2, only Channel 2 signals are displayed. 2.3 REAR PANEL CONNECTORS The rear panel has an Amphenol 14·contact connector (JI8) and an Amphenol 24-contact connector (JI 7). Tables 2-1 and 2-2 list rear connector pin assignments. 2.4 INTERNAL CONTROLS The VR14/VRI7 internal adjustments include six potenti- ometers: X position, X gain, Y position, Y gain, focus, and brightness preset. Access to the adjustments is gained by removing the case cover (Figure 2-2). The gain and position adjustments are located on the top, left central portion of the VR14/VR17 (as viewed from the front). The two forward potentiometers on the deflection circuits are the horizontal gain on the left, and vertical gain on the right. The two rear potentiometers are the hori- zontal position on the left, and the vertical position on the right. The gain adjustments allow the VR14/VR17 to accom- modate a range of input signal amplitudes and expand or contract the horizontal and vertical deflection to suit full screen requirements. The position controls accommodate a 2-2 variety of input signals and allow offset inputs to be centered on the CRT screen. Once initially adjusted for the particular input Signals used, the gain and position controls rarely have to be adjusted. Gross positioning off screen or excessive gain deflecting off the extremities of the screen should be avoided, since the deflection amplifiers will go into current limiting and may overheat if allowed to stay in this condition any length of time. Turning the X and Y gain controls clockwise, increases the gain or displayed image size. Turning the X and Y positions clockeise moves the displayed information right and up, respectively. The focus and brightness preset adjustments are located at the top, right central portion of the unit. They are on the power supply regulator circuit (G836) that is somewhat recessed from the top of the unit. The brightness preset is the rear-most of the two. This potentiometer allows the range of the front panel brightness control to be limited to any maximum brightness desired. Turning the brightness preset counterclockwise increases the maximum brightness range of the front panel control. Generally, this control is set so that at maximum brightness setting on the front panel knob, the displayed information does not "bloom" causing a degradation in resolution. The focus potenti- ometer is in front of the brightness preset. The adjustment is quite insensitive and requires several turns to go through focus. The VR14L and VR17L also contain a contrast adjusting potentiometer (R29), located on the W684 module. It is accessible from the top of the VR14/VR17. This control is used to extend or contract the brightness range of the CRT display. It does not normally have to be changed after an initial adjustment is made to compensate for component variations. 2.5 INPUT SIGNAL REQUIREMENTS NOTE The deflection amplifiers must not be driven so that the CRT beam is off screen for any length of time or permanent damage may occur. Ensure that input deflection signals fail to a safe, on-screen value. The VR14/VR17 requires analog voltage inputs for X- and V-deflection, and a logic level change or pulse for intensify. The X- and V-inputs are identical. However, because the CRT is a 3 X 4 rectangle, only 3/4 of the horizontal deflection is required for full vertical deflection. The deflection inputs are differential but may be driven from single-ended sources. When using single-ended sources, the differential input is helpful in eliminating annoying ground loops and hum. By carrying the "local" common or ground

VR14 VR14 L/VRI7 L 11724-Pin Destination Signal Name Function Signal Name Function Connector Pin 1 A4L Z-Select High input enables Z-intensify to Intensity 2 Determines intensity level occur if channel select switch on 1. A low input enables Z-intensify to occur if channel select switch on 2. Pin 2 A4B Not Used Intensity 0 Determines intensity level Pin 3 A4K Not Used Intensity 1 Determines intensity level Pin 4 A4J Z-Input When this input goes from high to low, Z-Input When this input is low, an intensify an intensify pulse is generated. signal is applied to the CRT. Pin 5 GND Pin 6 GND Pin 7 A2B -X Input One side of X~input signal line -x Input One side of X-input signal line Pin 8 A2E +X Input Other side of X input signal line +X Input Other side of X-input signal line (ground for single ended input) (ground for single ended input) Pin 9 A2H X-Signal GND X signal reference ground X-Signal GND X signal reference ground Pin 10 A3B -Y Input One side of V-input signal line -Y Input One side of Y -input signal line Pin 11 A3E +Y Input Other side of Y input signal line +Y Input Other side of Y input signal line (ground for single ended input) (ground for single ended input) Pin 12 A3H V-Signal GND Y signal reference ground V-Signal GND Y signal reference ground Pin 13 A4D Z-Direct Input signal that directly modulates Not Used CRT grid (ac coupled) Pin 14 N/C

J1 7 Rear Connector Pin Assignments VR14 VRI4L/VRI7L J1724-Pin Destination Signal Name Function Signal Name Function Connector Pin 15 JI8-Pin4 Not Used Bell (Speaker) Used in LK40 option Pin 16 N/C Pin 17 JI8-Pin 5 Not Used +K.B Signal Used in LK40 option Pin 18 JI8-Pin 6 Not Used - K.B Signal Used in LK40 option Pin 19 AIH Not Used Light Pen Out Amplified light pen pulses Pin 20 JI8-Pin 12 Not Used +5 VIN Used in LK40 option Pin 21 N/C Pin 22 JI8-Pin 8 +22 V +22 V is available if JI8-Pin 8 is +22V +22 V is available if JI8-Pin 8 is jumpered to JI8 pin 1. jumpered to J 18 pin 1. Pin 23 JI8-Pin 10 -22 V - 22 V is available if JI8 pin 10 is - 22 V is available if JI8 pin lOis jumpered to JI8 pin 3. jumpered to JI8 pin 3. Pin 24 JI8-Pin9 GND JI8 pin 9 must be jumpered to JI8 pin GND JI8 pin 9 must be jumpered to JI8 2. pin 2.

Jl8 14-Pin Connector Destination Pin 1 +22 V Regulated Pin 2 GND Pin 3 - 22 V Regulated Pin 4 117 Pin 15 Pin 5 117 Pin 17 Pin 6 117 Pin 18 Pin 7 N/C Pin 8 117 Pin 22 Pin 9 117 Pin 23 Pin 10 117 Pin 24 Pin 11 N/C Pin 12 117 Pin 20 Pin 13 GND Pin 14 -22 V along with the deflection signal from where it is generated, a quasi-differential signal is generated. Instead of termi- nating this ground at the VRI4/VRI7 chassis, use the ground as if it were one side of a differential signal (the other side being the deflection signal itself). The, VRI4/VRI7 uses the deflection signal with respect to its own ground and not the VRI4/VRI7 ground, which, most likely, is different and could cause picture ripple and hum. If a separate ground is not available, the single deflection Signal is applied to one side of the differential input. The remaining differential input is terminated with the source impedance of the driving signal or, if this is low, the input is simply grounded (signal ground not chassis ground). (Signal ground is pin 9 and pin 12" X- and Y -signal ground, Signal Name Function +22 V For VRI4/VRI7 options GND For VRI4/VRI7 options -22 V For VR14/VR17 options Bell (Speaker) Used with LK40 option +KB Signal Used with LK40 option -KB Signal Used with LK40 option Not Used +22 V Jumpered from J18 pin 1 to 118 pin 8 by P18 GND Jumpered from 118 pin 2 to 118 pin 9 by P18 -22V Jumpered from 118 pin 3 to 118 pin 10 by P18 +5V Provides +5 V to LK40 option GND Provides GND to LK40 option -22 V Provides -22 V to LK40 option respectively.) Never use chassis ground for X- and V-input reference - always use Signal ground. When using balanced or differential inputs, tie each side of the twisted-pair shielded cable to the two inputs and the shield to the signal ground. The importance of using signal ground cannot be overstated; most noise and washing displays are a result of indiscriminate grounding. .2-5 The minimum voltage Signal for full X-deflection is 2 V peak-to-peak and 1.7 V for Y when Rl and R2 on the A225 are 3.3 kn (Figure 3-1). For larger input signals, Rl and R2 are normally 10 kn. With 10 kn, the maximum input sensitivity is 0.5 V linch. The input impedance is 5 kn minimum for maximum sensitivity (RI and R2: 3.3 kn)

and 20 kQ minimum for Rl and R2 = 10 kQ. When driving long cables (more than 30 feet), high-speed deflection may not be possible unless the cables are terminated in a low impedance (less. than 100 Q) since the VR14/VR17 input impedance is too high for this application. Input signals larger than 2 V may be used by attenuating with the gain controls and Rl and R2 on the X- and Y -deflection circuit boards. However, the potentiometers become much too sensitive for input signals greater than 10 V peak-to-peak and Rl and R2 should be increased to provide pre-attenuation for these larger input signals. The input signals may be bipolar such as ±5 V or unipolar such 2-6 as 0 V to +5 V or 0 V to - 5 V. The position potentiometer allows the deflection to be offset plus or minus half a screen; thus, a unipolar signal may be completely centered on the screen. Offsets more than half of the full-scale inputs cannot be handled. In other words, if the full-scale deflection is offset from 0 V by more than half its 'full scale value, centering on the screen cannot be accomplished. A 3 V peak-to-peak deflection signal, for example, may not be offset from 0 by more than ±1.5 V. So ±1.5 V, 0 V to -3 V or 0 V to +3 V are all acceptable, but a deflection input that goes from + 1 V to +4 V cannot be used until it is shifted down a minimum of 1 V. Table 2-3 summarizes the control settings for various inputs.

0,0 = center +2 V to +5 V is up and to right o V to +2 V to +5 V 0,0 = upper right screen o V to - 2 V to - 5 V 0,0 = lower left Table 2-3 Control Settings Position Setting With no inputs, set X- and Y- position potentiometers to get o Vat A02-A (for X) and A03-A (for Y). With no inputs, set -2.2 V @ A02-A, A03-A with X- and V-position potentiometers. With no inputs, set +2.2 V @ A02-A, A03-A with X- and Y -position potentiometers. The Z-intensify input requirement is simply a TTL transi- tion from high to low. In VR14s using a W682 Intensity Control, this triggers the intensity circuit to generate a 300 ns intensify pulse. In VR14Ls and VR17Ls, which use the W684 Intensity Control, the intensify circuit is trig- gered, and remains active, until Z-intensify goes high. NOTE The intensify signal must be delayed from the X- and V-position signal for an appropriate length of time to allow the deflection coil to settle the electron beam to its required posi- tion. Failure to do so displays smeared dots that are located incorrectly on the screen. Also, at least a 500 ns waiting period must be allowed to intensify a dot before commanding the electron beam to move to its next location. Not giving enough time to intensify a dot after the deflection is settled will also smear the dot, since the deflection amplifier will start "drag- ging" the dot to the new position. The amount of delay required from the time new X- and V-position information is presented to the VRI4/VRI7 and the intensify pulse is requested depends upon how large a position change is requested and how perfectly settled the dot has to be to its final ideal position. Full-scale deflection changes, such as far left to far right or corner to corner, require a 20 J.ls waiting period for the dot to settle to within 0.01 inch of its final value. If larger errors can be tolerated, 18 J.ls may be used. Small deflec- tion changes require much less time. A 0.1 inch change can be settled in less than 1 J.lS. If there 2-7 is no way for the circuits driving the VRI4/VRI7 to distinguish small position changes from large ones, each change must be assumed to be large and thus requires the worst-case delay. Also, if the D/ A converters driving the display have "gliches" (error spikes generated while changing values), proportion- ately longer delays are required since the deflection amplifiers have to recover from the "gliches. " The Z-direct input (applicable only to VR14s without light pen option) allows direct modulation of the brightness. Positive-going signals increase brightness. This input is not direct coupled; therefore, dc brightness information cannot be used. The RC time constant is approximately 30 ms. The Z-direct may be used with or without the Z-intensify input. If Z-direct is used with Z-intensify, it can alter the brightness of the normal intensify pulse by adding or subtracting at the CRT grid. This is accomplished by pulsing the Z-direct with a pulse of equal duration with the Z-intensify. By varying the amplitude and polarity of the Z-direct pulse, the dot will be of a different brightness. When using Z-direct without the Z-intensify (such as for vector intensity control or any other non-point plotting application) the signal must be large enough to overcome the CRT cutoff. A typical direct signal will have 5 V to 10 V of actual brightness information riding on top of a 40 V pedestal; the 40 V pedestal ensures that the CRT will reside below cutoff. The Z-select input (applicable only to VR14s without light pen option) works in conjunction with the front panel channel select switch. The Z-select allows the Z-intensify pulse to be gated or time multiplexed. When the channel select switch is on the 1 & 2 position, Z-select inputs have no effect on the VR14. When the channel select switch is in the 1 position, Z-intensification occurs only when Z-select input is a TTL high. When the channel select switch is at 2, Z-intensification occurs only when Z-select is held at a TTL low. Thus, if two separate pieces of information are to be displayed, by placing Z-select at a high only during Channel 1 intensification times, and low only during Channel 2 intensification times, both curves will be displayed when the channel select switch is at 1 & 2, and only Channel 1 when Channel 1 is selected, and Channel 2 when Channel 2 is selected. In the VR14L and VR17L, brightness level is a function of three input signals [Intensity (2:0)], as well as the front panel brightness control. These input signals combine in the W684 module to generate a voltage which is applied to grid 1 of the CRT, establishing a particular brightness level.

The X- and Y -deflection circuits are identical; therefore, only one axis will be described. The deflection circuit consists of the A22S circuit board, two power transistors, and a deflection yoke (Figure 3-1). The input signal is applied to pins E and B on the A22S circuit board. The input signal is handled as a differential or balanced signal, even if the input is driven from a single-ended source (the single-ended source being a special case of a balanced input where one side is grounded). RI and R2 establish the minimum input impedance and form an attenuator with R3, the gain potentiometer. The voltage developed across R3 is amplified and converted from balanced to single- ended by amplifier E1. EI is an inverting amplifier whose gain is established by the resistor ratios of R7 to R4 and R6 to RS. The bandwidth of the amplifier is tailored by CS and C6, which act internally on the integrated circuit, and CI3 and CI4, which act at high frequency to roll off the low frequency gain established by the R7 to R4 and R6 to RS ratios. A ±6 V is generated for both EI and E2 from the ±22 V. This is done by dropping resistors RI8 and RI9 and Zener diodes DS and D6. CI and C3, and C2 and C4 are local high frequency bypass filters for the ±6 V to reduce any high frequency signal noise at each operational amplifier, thus avoiding the possibility of parasitic oscillation. The single-ended output of EI is conducted to RII, which is the input to the actual deflection amplifier; EI serves more as a signal conditioner- preamplifier. The amplifier is essentially an inverting voltage-to-current amplifier, i.e., an input voltage is converted to an output current 180 0 out of phase or inverted with respect to this input. Because the input is a voltage, however, the output current must be converted back into a voltage in order that the feedback compare volts with volts. Current is converted to voltage with a O.S n resistor in series with the yoke. The voltage across this resistor is an exact replica of the current flowing in the yoke; thus, the amplifier compares the input voltage with the yoke current to ensure that the yoke CHAPTER 3 THEORY OF OPERATION 3-1 current is an exact replica of the input position signal. E2 compares the input voltage at RII with the feedback voltage at R3I, RIO. Because the amplifier has voltage gain, only a small voltage is needed between pins 10 and 9 of E2 to cause large changes in the output. Pin 9 of E2 is referenced to ground through RI3, which is strictly an impedance balancing resistor that minimizes offsets in E2 due to temperature changes. Therefore, pin 9 is essentially grounded. If any voltage appears at pin 10 of E2, the output will immediate- ly respond in a manner that tends to reduce the voltage at pin 10 to zero; thus, a null is always achieved at pin 10 of E2. If a variable voltage is present at the input of RII, the output (or yoke current) will vary in such a manner that a continuous null is achieved at pin 10. The only way this can occur is if instantaneously the yoke current undergoes exact equal and opposite changes to those occurring at the input to Ril. Therefore, the yoke current will be an exact but opposite polarity replica of the input voltage. In absolute numbers, the actual yoke current versus input voltage can be determined by comparing resistor ratios. For example, if + 1 V is applied to the input of RII, 1 rnA will flow through RII. This occurs because the amplifier forces pin 10 of E2 to 0 V; thus, one side of RII is 0 V, the other is 1 V, so 1 rnA flows. This current does not flow into pin 10 of E2 because, if it did, pin 10 would rise in voltage because the input of E2 looks like a high impedance. The current must flow through RIO and R31. This occurs only if the feedback voltage is a negative value, because RIO/R31 is tied to pin 10 which is 0 V; so pin A must be negative. In fact, if 1 rnA flows through RIO and R3I, the feedback voltage must be 3.2 V and negative. The -3.2 V originates from the 0.5 n resistor in series with the yoke; therefore, -3.2 V divided by O.S n current is flowing through the yoke. This, of course, is -6.4 A which is an excessive amount of voltage, and current limit circuits (explained later) would probably be called into action to limit the output transistors.

from E2 to a sufficient drive level to operate the power transistors on the large heat sink. The output of E2 drives Ql through its base resistor R14. Ql serves two pur- poses: a stage of inversion and a level shifter. Inversion is necessary to get the final output in the proper polarity for negative feedback. Level shifting is required to drive Q2 at its base voltage; E2 cannot do this alone. The Ql stage has no voltage gain but has current gain. Q2, however, has voltage and current gain and is where the true output voltage is first generated. Q2 is a "grounded" emitter amplifier where, in this case, the emitter, although tied to +22 V, can be considered "grounded" and the col1ector resistor R23 is not tied to - 22 V but, for analysis, tied to -44 V. Q2 has the capability of swinging its collector almost a full ±22 V. This large swing is necessary for the yoke, which must swing as dose as possible to the ±22 V. The reason for this wi1l be explained later. The collector of Q2 drives Q3 and Q4 which are emitter followers for the positive and negative outputs. Since a low output impedance is necessary, emitter followers are used; however, Q3 and Q4 are not capable of handling the output power necessary since each can only drive 0.5 A. A bootstrap power stage is used to raise the emitter follower current capability to the ±4 A required. This is accom- plished with two power transistors on an external forced-air cooled heat sink. These external transistors are essentia11y "slaved" to the Q3 and Q4 emitter followers. Because the positive swing and negative swing work in the same way, only the positive is described. When the amplifier is required to deliver positive current in the yoke, the circuit responds by turning Q2 on, thus placing a positive voltage on the base of Q3. Q3's emitter responds in a similar manner; however, it cannot supply the necessary yoke current. Still, Q3 attempts to deliver the necessary current. Unlike a normal emitter fol1ower, Q3's collector is not tied to +20 V, but instead to the base of the 2N4399 Power Transistor, Thus, when Q3 tries to deliver the output current from its emitter, this very current must flow into Q3's collector from the base of the 2N4399 which will now turn on. Because the 2N4399's collector is also tied to the output (the yoke) it also supports the output current and, in fact, becomes the primary source of output current. Depending on Q3's demands, the 2N4399 is completely slaved to Q3. If Q3 turns on harder, so does the 2N4399. If Q3 shuts off, so does the 2N4399. Therefore, the output looks like it is an emitter follower (Q3) but the 2N4399 deHvers a11 the current and handles the necessary power dissipation re- quirement. 3-2 To minimize power consumption, the output would like to operate in Class B;i.e., while positive current is required, no negative current transistors should be turned on and vice versa. However, this approach creates problems at the point where the transition between positive and negative current takes place. The reason is that one set of transistors does not shut off exactly where the other set takes over, but instead shut off prematurely. This creates a dead zone or "no man's land" where neither the positive nor the negative transistors are on and control1able. The appearance on the CRT screen of such a phenomenon is a bunching or nonlinear compression of displayed information where it occurs (usually near the center of the screen). This problem can be solved by not allowing the positive transistors to shut off at zero, but rathe:r conduct somewhat into the opposite side's region. In SOl doing, the positive transistors would not shut off, for example, until the negative transistors were weB turned on. Thus, the amplifier would have control to cancel any nonlinearities that might occur. This task is accomplished with R23, R26, R27. The major influence is R23 because it places voltage between Q3 and Q4 bases which al10w one to be on a little into the conduction region of the other. If R23 were 0, the dead zone would be very abrupt, causing maximum distortion. On the other hand, as R23 is increased, the transistor conducts further and further into the opposite side's operating region. This creates two major problems. The power dissipation causes excessive heating of the output stage and the extra current required overloads the power supply. The value of R23 is chosen, therefore, to minimize dissipation but also to minimize the cross-over distortion. The output at the yoke has the capability of swinging a full ±22 V. This is necessary beeause even though the yoke is less than 0.1 n at dc, it has inductance; thus, to force curr~nt through at high speeds requires a lot of voltage (V = L LlI/Llt). To change 2 A through 20 J.LH in 2 J.LS requires 20 V. That is why the A225 not only has to boost the input signal to a large current but also has to have good voltage capability to force the yoke current to change quickly. Position control in the A225 is accomplished by adding another input to E2 exactly the way the signal comes in. This is accomplished with R9. The position "signal" is nothing more than an adjustable dc level (from R8) which,. through R9, adds or subtracts voltage from the actual input signal. This allows the displayed information to move up/down, left/right on the screen or, in the case of offset input signals, allows the information to be centered on the screen.

A 2.2K IK NOT USED R30 D 270 *Rl E 10K -'VVV- R3 J ~ .. 5K, + INPUT SIGNAL B *R2 10K PW GN R V D~ L H SIGNA GND Dl . I ~2 t CW 03 04 R4 IK 1/8W I%MF R5 IK 1/8W,I%MF R6 ,C14 4.64 1/8W 1% MF R9 C13 R8 4.7K If 5K R7 4.64 1/8W I%MF Rll C5 IK ~ 1/4W 5% 8 2 10 6 El 5 MC1520G R32 2.2K 9 4 7 3 I NC C6 27pF Cl C2 r'.OluF '.OluF R13 20% 20% 470 R18 270 lW R20 10% 10 R17 -;t' PJ753A leg 75 <) 6.8uF 1/8W I35V 6.2V -= 20% 1% () -= r? 02 2N2904A R29 ~ I K 1/4W CI6 5% R12 It 10K 1\ RI6 f? 100 . C12 R23 1°9,PF 47 1/2W 1\ R32 22 R14 lK 01 C3 1/4W f? DEC2219 .01 C7 5% 20% ~ .~ ~ 10 r------ E2 6 5 Cll R22 MCI520G R15 ;:;"220pF 680 4 316 2W 9 7 ;; C15 1/8W '----- I NC t% 3 C8 RI9 -= 200 lW R21 10% 10 "i'.g~uF 06 CIO )~IN753A ::~~.~~F 20% 6.2V 20% - [ R25 47 1/2W r 03 2N4923 R26 10 L 1/2W R27 10 1/2W 04 294920 L R28 47 1/2W I T ---._+_2::..2::..V_--,,---___ -7 + 22V U S R ---'-~--I--1 N p L M L_ K -22V 7007ci2J 0.1 5W 2N4399 0.1 I I I I ~-.J -22V UNLESS OTHERWISE INDICATED ,..-- I I I I L ALL CAPACITORS ARE 10pF, 100V. 5% ALL DIODES ARE 0664 0--0= JUMPERS *FOR THE A-225-YA VARIATION, RI 8 R2 ARE 3.3K. 1/4W, 5% FOR I NPUT SIGNALS LESS THAN 5V P-P. NOTE: Tnis schematic may not reflect most-recent engineering changes. -...., YOKE ASSY I 7007088 I I I _-.J TO PIN A YOKE RETURN 0.5 25W 1% TO PIN H SIGNAL GND CP-O?62 Figure 3·1 X and Y Deflection Circuit 3·3

compensation which allows the amplifier to operate over its required bandwidth without oscillation. Because the ampli- fier must operate from dc to beyond 1 MHz, the voltage gain must be reduced continuously at higher and higher frequencies. If this were not done, excessive phase shift between input and output (from feedback) could cause the output to be in phase with the input and. thus oscillate. R12, R3, R32, C16, CIS, and Cll perform the required gain reduction functions. R12 reduces the open-loop gain of E2 at all frequencies. C 11 reduces the gain of Q2 at high frequencies and is of major significance to the overall bandwidth. The yoke itself represents a major roll off for the amplifier, and its high frequency characteristics domi- nate the stability of the amplifier. An RC network across the yoke enhances the high frequency settling character- istics of the yoke. The power output stage (2NS302 and 2N4399) is current limited by the +22 V and -22 V power supply regulators. If the deflection amplifiers are driven way off screen, the power supply limits the maximum current to 11 A. If this condition is allowed to exist, eventually either the +22 V fuse or the - 22 V fuse will blow, rendering the circuit safe from such overloads. 3.2 PLUS AND MINUS LOW VOLTAGE REGULATED SUPPLY The input line voltage is stepped down in the power transformer to approximately 36 Vrms. There are two identical secondary windings to deliver these 36 V. Both windings are connected in series, making a 72 V center- tapped Winding. Using full wave bridge rectification, the ac becomes approximately 86 Vdc. By grounding the center tap, the 86 Vdc split evenly with respect to ground; thus, a +43 V and a -43 V are available with respect to ground. A filter capacitor on each ±43 V line smooths the ripple and finishes the task of generating the raw, unregulated dc for the ±22 V regulators. The regulators are contained on the G836 circuit board (Figure 3-2) and the heat sink adjacent to the G836. Since the ±22 V regulators are symmetrical, only the negative regulator is described. The ±43 V is dropped by R33 and R34 and preregulated with 05 and 06 to +12 Vdc and 07 and 08 to -12 Vdc. The ±12 Vdc are the voltages necessary to operate El and E2; they are also used to generate the reference voltages with which the 3-5 output voltage will be compared. The reference for the -22 V regulator is made with the +12 Vdc passing through Rl and establishing +6.2 V across 01. Cl across 01 reduces the dynamic resistance of the reference by removing high frequency fluctuations. The reference voltage is delivered to R2, which ties to the summing point (pin 2) of operational amplifier El. The feedback from the output regulated voltage through R3 is also applied to the summing point of El. The nature of the circuit is that a null will be maintained at pin 2 of E1. Therefore, because the voltage on R2 (reference) is stable, the only variable is the output. Whenever the output changes for any reason, the null is disturbed at pin 2 of El; El then forces the output to change in a manner that returns the null. For example, if the input line voltage increases, causing the -43 V to increase, the -22 V regu- lated output starts to climb. The null would then be disturbed and El would shut the output down somewhat so that the null could be maintained. On the other hand, if a heavy load occurred on the -22 V regulator causing the -43 V to drop, the null would again be disturbed and El would act in a way that would turn on the output hard enough to return to its proper level, the level that maintains the null. This regulating action takes place in a matter of micro- seconds. The actual output voltage at which the null will be maintained is determined by the ratio of R3 to R2 times the reference voltage. The mechanics of how El controls the output can be traced stage by stage. El drives an emitter follower, Q 1, to give the output of E 1 sufficient drive capability to fully turn on Q2, if required. Q2, through R12, controls the base current of the series pass transistors that are external to the G836 board. The pass transistors maintain a constant output, since they are supplied power from the raw dc source. Because of the high open-loop voltage gain, high frequency networks are used to roll off the gain of the regulator to ensure stable nonoscillatory operation. C2, R5, and C5 serve this purpose. The output power transistors are current limited by 013 and 014. These diodes conduct whenever excessive collec- tor current is demanded. In so doing, the diodes limit the base drive, thereby limiting the maximum fault current that may flow.

The CRT requires the fol1owing electrode voltages: fila- ment, cathode, grid 1, grid 2, focus, and anode. The filament voltage is derived from the ±3.5 Vac windings of the power transformer. The ±3.5 Vac windings are connected in series yielding 7 Vac. Due to resistance losses, approximately 6.3 Vac is provided across the CRT fIlament. The 70 Vrms winding is used to provide cathode and grid 1 bias voltages. The 70 Vrms winding terminates on the G836 (Figure 3-2). Through Dll, C17, R36, and C16, this winding generates a -80 Vdc by half wave rectification. The same winding, in like manner, generates +80 Vdc from D12, C18, R37, and C19. The -80 V is applied to one side of the front panel brightness potentiometer. The other side of the potentiometer returns to the brightness preset potenti- ometer (G836-R38). R38 setting determines the maximum voltage that can be made available to grid 1, and thereby acts as a limiter of the maximum intensity. The wiper of the brightness potentiometer is connected to pin E of the W682/W684 circuit board. In VR14 versions where the W682 Intensity Control (Figure 3-3) is used, pin E connects by way of R9 to grid 1 of the CRT. The W684 Intensity Control is used in the VR14L and VRI7L. In the W684 (Figure 3-4 and drawing D-CS-W684-O-1), the voltage at pin E is "modulated" by the three intensity signals [Intensity (2:0)] , before it is sent to grid 1. (Operation of W682/W684 circuitry is explained in Paragraph 3.5.) The bias voltage applied to grid 1 of the CRT may vary from -80 Vdc to 0 V, the upper limit being determined by the setting of R38 on G836. Intensity on the screen is generated by cathode pulses from the W682/W684 card. When not intensifying, the cathode is held at +62 V. The +62 V is derived from the +80 Vdc at the W682/W684. When the beam is to be turned on, the +62 V on the cathode is grounded, or made 0 V. However, this alone does not determine brightness, since intensity is related to grid-to-cathode voltage. Thus, the cathode is constantly going between +62 V and 0 V but, depending on where the grid voltage (brightness potentiometer) is set, the beam may never be on, dim, or very bright. Grid 2 of the CRT is operated at approximately +400 Vdc. The 400 V is generated from the 150 Vac tap of the power transformer by a voltage doubler on the G836 board. The ac passes through C 14 and is prevented from going negative by D9. This causes the entire peak-to-peak voltage to become positive. D 1 0 rectifies this voltage and CIS filters it; the resultant output is +400 Vdc. The 400 Vdc goes 3-6 directly to grid 2. If grid 2 i.s not substantially positively biased, the CRT beam can never be turned on, regardless of how much grid-to-cathode drive occurs. The 400 Vdc also goes to one side of the focus potentiometer R35 on the G836 board. The other side of the potentiometer goes to - 80 V dc. The wiper goes to the focus electrode on the CRT. Because of CRT manufacturing tolerances, proper focus may occur from unit to unit anywh~re between -80 Vdc and +400 Vdc. The anode is supplied 10.5 kV from the high voltage supply. 3.4 HIGH VOLTAGE POWER SUPPLY The high voltage supply is a self-contained high voltage source that requires only line voltage input. The input is actually the split primary of its own internal step-up transformer. For 115 V operation, the primary windings are operated in parallel; for 230 V operation, they are operated in series. The step-up transformer delivers high voltage ac to a voltage doubler and filter. The ultimate dc voltage is 10.5 kV and unregulated. Thus, the high voltage is slaved to the line voltage, and varies linearity with it. Because the electron beam is accelerated by the high voltage, the ability to deflect the beam will change as the high voltage changes. If a constant deflection current flows through the yoke, the amount of deflection is reduced if the anode high voltage is increased (smaller displayed picture); the deflection grows if the anode high voltage decreases (larger displayed picture). The actual deflection factor change is proportional to the square root of the ratio of the old anode voltage to the new anode voltage, i.e., deflection factor = ".;V 1 /V;.. For example, if the high voltage is halved, the deflection would grow 1.414 ('\/2/1). In terms of line voltage, the deflection factor is approxi- mately 0.4 of the change, i.e., a 5 percent line change causes a 2 percent deflection change. The VRI4/VRI7 incorporates circuitry which protects the unit from possible damage due to arcing. Arcing is due to transient conditions within the CRT, which cause a spark to jump between the anode and other CRT elements. The protection circuitry consists of two voltage transient suppressors (DEC part no. 11 11562), R30 and D13 on W684 , R43 on G836, R9 on W682, and a lK resistor mounted on the CRT socket. The resistors act as current limiters; diode D13 prevents grid 1 from becoming more positive than 0 V; the voltage transient suppressors, mounted on the CRT socket, prevent grid 2 and the focus electrode from exceeding +600 V.

hRAW-22V) I I I 20.1 0.1 I I 5W 5W .------AR2 a 2N5302 I rR2-~-0~~R4-''--'R-I-2---------------4--~---L~~------~I~4-I·~\ ~ I R3 *~60PF 6.SIK 1/8W 1% R5 10 27pF 2 7 BN2 1I2W 108wO 80 • ~ «{2N5302 f7 lOW I IBR2 ~--'-'VVI...--.--I-+-l \ "- giC2904 r- r A H 2 • J yoc U S "-..,; 02 L __ _ l.o~o MJE2955 ~-----<'~-22 REG R43 BS2 IK 400VDC G2~I~VV~~------~--~~~------~ ~ 5 R7 El 6 lK ,Mf{( R39 r---- 8 2.2K V4 R6 5% R4 C4 1.5K 330 RIO f? R34 10 750 .~ -80V 470pF lW R9 220 1r0B ,F--IN752A Ct3 O.OIIJ.F Ir 07 ,F--,N752A 20% R13 2.7 lW 10% 22AJF..,~ RI4 .;; 470 C6 ,L.- 22.uF 2W + 50V 1r03 IN4004 2W 010 C14 4~ I N4004 A02 ----, Jgo~ I AJ2 150 VAC>--L----1~ 09 RI6 IN4004 lK R35 500K IW 10% + CI5 CI6 10JJ,F :::~25IJ.F 450V + 150V R36 2W 10"10 C17 .*25 ..... F + 150V AE2 70VAC Oil IN4004 . BP2 +80V 012 IN4004 ~ R37 120 2W 10% AF2 BRIGH '--- + CI9 ·:;:,25IJ.F 150V [ L-~----1-~---4--------~~~--~--~--------~-------+----~~------4-------~f'~'(+)GND SENSE GNO.B02.BS2----~t_II--~--lI----t_~--~--~L-~------'-------J-----L-L------L----~-L--------------------------__ -L ______ -L ______ L-____ ~ ____________________ 1_ ______ L_ __ ~ BJ2---r--<} + 43V I---< I--< r-+rn . ~ - - -, R33 ~ (RAW,+ 22V) 750 lW 015 IN4001 016 IN4001 I (RAW+22V) I ~ I ""--0-.,--'--- 0.1 I I I BK2 I 5W 5W I R19r--JLr----i----------------~--------~--~R~3~1-.6~8~-------------.----------+------+~~(+lSENSE ~.~~ TrgOPF R,~I C20 R2~2W. 10% I H BEl2 II (C 2N4399 I 2nF *'OOOpF F20W f----

~-SELECT L~~rvv-+-----~~--~~----------------~~ I-DIRECT R3 100 RIO lOOK I N PUT D --------....... ---------------------H--------..... ------------------- F TO GRID 1 UNLESS OTHERWISE INDICATED: DIODES ARE D664 CAPAC ITORS ARE 100V,20% E I IS DEC7400N PIN 7 ON IC = GND PIN 140N IC= +5V RESISTORS ARE 1/4W, 10% NOTE: C5 .047 MFo 10% 200V R9 lOOK '-------------------E TO BRIGHTNESS POT SLIDER This schematic may not reflect most-recent CP -0764 engineeritg changes. Figure 3-3 Intensity Amplifier W682, Circuit Schematic

INT 1 L ------4["1 INTENSITY LEVEL GENERATOR INT 2 L NOTE lOne of eight intensi ty levels as determined by the three intensity inputs. NOTE 2 Brightness determined by grid 1 voltage which is a function of the intensity level generated and BRIGHTNESS pot posit ion. GENERATOR ~ IL NOTE1 62V >-------L----..CATHODE CONTRAST r-- -, I BRIGHTNESS I FRONT J PANEL --- BRIGHTNESS I PRESET '=' -80v __ I_~ L __ !f!3~ J GRID LEVEL /GENERATOR >------.... GRID 1 -8()V~ NOTE 2 CP-0761 Figure 34 W684 Intensity Control 3.5 W682 AND W684 INTENSITY CIRCUITS In the VRI4 without the light pen option the intensifi- cation of points on the screen is controlled by the W682 circuit board. The intensity signal is routed to pin J. This signal is. a transition from a high to a low. While the Z-signal is at a high (above +2.4 V), the output from gate A (pins 8, 9, 10) is low. When the Z-input is low momentarily, the output of A goes high. This positive-going transition is ac coupled through C2 and becomes a positive spike that exponentially decays to o. The time constant of this decay is determined by C2 and R4. This positive-going spike is the input to gate B (pins 11, 12, and 13). Also, as input to B, is the channel select information which comes from pin R. This information either enables gate B to respond to the intensification spike or not. Assuming B is enabled from pin R, the positive spike causes the output of B to go to a low. This low remains as long as the input spike to B is above its 1 ~r high threshold level. As soon as the spike decays below the threshold, B's output immediately reverts to the high state. B's output is fed back to A's input (pin 10) to allow A's output to latch high, thus not requiring A's input (pin 9) to remain low, but rather be a momentary drop from a high. Of course, when the spike decays at B's input, the 3·10 latching input is removed from A (pin 9) thus enabHng A to respond to the next negative-going transition on the Z-intensify input. DS clamps the input from going negative during the negative-going transition that occurs when A resets. Gate C (pins 1,2, and 3) simply inverts the intensify pulse to drive the output pulse amplifier Q 1. Gate C normal1y is low until a pulse comes along. This low "grounds" out the base drive for QI; therefore, it will be off. DI3 and DIS guarantee that QI will be off, even though there is a residual voltage drop across D6 and the output of gate C. QI's collector is tied through R7 and D8 to +80 Vdc. With QI off, the collector tries to ride up to +80 V dc, but D7 begins to conduct at +62 V clamping the collector at +62 V. The +62 V is generated by dropping the +80 V across R8 and Zener diode D14. QI's collector is tied through RI2 to the CRT cathode. Therefore, in the absence of an intensify input, the cathode resides at +62 V. This, along with the negative bias on the grid, keeps the CRT beam shut off. When an intensify signal occurs, gate C's output goes high, allowing Q I to receive base current from the +80Vdc via D17, Rll, RS, DI3, and DIS. This base drive turns on QI, causing its collector (and the cathode of the CRT) to go from +62 V to 0 V. This turns

detennined by the time constant of C2, R4 and is normally 300 ns. D16 prevents the voltage supplied to RS from exceeding S V; this is necessary to prevent damage to gate C. When power is removed from the VRI4, the CRT must be prevented from blooming and possibly burning the phos- phor. Blooming can occur because the necessary voltages (±80 Vdc) that keep the CRT shut off, drain to 0 V faster than the high voltage supply. When the grid-to-cathode voltage becomes more positive than cutoff, the CRT turns on very hard. D8 and C14 prevent this from happening. When power is turned off, the +80 V goes to 0 V but, in so doing, C4 hangs on to its voltage and thus back biases D8 which does not allow C4 to discharge. C4 momentarily acts like Ql 's power source, allowing the collector (and CRT cathode) to hold at +62 V which is the safe or off condition. Eventually C4 discharges; however, by that time the high voltage has also discharged, rendering the CRT safe. Five volts are supplied at pin A for El and also as a clamp for D16. A +3 V logical 1 level is generated across D9, 10, 11, and 12 through R2. D2 and D3 protect gate A and gate D inputs from exceeding +S V. Dl and D4 prevent the same inputs from becoming negative. The two remaining inputs on the W682 are the Z-select and Z-direct. The Z-select is a bit that allows the intensity pulse to be multiplexed or time enabled. As mentioned before, whether or not the intensity pulse is allowed to pass to the output through gate B depends on whether or not a high input is available at pin 13 of gate B. This high is continuously available, independently of the Z-select input, when the channel select switch is in the 1 & 2 position. When the channel select switch is in the 1 position, intensification occurs only when a high is presented at Z-select and an intensify input is presented. When the channel select switch is in the 2 position, gate B is enabled only when the Z-select input is a low. The Z-direct is an input directly to the grid through CS. Video or other time varying brightness information may be coupled to the grid at pin D. In the event of a failure of either the ±22 V supplies, deflection ceases and a bright spot could occur on the CRT, causing a burn. To prevent this, G838 (Figure 3-5) contains a circuit that supplies +5 V to the W682. If either the +22 V or - 22 V goes to 0 (in the case of a short circuit or blown secondary fuse), the circuit supplying the +5 V shuts down. Because the G838 has a low value resistor across the 5 V (47 n), the 5 V line (pin A) on the W682 is grounded. 3-11 This causes the base drive to Ql to be shunted to ground through D16 and renders Ql off; this shuts off the CRT. -22 V K R4 R3 2K 4.7K 1/2W R5 100 + 22 V U R6 47 112W V-'~--------~----~ UNLESS OTHERWISE INDICATED: RESISTORS=1I4 W,5"lo +5V p CP-0757 Figure 3-5 G838 Circuit Diagram In the VR14L and VRI7L, the intensification of points on the screen is controlled by the W684 module. The Z-input intensity signal enters the W684 at pin J (drawing D-CS-W684.Q-l). Before the Z-input is asserted, pin J is a TTL high. The output of E2 pin 3 is low, disabling the two AND gates, E2 pin 6 and E2 pin 11. This causes Q7 to be cut off and Q6 to conduct. Consequently, Q2 is cut off because its base is low at this time. With Q2 cut off, the cathode voltage at pin U will be positive, approximately +62 V, and no beam is generated. The cathode voltage is produced by the Zener action of D4 from +80 V input from the G836. When the Z-input is asserted, E2 pin 3 is disabled and E2 pin 6 and E2 pin 11 are enabled. Now the situation is reversed: Q6 is cut off and Q7 conducts. With Q7 conducting, +5 REG is coupled to the base of Q2 causing it to conduct. The cathode voltage goes from +62 to 0 V and a beam can be produced, provided one other condition is satisfied - grid 1 must be sufficiently positive before the grid-to-cathode voltage results in a beam strong enough to cause screen fluorescence. Grid voltage can be varied from approximately -80 to almost 0 V; brightness increases as the voltage becomes more positive. Q3 controls the grid voltage with the screen brightest when Q3 is cut off. When Q3 conduction increases, the image becomes dimmer. Conduction of Q3 is determined, along with the contrast control setting, by the voltages present at the base of Q4 and the emitter of Q5.

panel brightness control. Turning this control clockwise causes Q4 to conduct less; the emitter voltage becomes more positive. As a result, the, base of Q3 becomes more positive. Coincident with this, the emitter voltage of Q5 is determined by the state of the three intensity level signals [Intensity (2:0) L] . These signals forward bias three diodes (D8, D9, and DI0) that control the conduction of+5 REG through a voltage divider consisting of R21, R22, and R23. Table 3·1 shows the relationship between the three inten· sity levels and the resultant brightness level. As the number of levels asserted increases from 0 through 3, the brightness level increases from 0 through 7. The higher the brightness level, the more positive the emitter of Q5 and therefore the harder Q5 conducts. As Q5 conducts harder, more voltage is dropped over the Q4, R18, R19, and R29 network, causing the base of Q3 to become more positive. This, in turn, decreases Q3 conduction and the emitter (grid 1) voltage approaches 0 V. Figure 3-6 illustrates the relationship between the eight brightness levels, that are program controlled, and the brightness control, which can be changed by the operator. Reference A shows the relative brightness at a particular brightness control setting, for each of the brightness levels. As the control is turned c1ockwise, there is a linear increase in brightness at each level (reference B). The contrast control, R19, is positioned between Q4 and Q5. As the control is turned clockwise, dropping more voltage, the brightness range between brightness level 0 and brightness level 7 is increased; i.e., the image contrast is increased. This is indicated in Figure 3-6 as the change from reference A to reference C; the original brightness spread (x) is increased (y). Actually, level 0 becomes dimmer and level 7 becomes brighter. Therefore, the brightness control i IMAGE BIGHTNESS must also be adjusted at the same time to compensate for the decreased lower intensity levels. Reference D shows the result of this final adjustment. Note that grid 1 voltage is the consequence of the three intensity levels generating a brightness level (one of eight) that is then combined with the particular brightness control setting. At the same time, the contrast control setting determines the difference in brightness between the bright· ness levels. Intensity Level 2L IL H H H H H L H L L H L H L L L L Table 3·1 Brightness Control Brightness OL Level H 0 L 1 H 2 L 3 H 4 L 5 H 6 L 7 Front Panel Brightness Control In case of a decrease in the +5 or +80 V input to the W684, the cathode and grid circuits described above are disabled. If these circuits were not shut off when this low voltage condition occurred, the phosphor would be burned and the screen damaged. This is because X and Y deflection circuits are disabled by the same power failure and the electron beam would be continually directed to the same spot on the screen. If the +5 V input from the G840 at pin A drops to about +4 V, Q9 loses forward bias and ceases to conduct. r -- I r-J I 7 r-J I r- J I r-.J I r-.J I 3 y r-.J l D--~ ~ __ 2 _________ _ CP-0584 Figure 3·6 VRI4L/VRI7L Brightness and Contrast Control 3·12

(cathode circuit) and to the R21, R22, and R23 voltage divider (grid 1 circuit). The same result occurs if the +80 V input to the cathode circuit fails. In this instance, the base of Q9 becomes more positive; Q9 is cut off and the +5 V input opens. When power is removed from the VR14L/VR17L, the CRT must be prevented from blooming and possibly burning the phosphor. Blooming can occur because the necessary voltages (±80 V), that keep the CRT shut off, drain to 0 V faster than the high voltage supply. When the grid-to- cathode voltage becomes more positive than cut-off, the CRT turns on very hard. D2 and C1 prevent this from happening. When power is turned off, the +80 V goes to o V but, in so dOing, Cl hangs on to its voltage (+60 V) and thus back biases D2, which does not allow Cl to discharge. C1 momentarily acts like Q1 's power source, allowing the emitter (and CRT cathode) to hold at +62 V, which is the safe or off condition. Eventually C1 discharges; however, by that time the high voltage has also discharged, rendering the CRT safe. Jl PEAKING CIRCUIT +3V 3.6 LIGHT PEN AMPLIFICATION The input from the 375 Light Pen that results from detection of beam intensification is not usable in its analog form; it must first be converted to a TTL compatible signal. This is the prime function of the G840 Light Pen Amplifier module (drawing D-CS-G840.o-1 and Figure 3-7). In relation to the G840, the light pen phototransistor acts as a variable resistor that presents a low-going signal at the input (11, pin 3) to the module when screen intensification occurs within the light pen's angle of acceptance. This negative-going analog signal is inverted by Ql, and peaked by the circuit at the collector of Q1. The signal, now positive-going with a greatly decreased rise time (about 1 ps), is differentiated before being input to the LM 306 Comparator . The LM 306 is a high-speed voltage comparator designed to produce a sharp-edged, TTL compatible output when the input attains a predetermined threshold voltage. In this application, the (+) input to the LM 306 (pin 2) is held at about 400 mY. When the differentiated input at the (-) ., ,t1 --~N-·· ov-I '" DIFFERENTIATOR ENABLE L ~400mv "1 r t1 +5vi I VOLTAGE COMPARATOR ovU, 9602 SINGLE 9602 1 SINGLE SHOT 0 SHOT 0 L--__ LIGHT PEN PULSE L ~ CP -0759 Figure 3-7 Light Pen Amplifier 3-13

is produced at pin 7, provided an ENABLE signal is present at E3 pin 13. This qualifying signal ensures that all light pen hits (LIGHT PEN PULSE L) from the G840 are valid, inhibiting those hits that might be generated by spurious noise from the light pen. The LM 306 output occurs about 30 ns after the two input voltages compare (fal1 time is approxima tely 20 ns) and remains low as long as the (-) input stays above the 400 mV threshold. This assertion time is indicated in Figure 3-7 as t1. Positive feedback is provided from the output to the (+) input to assist the input signal comparison. The negative-going output from the LM 306 triggers one stage of a 9602 Monostable Multivibrator, which, in this application, functions as a single-shot to produce alSO ns output signal, LIGHT PEN PULSE L. Coincident with this signal from the 0 output, the 1 output from the first stage of the 9602 triggers the second stage, also configured as a single-shot. The 1 output of the second stage, high for 70 IlS, inhibits a second light pen hit immediately following the first one. Timing for this operation is shown in Figure 3-8. The comparator output assertion time is unimportant because only the negative-going transition is needed to initiate LIGHT PEN PULSE L. COMPARATOR OUTPUT (E4 -7) LIGHT PEN PULSE L (E1-3) In the event of a failure of either 22 V supply, deflection ceases and a bright spot occurs on the CRT, resulting in a burn. To prevent this, the circuit on the G840 module that produces +5 V for the W684 intensity module will be disabled if either the +22 V or -22 V goes to 0 (in the case of a short circuit or blown secondary fuse). Referring to drawing D-CS-G840-O-1, if +22 V fails, Q3 loses forward bias (at the emitter) and turns off, shutting down the +5 V. If the -22 V goes to 0, Q2 loses emitter voltage and the base of Q3 goes high. This causes Q3 to turn off and +5 V drops. This circuitry (aside from some component values) is identical to the fault protection circuitry on the G838 (Figure 3-5). Note that this failure detection circuit is in addition to the W684 low +5 V voltage protection circuit previously described (paragraph 3.5). 3.6.1 375 Light Pen The 375 Light Pen is simply (;onstructed. A phototransistor is recess-mounted (drawings C-UA-375-O-O and D-CS-5410268-O-O) in a polished cylinder approximately 0.45 X 5.0 inches. The output signal connection is via a cable that plugs into the VR14L/VRI7L front panel. When an intensified beam strikes the CRT phosphor where the light pen is being aimed, the phototransistor (Ql) conducts and negative-going alternation is output to the G840 Light Pen Amplifier module (Figure 3-7). In the G840, the light pen output is shaped to become the TTL compatible signal LIGHT PEN PULSE L. ~-------------~70~s--------------~·1 (E2-6) L......-_~~~ ~-----------70~s------------~·1 (E2-10) ~ NOTE: 1. This output must be low before a second LIGHT PEN PULSE L signal can be asserted. CP-O!i71 Figure 3-8 Light Pen Pulse Timing, G840 Module 3-14

of fault conditions. Successful troubleshooting of the VRI4/VRI7 can be performed using a volt-ohm- milliampere meter; however, an oscilloscope facilitates and expedites isolation and repair of faults. 4.1 PREVENTIVE MAINTENANCE VRI4/VRI7 preventive maintenance consists of ensuring that the equipment is getting and maintaining proper air flow for cooling and a periodiC, cursory inspection for abnormal hardware conditions. Because of the power dissipation on the deflection and regulator heat sinks, good air flow must be maintained. A periodic check is required to see that fans are operating properly and are not obstructed by dirt, dust accumulation, or inadvertently blocked by external equipment or surfaces. Prolonged off-screen deflection of the CRT beam can damage the VRI4/VRI7. Ensure that the X and Y driving signals into the VRI4/VRI7 never drive the CRT beam off screen because of intermittent incorrect signals. 4.2 TROUBLESHOOTING VRI4/VRI7 voltage checks (Table 4-1) and most tests can be done with a volt-ohm-milliampere meter; however, an oscilloscope will be needed if waveform analysis is required. NOTE When making voltage measurements on a malfunction VR 14/VRI7, set the voltmeter (or oscilloscope) to the proper range, connect the leads to the test points, then tum the power on and off very quickly so that the anticipated reading may be taken. Power is only on for a very brief moment. In this way, fault condi- tions may be discovered without causing further damage. Never leave power on to a malfunctioning or repaired VRI4/VRI7 until all necessary checkpoints are measured and proved nominal. 4-1 CHAPTER 4 MAINTENANCE The circuit card connector block, as viewed from the wiring side, is labeled AO 1 and A04 left to right on the top section, and BOI to B04 on the bottom section. Figure 4-1 shows pin and connector locations for PI, P2, P3 and P4. 4.2.1 No Picture Probably the most common failure mode with this type of equipment is "no picture." Unfortunately, this condition can be caused by almost any malfunction such as a loss of input intensity pulse, incorrect input deflection signals driving the beam off the screen, a power supply fuse, or fan failure (thermal cutout). The following sequence of events leads to the isolation of the fault(s): 1. Check fuses. If they are in good condition, continue. If not, replace any that are blown and then continue. (If a blown fuse is replaced, leave power on only long enough to complete each check in this procedure.) 2. Remove all input signals at the rear of the unit and all modules except W682/W684 and G836. 3. With a voltmeter (or oscilloscope), measure the +22 Vdc (20 Vdc to 22 Vdc is acceptable). This can be measured between AOI-U (red wire) and A02-V which is ground. Momentarily apply and shut down power. If the +22 V is above +22 V, the regulator has a fault; refer to Appendix A. If 0 V or below +20 Vdc occurs, the +22 V is overloaded; continue to the next step. 4. Set up to measure -22 V. This can be found between AOI-K (blue wire) and A02-V which is ground. Momentarily apply and shut down power. If the - 22 V is more negative than -22 Vdc, the -22 V regulator has a fault; refer to Appendix A. If 20 V or more positive, the - 22 V is overloaded; continue to next step.

A02A A03A A02E,B A03E,B AOIU AOIK AOIP Deflection Heat Sink Pin X-Axis Y-Axis P5 - 2 P5 - 14 P5 - 1 P5 - 15 P5 - 3 P5 - 13 P5 - 4 P5 - 12 P5 - 5 P5 - 11 Regulator Heat Sink Pin P3 - 1 P3 - 2 P3 - 3 P3 - 12 P3 - 11 P3 - 10 7007165 (G836) Regulator Circuit Connectors PI, P2, P4 PI - 1 PI - 3, 6 PI - 4 P2 - 1 P2 - 2, 4, 7, 9 P2 - 3 P2 - 5 P2 - 6 P4 - 1 P4 - 2, 14 P4 - 3 P4 - 4 P4 - 5 P4 - 6 *Indicates voltage depends upon input signal. Table 4-1 VRI4/VRI7 Voltage Check Points Voltage *2.2V nominal *2.2V nominal * * +22 Vdc (Red) -22 Vdc (Blue) +5 Vdc Voltage +21 Vdc +22 Vdc *< IV -21 Vdc -22 Vdc Voltage +43 V dc Orange +42 V dc Gray/Yellow +22 Vdc Red -43 Vdc Green -42 Vdc Gray/Blue -22 Vdc Blue Voltage +43 Vdc Ground -43 Vdc 3.5 Vrms Ground 3.5 Vrms 70 Vrms (200 P-P) 150 Vrms (400 P-P) +22 Vdc Red Ground Black +22 Vdc Red o Vdc Black - 80 to +400 V dc Gray/Red +400 V dc Orange 4-2 Signal/Control X Current Sample Y Current Sample X Input Signal Y Input Signal + Regulated dc - Regulated dc For W682/W684 Component PNP Base (2N4399) PNP Emitter (2N4399) All Collectors NPN Base (2N5302) NPN Emitter (2N5302) Component Emitters of 2N4399 Bases of 2N4399 Collectors of 2N4399 Emitters of 2N5302 Bases of 2N5302 Collectors of 2N5302 Signal/Control Raw + dc Raw - dc 1/2 Filament 1/2 Filamtmt ±80V tap +400V tap + Regulated Hot + Sense Cold ± Sense Focus Grid 2

Circuit Connectors PI, P2, P4 P4 -7 P4 - 8 P4 ·9 P4·10 P4·11 P4·12 P4 - 13 P4·15 Table 4-1 (Cont) VRI4/VRI7 Voltage Check Points Voltage 3.5 Vrms Brown 3.5 Vrms Brown - 80 V dc Gray/Green o to -40 Vdc Gray/Violet +80 Vdc Gray/Orange -22 Vdc Blue o Vdc Black -22 Vdc Blue Note: All voltages measured with respect to ground (chassis or A02V). Pl P2 P3 EJ 7 4 10 7 4 13 10 5 2 8 5 2 11 8 5 2 14 11 6 3 9 6 3 12 9 6 3 15 12 7007165 8RIGHTNESS FOCUS ADJ (G836 W/CONNECTORS) PRESET ADJ Figure 4-1 VRI4/VRI7 Interior View 4·3 Signal/Control Filament Filament To Brightness Potentiometer Brightness Preset For W682/W684 Hot· Sense Cold· Sense - Regulated P4 7 4 8 5 2 9 6 3 HIGH VOLTAGE POWER SUPPLY 6582·5

maximum at A02-A with respect to ground (A02-V). This point (A02·A) is the X·axis deflection coil current sample. Because coil current flows through a 0.5 n resistor, voltage measured at A02·A multiplied by two equals the current flowing. With the A225 circuit cards removed, no coil current should flow. Momentarily turn on power to the VR14/VR17. If A02-A has any voltage plus or minus (refer to Appendix B), a deflection power transistor probably is shorted. 6. Measure the same as in step 5 for the Y-axis deflection coil current at A03-A with respect to ground (A02-V). Momentarily turn VR14/VR17 power on and off. No voltage should be read; this indicates no Y -deflection coil current is flowing. If any voltage is observed, refer to Appendix B, since a Y·axis deflection transistor is probably shorted. 7. Replace the G838/G840 circuit into A01 and the A225 circuit into A02. (Still leave the Y-axis, A03 board out.) Measure less than ±2.2 V at pin A02·A with respect to ground (A02-V). Momentarily apply power. If the voltage is within safe limits (within ±2.2 V), leave power on and adjust the position potenti- ometer on the A225 circuit. DOing this should change the voltage reading on A02·A, providing the A225 indeed is controHing the coil current. Return the position potentiometer to its origi· nal position. If the voltage at A02·A is beyond ±2.2 V, shut down immediately. Because the position potentiometer on the A225 can drive more current than the ±2.2 V limit signifies (4.4 A), it is possible that it (the position potentiometer) has been adjusted to one extreme or the other. To prove whether this is the case or if the A225 circuit board is faulty, turn the position potentiometer as fol· lows: clockwise if the voltage at A02·A was very negative; counterclockwise if the voltage at A02·A was very positive. If no change is noted at A02-A after adjusting the position potenti- ometer, the A225 board is faulty and should be replaced or repaired (refer to Appendix C). 8. Repeat the same tests as in step 7 for the Y-axis deflection circuit A225 plugged into A03. Monitor A03·A. Refer to Appendix C for A225 repair. 4-4 9. If the fault has not been isolated, the intensity circuit W682/W684, the electrode voltages, and the high voltage supply are suspect. The output of the W682/W684 drives the cathode. At rest, it should be +62 V and, when triggered, go to approximately 0 V. To check the W682, apply a proper Z·input (+3 V to 0 V transition) at J17 pin 4 and check to see that the signal reaches A04·J. If so, check A04-R with the channel select in the 1 & 2 position to see that a high is present there. If so, Sf!e that +5 V is being supplied to A04-A. If A04-A is less than +4 V replace or repair the G838 module as this is where the +5 V is developed. If the three preceding measurements are good and the W682 output (measured at A04-U) is not going from +60 V to 0 V for at least 300 ns, repair or replace the W682 module. To check the W684, apply 0 V (ground) to the Z-input at J17 pin 4 and check to see that it reaches A04-J. If so, see that +5 V is being supplied to A04-A. If A04-A is less than +4 V, replace or repair the G840 module, as this is where the +5 V is developed. If the two preceding measurements are good, and the W684 output (measured at A04-U) is not at approximately 0 V, repair or replace the W684 module. 10. Measure 6.3 Vac between P4-7 and P4-8 and observe the glowing filament on the CRT. No 6.3 Vac can be traced back to the power transformer by way of P2 pins 1 and 2. 11. Measure the grid 1 voltage at A04-F. It should vary from - 80 V dc to between - 30 V and 0 V when the front panel brightness control is varied. The -80 Vdc comes from the G836 board. Trace back to the G836. 12. Measure grid 2 at P4-6. It should be at least +300 V. Trace back to the G836. 13. The last item operating improperly for "no picture" is the high voltage supply itself. Generally, all other measurements should be made before considering the high voltage, since the majority of "no picture" conditions wiJ) not be caused by the high voltage supply. Measuring the high voltage directly is extremely

quick method is to take a long screwdriver and ground the blade with two separate clip leads for safety. Turn the VRI4/VRI7 on for 5 seconds and then SHUI' IT OFF. After it is off, ground out the anode cap on the CRT with the GROUNDED screwdriver. If done within 5 to 10 seconds after power is turned off, an arc should occur to the screwdriver indicating that the CRT was charged with high voltage. If no arc occurs, replace the high voltage supply. 4.2.2 Faulty Picture a. No Focus - Check the range of the focus potentiometer on the G838 by monitoring the focus voltage at P4-5 while adjusting the focus potentiometer through its range. Minimi.1m range is +350 Vdc to -60 Vdc. See G836 for repair. b. Half or Quarter of the Picture Missing - Gener- ally, this condition indicates that one of the two deflection transistors is not working; thus, only half deflection is available. The transistor in question can be identified by observing which side of the screen is not working. The left and bottom portions of the screen are controlled by the PNP (2N4399) power transis- tors on the deflection heat sink. These are the lower two transistors; the left side of the screen is controned by the left lower power transistor (if the deflection heat sink is viewed from the front of the VR14/VRI7), the lower part of the screen is controlled by the right lower power transistor. Of course, the upper and right are controned by the NPN (2N5302), the right side of the heat sink controlling the upper screen, the left side of the heat sink controlling the right screen. c. The remaining possible faulty picture patterns, such as picture swim (60 Hz), oscillations, distortion, etc., will be restricted generally to improper input signals (especially grounding techniques) or faults on the A225 circuit board. If input signals are not suspect, a faulty A225 may be isolated by swapping X and Y A225s with one another to see if the problem changes axis. 4-5 d. If a weak picture that is deflected off the screen on all sides is encountered, with excessive jitter and ripple, the high voltage supply should be replaced. 4.3 ASSEMBLY REPLACEMENT INSTRUCTIONS Other than the G838/G840, A225s, and W682/W684 circuit· modules, most repair and replacement will involve the G836 regulator subassembly; the regulator heat sink assembly; and the deflection heat sink assembly; and, in rare cases, the high voltage assembly, yoke, and CRT. It cannot be stressed too strongly that the VR14/VRI7 line cord be removed from the line before doing any mainte- nance. Turning power off or removing fuses does not render the unit safe from shock hazards, since the power switch and fuse interrupt only one side of the ac input line voltage, the other side is permanently connected as long as the line cord is plugged in. Do not take chances, UNPLUG the line cord. NOTE Photographs in this section are of a VR14 prototype, but generally apply to all VR14 and VR1' configurations. 4.3.1 Deflection Heat Sink Removal To remove the deflection heat sink (Figure 4-2) proceed as follows: 1. Remove the line cord and all circuit modules above the deflection heat sink assembly (G838/G840, A225s, W682/W684). 2. Remove the four 6-32 screws that hold the heat sink assembly to the rear chassis plate. 3. Lift the assembly out to make room for removing the assembly cable connector. The IS-pin connector is removed by squeezing the retaining tabs on each side of the connector so that when the connector is pulled, the tabs pass through the square holes that they were butted against. Do not pull the connector by its wires, only by its plastic body.

holding the deflection sink to the rear panel. b. Remove heat sink assembly (and its connectors if necessary) and remove faulty power transistor. Later models do not have the four BNC connectors at the top rear of the unit. Figure 4-2 Deflection Heat Sink Removal 4-6

6·32 screws that hold the transistor down. Then pull the transistor straight out from the socket. Apply an even coat (approximately 1/32 inch thick) of thermal compound to an mating surfaces of the new transistor. Replace the new transistor, making sure that the base and emitter pins are oriented properly; otherwise, the transistor case will not align with the two screw holes. Also, ensure that the insulating washer is between the transistor and the heat sink and each mounting screw has a star washer. 4.3.2 . 7007165 Power Regulator Assembly Removal The 7007165 Power Regulator Assembly comprises a G836 regulator printed circuit board with a mounting frame for 11 , J2, J3, and J4. To remove the 7007165 Power Regulator Assembly proceed as follows: 1. Remove the line cord and all circuit modules (G838/G840, A225 , W682/W684). 2. Remove all four cable connectors (Figure 4·3) coming into the connector bracket on the 7007165 by squeezing the two locking tabs on the sides of each connector, while pulling the connector straight up, allowing the locking tabs to pass through the square holes they were butted against. Do not pull the connector by its wires; only by its plastic body. TO VR14 I J4 I G836 REGULATOR BOARD I J2 I I J1 I Jffij W TO TRANSFORMER TO DIODES AND FILTERS 3. Remove the two mounting screws for the 7007165 from the opposite side of the 7007165 chassis wall. 4. The 7007165 is now free and may be pulled straight out. WARNING The 7007165 has +80 Vdc, -80 Vdc, and +400 V dc available on it. These voltages do not disappear immediately when power is shut off. Use extreme caution when throubleshooting the board. 5. For troubleshooting, the 7007165 may be operated outside its normal mounting position by laying the board flat and reconnecting the four cable connectors. Ensure that the etch side of the module does not touch the chassis, causing short circuits, by insulating the board with a book or piece of cardboard as shown in Figure 4-4b. NOTE When placing the 7007165 back into the unit, ensure that the bottom of the circuit board rests in the slotted groove insulator block provided on the bottom chassis. ~ ~ TO POWER J3 SUPPLY HEAT SINK ~ 12-0331 Figure 4·3 7007165 Power Regulator Assembly 4~7

7007165. Unscrew mounting screws from the opposite side of the vertical chassis wall. b. Reconnect connectors and place a cardboard under the 7007165 to prevent shorting out the circuit against the chassis when troubleshooting the board outside the unit. Figure 4-4 7007165 Removal 4·8

To remove the regulator heat sink (Figure 4-5) proceed as follows: 1. 2. Remove the 7007165. See Paragraph 4.3.2 for instructions. Remove the four heat sink mounting screws on the right chassis wall (when viewed from front). 3. Lift the heat sink assembly straight out. 4. To remove a faulty transistor(s), unscrew the two 6-32 screws holding the transistor(s) down; then pun the transistor(s) straight out from the socket. Apply an even coat (approximately 1/32 inch thick) of thermal compound to all mating surfaces of the new transistor. Rep]ace the new transistor, ensuring that the base and emitter pins are oriented properly; otherwise, the transistor case will not align with the two screw holes. Also, ensure that the insulating washer is between the transistor and the heat sink and that each mounting screw has a star washer. 4.3.4 Yoke and CRT Removal To remove the yoke proceed as follows: 1. Remove the line cord and all the circuit modules (G838/G840, A225, W682/W684) along with the plastic CRT socket cover. 2. Carefully remove the yoke cable connector from its mating connector on the inner side of the circuit board mounting bracket. 3. 4. 5. Using a screwdriver, loosen the screw that holds the yoke neck damp by inserting the nut driver through the access slot provided in the CRT shield. Loosen sufficiently for the yoke clamp to be slipped off the yoke. Careful1y remove the CRT socket connector and slide the yoke clamp off the CRT neck. Slip the yoke connector through the access slot in the CRT shield and pass it, along with the entire yoke assemb]y, off the CRT neck and out the rear. Sometimes the yoke gets stuck at the socket end of the CRT because the yoke 4-9 plastic mounting piece hugs the CRT neck tightly and must be spread to pass over the CRT socket. To remove the CRT proceed as fol1ows: 1. 2. 3. 4. Remove the yoke first, as described above, and double check that the line cord is removed. With a long-bladed screwdriver that is grounded to the chassis (a clip lead between the screw- driver blade and chassis plus a second clip lead for safety is adequate), slide the blade under the rubber cup on the high voltage connection at the CRT and touch the anode connection to discharge any remaining high voltage. At the same time, remove the high voltage connection. The connection is made by two stiff wires that each have a bend or hook on the end. The connection at the CRT is made by squeezing these two wires together so they can fit in the CRT metallic hole. Then those two wires are let go so they can expand and grab the inner lip of the CRT with the hooked ends. The connection is removed by squeezing the "hook wires" together and, at the same time, pu11ing them out so that the wires can dear the anode hole. Remove the CRT plastic mask by removing the top and bottom screws from the front bezel casting. The CRT is held by four screws, one at each corner of the screen. As each screw is removed, support the weight of the CRT. CAUTION The CRT is under high vacuum and is potentially in danger of implosion if subjected to sharp blows or very rough handling. Also, to avoid dropping the CRT accidentally, never place your hand over the anode high voltage button while picking up or carrying the CRT, in case the CRT has residual charge. The shock is not, in itself, dangerous but the surprise may cause the user to drop the CRT. Never hold the CRT by the neck (the thin cylindrical portion) alone since it will break off.

unscrew the four 6-32 heat sink mounting screws from the side chassis. Remove two pin connector from the high voltage bracket. b. Lift heat sink straight out and repair faulty transistor. NOTE Thermal cutouts have line voltage on them - be sure line cord is removed Figure 4-5 Regulator Heat Sink Removal 4-10

directly fastened. The VR17 CRT is fastened to its support bracket by four damp tubes (DEC part no. 7411301) mounted to the CRT by a worm gear damp (DEC part no. 9009555). The clamp tubes and worm gear damp are reused when replacing the VR17 CRT. When installing a new CRT on the VR17, mount the 4 clamp tubes to the CRT using the worm gear damp. Do not tighten fully, but leave sufficient slack so that the damp tubes may be aligned with the support bracket screw holes. Once the clamp tubes are aligned, and the CRT fastened to the support bracket, tighten the worm gear clamp. 4-11 4.3.S High Voltage Supply Removal To remove the high voltage supply proceed as follows: 1. Remove the yoke and CRT as outlined in Paragraph 4.3.4. Ensure that the line cord is unplugged. 2. Disconnect the two red and two white wires from the high vo1tage supply from TBI and TB2 of the right side chassis. 3. Remove the cast bezel by removing the three right and left retaining screws. 4. Remove the two side and two bottom high vo1tage assembly mounting bracket screws and remove the high vo1tage assembly out toward the front of the unit.

engineering drawings. If any discrepancies exist between the schematics in this manual, and those delivered with the unit, the set of drawings shipped with the unit should be considered the most accurate. Tables S-1 and S-2 list ~he drawings shipped with the VR14 and VR17, respectively. Table 5-1 VR14 Engineering Drawings Title Drawing Directory Engineering Specification Block Schematic Module Utilization Module Utilization Circuit Schematic (G836) Circuit Schematic (G840) Circuit Schematic (G838) Circuit Schematic (PL) Circuit Schematic (A22S) Circuit Schematic (W684) Circuit Schematic (W682) Circuit Schematic (PL) Cable Keybd. Interlock Circuit Schematic (Heat Sink) Circuit Schematic (Deflection) Circuit Schematic (Power Supply) VR14 Display Assy VR14 Display Assy (PL) Wired Assy Wired Assy (PL) Top Mtg Assy Top Mtg Assy (PL) CRT Yoke Assy Light Pen Assy VR14 Accessory List Drawing No. B-DD-VR14-O A-SP-VR14-04 D-IC-VR14-O-1 C-MU-VR14-O-3 A-PL-VR14-O-3 D-CS-G836-O-1 D-CS-G840-O-1 B-CS-G838-0-1 A-PL-G838-0-O D-CS-A22S -0-1 D-CS-W684-O-1 B-CS-W682-O-1 A-PL-W682-O-0 C-IA-7009248-O-O C-CS-7007080-O-1 C-CS-7007082-O-1 D-CS-7007084-0-1 D-UA-VR14-O-O A-PL-VR14-O-O D-AD-7007078-0-O A-PL-7007078-0-O D-AD-7007077-0-O A-PL-7007077-O-O D-IA -7007088-0-0 C-UA-37S-0-0 A-AL-VR14-0-7 S-l Table 5-2 VR1' Engineering Drawings Title Drawing Directory Engineering Specification Block Schematic Module Utilization Module Utilization Circuit Schematic (G836) Circuit Schematic (G840) Circuit Schematic (A22S) Circuit Schematic (W684) Cable Keybd. Interlock Circuit Schematic (Heat Sink) Circuit Schematic (Deflection) Circuit Schematic (Power Supply) VR17 Display Assy VR17 Display Assy (PL) Wired Assy Wired Assy (PL) Top Mtg Assy Top Mtg Assy (PL) CRT Yoke Assy Light Pen Assy VR17 Accessory List Drawing No. B-DD-VR17-0 A-SP-VR17-04 D-IC-VR14-O-1 C-MU-VR14-O-3 A-PL-VR14-O-3 D-CS-G836-O-1 D-CS-G840-O-1 D-CS-A22S-0-1 D-CS-W684-O-1 C-IA -7009248-0-0 C-CS-7007080-O-1 C-CS-7007082-0-1 D-CS-7007084-O-1 D-UA-VR17-0-O A-PL-VR17-O-O D-AD-7007078-O-O A-PL-7007078-O-O D-AD-7007077 -0-0 A-PL-7007077-0-0 D-IA-7007088-O-O C-UA-37S-O-O A-AL-VR17-O-6

thennal cutout connected to the input line voltage. Always remove the line cord before handling the heat sink. Generally, if the ±22 V reads above ±2S V, one or both of the regulator transistors has shorted. The +22 V is con- trolled by the PNPs (2N4399) that are the front set of transistors on the regulator heat sink (as viewed from the front of the VRI4/VRI7). The -22 V is controlled by the NPNs (2NS302) on the rear section of the regulator heat sink. If, after replacing the power transistors, the problem is not corrected, the G836 board itself is suspect. If the A-I APPENDIX A POWER SUPPLY TROUBLESHOOTING regulator circuits are not working, the output could be beyond its nominal value. The MCl709 is the most likely suspect, followed by the drive transistors, Q3 for +22 Vand QI for -22 V. If, on the other hand, the ±22 V read zero, the same power transistors are still suspect (they may be open). Also, in this case, if the two IN4001 diodes used as current limiting for the power transistors are shorted, the power transistors cannot receive base current and thus will not turn on, rendering their output 0 V. To check for this condition, turn off the power and measure resistance with a YOM set at RXI across DIS and Dl6 if the +22 V was 0, and D13 and Dl4 if the -22 V was O. The resistance with the YOM lead connected either way should always be above S n.

respective power transistors receive no drive and, therefore, are off. When monitoring A02-A (X-yoke current sample) and A03-A (Y -yoke current sample) no reading should be observed. Any voltage at these points indicates a power transistor is on by itself. Generally this transistor is shorted. To determine which transistor is faulty, observe which pin, A02-A or A03-A, has voltage. The A02-A (X-axis) transis- tors are on the right side of the heat sink assembly when viewed from the front of the VR14/VRI7; A03-A (Y-axis) transistors are on the left side. In both cases, a plus voltage at A02-A or A03-A means the PNPs (2N4399) are at fault. These are the lower transistors on both sides. If the voltage APPENDIX B DEFLECTION AMPLIFIER B-1 TROUBLESHOOTING at A02-A or A03-A is minus, the NPNs (2N5302) are faulty. These are the upper transistors on both sides. If no readings are observed at A02-A or A03-A when the A225 boards are removed, then the deflection fault is on the boards themselves (assuming, of course, proper input signals are applied and all power supply voltages are nominal). If the yoke current goes full negative only when the A225 card is plugged into that axis, the most likely suspect is the 2N2904A, Q2. If one axis is faulty, a quick check can be made by swapping the X- and Y -deflection boards (A225) to see if the faulty axis follows the circuit board in question.

have been proven sound, incorrect deflection coil current readings may be isolated to the A225 circuit board itself. If, when the A225 is plugged in, the deflection current goes full negative (about -4 V as measured at A02-A for X, A03-A for Y) and not controllable, Q2 has probably opened and should be replaced. If only half deflection is working (no positive current or no negative current C-I APPENDIX C A225 REPAIR capability) and the power transistors are operating properly, Q3 should be replaced for no positive current and Q4 for no negative current. Also, check R26 and R27 for burns. These resistors overheat if the deflection amplifier is operated in the fault current limit condition for any length of time. Finally, if C9 or CIO become shorted, R9 or RIO, respectively, will burn out. Check C9 or CIO with an ohmmeter to verify this type of failure.

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