Apple CEC IIe Instruction Manual

personal computer using ROM SLOT (J21)' one 60 pin auxiliary'slot for 80 seven I/A slots for General Purpose peripheral computer's capability. a 6502 CPU with 64K Column Text Card'r and cards to extend the key and then press and release cold start instead of turning ' t us e the co ld start f unctiorl r Keyboerd interface is provided with a 16 pin DIP socketi each pin name is described in chapter III.Game I/O is also built lnto the board ttith a 16 pin DIP socket (J15) ancl 9 pin D type connector (JB) to connect with the outside world. Speaker, Casette and Video interfaces are provided. Ihere are two switches on CEC IIe that will activate two special functions ! A . Forced cold Remove JP3, the RESET the powet JP3 must be start. hold down the CONTROL key i you can force a off and on. If you don i n p l a c e . B . Automatic seef-test. Remove JP4, hold down the CONTROL key; then press and release the RESET. CEg IIe will start'running the built-in self-test. The self-test, takes several seconds to run, l{hile it is runningr the display r changes from black to white and back twice. If the test finishes normAlly, the CEC IIe displays a message I'KBRNEL OKn and waits for you to request a normal reset. After doing automatic self-testiremember to insert the JP4 jumper to do the normal reset. II. Instal lation. 1. Turn off the systen unit power. 2. Connect the keyboard to Jl7. 3. Connect the Video cable from Jll to Video nonitor. 4. Insert the RoM CARD into iI21, component side faceing the ' righthand side, components facing anay fron the power connectors. 5. Insert the 80 colurnn text card into ilo if you want 80 column displ ay. 5. Insert any peripheral card into an expansion slot lf desired. 7. connect power cable to power connector. 8. Turn on the system unit power. 9. Remove ,fP4 shorting plug and press CoNTROL RESET KEY. The automatic self-test will start. If there are no errors, the nonitor will display "KERNEL OK".

I, The Auxiliary Slot (J0) Pin Assignment Pin no. Name Description I 3 , 5 8 M 3. 58MHz video color reference signal. This line drives Z LS TTL loads . 2 VIDTM C1dcks the video dot out of ttre parallel-to-serial shift register. This line drives 2 LS TTL loads. Video horizontal and vertical sync signal. This line drives 2 LS TTL I oads . 3 SYNC* 4 ' PRAS * Mutipl exed RAI{ row-address strobe. This line drives 2 LS TTL loads. t 5 VC Third low-order vertical-counter bit. This line drives Z LS TTL loads. 6 C07X* Hand-control reset signal. This line a drives 2 LS TTL loads.r 7 wNDw* Video non-blank window. This line : drives 2 LS TTL loads, . I SEGA First lower vertical counter bit. This Iine drives 2 LS TTL 1oads. 9 ,46 ,L4 ' RA7-RAO Multiplexed Ram-address bus. This 1 3, 4 I , 49 ' line drives 2 LS TTL loads . 1 0 , 5 1 LI ,LZ ROMEN1 ' Enable signals for the ROIvIs on the ROl,lEN2 ROM card. 15 ' 18 ' I 9 ' VIDO-VID7 Video data bus. This three-state 22r38r4L, bus carries video data to the 42 | 45 character generateri 16'17,20' MD7-MDO Internal data bus. This line drives 2L ,39 | 40 | 2 -LS TTL loads . 4 3 , 4 4 23 0 6502 clock phase 0. This line drives 2 LS TTL loads.

ALTVID* SEROUT* ENVID* +5V GND 14t4 PCAS * LDPS * Color-burst gating signal. This drives 2 LS TTL loads. Enables 8O-column display timing. This line drives'2 LS TTL loads. Enable for auxiliary RAM. This line drives 2 LS TTL loads Alternative video outPut to the video summing amplifier. Video serial output from parallel- to-serial shift register. Normally low; driving this line high disabl es the character generator such that the video dots from the shift register are all high (white). and alternative video can be sent out via ALTVID'. This line has a 1000 ohm pul ldown resistor to ground. +5V power supply. System common ground. 14 .3MHz master clock signal . This 1 ine drives 2 LS TTL loads . Ivlultiplexed column-address strobe. This line drives 2 LS TTL loads. Strobe to video paralle1-to-serial shift register. This signal goes low to load the contents of the video data bus into the shift register. This line drives 2 LS TTL loads. Read,/write signa I f or RAM on the I0- column text card. This line drives 2 LS TTL loads. 6502 clock phase L. This line drives 2 LS TTL loads. 3 0 3.1 3 2 3 3 3 4 3 5 R/w 80 3 5

F - - - - F - - C - - - F - - - * - - - - - Pin no. Name DescriPtion 3 7 47 50 5 2 5 3 54 55 5 6 , 5 7 5 8 5 9 6 0 CASEN* HO AN3 R/Yg't Q3 SEGB ENFIRM R A 9 * r R A l 0 * GR 7I.{ ENTl,lG* Column-address enable. This signal is disabled (heId high ) , during aciesses to memory on the auxiliary card, This line drives 2 LS TTL loads . Low-order horizontal byte This line drives 2 LS TTL Output of annunciator 3. drives 2 LS TTL loads. 6502 read/write signal . drives 2 LS TTL loads. 2MHz asymmetrical clock. drives 2 LS TTL loads. counter. loads. This line This line This line Second low-order vertical-counter bit. This line drives 2 LS TTL loads. t Norma1 ly high r pul ling this disables ROMI and ROM2 on CARD. , Character-generator control signals from the IOU . This line drives 2 LS TTL loads. . Graphics-mode enable signal. This 1 ine can drive 2 LS TTL loads. TMHz timing signal. This line drives 2 LS TTL loads. Normally lowr pulling this line high disables the master timing from the PAL. line low the ROM

25 +5V +5 VoIt power supply. 26 GND System common ground. , 27 DIVIA IN DITIA priority daisy-chain input. Usually connected to pin 24 (nUe O U T ) . 28 INT IN Interrupt priority daisy-chain input. Usually connected to pin 23 ( r u t r N ) . 29 NMI* Non-maskable interrupt to 6502. Pul 1 ing this line low starts an interrupt cycle. 30 IRq* Interrupt request Lo 6502. Pulling this line low starts an interrupt cycle only if the interrupt-disable (I) flag in the 6502 is not set. 31' RES* Pulling this line low initiates a reset routine. 32 . . INH* Pul ling this line low during 1 inhibits ( disables ) tne memory on .. the main circuit board. ... 33 -LZV lzV power supply. 34 ; -5V -5V power supply. 35 3. 581'1 3. sSItlHz color ref erenie signal, on slot 7 only. This line drives 2 LS TTL loads. 35 7M System TMHz clock. This line drives 2 LS TTL loads. 37 Q3 System 2MHz asymmetric clock. This line drives 2 LS TTL loads. 38 6502 phase I clock. This line drives 2 LS TTL loads. 39 UPSYNC The 6502 signals an operand fetch by driving this line high during the first read cycle of each instruction.

6502 phase 0 clock. This line drives 2 LS TTL loads. Normal ly high i goes low during 0 when the 6502 addresses location $Conx, where n ig the slot number plus 8. This line drives 10 LS TTL I o a d s . Three-state buffered bi-directional data bus. Data becomes valid during 0 high and remains valid until 0 goes low. Each data line can drive one LS TTL loads. +L2 volt power supply, +5V power supply. Switch input, a rstandard 7 4 LS input. Switch input, a standard 7 4 LS input. Switch input, a standard 7 4 LS input. Strobe output. This line goes low during 0 of a read or write instruction to location $ c 0 4 0 . Hand control inputs. Each of these should be connected to a 150K-ohm variable resistor connected to +5V System ground. Description J 1 5 J 8 Pin no. Pin no. Signa I Name + 5 V SW,/OAPC swl /C.APL sw2 STB PDLO-PDL3 GND i , ' 7 6 r 1 0 , 7 r 1 1 5 t 8 t 4 r 9

1 3 r 1 2 AN0-AN3 Annuciators. These lines are standard 7 4 LS TTL outputs. 9116 N.C. N?thing is connected to these plns . 4. Cassette T/o ( J9 , Jl 0 ) . J9 Phone jack is used as an input from the cassette recorder . J10 Phone jack is used as an output to the cassette recorder . The signal specification for cassette I/O are , , Input: I volt (nominal) from recorder Earphone or Monitor output, Input impedance is 12K ohms. Output z 25 .,millivolts to recoder Microphone input. Output impgdance is 100 ohms. .' 5. The Speaker ( Jl I ) . F Pin no. Name Description 1 SPKR 2 +5V Speaker signal . This line wil I deliver about 0.5 watts into an B-ohm speaker " +5V power supply. I O

(J17) Pin tlo. Name Description 4 r 9 8 L 2 , L 3 , r 0 , 1 1 r 6 , 5 , 7 1 4 1 s 1 6 +5v KSTRB RESET NC GND DATAO-DATA6 swo/oAPr -L2V swl /3APL Switch input, a input, normally -I2 volt power Switch input, input, normal Iy 1 2 +5V power supply. Strobe output from keyboard. This line should be given a pulse at least 10us long each time a key is pressed on the keyboard. THe strobe can be of either polarity, 6 5 0 2 ' s r e s e t l i n e . N o r m a l l y ' h i g h ; this line should be pulled low to restart the computer. No connection. System common ground. Seven bit ASCII Keyboard data input. : standard 74 LS TTL I o w . suppl y. , a standard 7 4 LS TTL l o w . 7 . V i d e o O u t p u t S i g n a l s ( J l 1 r J 1 3 ) . The video signal is an NTSC-compatible composite-video signal that can be displayed on a standard video monitor. This signal is available in two places; JlI (nCa JACK) and J13 ( tlot ex-type pins ) on Jl I . The sleeve of this jack is connected to ground and the tip is connected to the video signal on J13. The pin assignment is as follows: I 1

Power Connector (,rra, J20). J20 pin assignment: System common ground. NTSC-compatibl e po sitive video. white leve1 is volts, black level is vo1ts, and sync level is -5V power supply. +12V power supply. I 2 i L 1 composite about 2.0 about, 0.75 0 volts. 3 4 8 . Pin no. Name Des cr ipt ion I 2 3 4 5 6 Ground + 1 2 V -5V - 1 2 v +5V +5V Common electrical ground. +12V from power supply. -5V .f rom power supply. -12V from power supply. + 5V f rom power suppl y .' +5V from power supply. J14 pin assignment: Pin no. Name Description I 2 3 4 5 6 Ground Ground +5V +L2Y - 12V -5V Common electrical ground. Common el,ectrica I ground . +5V form power supply. +12V from power supply. -L2V from power supply. -5v from power supply. L 2

ROM slot is a 16K ROM expansion card to install the dedicated operating program for the CEC IIe single board computers. Pin assignment as follows: Pin no. Name Description 1 r 1 5 * 2 4 , N . C . 3 7 - 4 9 r 5 0 2-L 4 A0 -A12 No connection. Three state address lines from'6502. 25 +5V +5V power supply, 26 GND System ground.' 27-34 I4D7-MD0 Internal data bus. 3s ' 36 il3ilHil1:, Enab1e sisnals for the RoMs. 49 ROIIIOE* Enable signals for the ROM€ on the ROM card. IV. POWER REQUIREMENT. I To operate. .,the CEC IIe plus a full complement of peripheral cards. inc\.uding disk controller cards and coumunications interfaces, we suggest the basic power specification bs follows: Maximum polrer consumption: 60w continuous 80w intermittent Voltages and Maximum current! d . + 5 V ( + 3 t ) : 2 . 5 A b . + L z V ( + 6 8 ) : 1 . 5 A c o n t i n u o u s 2.5A intermittent c. -5V (+10t ) : 250 MA d . - L 2 V ( + 1 0 t ) 3 2 5 0 M A 1 3

single board computer should any trouble occur, do the following: 1. Make sure JP3 and JP4 short plugs are in position when t,he CEC IIe is in normal use. 2. Remove JP4 and press CONTROL RESET on keyboard to start self- test. If test fail s, contact the dealer for repair. 3. When a color monitor is used but color is not correctrtry to adjust the color trimmer VCl and VCz to get the right color. If there is no color, odjust VCI first, then VC2. 4. If there is any trouble you*can not fix, contact your deaLer. VI . TECHNICAL INFORMATION. I, The PAL Circuit. A Programmed Array Logic device, type PAL l6Rsrgenerates several timing and control signals in the CEC IIe. These signals are listed as follows: ,: The PAL pinout: ' ; 1 4 M 1 2 0 + 5 V HO 2 19 VIDTM 8 OVID * 3 18 PRAS * V I D T 4 L 7 O 3 . 5 8 M 5 1 6 L D P S * cAsEN* 6 15 Q3 cR 7 14 01 TIvl 8 13 N. C. SEGB 9 L2 PCAS GND 10 11 ENTI\,IG* L 4

lvlHz master timing s i g n a l . Horizontal videos timing signal. Enab1e 8O-column disp}ay mode. Video data bit, 7 . 3. 57 9545 MHz timing signal . RAM enable. t Video display graphics-ffiod€ e n a b l e . 7 .L5909 MHz timing signal. Video timing signal. Power and signal cornmon. Enable master timing. j RAM .co lumn-address strobe . (fhis pin is not used, ) Phase I system cIock. t Intermediate timing and strobe s i g n a l . Video shift-register enable. Phase 0 system clock. RAIvI Row-address strobe. Video dot clock, 7 or 14 MHz. Power. 1 3 - N . c . f, 1 i 1 I t r ' r 1 5 - ' Q 3 ' i $ I 5

6530L is designed with CMOS techonology; implements the following soft switches: ir Page 2 display (PAGE2), Hi-res mode (HIRES)' Text mode ( TEXT ) , Mixed mode (MIXED') , 80-column display ( B0 co1 ) , character-set select (ALTCHARSET ) any-key-down ' At'rnunciators , Vertica 1 bl anking ( VBL ) . The IOU generates the mulLiplexed address for the 64K dynamic RAIt'Is used in the CEC IIe for the data trarlsfers required for display and memory refresh during clock phase 1. The 55301 pinout: v c l 6 0 / 5 0 2 WNDW* 3 SYNC* 4 CLRGAT* 5 H O 6 RAO 7 RAl 8 RA2 9 RA3 10 GND 11 *il i3 RA6 14 RA7 15 t ' 0 1 6 Q 3 L 7 :" PRAS * 18 ' r u 1 A 5 1 9 coxx* 20 t ' . _ 4 0 3 9 3 8 3 7 3 5 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 L SEG B SEG A GR VID 6 VID 7 RAl O RA9 AKD KSTRB VDD 8 0 V I D ANO ANI AN2 AN3 RESET* IVIDT R/w CASSO SPKR Pin no. Name Des cript ion VC 6 0 / 5 0 WNDW* SYNC* _ CLRGAT* Display vertical counter bit. 60Hz or 50 Hz. Display blanking signal. Display synchronization signal. Color-burst gate. 1 6

Name Description 6 HO Display horizontal timing. 7-10 RA0-RA3 lvtultiplexed RAM address (phase 0). I I GND Signal common. t2-1 5 RA4-RA7 M"ltiplexed RAM address ( phase 0 ) . 16 0 lvlaster clock phase 0. L7 e3 Intermediate timing signal. 18 PRAS* Row-address strobe (phase 0). 19 A5 Address bit 6 from 6502. 20 coxx* r/O address enable. 2L SPKR Speaker output signal. 22 CASSO Cassette output signal. 23 R/W 6502 Read-Write control signal. 24 MD7 Internal flag to data bus 25 RESET* Power on and reset output. t ' , 26-29 AN3-AN0 Annunciator output. 30 " 80VID* 8O-column video enable. 31, ; vDD +5v System po\^rer. 32 KSTRB Keyboard strobe signa|, 33 AKD Any-key-down signal. 34-35 RA9,RA10 Video display control bits. 36-37 VIDT , VID6 Video data b j-ts . 38 GR Graphics mode enable. '39 , 4 0 SEGA, SEGB Disp}ay vertieal eounter bits . l 7

65371 65371 is designed with CMOS technology, implements the fol lowing soft-switches : Page 2 display (PAGE2), Hi-res mode ( HrREs ) , store to 80- column card ( S0 STORE ) , select bank 2, enable bank-switched RAIvl, read auxiliary memory (RAMWRT ) , auxiliary stack and zero page (ar,rzpl , slot ROI'I for connector #3 (SLorC3Roll), slot ROIt'l in I/O space ( Sf-,OfCXROl*1) . The 65371 generates multiplexed address for memory reading and writing by the 6542 CPU. The 65371 pinouts: cxxx R/W245 * ROMEN1 * ENSO* 0 PRAS * Q3 RA7 RA5 RA5 GND RA4 RA3 RA2 RAl MD7 AO A1 A2 I 2 3 4 5 6 7 I 9 1 0 1 1 L 2 1 3 1 4 1 5 L 7 1 8 1 9 2 0 40 cAsEN* 3 9 INH* 3 8 R/w* 37 ROMEN2* 36 KBD* 3 5 DIvIA* 3 4 A 1 5 3 3 A 1 4 3 2 A 1 3 3 1 A 1 2 30 VDD 2 9 A I l 2 8 A 1 0 2 7 A 9 26 A8 24 A6 23 A5 22 A4 2L A3 1 8

Name Description ' I cxxx Enables peripheral-card memory. 2 R/w245* Control data bus buffer. 3 RoMENI * Enables ROM #1. 4 EN80* Enables auxiliary RAM. 5 0 Ctock phase 0. 6 PRAS* Memory row-address strobe. 7 Q3 Timing signal. 8-10 RA7-RA5 Multiplexed address output. 11 cND Signal conmon. L2-I6 RA4-RA0 Multiplexed address output. 17 MD7 Data bus bit. 18-29 A0-A11 6502 address output. 30 VDD +5V system power. 31-34 A12-A15 65A2 address output. t ' 3s .. 36 ;' KBD* Enables keyboard data bits. 3':-, ; ROMEN2* Enables ROIvI #2. 38 R/v1* 6502 read write control signal . 39 rNH* rnhibits main memory. 40 CASEN* Enables RAM. 1 9

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