Sun Microsystems 2060 Manuals

Sun Microsystems 2060 Hardware engineering manual (405 pages)

• Identifier: id-2249350
• Brand: Sun Microsystems
• Device: Computer Hardware
• Type: Hardware engineering manual, PDF
• Key Aspects: Safety Features Description, Tips for Best Performance, Environmental Impact Assessments
• UPD Date: 19.07.2026
• Source File: 2038282.pdf
• Pages: 405
• Description: Reference manual for the Sun Microsystems 2060. The manual elaborates on features and technical specifications, troubleshooting tips, service procedures.

Key Pages and Contents:

• Chapter 19 -

  Page Map RA.\1 129 ctlspc*/p_a31*/p_a30*/p_a29*p_a28* /p2_aOl*p2_aOO*p2_rw*cs4 + ctlspc*/p_a31*/p_a30*/p_a29* p_a2B* /p2_aOl*p2_aOO*cs4*/p2_rw*/ttlwend This mrnu~16 signal is asserted when: 1. you are doing a control space access and address bits pa_31 :28 decode to the page map RAM (00

• Interrupt Circuitry -

  U302-U304 PALs, U305 Register This Chapter covers the three interrupt PALs, U304:2, on page three of the schematics. It also describes the interrupt priority latch, U305. Interrupts can come from the [J Vrv1Ebus (through J300 header) [J on-board devices . [J interrupt enable

• 2060 CPU Board Engineering Manual CONFIDE~TIAL!

  4. e_reset- : resets the Ethernet controller. U1405 read buffer's outputs are held static to the Ethernet controller until the buffer is either cleared or new data is clocked into it by the rising edge of wr_ether-. U1405 is cleared (all Qoutputs a

• 2060 CPU Board Engineering Manual CO~FlDE~IIAL!

  ..2. U612 Output Signals Outputs from U612 are: ltypO mmu vrne- mmu io- latched version of typeO valid VME master cycle (to type2 or type3 space) valid IO cycle (to typel space) The above signals are asynchronous state machines tJuJt latch when ass