Keysight U7233A Testing Notes

173 Calibrating the Infiniium Oscilloscope and Probe 13 d During the calibration of channel 1, if you are prompted to perform a Time Scale Calibration, as shown in Figure 56 below. Figure 56 Time Scale Calibration Dialog box e Click on the Std+Dflt button to continue the calibration, using the Factory default calibration factors. f When the calibration procedure is complete, you will be prompted with a Calibration Complete message window. Click the OK button to close this window. g Confirm that the Vertical and Trigger Calibration Status for al ...

52 DDR1 Compliance Testing Methods of Implementation ...

124 DDR1 Compliance Testing Methods of Implementation tDQSCK, DQS Output Access Time from CK/CK #- Test Method of Implementation The purpose of this test is to verify that the time interval from the data strobe output (DQS rising and falling edge) access time to the nearest rising or falling edge of the clock is within the conformance limit as specified in the JEDEC Standard JESD79E. There is tDQSCK(min) and tDQSCK(max) as shown in Figure 39. From the specification, you can observe that the minimum value is at negative while the maximum is at positive. Figure 39 DQS O ...

Notices © Keysight Technologies 2015 - 2017 No part of this manual may be reproduced in any form or by any means (including elec- tronic storage and retrieval or translation into a foreign language) without prior agree- ment and written consent from Keysight Technologies as governed by United States and international copyright laws. Manual Part Number U7233-97002 Edition Fifth Edition, April 2017 Printed in Malaysia Keysight Technologies. 1900 Garden of the Gods Road Colorado Springs, CO 80907 USA Warranty THE MATERIAL CONTAINED IN THIS DOCU ...

155 Advanced Debug Mode Clock Tests 11 Cycle to Cycle Period Jitter - tJIT(cc) - Test Method of Implementation This test is applicable to the Rising Edge Measurement as well as Falling Edge Measurement. The purpose of this test is to measure the difference in the clock period between two consecutive clock cycles. The tJIT(cc) Rising Edge Measurement measures the clock period from the rising edge of a clock cycle to the next rising edge. The tJIT(cc) Falling Edge Measurement measures the clock period from the falling edge to falling edge. The te ...

100 DDR1 Compliance Testing Methods of Implementation tDQSH, DQS Input High Pulse Width - Test Method of Implementation The purpose of this test is to verify that the width of the high level of the data strobe signal is within the conformance limit as specified in the JEDEC Standard JESD79E. Signals of Interest Based on the test definition (Read cycle only): • Data Strobe Signal (DQS as Pin Under Test Signal) Signals required to perform the test on the oscilloscope: • Data Strobe Signal (DQS as Pin Under Test Signal) • Data Signal (DQ as Supporting Signal ...

192 DDR1 Compliance Testing Methods of Implementation Missing Signal Error This error occurs when the required signals are either not selected in the “Channel Setting” configuration or not connected to the oscilloscope. Ensure that correct channel is selected based on the signal that is physically present at the oscilloscope channel. Figure 72 Missing Signal Error Message ...

191 Common Error Messages 15 Frequency Out of Range Error You are allowed to type in the DUT data rate for the Advanced Debug Mode tests. However, if you enter an incorrect data strobe test signal frequency, the following error dialog box appears. For example, if the selected DDR1 speed grade option is DDR1-400, the expected frequency of the data strobe signal, DQS is 200MH (half of the data transfer rate). However, if the measured DQS frequency is out by +/-10% of the expected frequency value, exception will be thrown. Type in the correct data ...