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TMS320DM357 DMSoC Enhanced Direct
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Submit Documentation Feedback
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List of Figures
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List of Tables
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Read This First
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Terminology Used in This Document
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EDMA3 Controller Block Diagram
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EDMA3 Transfer Controller (EDMA3TC)
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Types of EDMA3 Transfers
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Each array submit
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Parameter RAM (PaRAM)
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Parameter set 1
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EDMA3 Channel Parameter Set Fields
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Source B Index (SRCBIDX)
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Null PaRAM Set
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Initiating a DMA Transfer
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Manually-Triggered Transfer Request
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Autotriggered and Link-Triggered Transfer Request
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Completion of a DMA Transfer
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Dummy or Null Completion
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DMA Channel to PaRAM Mapping
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0000 0000 0000 00
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Channel Controller Regions
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Chaining EDMA3 Channels
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Transfer Completion Interrupts
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Enabling Transfer Completion Interrupts
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Example 2-1. Interrupt Servicing
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Interrupt Evaluation Operations
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Figure 2-13. Error Interrupt Operation
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DMA/QDMA Channel to Event Queue Mapping
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Destination FIFO Register Pointer
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Trigger Source Priority
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EDMA3 Transfer Examples
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Block Move Example
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Subframe Extraction Example
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Data Sorting Example
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Peripheral Servicing Example
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Synchronization with the CPU
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Transfer Chaining Examples
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Channel 32, array 0
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16 KBytes data transfer
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Register Memory Maps
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Channel Options Parameter (OPT)
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Parameter RAM (PaRAM) Entries
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Channel Source Address Parameter (SRC)
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Channel Destination Address Parameter (DST)
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EDMA3 Channel Controller Control Registers
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Peripheral Identification Register (PID)
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QDMA Channel Map n Registers (QCHMAPn)
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DMA Channel Queue Number Registers (DMAQNUMn)
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QDMA Channel Queue Number Register (QDMAQNUM)
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Queue Priority Register (QUEPRI)
102
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Event Missed Clear Registers (EMCR/EMCRH)
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QDMA Event Missed Register (QEMR)
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QDMA Event Missed Clear Register (QEMCR)
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EDMA3CC Error Register (CCERR)
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EDMA3CC Error Clear Register (CCERRCLR)
108
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Error Evaluation Register (EEVAL)
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Region Access Enable Registers
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QDMA Region Access Enable Registers (QRAEm)
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Status/Debug Visibility Registers
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Queue n Status Registers (QSTATn)
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Queue Watermark Threshold A Register (QWMTHRA)
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EDMA3CC Status Register (CCSTAT)
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DMA Channel Registers
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Event Clear Registers (ECR, ECRH)
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Event Set Registers (ESR, ESRH)
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Chained Event Registers (CER, CERH)
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Event Enable Registers (EER, EERH)
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Event Enable Clear Register (EECR, EECRH)
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Event Enable Set Registers (EESR, EESRH)
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Secondary Event Registers (SER, SERH)
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Secondary Event Clear Registers (SECR, SECRH)
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Interrupt Enable Registers (IER, IERH)
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Interrupt Enable Clear Register (IECR, IECRH)
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Interrupt Enable Set Registers (IESR, IESRH)
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Interrupt Pending Register (IPR, IPRH)
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Interrupt Clear Registers (ICR, ICRH)
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Interrupt Evaluate Register (IEVAL)
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QDMA Event Register (QER)
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QDMA Event Enable Register (QEER)
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QDMA Event Enable Clear Register (QEECR)
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QDMA Event Enable Set Register (QEESR)
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QDMA Secondary Event Register (QSER)
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QDMA Secondary Event Clear Register (QSECR)
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EDMA3 Transfer Controller Control Registers
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EDMA3TC Configuration Register (TCCFG)
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EDMA3TC Channel Status Register (TCSTAT)
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Error Status Register (ERRSTAT)
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Error Enable Register (ERREN)
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Error Clear Register (ERRCLR)
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Error Details Register (ERRDET)
147
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Error Interrupt Command Register (ERRCMD)
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Read Rate Register (RDRATE)
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Source Active Options Register (SAOPT)
150
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Source Active Source Address Register (SASRC)
151
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Source Active Destination Address Register (SADST)
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Source Active Count Reload Register (SACNTRLD)
154
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Destination FIFO Options Register (DFOPTn)
156
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Destination FIFO Source Address Register (DFSRCn)
157
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Destination FIFO Count Register (DFCNTn)
158
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Destination FIFO Count Reload Register (DFCNTRLDn)
161
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Miscellaneous Programming/Debug Tips
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Setting Up a Transfer
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5. Wait for completion:
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