Texas Instruments TMS320DM357 Operation & User’s Manual

Memory Access (EDMA3) Controller User's Guide Literature Number: SPRUG34 November 2008

1.1 Overview..................................................................................................................... 18 1.2 Features ..................................................................................................................... 18 1.3 Terminology Used in This Document.................................................................................... 19 2 EDMA3 Architecture ................................................................................................. 21 2.1 Functional Overview ....................................................................................................... 22 2.1.1 EDMA3 Controller Block Diagram............................................................................... 22 2.1.2 EDMA3 Channel Controller (EDMA3CC) ...................................................................... 22 2.1.3 EDMA3 Transfer Controller (EDMA3TC)....................................................................... 24 2.2 Types of EDMA3 Transfers............................................................................................... 25 2.2.1 A-Synchronized Transfers........................................................................................ 26 2.2.2 AB-Synchronized Transfers...................................................................................... 27 2.3 Parameter RAM (PaRAM) ................................................................................................ 28 2.3.1 PaRAM Set......................................................................................................... 29 2.3.2 EDMA3 Channel Parameter Set Fields ........................................................................ 31 2.3.3 Null PaRAM Set ................................................................................................... 33 2.3.4 Dummy PaRAM Set............................................................................................... 33 2.3.5 Dummy Versus Null Transfer Comparison..................................................................... 33 2.3.6 Parameter Set Updates .......................................................................................... 33 2.3.7 Linking Transfers.................................................................................................. 35 2.4 Initiating a DMA Transfer.................................................................................................. 38 2.4.1 DMA Channel...................................................................................................... 38 2.4.2 QDMA Channels .................................................................................................. 41 2.4.3 Comparison Between DMA and QDMA Channels............................................................ 41 2.5 Completion of a DMA Transfer ........................................................................................... 42 2.5.1 Normal Completion................................................................................................ 43 2.5.2 Early Completion .................................................................................................. 43 2.5.3 Dummy or Null Completion ...................................................................................... 43 2.6 Event, Channel, and PaRAM Mapping.................................................................................. 43 2.6.1 DMA Channel to PaRAM Mapping.............................................................................. 44 2.6.2 QDMA Channel to PaRAM Mapping............................................................................ 44 2.7 EDMA3 Channel Controller Regions .................................................................................... 45 2.7.1 Region Overview .................................................................................................. 45 2.7.2 Channel Controller Regions...................................................................................... 47 2.8 Chaining EDMA3 Channels............................................................................................... 47 2.9 EDMA3 Interrupts .......................................................................................................... 49 2.9.1 Transfer Completion Interrupts .................................................................................. 49 2.9.2 EDMA3 Interrupt Servicing....................................................................................... 51 2.9.3 Interrupt Evaluation Operations ................................................................................. 54 2.9.4 Error Interrupts..................................................................................................... 54 SPRUG34–November 2008 Contents 3 Submit Documentation Feedback

2.10.1 DMA/QDMA Channel to Event Queue Mapping ............................................................. 56 2.10.2 Queue RAM Debug Visibility ................................................................................... 56 2.10.3 Queue Resource Tracking ...................................................................................... 56 2.10.4 Performance Considerations ................................................................................... 56 2.11 EDMA3 Transfer Controller (EDMA3TC)................................................................................ 57 2.11.1 Architecture Details .............................................................................................. 57 2.11.2 Error Generation.................................................................................................. 58 2.11.3 Debug Features .................................................................................................. 59 2.11.4 EDMA3TC Configuration........................................................................................ 59 2.12 Event Dataflow.............................................................................................................. 60 2.13 EDMA3 Prioritization....................................................................................................... 61 2.13.1 Channel Priority .................................................................................................. 61 2.13.2 Trigger Source Priority........................................................................................... 62 2.13.3 Dequeue Priority.................................................................................................. 62 2.13.4 System (Transfer Controller) Priority.......................................................................... 62 2.14 EDMA3 Operating Frequency (Clock Control) ......................................................................... 62 2.15 Reset Considerations...................................................................................................... 62 2.16 Power Management........................................................................................................ 63 2.17 Emulation Considerations................................................................................................. 63 3 EDMA3 Transfer Examples ........................................................................................ 65 3.1 Block Move Example ...................................................................................................... 66 3.2 Subframe Extraction Example............................................................................................ 68 3.3 Data Sorting Example ..................................................................................................... 70 3.4 Peripheral Servicing Example ............................................................................................ 72 3.4.1 Nonbursting Peripherals.......................................................................................... 72 3.4.2 Bursting Peripherals .............................................................................................. 74 3.4.3 Continuous Operation ............................................................................................ 76 3.4.4 Ping-Pong Buffering............................................................................................... 79 3.4.5 Transfer Chaining Examples..................................................................................... 82 4 Registers ................................................................................................................. 85 4.1 Register Memory Maps.................................................................................................... 86 4.2 Parameter RAM (PaRAM) Entries ....................................................................................... 86 4.2.1 Channel Options Parameter (OPT)............................................................................. 87 4.2.2 Channel Source Address Parameter (SRC)................................................................... 89 4.2.3 A Count/B Count Parameter (A_B_CNT) ...................................................................... 89 4.2.4 Channel Destination Address Parameter (DST) .............................................................. 90 4.2.5 Source B Index/Destination B Index Parameter (SRC_DST_BIDX)........................................ 90 4.2.6 Link Address/B Count Reload Parameter (LINK_BCNTRLD)............................................... 91 4.2.7 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ....................................... 92 4.2.8 C Count Parameter (CCNT) ..................................................................................... 92 4.3 EDMA3 Channel Controller Control Registers ......................................................................... 93 4.3.1 Global Registers................................................................................................... 97 4.3.2 Error Registers ................................................................................................... 102 4.3.3 Region Access Enable Registers.............................................................................. 110 4.3.4 Status/Debug Visibility Registers .............................................................................. 112 4.3.5 DMA Channel Registers ........................................................................................ 116 4.3.6 Interrupt Registers............................................................................................... 128 4 Contents SPRUG34–November 2008 Submit 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4.4 EDMA3 Transfer Controller Control Registers........................................................................ 140 4.4.1 Peripheral Identification Register (PID)....................................................................... 141 4.4.2 EDMA3TC Configuration Register (TCCFG)................................................................. 142 4.4.3 EDMA3TC Channel Status Register (TCSTAT) ............................................................. 143 4.4.4 Error Registers ................................................................................................... 144 4.4.5 Read Rate Register (RDRATE)................................................................................ 149 4.4.6 EDMA3TC Channel Registers ................................................................................. 149 A Tips ....................................................................................................................... 163 A.1 Debug Checklist........................................................................................................... 163 A.2 Miscellaneous Programming/Debug Tips.............................................................................. 164 B Setting Up a Transfer .............................................................................................. 165 SPRUG34–November 2008 Contents 5 Submit Documentation Feedback

2-1 EDMA3 Controller Block Diagram........................................................................................ 22 2-2 EDMA3 Channel Controller (EDMA3CC) Block Diagram............................................................. 23 2-3 EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................. 24 2-4 Definition of ACNT, BCNT, and CCNT ................................................................................. 25 2-5 A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)....................................................... 26 2-6 AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)..................................................... 27 2-7 PaRAM Set.................................................................................................................. 29 2-8 Linked Transfer............................................................................................................. 36 2-9 Link-to-Self Transfer ....................................................................................................... 37 2-10 QDMA Channel to PaRAM Mapping .................................................................................... 45 2-11 Shadow Region Registers ................................................................................................ 46 2-12 Interrupt Diagram........................................................................................................... 51 2-13 Error Interrupt Operation .................................................................................................. 55 2-14 EDMA3 Prioritization....................................................................................................... 61 3-1 Block Move Example ...................................................................................................... 66 3-2 Block Move Example PaRAM Configuration............................................................................ 67 3-3 Subframe Extraction Example............................................................................................ 68 3-4 Subframe Extraction Example PaRAM Configuration................................................................. 69 3-5 Data Sorting Example ..................................................................................................... 70 3-6 Data Sorting Example PaRAM Configuration .......................................................................... 71 3-7 Servicing Incoming ASP Data Example................................................................................. 72 3-8 Servicing Incoming ASP Data Example PaRAM....................................................................... 73 3-9 Servicing Peripheral Burst Example ..................................................................................... 74 3-10 Servicing Peripheral Burst Example PaRAM........................................................................... 75 3-11 Servicing Continuous ASP Data Example .............................................................................. 76 3-12 Servicing Continuous ASP Data Example PaRAM .................................................................... 77 3-13 Servicing Continuous ASP Data Example Reload PaRAM........................................................... 78 3-14 Ping-Pong Buffering for ASP Data Example ........................................................................... 80 3-15 Ping-Pong Buffering for ASP Example PaRAM........................................................................ 80 3-16 Ping-Pong Buffering for ASP Example Pong PaRAM................................................................. 81 3-17 Ping-Pong Buffering for ASP Example Ping PaRAM.................................................................. 82 3-18 Intermediate Transfer Completion Chaining Example................................................................. 83 3-19 Single Large Block Transfer Example................................................................................... 84 3-20 Smaller Packet Data Transfers Example................................................................................ 84 4-1 Channel Options Parameter (OPT)...................................................................................... 87 4-2 Channel Source Address Parameter (SRC)............................................................................ 89 4-3 A Count/B Count Parameter (A_B_CNT) ............................................................................... 89 4-4 Channel Destination Address Parameter (DST) ....................................................................... 90 4-5 Source B Index/Destination B Index Parameter (SRC_DST_BIDX)................................................. 90 4-6 Link Address/B Count Reload Parameter (LINK_BCNTRLD)........................................................ 91 4-7 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ................................................ 92 4-8 C Count Parameter (CCNT) .............................................................................................. 92 4-9 Peripheral ID Register (PID).............................................................................................. 97 4-10 EDMA3CC Configuration Register (CCCFG)........................................................................... 97 4-11 QDMA Channel Map n Registers (QCHMAPn) ........................................................................ 99 4-12 DMA Channel Queue Number Registers (DMAQNUMn)............................................................ 100 4-13 QDMA Channel Queue Number Register (QDMAQNUM) .......................................................... 101 4-14 Queue Priority Register (QUEPRI) ..................................................................................... 102 4-15 Event Missed Register (EMR)........................................................................................... 103 4-16 Event Missed Register High (EMRH) .................................................................................. 103 4-17 Event Missed Clear Register (EMCR) ................................................................................. 104 4-18 Event Missed Clear Register High (EMCRH)......................................................................... 104 6 List of Figures SPRUG34–November 2008 Submit Documentation Feedback

4-20 QDMA Event Missed Clear Register (QEMCR) ...................................................................... 106 4-21 EDMA3CC Error Register (CCERR) ................................................................................... 107 4-22 EDMA3CC Error Clear Register (CCERRCLR)....................................................................... 108 4-23 Error Evaluation Register (EEVAL)..................................................................................... 109 4-24 DMA Region Access Enable Register for Region m (DRAEm)..................................................... 110 4-25 DMA Region Access Enable High Register for Region m (DRAEHm) ............................................ 110 4-26 QDMA Region Access Enable for Region m (QRAEm) ............................................................. 111 4-27 Event Queue Entry Registers (QxEy).................................................................................. 112 4-28 Queue n Status Register (QSTATn) ................................................................................... 113 4-29 Queue Watermark Threshold A Register (QWMTHRA)............................................................. 114 4-30 EDMA3CC Status Register (CCSTAT) ................................................................................ 115 4-31 Event Register (ER) ...................................................................................................... 117 4-32 Event Register High (ERH).............................................................................................. 117 4-33 Event Clear Register (ECR)............................................................................................. 118 4-34 Event Clear Register High (ECRH)..................................................................................... 118 4-35 Event Set Register (ESR)................................................................................................ 119 4-36 Event Set Register High (ESRH) ....................................................................................... 120 4-37 Chained Event Register (CER) ......................................................................................... 121 4-38 Chained Event Register High (CERH)................................................................................. 121 4-39 Event Enable Register (EER) ........................................................................................... 122 4-40 Event Enable Register High (EERH)................................................................................... 122 4-41 Event Enable Clear Register (EECR).................................................................................. 123 4-42 Event Enable Clear Register High (EECRH).......................................................................... 123 4-43 Event Enable Set Register (EESR) .................................................................................... 124 4-44 Event Enable Set Register High (EESRH) ............................................................................ 124 4-45 Secondary Event Register (SER)....................................................................................... 125 4-46 Secondary Event Register High (SERH) .............................................................................. 126 4-47 Secondary Event Clear Register (SECR) ............................................................................. 126 4-48 Secondary Event Clear Register High (SECRH) ..................................................................... 127 4-49 Interrupt Enable Register (IER)......................................................................................... 128 4-50 Interrupt Enable Register High (IERH)................................................................................. 128 4-51 Interrupt Enable Clear Register (IECR)................................................................................ 129 4-52 Interrupt Enable Clear Register High (IECRH)........................................................................ 129 4-53 Interrupt Enable Set Register (IESR) .................................................................................. 130 4-54 Interrupt Enable Set Register High (IESRH) .......................................................................... 130 4-55 Interrupt Pending Register (IPR)........................................................................................ 131 4-56 Interrupt Pending Register High (IPRH) ............................................................................... 131 4-57 Interrupt Clear Register (ICR)........................................................................................... 132 4-58 Interrupt Clear Register High (ICRH)................................................................................... 132 4-59 Interrupt Evaluate Register (IEVAL).................................................................................... 133 4-60 QDMA Event Register (QER) ........................................................................................... 134 4-61 QDMA Event Enable Register (QEER) ................................................................................ 135 4-62 QDMA Event Enable Clear Register (QEECR)....................................................................... 136 4-63 QDMA Event Enable Set Register (QEESR) ......................................................................... 137 4-64 QDMA Secondary Event Register (QSER)............................................................................ 138 4-65 QDMA Secondary Event Clear Register (QSECR) .................................................................. 139 4-66 Peripheral ID Register (PID)............................................................................................. 141 4-67 EDMA3TC Configuration Register (TCCFG).......................................................................... 142 4-68 EDMA3TC Channel Status Register (TCSTAT) ...................................................................... 143 4-69 Error Status Register (ERRSTAT)...................................................................................... 144 4-70 Error Enable Register (ERREN) ........................................................................................ 145 4-71 Error Clear Register (ERRCLR) ........................................................................................ 146 SPRUG34–November 2008 List of Figures 7 Submit Documentation Feedback

4-73 Error Interrupt Command Register (ERRCMD)....................................................................... 148 4-74 Read Rate Register (RDRATE)......................................................................................... 149 4-75 Source Active Options Register (SAOPT)............................................................................. 150 4-76 Source Active Source Address Register (SASRC)................................................................... 151 4-77 Source Active Count Register (SACNT)............................................................................... 151 4-78 Source Active Destination Address Register (SADST) .............................................................. 152 4-79 Source Active Source B-Dimension Index Register (SABIDX) ..................................................... 152 4-80 Source Active Memory Protection Proxy Register (SAMPPRXY).................................................. 153 4-81 Source Active Count Reload Register (SACNTRLD) ................................................................ 154 4-82 Source Active Source Address B-Reference Register (SASRCBREF)............................................ 154 4-83 Source Active Destination Address B-Reference Register (SADSTBREF)....................................... 155 4-84 Destination FIFO Options Register (DFOPTn)........................................................................ 156 4-85 Destination FIFO Source Address Register (DFSRCn).............................................................. 157 4-86 Destination FIFO Count Register (DFCNTn).......................................................................... 158 4-87 Destination FIFO Destination Address Register (DFDSTn)......................................................... 159 4-88 Destination FIFO B-Index Register (DFBIDXn)....................................................................... 159 4-89 Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)............................................. 160 4-90 Destination FIFO Count Reload Register (DFCNTRLDn)........................................................... 161 4-91 Destination FIFO Source Address B-Reference Register (DFSRCBREFn) ...................................... 161 4-92 Destination FIFO Destination Address B-Reference Register (DFDSTBREFn).................................. 162 List of Figures 8 SPRUG34–November 2008 Submit Documentation Feedback

2-1 EDMA3 Parameter RAM Contents....................................................................................... 28 2-2 EDMA3 Channel Parameter Description................................................................................ 30 2-3 Dummy and Null Transfer Request...................................................................................... 33 2-4 Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set)....................................... 34 2-5 EDMA3 Channel Synchronization Events............................................................................... 38 2-6 Expected Number of Transfers for Non-Null Transfer................................................................. 42 2-7 EDMA3 DMA Channel to PaRAM Mapping ............................................................................ 44 2-8 Shadow Region Registers ................................................................................................ 46 2-9 EDMA3 Shadow Regions ................................................................................................. 47 2-10 Chain Event Triggers ...................................................................................................... 48 2-11 EDMA3 Transfer Completion Interrupts................................................................................. 49 2-12 EDMA3 Error Interrupts ................................................................................................... 49 2-13 Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping................................................... 50 2-14 Number of Interrupts....................................................................................................... 50 2-15 Read/Write Command Optimization Rules.............................................................................. 58 2-16 EDMA3 Transfer Controller Configurations............................................................................. 59 4-1 EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries...................................... 86 4-2 Channel Options Parameters (OPT) Field Descriptions .............................................................. 87 4-3 Channel Source Address Parameter (SRC) Field Descriptions...................................................... 89 4-4 A Count/B Count Parameter (A_B_CNT) Field Descriptions......................................................... 89 4-5 Channel Destination Address Parameter (DST) Field Descriptions................................................. 90 4-6 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .......................... 90 4-7 Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions.................................. 91 4-8 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions.......................... 92 4-9 C Count Parameter (CCNT) Field Descriptions........................................................................ 92 4-10 EDMACC Registers........................................................................................................ 93 4-11 Peripheral ID Register (PID) Field Descriptions........................................................................ 97 4-12 EDMA3CC Configuration Register (CCCFG) Field Descriptions .................................................... 98 4-13 QDMA Channel Map n Registers (QCHMAPn) Field Descriptions.................................................. 99 4-14 DMA Channel Queue Number Registers (DMAQNUMn) Field Descriptions ..................................... 100 4-15 Bits in DMAQNUMn ...................................................................................................... 100 4-16 QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions.................................... 101 4-17 Queue Priority Register (QUEPRI) Field Descriptions............................................................... 102 4-18 Event Missed Register (EMR) Field Descriptions .................................................................... 103 4-19 Event Missed Register High (EMRH) Field Descriptions............................................................ 103 4-20 Event Missed Clear Register (EMCR) Field Descriptions........................................................... 104 4-21 Event Missed Clear Register High (EMCRH) Field Descriptions................................................... 104 4-22 QDMA Event Missed Register (QEMR) Field Descriptions ......................................................... 105 4-23 QDMA Event Missed Clear Register (QEMCR) Field Descriptions................................................ 106 4-24 EDMA3CC Error Register (CCERR) Field Descriptions............................................................. 107 4-25 EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................ 108 4-26 Error Evaluation Register (EEVAL) Field Descriptions .............................................................. 109 4-27 DMA Region Access Enable Registers for Region m (DRAEm/DRAEHm) Field Descriptions................. 110 4-28 QDMA Region Access Enable for Region m (QRAEm) Field Descriptions....................................... 111 4-29 Event Queue Entry Registers (QxEy) Field Descriptions............................................................ 112 4-30 Queue n Status Register (QSTATn) Field Descriptions ............................................................. 113 4-31 Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions....................................... 114 4-32 EDMA3CC Status Register (CCSTAT) Field Descriptions.......................................................... 115 4-33 Event Register (ER) Field Descriptions................................................................................ 117 SPRUG34–November 2008 List of Tables 9 Submit Documentation Feedback

4-35 Event Clear Register (ECR) Field Descriptions....................................................................... 118 4-36 Event Clear Register High (ECRH) Field Descriptions .............................................................. 118 4-37 Event Set Register (ESR) Field Descriptions ......................................................................... 119 4-38 Event Set Register High (ESRH) Field Descriptions................................................................. 120 4-39 Chained Event Register (CER) Field Descriptions................................................................... 121 4-40 Chained Event Register High (CERH) Field Descriptions........................................................... 121 4-41 Event Enable Register (EER) Field Descriptions..................................................................... 122 4-42 Event Enable Register High (EERH) Field Descriptions............................................................. 123 4-43 Event Enable Clear Register (EECR) Field Descriptions............................................................ 123 4-44 Event Enable Clear Register High (EECRH) Field Descriptions ................................................... 124 4-45 Event Enable Set Register (EESR) Field Descriptions ............................................................. 124 4-46 Event Enable Set Register High (EESRH) Field Descriptions...................................................... 125 4-47 Secondary Event Register (SER) Field Descriptions ................................................................ 125 4-48 Secondary Event Register High (SERH) Field Descriptions........................................................ 126 4-49 Secondary Event Clear Register (SECR) Field Descriptions ....................................................... 126 4-50 Secondary Event Clear Register High (SECRH) Field Descriptions............................................... 127 4-51 Interrupt Enable Register (IER) Field Descriptions................................................................... 128 4-52 Interrupt Enable Register High (IERH) Field Descriptions .......................................................... 128 4-53 Interrupt Enable Clear Register (IECR) Field Descriptions.......................................................... 129 4-54 Interrupt Enable Clear Register High (IECRH) Field Descriptions ................................................. 129 4-55 Interrupt Enable Set Register (IESR) Field Descriptions ............................................................ 130 4-56 Interrupt Enable Set Register High (IESRH) Field Descriptions.................................................... 130 4-57 Interrupt Pending Register (IPR) Field Descriptions ................................................................. 131 4-58 Interrupt Pending Register High (IPRH) Field Descriptions......................................................... 131 4-59 Interrupt Clear Register (ICR) Field Descriptions..................................................................... 132 4-60 Interrupt Clear Register High (ICRH) Field Descriptions ............................................................ 132 4-61 Interrupt Evaluate Register (IEVAL) Field Descriptions ............................................................. 133 4-62 QDMA Event Register (QER) Field Descriptions..................................................................... 134 4-63 QDMA Event Enable Register (QEER) Field Descriptions.......................................................... 135 4-64 QDMA Event Enable Clear Register (QEECR) Field Descriptions................................................. 136 4-65 QDMA Event Enable Set Register (QEESR) Field Descriptions ................................................... 137 4-66 QDMA Secondary Event Register (QSER) Field Descriptions ..................................................... 138 4-67 QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................ 139 4-68 EDMA3 Transfer Controller Registers ................................................................................. 140 4-69 Peripheral ID Register (PID) Field Descriptions ...................................................................... 141 4-70 EDMA3TC Configuration Register (TCCFG) Field Descriptions ................................................... 142 4-71 EDMA3TC Channel Status Register (TCSTAT) Field Descriptions................................................ 143 4-72 Error Status Register (ERRSTAT) Field Descriptions ............................................................... 144 4-73 Error Enable Register (ERREN) Field Descriptions.................................................................. 145 4-74 Error Clear Register (ERRCLR) Field Descriptions .................................................................. 146 4-75 Error Details Register (ERRDET) Field Descriptions ................................................................ 147 4-76 Error Interrupt Command Register (ERRCMD) Field Descriptions................................................. 148 4-77 Read Rate Register (RDRATE) Field Descriptions .................................................................. 149 4-78 Source Active Options Register (SAOPT) Field Descriptions....................................................... 150 4-79 Source Active Source Address Register (SASRC) Field Descriptions ............................................ 151 4-80 Source Active Count Register (SACNT) Field Descriptions......................................................... 151 4-81 Source Active Destination Address Register (SADST) Field Descriptions........................................ 152 4-82 Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions............................... 152 4-83 Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions............................ 153 4-84 Source Active Count Reload Register (SACNTRLD) Field Descriptions.......................................... 154 10 List of Tables SPRUG34–November 2008 Submit Documentation Feedback

4-86 Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions................. 155 4-87 Destination FIFO Options Register (DFOPTn) Field Descriptions ................................................. 156 4-88 Destination FIFO Source Address Register (DFSRCn) Field Descriptions ....................................... 157 4-89 Destination FIFO Count Register (DFCNTn) Field Descriptions ................................................... 158 4-90 Destination FIFO Destination Address Register (DFDSTn) Field Descriptions................................... 159 4-91 Destination FIFO B-Index Register (DFBIDXn) Field Descriptions................................................. 159 4-92 Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Field Descriptions ...................... 160 4-93 Destination FIFO Count Reload Register (DFCNTRLDn) Field Descriptions..................................... 161 4-94 Destination FIFO Source Address B-Reference Register (DFSRCBREFn) Field Descriptions................ 161 4-95 Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) Field Descriptions ........... 162 A-1 Debug List ................................................................................................................. 163 SPRUG34–November 2008 List of Tables 11 Submit Documentation Feedback

About This Manual Describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documentation From Texas Instruments The following documents describe the TMS320DM357 Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. SPRUG06 — TMS320DM357 DMSoC Video Processing Back End (VPBE) User's Guide. Describes the video processing back end (VPBE) in the TMS320DM357 Digital Media System-on-Chip (DMSoC) video processing subsystem. Included in the VPBE is the video encoder, on-screen display, and digital LCD controller. SPRUG25 — TMS320DM357 DMSoC ARM Subsystem Reference Guide. Describes the ARM subsystem in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the video processing subsystem, and a majority of the peripherals and external memories. SPRUG26 —TMS320DM357 DMSoC Universal Asynchronous Receiver/Transmitter (UART) User's Guide. This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU. SPRUG27 — TMS320DM357 DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide. Describes the inter-integrated circuit (I2C) peripheral in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DMSoC through the I2C peripheral. This document assumes the reader is familiar with the I2C-bus specification. SPRUG34–November 2008 Read This First 13 Submit Documentation Feedback

software-programmable 64-bit timer in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as a watchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanced direct memory access (EDMA) synchronization events. The watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. SPRUG29 — TMS320DM357 DMSoC Serial Peripheral Interface (SPI) User's Guide. Describes the serial peripheral interface (SPI) in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communication between the DMSoC and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters. SPRUG30 — TMS320DM357 DMSoC Host Port Interface (HPI) Reference Guide. This document describes the host port interface in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The HPI provides a parallel port interface through which an external host processor can directly access the TMS320DM357 DMSoC processor's resources (configuration and program/data memories). SPRUG31 — TMS320DM357 DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describes the general-purpose input/output (GPIO) peripheral in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin. SPRUG32 — TMS320DM357 DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide. Describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of applications to provide removable data storage. The MMC/SD controller provides an interface to external MMC and SD cards. The communication between the MMC/SD controller and MMC/SD card(s) is performed by the MMC/SD protocol. SPRUG33 — TMS320DM357 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide. Describes the asynchronous external memory interface (EMIF) in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices. SPRUG34 — TMS320DM357 DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide. Describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The EDMA3 controller’s primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DMSoC. SPRUG35 — TMS320DM357 DMSoC Audio Serial Port (ASP) User's Guide. Describes the operation of the audio serial port (ASP) audio interface in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface. SPRUG36 — TMS320DM357 DMSoC Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide. Discusses the ethernet media access controller (EMAC) and physical layer (PHY) device management data input/output (MDIO) module in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The EMAC controls the flow of packet data from the DMSoC to the PHY. The MDIO module controls PHY configuration and status monitoring. 14 Read This First SPRUG34–November 2008 Submit Documentation Feedback

Describes the pulse-width modulator (PWM) peripheral in the TMS320DM357 Digital Media System-on-Chip (DMSoC). SPRUG38 — TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2 memory controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. SPRUG39 — TMS320DM357 DMSoC Video Processing Front End (VPFE) User's Guide. Describes the video processing front end (VPFE) in the TMS320DM357 Digital Media System-on-Chip (DMSoC) video processing subsystem. Included in the VPFE is the preview engine, CCD controller, resizer, histogram, and hardware 3A (H3A) statistic generator. SPRUGH2 —TMS320DM357 DMSoC Peripherals Overview Reference Guide. This document provides an overview of the peripherals in the TMS320DM357 Digital Media System-on-Chip (DMSoC). SPRUGH3 —TMS320DM357 DMSoC Universal Serial Bus Controller User's Guide. This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices and also supports host negotiation. Trademarks SPRUG34–November 2008 Read This First 15 Submit Documentation Feedback

controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The EDMA3 is a high-performance, multichannel, multithreaded DMA controller that allows you to program a wide variety of transfer geometries and transfer sequences. Chapter 1 provides a brief overview, features, and terminology. Chapter 2 provides the architecture details and common operations of the EDMA3 channel controller (EDMA3CC) and the EDMA3 transfer controller (EDMA3TC). Chapter 3 contains examples and common usage scenarios. Chapter 4 describes the memory-mapped registers associated with the EDMA3 controller. Topic .................................................................................................. Page 1.1 Overview.................................................................................. 18 1.2 Features................................................................................... 18 1.3 Terminology Used in This Document........................................... 19 SPRUG34–November 2008 Introduction 17 Submit Documentation Feedback

user-programmed data transfers between two memory-mapped slave endpoints on the device. Typical usage includes, but is not limited to: • Servicing software driven paging transfers (for example, from external memory such as SDRAM to internal device memory such as TCM • Servicing event driven peripherals, such as a serial port • Performing sorting or subframe extraction of various data structures • Offloading data transfers from the main device CPU(s) (See the device data manual for specific peripherals that are accessible via EDMA3. See the section on SCR connectivity in the device data manual for EDMA3 connectivity.) The EDMA3 controller consists of two principal blocks: • EDMA3 channel controller (EDMA3CC) • EDMA3 transfer controller(s) (EDMA3TC) The EDMA3 channel controller serves as the user interface for the EDMA3 controller. The EDMA3CC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The EDMA3CC serves to prioritize incoming software requests or events from peripherals, and submits transfer requests (TR) to the transfer controller. The EDMA3 transfer controllers are slaves to the EDMA3 channel controller responsible for data movement. The transfer controller issues read/write commands to the source and destination addresses programmed for a given transfer. The operation is transparent to you. The EDMA3 channel controller has following features: • Fully orthogonal transfer description – 3 transfer dimensions – A-synchronized transfers: 1 dimension serviced per event – AB- synchronized transfers: 2 dimensions serviced per event – Independent indexes on source and destination – Chaining feature allows 3-D transfer based on single event • Flexible transfer definition – Increment or constant transfer addressing modes – Linking mechanism allows automatic PaRAM set update – Chaining allows multiple transfers to execute with one event • Interrupt generation for: – Transfer completion – Error conditions • Debug visibility – Queue watermarking/threshold – Error and status recording to facilitate debug • 64 DMA channels – Event synchronization – Manual synchronization (CPU(s) write to event set register) – Chain synchronization (completion of one transfer triggers another transfer) • 8 QDMA channels – QDMA channels are triggered automatically upon writing to a PaRAM set entry – Support for programmable QDMA channel to PaRAM mapping 18 Introduction SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com Terminology Used in This Document • 128 PaRAM sets – Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining) • 2 transfer controllers/event queues. The system-level priority of these queues is user programmable. (See the device data manual for the possible system priorities.) • 16 event entries per event queue The EDMA3 transfer controller has following features: • 2 transfer controllers (TC) • 64-bit wide read and write ports per TC • Up to 4 in-flight transfer requests (TR) • Programmable priority level • Supports 2 dimensional transfers with independent indexes on source and destination (EDMA3CC manages the 3rd dimension) • Support for increment or constant addressing mode transfers • Interrupt and error support The following is a brief explanation of some terms used in this document: Term Meaning A-synchronized A transfer type where 1 dimension is serviced per synchronization event. transfer AB-synchronized A transfer type where 2 dimensions are serviced per synchronization event. transfer Chaining A trigger mechanism in which a transfer can be initiated at the completion of another transfer or subtransfer. CPU(s) The main processing engine or engines on a device. Typically an ARM or general-purpose processor. (See the device data manual to learn more about the CPU on your system.) Device TMS320DM357 DMSoC DMA channel One of the 64 channels that can be triggered by external, manual, and chained events. All DMA channels exist in the EDMA3CC. Dummy set or A PaRAM set for which at least one of the count fields is equal to 0 and at least one Dummy PaRAM set of the count fields is nonzero. A null PaRAM set has all the count set fields cleared. Dummy transfer A dummy set results in the EDMA3CC performing a dummy transfer. This is not an error condition. A null set results in an error condition. EDMA3 channel The user-programmable portion of the EDMA3. The EDMA3CC contains the controller parameter RAM (PaRAM) , event processing logic, DMA/QDMA channels, event (EDMA3CC) queues, etc. The EDMA3CC services events (external, manual, chained, QDMA) and is responsible for submitting transfer requests to the transfer controllers (EDMA3TC), which perform the actual transfer. EDMA3 Any entity on the chip that has read/write access to the EDMA3 registers and can programmer program an EDMA3 transfer. EDMA3 transfer Transfer controllers are the transfer engine for the EDMA3. Performs the read/writes controller(s) as dictated by the transfer requests submitted by the EDMA3CC. (EDMA3TC) Enhanced direct Consists of the EDMA3 channel controller (EDMA3CC) and EDMA3 transfer memory access controller(s) (EDMA3TC). Is referred to as EDMA3 in this document. (EDMA3) controller SPRUG34–November 2008 Introduction 19 Submit Documentation Feedback

www.ti.com Term Meaning Link parameter set A PaRAM set that is used for linking. Linking The mechanism of reloading a PaRAM set with new transfer characteristics on completion of the current transfer. Memory-mapped All on-chip memories, off-chip memories, and slave peripherals. These typically rely slave on the EDMA3 (or other master peripheral) to perform transfers to and from them. Master All peripherals that are capable of initiating read and write transfers to the peripherals peripherals system and may not solely rely on the EDMA3 for their data transfers. Null set or Null A PaRAM set that has all count fields cleared (except for the link field). A dummy PaRAM set PaRAM set has at least one of the count fields nonzero. Null transfer A trigger event for a null PaRAM set results in the EDMA3CC performing a null transfer. This is an error condition. A dummy transfer is not an error condition. QDMA channel One of the 8 channels that can be triggered when writing to the trigger word (TRWORD) of a PaRAM set. All QDMA channels exist in the EDMA3CC. Parameter RAM Programmable RAM that stores PaRAM sets used by DMA channels, QDMA (PaRAM) channels, and linking. Parameter RAM A 32-byte EDMA3 channel transfer definition. Each parameter set consists of 8 (PaRAM) set words ( 4-bytes each), which store the context for a DMA/QDMA/link transfer. A PaRAM set includes source address, destination address, counts, indexes, options, etc. Parameter RAM One of the 4-byte components of the parameter set. (PaRAM) set entry Slave end points All on-chip memories, off-chip memories, and slave peripherals. These rely on the EDMA3 to perform transfers to and from them. Transfer request A command for data movement that is issued from the EDMA3CC to the EDMA3TC. (TR) A TR includes source and destination addresses, counts, indexes, options, etc. Trigger event Action that causes the EDMA3CC to service the PaRAM set and submit a transfer request to the EDMA3TC. Trigger events for DMA channels include manual triggered (CPU triggered), external event triggered, and chain triggered. Trigger events for QDMA channels include autotriggered and link triggered. Trigger word For QDMA channels, the trigger word specifies the PaRAM set entry that when written results in a QDMA trigger event. The trigger word is programmed via the QDMA channel map register (QCHMAP) and can point to any PaRAM set entry. TR synchronization See Trigger Event. (sync) event Introduction 20 SPRUG34–November 2008 Submit Documentation Feedback

Topic .................................................................................................. Page 2.1 Functional Overview.................................................................. 22 2.2 Types of EDMA3 Transfers......................................................... 25 2.3 Parameter RAM (PaRAM) ........................................................... 28 2.4 Initiating a DMA Transfer ........................................................... 38 2.5 Completion of a DMA Transfer.................................................... 42 2.6 Event, Channel, and PaRAM Mapping.......................................... 43 2.7 EDMA3 Channel Controller Regions............................................ 45 2.8 Chaining EDMA3 Channels ........................................................ 47 2.9 EDMA3 Interrupts...................................................................... 49 2.10 Event Queue(s)......................................................................... 55 2.11 EDMA3 Transfer Controller (EDMA3TC)....................................... 57 2.12 Event Dataflow.......................................................................... 60 2.13 EDMA3 Prioritization ................................................................. 61 2.14 EDMA3 Operating Frequency (Clock Control)............................... 62 2.15 Reset Considerations ................................................................ 62 2.16 Power Management................................................................... 63 2.17 Emulation Considerations.......................................................... 63 SPRUG34–November 2008 EDMA3 Architecture 21 Submit Documentation Feedback

DMA/QDMA channel logic PaRAM Transfer request submission Completion and error interrupt logic EDMA3CC_INT[2:0] EDMA3CC_ERRINT Completion detection To/from EDMA3 programmer Channel controller TC0 Transfer controllers Read/write commands and data EDMA3TC_ ERRINT0 MMR TC1 commands Read/write and data MMR EDMA3TC_ ERRINT1 Event queue 2.1.2 EDMA3 Channel Controller (EDMA3CC) Functional Overview www.ti.com This section provides a block diagram of the EDMA3 controller, EDMA3 channel controller (EDMA3CC), and EDMA3 transfer controller (EDMA3TC). Figure 2-1 shows a block diagram for the EDMA3 controller. Figure 2-1. EDMA3 Controller Block Diagram Figure 2-2 shows a functional block diagram of the EDMA3 channel controller (EDMA3CC). The main blocks of the EDMA3CC are: • Parameter RAM (PaRAM): Maintains parameter set entries for channel and reload parameter sets. The PaRAM needs to be written with the transfer context for the desired channels and link parameter sets. EDMA3CC processes PaRAM sets based on a trigger event and submits a transfer request (TR) to the transfer controller. • EDMA3 event and interrupt processing registers: Enable/disable events, enable/disable interrupt conditions, and clearing interrupts. • Completion detection: The completion detect block detects completion of transfers by the EDMA3TC and/or slave peripherals. Completion of transfers can optionally be used to chain trigger new transfers or to assert interrupts. • Event queues: These form the interface between the event detection logic and the transfer request submission logic. Other functions include: • Region registers: Region registers allow DMA resources (DMA channels and interrupts) to be assigned to unique regions, which are owned by different EDMA3 programmers (for example, ARM). • Debug registers: Region registers allow debug visibility by providing registers to read the queue status, controller status, and missed event status. The EDMA3CC includes two channel types: DMA channels (64 channels) and QDMA channels (8 channels). Each channel is associated with a given event queue/transfer controller, and with a given PaRAM set. The main difference between a DMA channel and QDMA channel is how the transfers are triggered by the system. Refer to Section 2.4. EDMA3 Architecture 22 SPRUG34–November 2008 Submit Documentation Feedback

A trigger event is needed to initiate a transfer. For DMA channels, a trigger event may be due to an external event, manual write to the event set register, or chained event. QDMA channels are autotriggered when a write is performed to the user-programmed trigger word. All such trigger events are logged into appropriate registers upon recognition. Refer to DMA channel registers (Section 4.3.5) and QDMA registers (Section 4.3.7). Once a trigger event is recognized, the event type/channel is queued in the appropriate EDMA3CC event queue. The assignment of each DMA/QDMA channel to event queue is programmable. Each queue is 16 deep, so up to 16 events may be queued (on a single queue) in the EDMA3CC at an instant in time. Additional pending events mapped to a full queue are queued when event queue space becomes available. Refer to Section 2.10. If events on different channels are detected simultaneously, the events are queued based on fixed priority arbitration scheme with the DMA channels being higher priority than the QDMA channels. Among the two groups of channels, the lowest-numbered channel is the highest priority. Each event in the event queue is processed in the order it was queued. On reaching the head of the queue, the PaRAM associated with that channel is read to determine the transfer details. The TR submission logic evaluates the validity of the TR and is responsible for submitting a valid transfer request (TR) to the appropriate EDMA3TC (based on the event queue to EDMA3TC association, Q0 goes to TC0, Q1 goes to TC1, etc.). For more details, see Section 2.3. The EDMA3TC receives the request and is responsible for data movement as specified in the transfer request packet (TRP) and other necessary tasks like buffering, ensuring transfers are carried out in an optimal fashion wherever possible. For more details on EDMA3TC, see Section 2.1.3. SPRUG34–November 2008 EDMA3 Architecture 23 Submit Documentation Feedback

Read data Write command Write data Destination FIFO register set SRC Transfer request submission EDMA3TCn EDMA3TC_ERRINT To completion detection logic in EDMA3CC Read command SRC active register set Read controller Write controller Program register set Functional Overview www.ti.com You may have chosen to receive an interrupt or chain to another channel on completion of the current transfer in which case the EDMA3TC signals completion to the EDMA3CC completion detection logic when the transfer is done. You can alternately choose to trigger completion when a TR leaves the EDMA3CC boundary rather than wait for all the data transfers to complete. Based on the setting of the EDMA3CC interrupt registers, the completion interrupt generation logic is responsible for generating EDMA3CC completion interrupts to the CPU. For more details, see Section 2.5. Additionally, the EDMA3CC also has an error detection logic, which causes error interrupt generation on various error conditions (like missed events, exceeding event queue thresholds, etc.). For more details on error interrupts, see Section 2.9.4. Figure 2-3 shows a functional block diagram of the EDMA3 transfer controller (EDMA3TC). The main blocks of the EDMA3TC are: • DMA program register set: The DMA program register set stores the transfer requests received from the EDMA3 channel controller (EDMA3CC). • DMA source active register set: The DMA source active register set stores the context for the DMA transfer request currently in progress in the read controller. • Read controller: The read controller issues read commands to the source address. • Destination FIFO register set: The destination (Dst) FIFO register set stores the context for the DMA transfer request(s) currently in progress in the write controller. • Write controller: The write controller issues write commands/write data to the destination slave. • Data FIFO: The data FIFO exists for holding temporary in-flight data. • Completion interface: The completion interface sends completion codes to the EDMA3CC when a transfer completes, and is used for generating interrupts and chained events (also, refer to Section 2.5 for details on transfer completion reporting). Figure 2-3. EDMA3 Transfer Controller (EDMA3TC) Block Diagram EDMA3 Architecture 24 SPRUG34–November 2008 Submit Documentation Feedback

Array�BCNT Array�2 Array�1 Frame�0 ACNT�bytes�in Array/1st�dimension Array�1 Frame�1 Array�BCNT Array�2 Array�1 Frame�CCNT Array�BCNT Array�2 CCNT�frames�in Block/3rd�dimmension BCNT�arrays�in�Frame/2nd�dimmension www.ti.com Types of EDMA3 Transfers When the EDMA3TC is idle and receives its first TR, the TR is received in the DMA program register set, where it transitions to the DMA source active set and the destination FIFO register set immediately. The second TR (if pending from EDMA3CC) is loaded into the DMA program set, ensuring it can start as soon as possible when the active transfer is completed. As soon as the current active set is exhausted, the TR is loaded from the DMA program register set into the DMA source active register set as well as to the appropriate entry in the destination FIFO register set. The read controller issues read commands governed by the rules of command fragmentation and optimization. These are issued only when the data FIFO has space available for the data read. When sufficient data is in the data FIFO, the write controller starts issuing a write command again following the rules for command fragmentation and optimization. For details on command fragmentation and optimization, see Section 2.11.1.1. Depending on the number of entries, the read controller can process up to 4 transfer requests ahead of the destination subject to the amount of free data FIFO. An EDMA3 transfer is always defined in terms of three dimensions. Figure 2-4 shows the three dimensions used by EDMA3 transfers. These three dimensions are defined as: • 1st Dimension or Array (A): The 1st dimension in a transfer consists of ACNT contiguous bytes. • 2nd Dimension or Frame (B): The 2nd dimension in a transfer consists of BCNT arrays of ACNT bytes. Each array transfer in the 2nd dimension is separated from each other by an index programmed using SRCBIDX or DSTBIDX. • 3rd Dimension or Block (C): The 3rd dimension in a transfer consists of CCNT frames of BCNT arrays of ACNT bytes. Each transfer in the 3rd dimension is separated from the previous by an index programmed using SRCCIDX or DSTCIDX. Note that the reference point for the index depends on the synchronization type. The amount of data transferred upon receipt of a trigger/synchronization event is controlled by the synchronization types (SYNCDIM bit in OPT). Of the three dimensions, only two synchronization types are supported: A-synchronized transfers and AB-synchronized transfers. Figure 2-4. Definition of ACNT, BCNT, and CCNT SPRUG34–November 2008 EDMA3 Architecture 25 Submit Documentation Feedback

as one TR Array 0 Array 3 Array 1 Array 2 (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) CIDX (SRC|DST) BIDX Array 0 Array 3 (SRC|DST) Array 1 BIDX BIDX (SRC|DST) Array 2 (SRC|DST) CIDX Frame 0 Frame 1 Frame 2 Types of EDMA3 Transfers www.ti.com In an A-synchronized transfer, each EDMA3 sync event initiates the transfer of the 1st dimension of ACNT bytes, or one array of ACNT bytes. In other words, each event/TR packet conveys the transfer information for one array only. Thus, BCNT × CCNT events are needed to completely service a PaRAM set. Arrays are always separated by SRCBIDX and DSTBIDX, as shown in Figure 2-5, where the start address of Array N is equal to the start address of Array N – 1 plus source (SRC) or destination (DST) BIDX. Frames are always separated by SRCCIDX and DSTCIDX. For A-synchronized transfers, after the frame is exhausted, the address is updated by adding SRCCIDX/DSTCIDX to the beginning address of the last array in the frame. As in Figure 2-5, SRCCIDX/DSTCIDX is the difference between the start of Frame 0 Array 3 to the start of Frame 1 Array 0. Figure 2-5 shows an A-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes. In this example, a total of 12 sync events (BCNT × CCNT) exhaust a PaRAM set. See Section 2.3.6 for details on parameter set updates. Figure 2-5. A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) 26 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

as one TR Array 0 Array 3 Array 1 Array 2 (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX (SRC|DST) BIDX Array 0 Array 3 (SRC|DST) Array 1 BIDX BIDX (SRC|DST) Array 2 Frame 0 Frame 1 Frame 2 (SRC|DST) CIDX (SRC|DST) CIDX AB_Sync transfer www.ti.com Types of EDMA3 Transfers In a AB-synchronized transfer, each EDMA3 sync event initiates the transfer of 2 dimensions or one frame. In other words, each event/TR packet conveys information for one entire frame of BCNT arrays of ACNT bytes. Thus, CCNT events are needed to completely service a PaRAM set. Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 2-6. Frames are always separated by SRCCIDX and DSTCIDX. Note that for AB-synchronized transfers, after a TR for the frame is submitted, the address update is to add SRCCIDX/DSTCIDX to the beginning address of the beginning array in the frame. This is different from A-synchronized transfers where the address is updated by adding SRCCIDX/DSTCIDX to the start address of the last array in the frame. See Section 2.3.6 for details on parameter set updates. Figure 2-6 shows an AB-synchronized transfer of 3 (CCNT) frames of 4 (BCNT) arrays of n (ACNT) bytes. In this example, a total of 3 sync events (CCNT) exhaust a PaRAM set; that is, a total of 3 transfers of 4 arrays each completes the transfer. Figure 2-6. AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) Note: ABC-synchronized transfers are not directly supported. But can be logically achieved by chaining between multiple AB-synchronized transfers. SPRUG34–November 2008 EDMA3 Architecture 27 Submit Documentation Feedback

Parameter RAM (PaRAM) www.ti.com The EDMA3 controller is a RAM-based architecture. The transfer context (source/destination addresses, count, indexes, etc.) for DMA or QDMA channels is programmed in a parameter RAM table within EDMA3CC, referred to as PaRAM. The PaRAM table is segmented into multiple PaRAM sets. Each PaRAM set includes eight 4-byte PaRAM set entries (32-bytes total per PaRAM set), which includes typical DMA transfer parameters such as source address, destination address, transfer counts, indexes, options, etc. The PaRAM structure is shown in Table 2-1. The PaRAM structure supports flexible ping-pong, circular buffering, channel chaining, and autoreloading (linking). The contents of the PaRAM include: • 128 PaRAM sets • 64-channels are direct mapped. Can be used as link or QDMA sets, if not used for DMA channels. • 64-channels remain for link or QDMA sets Note: By default, all DMA channels map to PaRAM set 0. These should be remapped before use, refer to Section 2.6.2. Table 2-1. EDMA3 Parameter RAM Contents Address Parameters 01C0 4000h to 01C0 401Fh Parameters for event 0 (8 words) 01C0 4020h to 01C0 403Fh Parameters for event 1 (8 words) 01C0 4040h to 01C0 405Fh Parameters for event 2 (8 words) 01C0 4060h to 01C0 407Fh Parameters for event 3 (8 words) 01C0 4080h to 01C0 409Fh Parameters for event 4 (8 words) 01C0 40A0h to 01C0 40BFh Parameters for event 5 (8 words) 01C0 40C0h to 01C0 40DFh Parameters for event 6 (8 words) 01C0 40E0h to 01C0 40FFh Parameters for event 7 (8 words) 01C0 4100h to 01C0 411Fh Parameters for event 8 (8 words) 01C0 4120h to 01C0 413Fh Parameters for event 9 (8 words) 01C0 4140h to 01C0 415Fh Parameters for event 10 (8 words) 01C0 4160h to 01C0 417Fh Parameters for event 11 (8 words) 01C0 4180h to 01C0 419Fh Parameters for event 12 (8 words) 01C0 41A0h to 01C0 41BFh Parameters for event 13 (8 words) 01C0 41C0h to 01C0 41DFh Parameters for event 14 (8 words) 01C0 41E0h to 01C0 41FFh Parameters for event 15 (8 words) 01C0 4200h to 01C0 421Fh Parameters for event 16 (8 words) . . . . . . 01C0 47C0h to 01C0 47DFh Parameters for event 62 (8 words) 01C0 47E0h to 01C0 47FFh Parameters for event 63 (8 words) 01C0 4800h to 01C0 481Fh 1st reload/link set (8 words)(1) 01C0 4820h to 01C0 483Fh 2nd reload/link set (8 words) (1) . . . . . . 01C0 4FC0h to 01C0 4FDFh 62nd reload/link set (8 words) (1) 01C0 4FE0h to 01C0 4FFFh 63rd reload/link set (8 words) (1) (1) DM357 devices have 8 QDMA channels that can be mapped to any parameter set number from 0 to 127. 28 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

Parameter set 3 Parameter set 2 Parameter set 127 Parameter set 126 Set # Byte address 01C0 4000h 01C0 4020h 01C0 4040h 01C0 4060h 01C0 4FC0h 01C0 4FE0h 0 1 2 3 126 127 DSTBIDX BCNTRLD Rsvd DSTCIDX CCNT SRCCIDX LINK SRCBIDX DST BCNT ACNT SRC OPT PaRAM PaRAM set +0h +4h +8h +Ch Byte address +1Ch +18h +14h +10h offset www.ti.com Parameter RAM (PaRAM) Each parameter set of PaRAM is organized into eight 32-bit words or 32 bytes, as shown in Figure 2-7 and described in Table 2-2. Each PaRAM set consists of 16-bit and 32-bit parameters. Figure 2-7. PaRAM Set SPRUG34–November 2008 EDMA3 Architecture 29 Submit Documentation Feedback

www.ti.com Table 2-2. EDMA3 Channel Parameter Description Offset Address (bytes) Acronym Parameter Description 0h OPT Channel Options Transfer Configuration Options 4h SRC Channel Source Address The byte address from which data is transferred. 8h(1) ACNT Count for 1st Dimension Unsigned value specifying the number of contiguous bytes within an array (first dimension of the transfer). Valid values range from 1 to 65 535. BCNT Count for 2nd Dimension Unsigned value specifying the number of arrays in a frame, where an array is ACNT bytes. Valid values range from 1 to 65 535. Ch DST Channel Destination Address The byte address to which data is transferred. 10h(1) SRCBIDX Source BCNT Index Signed value specifying the byte address offset between source arrays within a frame (2nd dimension). Valid values range from –32 768 and 32 767. DSTBIDX Destination BCNT Index Signed value specifying the byte address offset between destination arrays within a frame (2nd dimension). Valid values range from –32 768 and 32 767. 14h(1) LINK Link Address The PaRAM address containing the PaRAM set to be linked (copied from) when the current PaRAM set is exhausted. A value of FFFFh specifies a null link. BCNTRLD BCNT Reload The count value used to reload BCNT when BCNT decrements to 0 (TR submitted for the last array in 2nd dimension). Only relevant in A-synchronized transfers. 18h(1) SRCCIDX Source CCNT Index Signed value specifying the byte address offset between frames within a block (3rd dimension). Valid values range from –32 768 and 32 767. A-synchronized transfers: The byte address offset from the beginning of the last source array in a frame to the beginning of the first source array in the next frame. AB-synchronized transfers: The byte address offset from the beginning of the first source array in a frame to the beginning of the first source array in the next frame. DSTCIDX Destination CCNT index Signed value specifying the byte address offset between frames within a block (3rd dimension). Valid values range from –32 768 and 32 767. A-synchronized transfers: The byte address offset from the beginning of the last destination array in a frame to the beginning of the first destination array in the next frame. AB-synchronized transfers: The byte address offset from the beginning of the first destination array in a frame to the beginning of the first destination array in the next frame. 1Ch CCNT Count for 3rd Dimension Unsigned value specifying the number of frames in a block, where a frame is BCNT arrays of ACNT bytes. Valid values range from 1 to 65 535. RSVD Reserved Reserved (1) It is recommended to access the parameter set entries as 32-bit words whenever possible. EDMA3 Architecture 30 SPRUG34–November 2008 Submit Documentation Feedback

2.3.2.1 Channel Options Parameter (OPT) 2.3.2.2 Channel Source Address (SRC) 2.3.2.3 Channel Destination Address (DST) 2.3.2.4 Count for 1st Dimension (ACNT) 2.3.2.5 Count for 2nd Dimension (BCNT) 2.3.2.6 Count for 3rd Dimension (CCNT) 2.3.2.7 BCNT Reload (BCNTRLD) www.ti.com Parameter RAM (PaRAM) The 32-bit channel options parameter (OPT) specifies the transfer configuration options. The channel options parameter (OPT) is described in Section 4.2.1. The 32-bit source address parameter specifies the starting byte address of the source. For SAM in increment mode, there are no alignment restrictions imposed by EDMA3. For SAM in constant addressing mode, you must program the source address to be aligned to a 256-bit aligned address (5 LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 2.11.2 for additional details. The 32-bit destination address parameter specifies the starting byte address of the destination. For DAM in increment mode, there are no alignment restrictions imposed by EDMA3. For DAM in constant addressing mode, you must program the destination address to be aligned to a 256-bit aligned address (5 LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 2.11.2 for additional details. ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65 535. Therefore, the maximum number of bytes in an array is 65 535 bytes (64K – 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3TC. A transfer with ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions. BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65 535. Therefore, the maximum number of arrays in a frame is 65 535 (64K – 1 arrays). A transfer with BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions. CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65 535. Therefore, the maximum number of frames in a block is 65 535 (64K – 1 frames). A transfer with CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. See Section 2.3.5 and Section 2.5.3 for details on dummy/null completion conditions. BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used. SPRUG34–November 2008 EDMA3 Architecture 31 Submit Documentation Feedback

2.3.2.9 Destination B Index (DSTBIDX) 2.3.2.10 Source C Index (SRCCIDX) 2.3.2.11 Destination C Index (DSTCIDX) 2.3.2.12 Link Address (LINK) Parameter RAM (PaRAM) www.ti.com SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between –32 768 and 32 767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers. Some examples: • SRCBIDX = 0000h (0): no address offset from the beginning of an array to the beginning of the next array. All arrays are fixed to the same beginning address. • SRCBIDX = 0003h (+3): the address offset from the beginning of an array to the beginning of the next array in a frame is 3 bytes. For example, if the current array begins at address 1000h, the next array begins at 1003h. • SRCBIDX = FFFFh (–1): the address offset from the beginning of an array to the beginning of the next array in a frame is –1 byte. For example, if the current array begins at address 5054h, the next array begins at 5053h. DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between –32 768 and 32 767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers. See SRCBIDX for examples. SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between –32 768 and 32 767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame (Figure 2-5), while the current array in an AB-synchronized transfer is the first array in the frame (Figure 2-6). DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between –32 768 and 32 767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame (Figure 2-5), while the current array in a AB-synchronized transfer is the first array in the frame (Figure 2-6). The EDMA3CC provides a mechanism, called linking, to reload the current PaRAM set upon its natural termination (that is, after the count fields are decremented to 0) with a new PaRAM set. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the EDMA3CC loads/reloads the next PaRAM set during linking. You must program the link address to point to a valid aligned 32-byte PaRAM set. The 5 LSBs of the LINK field should be cleared to 0. The EDMA3CC ignores the upper 2 bits of the LINK entry, allowing the programmer the flexibility of programming the link address as either an absolute/literal byte address or use the PaRAM-base-relative offset address. Therefore, if you make use of the literal address with a range from 4000h to 7FFFh, it will be treated as a PaRAM-base-relative value of 0000h to 3FFFh. 32 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

2.3.4 Dummy PaRAM Set 2.3.5 Dummy Versus Null Transfer Comparison 2.3.6 Parameter Set Updates www.ti.com Parameter RAM (PaRAM) You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM address that falls in the range of the available PaRAM addresses on the device. A LINK value of FFFFh is referred to as a NULL link that should cause the EDMA3CC to perform an internal write of 0 to all entries of the current PaRAM set, except for the LINK field that is set to FFFFh. Also, see Section 2.5 for details on terminating a transfer. A null PaRAM set is defined as a PaRAM set where all count fields (ACNT, BCNT, and CCNT) are cleared to 0. If a PaRAM set associated with a channel is a NULL set, then when serviced by the EDMA3CC, the bit corresponding to the channel is set in the associated event missed register (EMR, EMRH, or QEMR). This bit remains set in the associated secondary event register (SER, SERH, or QSER). This implies that any future events on the same channel are ignored by the EDMA3CC and you are required to clear the bit in SER, SERH, or QSER for the channel. This is considered an error condition, since events are not expected on a channel that is configured as a null transfer. See Section 4.3.5.8 and Section 4.3.2.1 for more information on the SER and EMR registers, respectively. A dummy PaRAM set is defined as a PaRAM set where at least one of the count fields (ACNT, BCNT, or CCNT) is cleared to 0 and at least one of the count fields is nonzero. If a PaRAM set associated with a channel is a dummy set, then when serviced by the EDMA3CC, it will not set the bit corresponding to the channel (DMA/QDMA) in the event missed register (EMR, EMRH, or QEMR) and the secondary event register (SER, SERH, or QSER) bit gets cleared similar to a normal transfer. Future events on that channel are serviced. A dummy transfer is a legal transfer of 0 bytes. See Section 4.3.5.8 and Section 4.3.2.1 for more information on the SER and EMR registers, respectively. There are some differences in the way the EDMA3CC logic treats a dummy versus a null transfer request. A null transfer request is an error condition, but a dummy transfer is a legal transfer of 0 bytes. A null transfer causes an error bit (En) in EMR to get set and the En bit in SER remains set, essentially preventing any further transfers on that channel without clearing the associated error registers. Table 2-3 summarizes the conditions and effects of null and dummy transfer requests. Table 2-3. Dummy and Null Transfer Request Feature Null TR Dummy TR EMR/EMRH/QEMR is set Yes No SER/SERH/QSER remains set Yes No Link update (STATIC = 0 in OPT) Yes Yes QER is set Yes Yes IPR/IPRH CER/CERH is set using early completion Yes Yes When a TR is submitted for a given DMA/QDMA channel and its corresponding PaRAM set, the EDMA3CC is responsible for updating the PaRAM set in anticipation of the next trigger event. For nonfinal events, this includes address and count updates; for final events, this includes the link update. The specific PaRAM set entries that are updated depend on the channel’s synchronization type (A-synchronized or B-synchronized) and the current state of the PaRAM set. A B-update refers to the decrementing of BCNT in the case of A-synchronized transfers after the submission of successive TRs. A C-update refers to the decrementing of CCNT in the case of A-synchronized transfers after BCNT TRs for ACNT byte transfers have submitted. For AB-synchronized transfers, a C-update refers to the decrementing of CCNT after submission of every transfer request. SPRUG34–November 2008 EDMA3 Architecture 33 Submit Documentation Feedback

www.ti.com See Table 2-4 for details and conditions on the parameter updates. A link update occurs when the PaRAM set is exhausted, as described in Section 2.3.7. After the TR is read from the PaRAM (and is in process of being submitted to EDMA3TC), the following fields are updated if needed: • A-synchronized: BCNT, CCNT, SRC, DST • AB-synchronized: CCNT, SRC, DST The following fields are not updated (except for during linking, where all fields are overwritten by the link PaRAM set): • A-synchronized: ACNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK • AB-synchronized: ACNT, BCNT, BCNTRLD, SRCBIDX, DSTBIDX, SRCCIDX, DSTCIDX, OPT, LINK Note that PaRAM updates only pertain to the information that is needed to properly submit the next transfer request to the EDMA3TC. Updates that occur while data is moved within a transfer request are tracked within the transfer controller, and is detailed in Section 2.11. For A-synchronized transfers, the EDMA3CC always submits a TRP for ACNT bytes (BCNT = 1 and CCNT = 1). For AB-synchronized transfers, the EDMA3CC always submits a TRP for ACNT bytes of BCNT arrays (CCNT = 1). The EDMA3TC is responsible for updating source and destination addresses within the array based on ACNT and FWID (in OPT). For AB-synchronized transfers, the EDMA3TC is also responsible to update source and destination addresses between arrays based on SRCBIDX and DSTBIDX. Table 2-4 shows the details of parameter updates that occur within EDMA3CC for A-synchronized and AB-synchronized transfers. Table 2-4. Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) A-Synchronized Transfer AB-Synchronized Transfer B-Update C-Update Link Update B-Update C-Update Link Update BCNT == 1 && BCNT == 1 && Condition: BCNT > 1 CCNT > 1 CCNT == 1 N/A CCNT > 1 CCNT == 1 SRC += SRCBIDX += SRCCIDX = Link.SRC in EDMA3TC += SRCCIDX = Link.SRC DST += DSTBIDX += DSTCIDX = Link.DST in EDMA3TC += DSTCIDX = Link.DST ACNT None None = Link.ACNT None None = Link.ACNT BCNT –= 1 = BCNTRLD = Link.BCNT in EDMA3TC N/A = Link.BCNT CCNT None –= 1 = Link.CCNT in EDMA3TC –=1 = Link.CCNT SRCBIDX None None = Link.SRCBIDX in EDMA3TC None = Link.SRCBIDX DSTBIDX None None = Link.DSTBIDX None None = Link.DSTBIDX SRCCIDX None None = Link.SRCBIDX in EDMA3TC None = Link.SRCBIDX DSTCIDX None None = Link.DSTBIDX None None = Link.DSTBIDX LINK None None = Link.LINK None None = Link.LINK BCNTRLD None None = Link.BCNTRLD None None = Link.BCNTRLD OPT(1) None None = LINK.OPT None None = LINK.OPT (1) In all cases, no updates occur if OPT.STATIC == 1 for the current PaRAM set. Note: The EDMA3CC includes no special hardware to detect when an indexed address update calculation overflows/underflows. The address update will wrap across boundaries as programmed by the user. You should ensure that no transfer is allowed to cross internal port boundaries between peripherals. A single TR must target a single source/destination slave endpoint. EDMA3 Architecture 34 SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com Parameter RAM (PaRAM) The EDMA3CC provides a mechanism known as linking, which allows the entire PaRAM set to be reloaded from a location within the PaRAM memory map (for both DMA and QDMA channels). Linking is especially useful for maintaining ping-pong buffers, circular buffering, and repetitive/continuous transfers all with no CPU intervention. Upon completion of a transfer, the current transfer parameters are reloaded with the parameter set pointed to by the 16-bit link address field (of the current parameter set). Linking only occurs when the STATIC bit in OPT is cleared to 0. Note: A transfer (DMA or QDMA) should always be linked to another useful transfer. If it is required to terminate a transfer, the transfer should be linked to a NULL set. The link update occurs after the current PaRAM set event parameters have been exhausted. An event's parameters are exhausted when the EDMA3 channel controller has submitted all the transfers associated with the PaRAM set. A link update occurs for null and dummy transfers depending on the state of the STATIC bit in OPT and the LINK field. In both cases (null or dummy), if the value of LINK is FFFFh then a null PaRAM set (with all 0s and LINK set to FFFFh) is written to the current PaRAM set. Similarly, if LINK is set to a value other than FFFFh then the appropriate PaRAM location pointed to by LINK is copied to the current PaRAM set. Once the channel completion conditions are met for an event, the transfer parameters located at the link address are loaded into the current DMA or QDMA channel’s associated parameter set. The EDMA3CC reads the entire PaRAM set (8 words) from the PaRAM set specified by LINK and writes all 8 words to the PaRAM set associated with the current channel. Figure 2-8 shows an example of a linked transfer. Any PaRAM set in the PaRAM can be used as a link/reload parameter set. The PaRAM sets associated with peripheral synchronization events (see Section 2.6) should only be used for linking if the corresponding events are disabled. If a PaRAM set location is mapped to a QDMA channel (by QCHMAPn), then copying the link PaRAM set onto the current QDMA channel PaRAM set is recognized as a trigger event and is latched in QER since a write to the trigger word was performed. This feature can be used to create a linked list of transfers using a single QDMA channel and multiple PaRAM sets. Link-to-self transfers replicate the behavior of autoinitialization, which facilitates the use of circular buffering and repetitive transfers. After an EDMA3 channel exhausts its current PaRAM set, it reloads all the parameter set entries from another PaRAM set, which is initialized with values identical to the original PaRAM set. Figure 2-9 shows an example of a linked-to-self transfer. In Figure 2-9, parameter set 127 has the LINK field address pointing to the address of parameter set 127 (4FE0h), that is, linked-to-self. Note: If the STATIC bit in OPT is set for a PaRAM set, then link updates are not performed. If either SAM or DAM is set to 1 (constant addressing mode), then the source or destination address must be aligned to a 256-bit aligned address, respectively, and the corresponding BIDX should be an even multiple of 32 bytes (256 bit). The EDMA3CC does not recognize errors here but the EDMA3TC asserts an error, if this is not true. See Section 2.11.2. Note: Constant (CONST) addressing mode has limited applicability. The EDMA3 should be configured for CONST mode (SAM/DAM = 1) only if the transfer source or destination (on-chip memory, off-chip memory controllers, slave peripherals) support constant addressing mode. See the device-specific data manual to verify if constant addressing mode is supported. If constant addressing mode is not supported, the similar logical transfer can be achieved using INCR mode (SAM/DAM = 0) by appropriately programming the count and indices values. SPRUG34–November 2008 EDMA3 Architecture 35 Submit Documentation Feedback

01C0 4040h 2 Parameter set 2 01C0 4060h 3 Parameter set 3 01C0 4FC0h 01C0 4FE0h 126 127 Parameter set 127 Parameter set 126 OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link X=4FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rsvd PaRAM set 3 PaRAM set 127 01C0 4FC0h 01C0 4FE0h 126 127 Parameter set 126 Parameter set 127 Parameter set 0 0 01C0 4000h 01C0 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set # PaRAM PaRAM set 3 (a) At initialization (b) After completion of PaRAM set 3 (link update) Link update 01C0 4FC0h 126 Parameter set 126 Parameter set 0 0 01C0 4000h 01C0 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set # PaRAM 0h 0h Link=FFFFh 0h 0h 0h 0h 0h 0h 0h 0h 0h PaRAM set 3 (Null PaRAM set) 0h 1CA0 4FE0h 127 Parameter set 127 (c) After completion of PaRAM set 127 (link to null set) OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y=FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y Rsvd OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y=FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y Rsvd PaRAM set 127 OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y=FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y Rsvd Parameter RAM (PaRAM) www.ti.com The EDMA3 controller does not use the concept of element-size and element-indexing. Instead, all transfers are defined in terms of all three dimensions: ACNT, BCNT, and CCNT. An element-indexed transfer is logically achieved by programming ACNT to the size of the element and BCNT to the number of elements that need to be transferred. For example, if you have 16-bit audio data and 256 audio samples that needed to be transferred to a serial port, this can be done by programming the ACNT = 2 (2 bytes) and BCNT = 256. Figure 2-8. Linked Transfer 36 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

01C0 4040h 2 Parameter set 2 01C0 4060h 3 Parameter set 3 01C0 4FC0h 01C0 4FE0h 126 127 Parameter set 127 Parameter set 126 OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link=4FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rsvd PaRAM set 3 PaRAM set 127 01C0 4FC0h 01C0 4FE0h 126 127 Parameter set 126 Parameter set 127 Parameter set 0 0 01C0 4000h 01C0 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set # PaRAM PaRAM set 3 (a) At initialization (b) After completion of PaRAM set 3 (link update) 01C0 4FC0h 126 Parameter set 126 Parameter set 0 0 01C0 4000h 01C0 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set # PaRAM CCNT X SRCCIDX X Link=4FE0h SRCBIDX X ACNT X DSTCIDX X Rsvd BCNTRLD X DSTBIDX X DST X SRC X PaRAM set 3 OPT X 1CA0 4FE0h 127 Parameter set 127 (c) After completion of PaRAM set 127 (link to self) OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link =4FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rsvd OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link =4FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rsvd PaRAM set 127 OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link =4FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rsvd BCNT X Link update www.ti.com Parameter RAM (PaRAM) Figure 2-9. Link-to-Self Transfer SPRUG34–November 2008 EDMA3 Architecture 37 Submit Documentation Feedback

2.4.1 DMA Channel 2.4.1.1 Event-Triggered Transfer Request Initiating a DMA Transfer www.ti.com There are multiple ways to initiate a programmed data transfer using the EDMA3 channel controller. Transfers on DMA channels are initiated by three sources: • Event-triggered transfer request (this is the more typical usage of EDMA3): Allows for a peripheral, system, or externally-generated event to trigger a transfer request. • Manually-triggered transfer request: The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH). • Chain-triggered transfer request: A transfer is triggered on the completion of another transfer or subtransfer. Transfers on QDMA channels are initiated by two sources: • Autotriggered transfer request: A transfer is triggered when the programmed trigger word is written to. • Link-triggered transfer requests: When linking occurs, the transfer is triggered when the trigger word is written to. When an event is asserted from a peripheral or device pins, it gets latched in the corresponding bit of the event register (ER.En = 1). See Table 2-5 for peripheral event to DMA event mapping. If the corresponding event in the event enable register (EER) is enabled (EER.En = 1), then the EDMA3CC prioritizes and queues the event in the appropriate event queue. When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the transfer controller. If the PaRAM set is valid (not a NULL set), then a transfer request packet (TRP) is submitted to the EDMA3TC and the En bit in ER is cleared. At this point, a new event can be safely received by the EDMA3CC. If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request (TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the corresponding channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to a null TR being serviced. Good programming practices should include cleaning the event missed error before retriggering the DMA channel. When an event is received, the corresponding event bit in the event register is set (ER.En = 1), regardless of the state of EER.En. If the event is disabled when an external event is received (ER.En = 1 and EER.En = 0), the ER.En bit remains set. If the event is subsequently enabled (EER.En = 1), then the pending event is processed by the EDMA3CC and the TR is processed/submitted, after which the ER.En bit is cleared. If an event is being processed (prioritized or is in the event queue) and another sync event is received for the same channel prior to the original being cleared (ER.En != 0), then the second event is registered as a missed event in the corresponding bit of the event missed register (EMR.En = 1). Table 2-5 gives an example of the synchronization events associated with each of the programmable DMA channels in the TMS320DM357 device. See the device-specific data manual to determine the event to channel mapping. Table 2-5. EDMA3 Channel Synchronization Events EDMA3 Channel Event Name Event Description 0-1 - Unused 2 XEVT Audio Serial Port (ASP) Transmit Event 3 REVT Audio Serial Port (ASP) Receive Event 4 HISTEVT VPSS Histogram Event 5 H3AEVT VPSS H3A Event 38 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

Table 2-5. EDMA3 Channel Synchronization Events (continued) EDMA3 Channel Event Name Event Description 6 PRVUEVT VPSS Preview Event 7 RSZEVT VPSS Resizer Event 8 IMXINT Reserved 9 VLCDINT Reserved 10 ASQINT Reserved 11 DSQINT Reserved 12-15 - Unused 16 SPIXEVT SPI Transmit Event 17 SPIREVT SPI Receive Event 18 URXEVT0 UART 0 Receive Event 19 UTXEVET0 UART 0 Transmit Event 20 URXEVT1 UART 1 Receive Event 21 UTXEVET1 UART 1 Transmit Event 22 URXEVT2 UART 2 Receive Event 23 UTXEVET2 UART 2 Transmit Event 24-25 - Unused 26 MMCRXEVT MMC/SD Receive Event 27 MMCTXEVT MMC/SD Transmit Event 28 I2CREVT I2C Receive Event 29 I2CXEVT I2C Transmit Event 30-31 - Unused 32 GPINT0 GPIO 0 Event 33 GPINT1 GPIO 1 Event 34 GPINT2 GPIO 2 Event 35 GPINT3 GPIO 3 Event 36 GPINT4 GPIO 4 Event 37 GPINT5 GPIO 5 Event 38 GPINT6 GPIO 6 Event 39 GPINT7 GPIO 7 Event 40 GPBNKINT0 GPIO Bank 0 Event 41 GPBNKINT1 GPIO Bank 1 Event 42 GPBNKINT2 GPIO Bank 2 Event 43 GPBNKINT3 GPIO Bank 3 Event 44 GPBNKINT4 GPIO Bank 4 Event 45-47 - Unused 48 TEVT0 Timer 0 Event 49 TEVT1 Timer 0 Event 50 TEVT2 Timer 1 Event 51 TEVT3 Timer 1 Event 52 PWM0 PWM 0 Event 53 PWM1 PWM 1 Event 54 PWM2 PWM 2 Event 55-63 - Unused SPRUG34–November 2008 EDMA3 Architecture 39 Submit Documentation Feedback

2.4.1.3 Chain-Triggered Transfer Request Initiating a DMA Transfer www.ti.com A DMA transfer is initiated by a write to the event set register (ESR) by the CPU (or any EDMA programmer). Writing a 1 to an event bit in the ESR results in the event being prioritized/queued in the appropriate event queue, regardless of the state of the EER.En bit. When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the transfer controller. As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again. If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request (TR) is submitted and the corresponding En bit in ER is cleared and simultaneously the corresponding channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to a null TR being serviced. Good programming practices should include clearing the event missed error before retriggering the DMA channel. If an event is being processed (prioritized or is in the event queue) and the same channel is manually set by a write to the corresponding channel bit of the event set register (ESR.En = 1) prior to the original being cleared (ESR.En = 0), then the second event is registered as a missed event in the corresponding bit of the event missed register (EMR.En = 1). Chaining is a mechanism by which the completion of one transfer automatically sets the event for another channel. When a chained completion code is detected, the value of which is dictated by the transfer completion code (TCC[5:0] in OPT of the PaRAM set associated with the channel), it results in the corresponding bit in the chained event register (CER) to be set (CER.E[TCC] = 1). Once a bit is set in CER, the EDMA3CC prioritizes and queues the event in the appropriate event queue. When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the transfer controller. As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again. If the PaRAM set associated with the channel is a NULL set (see Section 2.3.3), then no transfer request (TR) is submitted and the corresponding En bit in CER is cleared and simultaneously the corresponding channel bit is set in the event miss register (EMR.En = 1) to indicate that the event was discarded due to a null TR being serviced. In this case, the error condition must be cleared by you before the DMA channel can be retriggered. Good programming practices might include clearing the event missed error before retriggering the DMA channel. If a chaining event is being processed (prioritized or queued) and another chained event is received for the same channel prior to the original being cleared (CER.En != 0), then the second chained event is registered as a missed event in the corresponding channel bit of the event missed register (EMR.En = 1). Note: Chained event registers, event registers, and event set registers operate independently. An event (En) can be triggered by any of the trigger sources (event-triggered, manually-triggered, or chain-triggered). 40 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

2.4.3 Comparison Between DMA and QDMA Channels www.ti.com Initiating a DMA Transfer QDMA-based transfer requests are issued when a QDMA event gets latched in the QDMA event register (QER.En = 1). A bit corresponding to a QDMA channel is set in the QDMA event register (QER) when the following occurs: • A CPU (or any EDMA3 programmer) write occurs to a PaRAM address that is defined as a QDMA channel trigger word (programmed in the QDMA channel mapping register (QCHMAPn)) for the particular QDMA channel and the QDMA channel is enabled via the QDMA event enable register (QEER.En = 1). • EDMA3CC performs a link update on a PaRAM set address that is configured as a QDMA channel (matches QCHMAPn settings) and the corresponding channel is enabled via the QDMA event enable register (QEER.En = 1). Once a bit is set in QER, the EDMA3CC prioritizes and queues the event in the appropriate event queue. When the event reaches the head of the queue, it is evaluated for submission as a transfer request to the transfer controller. As in the event-triggered transfers, if the PaRAM set associated with the channel is valid (it is not a null set) then the TR is submitted to the associated EDMA3TC and the channel can be triggered again. If a bit is already set in QER (QER.En = 1) and a second QDMA event for the same QDMA channel occurs prior to the original being cleared, the second QDMA event gets captured in the QDMA event miss register (QEMR.En = 1). The primary difference between DMA and QDMA channels is the event/channel synchronization. QDMA events are either autotriggered or link triggered. Autotriggering allows QDMA channels to be triggered by CPU(s) with a minimum number of linear writes to PaRAM. Link triggering allows a linked list of transfers to be executed, using a single QDMA PaRAM set and multiple link PaRAM sets. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). Note that for CPU triggered (manually triggered) DMA channels, in addition to writing to the PaRAM set, it is required to write to the event set register (ESR) to kick-off the transfer. QDMA channels are typically for cases where a single event will accomplish a complete transfer since the CPU (or EDMA3 programmer) must reprogram some portion of the QDMA PaRAM set in order to retrigger the channel. In other words, QDMA transfers are programmed with BCNT = CCNT = 1 for A-synchronized transfers, and CCNT = 1 for AB-synchronized transfers. Additionally, since linking is also supported (if STATIC = 0 in OPT) for QDMA transfers, it allows you to initiate a linked list of QDMAs, so when EDMA3CC copies over a link PaRAM set (including the write to the trigger word), the current PaRAM set mapped to the QDMA channel will automatically be recognized as a valid QDMA event and initiate another set of transfers as specified by the linked set. SPRUG34–November 2008 EDMA3 Architecture 41 Submit Documentation Feedback

Completion of a DMA Transfer www.ti.com A parameter set for a given channel is complete when the required number of transfer requests is submitted (based on receiving the number of synchronization events). The expected number of TRs for a non-null/non-dummy transfer is shown in Table 2-6 for both synchronization types along with state of the PaRAM set prior to the final TR being submitted. When the counts (BCNT and/or CCNT) are this value, the next TR results in a: • Final chaining or interrupt codes to be sent by the transfer controllers (instead of intermediate). • Link updates (linking to either null or another valid link set). Table 2-6. Expected Number of Transfers for Non-Null Transfer Sync Mode Counts at time 0 Total # Transfers Counts prior to final TR A-synchronized ACNT (BCNT × CCNT ) TRs of ACNT bytes each BCNT == 1 && CCNT == 1 BCNT CCNT AB-synchronized ACNT CCNT TRs for ACNT × BCNT bytes each CCNT == 1 BCNT CCNT You must program the PaRAM OPT field with a specific transfer completion code (TCC) along with the other OPT fields (TCCHEN, TCINTEN, ITCCHEN, and ITCINTEN bits) to indicate whether the completion code is to be used for generating a chained event or/and for generating an interrupt upon completion of a transfer. The specific TCC value (6-bit binary value) programmed dictates which of the 64-bits in the chain event register (CER[TCC]) and/or interrupt pending register (IPR[TCC]) is set. See Section 2.9 for details on interrupts and Section 2.8 for details on chaining. You can also selectively program whether the transfer controller sends back completion codes on completion of the final transfer request (TR) of a parameter set (TCCHEN or TCINTEN), for all but the final transfer request (TR) of a parameter set (ITCCHEN or ITCINTEN), or for all TRs of a parameter set (both). See Section 2.8 for details on chaining (intermediate/final chaining) and Section 2.9 for details on intermediate/final interrupt completion. A completion detection interface exists between the EDMA3 channel controller and transfer controller(s). This interface sends back information from the transfer controller to the channel controller to indicate that a specific transfer is completed. All DMA/QDMA PaRAM sets must also specify a link address value. For repetitive transfers such as ping-pong buffers, the link address value should point to another predefined PaRAM set. Alternatively, a nonrepetitive transfer should set the link address value to the null link value. The null link value is defined as FFFFh. See Section 2.3.7 for more details. Note: Any incoming events that are mapped to a null PaRAM set results in an error condition. The error condition should be cleared before the corresponding channel is used again. See Section 2.3.5. There are three ways the EDMA3CC gets updated/informed about a transfer completion: normal completion, early completion, and dummy/null completion. This applies to both chained events and completion interrupt generation. EDMA3 Architecture 42 SPRUG34–November 2008 Submit Documentation Feedback

2.6 Event, Channel, and PaRAM Mapping www.ti.com Event, Channel, and PaRAM Mapping In normal completion mode (TCCMODE = 0 in OPT), the transfer or sub-transfer is considered to be complete when the EDMA3 channel controller receives the completion codes from the EDMA3 transfer controller. In this mode, the completion code to the channel controller is posted by the transfer controller after it receives a signal from the destination peripheral. Normal completion is typically used to generate an interrupt to inform the CPU that a set of data is ready for processing. In early completion mode (TCCMODE = 1 in OPT), the transfer is considered to be complete when the EDMA3 channel controller submits the transfer request (TR) to the EDMA3 transfer controller. In this mode, the channel controller generates the completion code internally. Early completion is typically useful for chaining, as it allows subsequent transfers to be chained-triggered while the previous transfer is still in progress within the transfer controller, maximizing the overall throughput of the set of the transfers. This is a variation of early completion. Dummy or null completion is associated with a dummy set (Section 2.3.4) or null set (Section 2.3.3). In both cases, the EDMA3 channel controller does not submit the associated transfer request to the EDMA3 transfer controller(s). However, if the set (dummy/null) has the OPT field programmed to return completion code (intermediate/final interrupt/chaining completion), then it will set the appropriate bits in the interrupt pending registers (IPR/IPRH) or chained event register (CER/CERH). The internal early completion path is used by the channel controller to return the completion codes internally (that is, EDMA3CC generates the completion code). Several of the 64 DMA channels are tied to a specific hardware event, thus allowing transfers to be triggered by events from device peripherals or external hardware. A DMA channel typically requests a data transfer when it receives its event (apart from manually-triggered, chain-triggered, and other transfers). The amount of data transferred per synchronization event depends on the channel’s configuration (ACNT, BCNT, CCNT, etc.) and the synchronization type (A-synchronized or AB-synchronized). The association of an event to a channel is fixed. Each of the DMA channels has one specific event associated with it. Table 2-5 provides the synchronization events associated with each of the programmable DMA channels. If in an application, a channel does not make use of the associated synchronization event or does not have an associated synchronization event (unused), that channel can be used for manually-triggered or chained-triggered transfers, for linking/reloading, or as a QDMA channel. SPRUG34–November 2008 EDMA3 Architecture 43 Submit Documentation Feedback

2.6.2 QDMA Channel to PaRAM Mapping Event, Channel, and PaRAM Mapping www.ti.com The mapping between the DMA channel numbers and the PaRAM sets is a fixed, one-to-one mapping (see Table 2-7). In other words, channel (event) 0 is mapped to PaRAM set 0, channel (event 1) is mapped to PaRAM set 1, etc. So, for example, in order to program a transfer for event number 3, DMA channel 3 is associated with PaRAM set number 3 and you need to program this PaRAM set for configuring transfers associated with event number 3. Table 2-7. EDMA3 DMA Channel to PaRAM Mapping PaRAM Set Number Address Mapping PaRAM Set 0 01C0 4000h to 01C0 401Fh DMA Channel 0/Reload/QDMA PaRAM Set 1 01C0 4020h to 01C0 403Fh DMA Channel 1/Reload/QDMA PaRAM Set 2 01C0 4040h to 01C0 405Fh DMA Channel 2/Reload/QDMA PaRAM Set 3 01C0 4060h to 01C0 407Fh DMA Channel 3/Reload/QDMA PaRAM Set 4 01C0 4080h to 01C0 409Fh DMA Channel 4/Reload/QDMA PaRAM Set 5 01C0 40A0h to 01C0 40BFh DMA Channel 5/Reload/QDMA PaRAM Set 6 01C0 40C0h to 01C0 40DFh DMA Channel 6/Reload/QDMA PaRAM Set 7 01C0 40E0h to 01C0 40FFh DMA Channel 7/Reload/QDMA PaRAM Set 8 01C0 4100h to 01C0 411Fh DMA Channel 8/Reload/QDMA PaRAM Set 9 01C0 4120h to 01C0 413Fh DMA Channel 9/Reload/QDMA PaRAM Set 10 01C0 4140h to 01C0 415Fh DMA Channel 10/Reload/QDMA PaRAM Set 11 01C0 4160h to 01C0 417Fh DMA Channel 11/Reload/QDMA PaRAM Set 12 01C0 4180h to 01C0 419Fh DMA Channel 12/Reload/QDMA PaRAM Set 13 01C0 41A0h to 01C0 41BFh DMA Channel 13/Reload/QDMA PaRAM Set 14 01C0 41C0h to 01C0 41DFh DMA Channel 14/Reload/QDMA PaRAM Set 15 01C0 41E0h to 01C0 41FFh DMA Channel 15/Reload/QDMA PaRAM Set 16 01C0 4200h to 01C0 421Fh DMA Channel 16/Reload/QDMA ... ... ... PaRAM Set 62 01C0 47C0h to 01C0 47DFh DMA Channel 62/Reload/QDMA PaRAM Set 63 01C0 47E0h to 01C0 47FFh DMA Channel 63/Reload/QDMA PaRAM Set 64 01C0 4800h to 01C0 481Fh Reload/QDMA PaRAM Set 65 01C0 4820h to 01C0 483Fh Reload/QDMA ... ... ... PaRAM Set 126 01C0 4FC0h to 01C0 4FDFh Reload/QDMA PaRAM Set 127 01C0 4FE0h to 01C0 4FFFh Reload/QDMA The mapping between the QDMA channels and the PaRAM sets is programmable .The QDMA channel mapping register (QCHMAP) in the EDMA3CC provides programmability for the QDMA channels to be mapped to any of the PaRAM sets in the PaRAM memory map. Figure 2-10 illustrates the use of QCHMAP. Additionally, QCHMAP allows you to program the trigger word in the PaRAM set for the QDMA channel. A trigger word is one of the 8 words in the PaRAM set. For a QDMA transfer to occur, a valid TR synchronization event for EDMA3CC is a write to the trigger word in the PaRAM set pointed to by QCHMAP for a particular QDMA channel. By default, QDMA channels are mapped to PaRAM set 0. Care must be taken to appropriately remap PaRAM set 0 before it is used. 44 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

31 13 14 PAENTRY 4 5 0 2 1 TR WORD 00 QCHMAPn Parameter set 0 Parameter set 1 Parameter set 3 Parameter set 2 Parameter set 127 Parameter set 126 Set # Byte address 01C0 4000h 01C0 4020h 01C0 4040h 01C0 4060h 01C0 4FC0h 01C0 4FE0h 0 1 2 3 126 127 DSTBIDX BCNTRLD Rsvd DSTCIDX CCNT SRCCIDX LINK SRCBIDX DST BCNT ACNT SRC OPT PaRAM PaRAM set +0h +4h +8h +Ch Byte address +1Ch +18h +14h +10h offset 00 0000 011 1 11 2.7 EDMA3 Channel Controller Regions 2.7.1 Region Overview www.ti.com EDMA3 Channel Controller Regions Figure 2-10. QDMA Channel to PaRAM Mapping The EDMA3 channel controller divides its address space into four regions. Individual channel resources are assigned to a specific region, where each region is typically assigned to a specific EDMA programmer. Application software is required to use the appropriate region. The EDMA3 channel controller memory-mapped registers are divided in three main categories: 1. Global registers 2. Global region channel registers 3. Shadow region channel registers The global registers are located at a single/fixed location in the EDMA3CC memory map. These registers control EDMA3 resource mapping and provide debug visibility and error tracking information. See the device-specific data manual for the EDMA3CC memory map. The channel registers (including DMA, QDMA, and interrupt registers) are accessible via the global channel region address range, or in the shadow n channel region address range(s). For example, the event enable register (EER) is visible at the global address of 01C0 1020h or region addresses of 01C0 2020h for region 0 and 01C0 2220h for region 1. The underlying control register bits that are accessible via the shadow region address space (except for IEVALn) are controlled by the DMA region access enable registers (DRAEm) and QDMA region access enable registers (QRAEn) . Table 2-8 lists the registers in the shadow region memory map. (Refer to EDMA3CC memory map figure for the complete global and shadow region memory maps.) Figure 2-11 illustrates the conceptual view of the regions. SPRUG34–November 2008 EDMA3 Architecture 45 Submit Documentation Feedback

IEVAL QSECR ER, ERH Shadow region 0 QRAE0 QRAE3 EDMA3 Channel Controller Regions www.ti.com Table 2-8. Shadow Region Registers DRAEm DRAEHm QRAEn ER ERH QER ECR ECRH QEER ESR ESRH QEECR CER CERH QEESR EER EERH EECR EECRH EESR EESRH SER SERH SECR SECRH IER IERH IECR IECRH IESR IESRH IPR IPRH ICR ICRH Register not affected by DRAE\DRAEH IEVAL Figure 2-11. Shadow Region Registers EDMA3 Architecture 46 SPRUG34–November 2008 Submit Documentation Feedback

2.8 Chaining EDMA3 Channels www.ti.com Chaining EDMA3 Channels An EDMA3 transfer is programmed/configured by the ARM. In order to provide autonomous operation for each master, the EDMA3 channel controller allows partitioning of the resources between different masters via the shadow regions. There are four EDMA3 shadow regions (and its associated memory maps). The first shadow region is associated to the EDMA3 programmers (ARM) that have read/write access to the memory-mapped registers of the EDMA3CC. The remaining three shadow regions are reserved and should not be used. Associated with each shadow region are a set of registers defining which channels and interrupt completion codes belong to that region. These registers are user-programmed per region, in order to assign ownership of the DMA/QDMA channels to a region. • DRAEm and DRAEHm: One register pair exists for the ARM shadow region. The number of bits in each register pair matches the number of DMA channels (64 DMA channels). These registers need to be programmed to assign ownership of DMA channels and interrupt (or TCC codes) to the respective region. Accesses to DMA and interrupt registers via the shadow region address view are filtered through the DRAE/DRAEH pair. A value of 1 in the corresponding DRAE(H) bit implies that the corresponding DMA/interrupt channel is accessible; a value of 0 in the corresponding DRAE(H) bit forces writes to be discarded and returns a value of 0 for reads. • QRAE: The number of bits in the register matches the number of QDMA channels (8 QDMA channels).These registers need to be programmed to assign ownership of QDMA channels to the respective region. To enable a channel in a shadow region, using shadow region 0 QEER, writing into QEESR will not have the desired effect if the respective bit in QRAE is not set. The EDMA3CC has four DMA region access registers (DRAE0-3 and DRAEH0-3) and four QDMA region access registers (QRAE0-3). Table 2-9 provides the shadow region and region access registers assignment to each of the EDMA3 masters. Table 2-9. EDMA3 Shadow Regions EDMA3 Master Region Region Access Registers ARM Shadow Region 0 DRAE0, DRAEH0, and QRAE0 - Shadow Region 1 DRAE1, DRAEH1, and QRAE1 - Shadow Region 2 DRAE2, DRAEH2, and QRAE2 - Shadow Region 3 DRAE3, DRAEH3, and QRAE3 A value of 1 in a given bit position in the DMA/QDMA region access enable register corresponding to a particular shadow region implies that the corresponding channel (and the corresponding bit position) can be manipulated via the EDMA3 master associated to that shadow region. For example, DRAEH0 = 0000 0001h implies that DMA channel 32 (which is accessed at bit position 32) is manipulated by ARM (shadow region 0). Note: An EDMA programmer is limited to only using the appropriate region via software convention. illustrates a judicious resource pool division across two regions, assuming the ARM needs to be allocated 16 DMA channels (0-15) and 4 QDMA channels (0, 3, 5, and 7) and 32 TCC codes (0-15 and 48-63). The image coprocessor needs to be allocated 16 DMA channels (16-32) and the remaining 4 QDMA channels (1, 2, 4, and 6) and TCC codes (16-47). DRAE should be equal to the OR of the bits required for the DMA channels and the TCC codes: The channel chaining capability for the EDMA3 allows the completion of an EDMA3 channel transfer to trigger another EDMA3 channel transfer. The purpose is to allow you the ability to chain several events through one event occurrence. SPRUG34–November 2008 EDMA3 Architecture 47 Submit Documentation Feedback

www.ti.com Chaining is different from linking (Section 2.3.7). The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event to the chained channel (see Section 2.4.1.3 for chain-triggered transfer requests). Chaining is achieved at either final transfer completion or intermediate transfer completion, or both, of the current channel. Consider a channel m (DMA/QDMA) required to chain to channel n. Channel number n (0-63) needs to be programmed into the TCC field of channel m channel options parameter (OPT) set. • If final transfer completion chaining (TCCHEN = 1 and ITCCHEN = 0 in channel m OPT) is enabled, the chain-triggered event occurs after the last transfer request of channel m is submitted (early completion) or completed (normal completion). • If intermediate transfer completion chaining (ITCCHEN = 1 and ITCCHEN = 0 in channel m OPT) is enabled, the chain-triggered event occurs after every intermediate transfer request of channel m is submitted (early completion) or completed (normal completion). • If both final and intermediate transfer completion chaining (TCCHEN = 1 and ITCCHEN = 1 in channel m OPT) are enabled, the chain-trigger event occurs after every transfer request of channel m is submitted (early completion) or completed (normal completion). Table 2-10 shows the number of chain event triggers occurring in different synchronized scenarios. Consider channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30. Table 2-10. Chain Event Triggers (Number of chained event triggers on channel 30) Options A-Synchronized AB-Synchronized TCCHEN = 1, ITCCHEN = 0 1 (Last TR) 1 (Last TR) TCCHEN = 0, ITCCHEN = 1 19 (All but the last TR) 4 (All but the last TR) TCCHEN = 1, ITCCHEN = 1 20 (All TRs) 5 (All TRs) EDMA3 Architecture 48 SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com EDMA3 Interrupts The EDMA3 interrupts are divided into 2 categories: • Transfer completion interrupts • Error interrupts The transfer completion interrupts are listed in Table 2-11 and the error interrupts are listed in Table 2-12. For more information on the ARM interrupt controller (AINTC), see the TMS320DM357 DMSoC ARM Subsystem Reference Guide (SPRUG25). Table 2-11. EDMA3 Transfer Completion Interrupts Interrupt Number Name Description ARM AINTC EDMA3CC_INT0 EDMA3CC Transfer Completion Interrupt Shadow x 16 Region 0 EDMA3CC_INT1 EDMA3CC Transfer Completion Interrupt Shadow - - Region 1 EDMA3CC_INT2 EDMA3CC Transfer Completion Interrupt Shadow - - Region 2 Table 2-12. EDMA3 Error Interrupts Interrupt Number Name Description ARM AINTC EDMA3CC_ERRINT EDMA3CC Error Interrupt x 17 EDMA3TC_ERRINT0 TC0 Error Interrupt x 18 EDMA3TC_ERRINT1 TC1 Error Interrupt x 19 The EDMA3CC is responsible for generating transfer completion interrupts to the CPU(s) (and other EDMA3 masters). The EDMA3 generates a single completion interrupt per shadow region on behalf of all DMA/QDMA channels. Various control registers and bit fields facilitate EDMA3 interrupt generation. The transfer completion code (TCC) value is directly mapped to the bits of the interrupt pending register (IPR/IPRH), as shown in Table 2-13. For example, if TCC = 10 0001b, IPRH[1] is set after transfer completion, and results in interrupt generation to the CPU(s) if the completion interrupt is enabled for the CPU. See Section 2.9.1.1 for details on enabling EDMA3 transfer completion interrupts. When a completion code is returned (as a result of early or normal completion), the corresponding bit in IPR/IPRH is set. For the completion code to be returned, the PaRAM set associated with the transfer must enable the transfer completion interrupt (final/intermediate) in the channel options parameter (OPT). The transfer completion code (TCC) can be programmed to any value for a DMA/QDMA channel. There does not need to be a direct relation between the channel number and the transfer completion code value. This allows multiple channels having the same transfer completion code value to cause a CPU to execute the same interrupt service routine (ISR) for different channels. If the channel is used in the context of a shadow region and you intend for the shadow region interrupt to be asserted, then ensure that the bit corresponding to the TCC code is enabled in IER/IERH and in the corresponding shadow regions's DMA region access registers (DRAE/DRAEH). SPRUG34–November 2008 EDMA3 Architecture 49 Submit Documentation Feedback

EDMA3 Interrupts www.ti.com Table 2-13. Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping TCC Bits in OPT TCC Bits in OPT (TCINTEN/ITCINTEN = 1) IPR Bit Set (TCINTEN/ITCINTEN = 1) IPRH Bit Set(1) 00 0000b IPR0 10 0000b IPR32/IPRH0 00 0001b IPR1 10 0001b IPR33/IPRH1 00 0010b IPR2 10 0010b IPR34/IPRH2 00 0011b IPR3 10 0011b IPR35/IPRH3 00 0100b IPR4 10 0100b IPR36/IPRH4 … … … … … … … … 01 1110b IPR30 11 1110b IPR62/IPRH30 01 1111b IPR31 11 1111b IPR63/IPRH31 (1) Bit fields IPR[32-63] correspond to bits 0 to 31 in IPRH, respectively. You can enable Interrupt generation at either final transfer completion or intermediate transfer completion, or both. Consider channel m as an example. • If the final transfer interrupt (TCINTEN = 1 and ITCINTEN = 0 in OPT) is enabled, the interrupt occurs after the last transfer request of channel m is either submitted or completed (depending on early or normal completion). • If the intermediate transfer interrupt (TCINTEN = 0 and ITCINTEN = 1 in OPT) is enabled, the interrupt occurs after every intermediate transfer request of channel m is either submitted or completed (depending on early or normal completion). • If both final and intermediate transfer completion interrupts (TCINTEN = 1 and ITCINTEN = 1 in OPT) are enabled, the interrupt occurs after every transfer request of channel m is submitted or completed (depending on early or normal completion). Table 2-14 shows the number of interrupts occurring in different synchronized scenarios. Consider channel 31 programmed with ACNT = 3, BCNT = 4, CCNT = 5, and TCC = 30. Table 2-14. Number of Interrupts Options A-Synchronized AB-Synchronized TCINTEN = 1, ITCINTEN = 0 1 (Last TR) 1 (Last TR) TCINTEN = 0, ITCINTEN = 1 19 (All but the last TR) 4 (All but the last TR) TCINTEN = 1, ITCINTEN = 1 20 (All TRs) 5 (All TRs) For the EDMA3 channel controller to assert a transfer completion to the external world, the interrupts have to be enabled in the EDMA3CC. This is in addition to setting up the TCINTEN and ITCINTEN bits in OPT of the associated PaRAM set. The EDMA3 channel controller has interrupt enable registers (IER/IERH) and each bit location in IER/IERH serves as a primary enable for the corresponding interrupt pending registers (IPR/IPRH). All the interrupt registers (IER, IESR, IECR, and IPR) are either manipulated from the global DMA channel region or by way of the DMA channel shadow regions. The shadow regions provide a view to the same set of physical registers that are in the global region. The EDMA3 channel controller has a hierarchical completion interrupt scheme that makes use of a single set of interrupt pending registers (IPR/IPRH) and single set of interrupt enable registers (IER/IERH). A second level of interrupt masking is provided by the programmable DMA region access enable registers (DRAE/DRAEH) for asserting the completion interrupts. See Figure 2-12. 50 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

DMA region EDMA3CC_INT1 EDMA3CC_INT2 EDMA3CC_INT3 pulse Eval Eval pulse access enable 3 X 1 0 (DRAE2) access enable 2 DMA region X 1 DMA region (DRAE3) 0 (not connected) IEVAL1.EVAL IEVAL3.EVAL IEVAL2.EVAL (not connected) (not connected) 2.9.1.2 Clearing Transfer Completion Interrupts 2.9.2 EDMA3 Interrupt Servicing www.ti.com EDMA3 Interrupts Figure 2-12. Interrupt Diagram In order for the EDMA3CC to generate the transfer completion interrupts associated with each shadow region, the following conditions need to be true: • EDMACC_INT0 (to ARM): (IPR.E0 & IER.E0 & DRAE0.E0) | (IPR.E1 & IER.E1 & DRAE0.E1) | …|(IPRH.E63 & IERH.E63 & DRAHE0.E63) Enabling the transfer completion region interrupts by DRAE/DRAEH makes provision for unique assignment of channels and interrupts in a multiple-CPU environment. This allows independent operations for all CPU(s) (or EDMA3 masters) in using the EDMA3 resources. Transfer completion interrupts that are latched to the interrupt pending registers (IPR/IPRH) are cleared by writing a 1 to the corresponding bit in the interrupt pending clear register (ICR/ICRH). For example, a write of 1 to ICR.E0 clears a pending interrupt in IPR.E0. If an incoming transfer completion code (TCC) gets latched to a bit in IPR/IPRH, then additional bits that get set due to a subsequent transfer completion will not result in asserting the EDMA3CC completion interrupt. In order for the completion interrupt to be pulsed, the required transition is from a state where no enabled interrupts are set to a state where at least one enabled interrupt is set. On completion of a transfer (early or normal completion), the EDMA3 channel controller sets the appropriate bit in the interrupt pending registers (IPR/IPRH) as specified by the transfer completion codes. If the completion interrupts are appropriately enabled, then the CPU enters the interrupt service routine (ISR) when the completion interrupt is asserted. Since there is a single completion interrupt for all DMA/QDMA channels. SPRUG34–November 2008 EDMA3 Architecture 51 Submit Documentation Feedback

recognition of future interrupts. Only when all IPR/IPRH bits are cleared, the EDMA3CC will assert additional completion interrupts. It is possible that when one interrupt is serviced; many other transfer completions result in additional bits being set in IPR/IPRH, thereby resulting in additional interrupts. It is likely that each of these bits in IPR/IPRH would need different types of service; therefore, the ISR must check all pending interrupts and continue until all the posted interrupts are appropriately serviced. Following are examples (pseudo code) for a CPU interrupt service routine for an EDMA3CC completion interrupt. The ISR routine in Example 2-1 is more exhaustive and incurs a higher latency. 52 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

The pseudo code: 1. Read the interrupt pending register (IPR/IPRH). 2. Perform the operations needed. 3. Write to the interrupt pending clear register (ICR/ICRH) to clear the corresponding IPR/IPRH bit. 4. Read IPR/IPRH again: a. If IPR/IPRH is not equal to 0, repeat from step 2 (implies occurrence of new event between step 2 to step 4). b. If IPR/IPRH is equal to 0, this should assure you that all enabled interrupts are inactive. Note: It is possible that during step 4, an event occurs while the IPR/IPRH bits are read to be 0 and the application is still in the interrupt service routine. If this happens, a new interrupt is recorded in the device interrupt controller and a new interrupt is generated as soon as the application exits the interrupt service routine. Example 2-2 is less rigorous, with less burden on the software in polling for set interrupt bits, but can occasionally cause a race condition, as mentioned above. Example 2-2. Interrupt Servicing If it is desired to leave any enabled and pending (possibly lower priority) interrupts, it is required to force the interrupt logic to reassert the interrupt pulse by setting the EVAL bit in the interrupt evaluation register (IEVAL). The pseudo code: 1. Enter ISR. 2. Read IPR/IPRH. 3. For the condition set in IPR/IPRH that you desire to service: a. Service interrupt as required by application. b. Clear bit for serviced conditions (others may still be set, and other transfers may have resulted in returning the TCC to EDMA3CC after step 2). 4. Read IPR/IPRH prior to exiting ISR: a. If IPR/IPRH is equal to 0, then exit ISR. b. If IPR/IPRH is not equal to 0, then set IEVAL so that upon exit of ISR, a new interrupt is triggered if any enabled interrupts are still pending. The EVAL bit must not be set when IPR and IPRH are read to be 0, to avoid generation of extra interrupt pulses. Note: Since the DMA region access registers (DRAE/DRAEH) are required to enable the transfer completion region interrupts, it is assumed that there will be a unique and nonoverlapping (in most cases) assignment of the channels and interrupts among the different shadow regions. This allows the interrupt registers (IER, IESR, IECR, IPR, and ICR) in the different shadow regions to functionally operate in an independent manner and nonoverlapping. The above examples for the interrupt service routine is based on this assumption. SPRUG34–November 2008 EDMA3 Architecture 53 Submit Documentation Feedback

2.9.4 Error Interrupts EDMA3 Interrupts www.ti.com The EDMA3CC has interrupt evaluate registers (IEVAL) in each shadow region. These registers are the only registers in the DMA channel shadow region memory map that are not affected by the settings for the DMA region access enable registers (DRAE/DRAEH). A write of 1 to the EVAL bit in these registers associated with a particular shadow region results in pulsing the associated region interrupt, if any enabled interrupt (via IER/IERH) is still pending (IPR/IPRH). This register can be used in order to assure that the interrupts are not missed by the CPU (or the EDMA3 master associated with the shadow region) if the software architecture chooses not to use all interrupts. See Example 2-2 for the use of IEVAL in the EDMA3 interrupt service routine (ISR). Similarly an error evaluation register (EEVAL) exists in the global region. A write of 1 to the EVAL bit in EEVAL causes the pulsing of the error interrupt if any pending errors are in EMR/EMRH, QEMR, or CCERR. See Section 2.9.4 for additional details on error interrupts. Note: While using IEVAL for shadow region completion interrupts, you should make sure that the IEVAL operated upon is from that particular shadow region memory map. The EDMA3CC error registers provide the capability to differentiate error conditions (event missed, threshold exceed, etc.). Additionally, if the error bits are set in these registers, it results in asserting the EDMA3CC error interrupt. If EDMA3CC error interrupt is enabled in the device interrupt controller(s), then it allows the CPU(s) to handle the error conditions. The EDMA3CC has a single error interrupt (EDMA3CC_ERRINT) that gets asserted for all EDMA3CC error conditions. There are four conditions that cause the error interrupt to be pulsed: • DMA missed events: for all 64 DMA channels. These get latched in the event missed registers (EMR/EMRH). • QDMA missed events: for all QDMA channels. These get latched in the QDMA event missed register (QEMR). • Threshold exceed: for all event queues. These get latched in EDMA3CC error register (CCERR). • TCC error: for outstanding transfer requests expected to return completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This also gets latched in the EDMA3CC error register (CCERR). Figure 2-13 illustrates the EDMA3CC error interrupt generation operation. If any of the bits are set in the error registers due to any error condition, the EDMA3CC_ERRINT always is asserted, as there are no enables for masking these error events. Similar to transfer completion interrupts (EDMA3CC_INT*), the error interrupt also is pulsed only when the error interrupt condition transitions from a state where no errors are set to a state where at least one error bit is set. If additional error events are latched prior to the original error bits being cleared, the EDMA3CC does not generate additional interrupt pulses. To reduce the burden on the software, similar to the interrupt evaluate register (IEVAL), there is an error evaluate register (EEVAL) that allows reevaluation of pending set error events/bits. This can be used so that the CPU(s) does not miss any error events. Note: It is a good practice to have the error interrupt enabled in the device interrupt controller and associate an interrupt service routine with it to address the various error conditions appropriately. This puts less burden on software (polling for error status) and additionally provides a good debug mechanism for unexpected error conditions. EDMA3 Architecture 54 SPRUG34–November 2008 Submit Documentation Feedback

Event queues are a part of the EDMA3 channel controller. Event queues form the interface between the event detection logic in the EDMA3CC and the transfer request (TR) submission logic of the EDMA3CC. Each queue is 16 entries deep, that is, a maximum of 16 queued events per event queue. If there are more than 16 events, then the events that cannot find a place in the event queue remain set in the associated event register. There are two event queues (Queue0 and Queue1) for DM357 devices. Events in Queue0 result in submission of its associated transfer requests (TRs) to TC0. Similarly, transfer requests associated with events in Queue1 are submitted to TC1. An event that wins prioritization against other DMA and/or QDMA pending events is placed at the end of the appropriate event queue. Each event queue is serviced in a FIFO (first in–first out) order. Once the event reaches the head of its queue and the corresponding transfer controller is ready to receive another TR, the event is dequeued and the PaRAM set corresponding to the dequeued event is processed and submitted as a transfer request packet (TRP) to the associated EDMA3 transfer controller. Queue0 has higher priority than Queue1, if Queue0 and Queue1 both have at least one event entry and if both TC0 and TC1 can accept transfer requests, then the event in Queue0 is dequeued first and its associated PaRAM set is processed and submitted as a transfer request (TR) to TC0. See Section 2.10.4 for system-level performance considerations. All the event entries in all the event queues are software readable (not writeable) by accessing the event entry registers (Q0E0, Q0E1,…Q1E15, etc.). Each event entry register characterizes the queued event in terms of the type of event (manual, event, chained or autotriggered) and the event number. See Section 4.3.4.1 for a description of the bit fields in the queue event entry registers. SPRUG34–November 2008 EDMA3 Architecture 55 Submit Documentation Feedback

2.10.2 Queue RAM Debug Visibility 2.10.3 Queue Resource Tracking 2.10.4 Performance Considerations Event Queue(s) www.ti.com Each of the 64 DMA channels and 8 QDMA channels are independently programmed to map to a specific queue using the DMA queue number register (DMAQNUM) and the QDMA queue number register (QDMANUM). The mapping of DMA/QDMA channels is critical to achieving the desired performance level for the EDMA and most importantly in meeting real-time deadlines. See Section 2.10.4. Note: If an event is ready to be queued and both the event queue and the EDMA3 transfer controller associated to the event queue are empty, then the event bypasses the event queue, and goes to the PaRAM processing logic and eventually to the transfer request submission logic for submission to the EDMA3TC. In this case, the event is not logged in the event queue status registers. Each event queue has 16 entries. These 16 entries are managed in a circular FIFO manner. All event queue entries for all event queues are software readable by the event queue entry register (QxEx). Additionally, for each queue there is a queue status register (QSTATn). These registers provide user visibility and may be helpful while debugging real-time issues (typically post-mortem), involving multiple events and event sources. The event queue entry register (QxEx) uniquely identifies the specific event type (event-triggered, manually-triggered, chain-triggered, and QDMA events) along with the event number (for DMA/QDMA channels) that are in the queue or have been de-queued (passed through the queue). QSTATn includes fields for the start pointer (STRTPTR) that provides the offset to the head entry of an event. It also includes a NUMVAL field that provides the total number of valid entries residing in the event queue at a given instance of time. The STRTPTR field may be used to index appropriately into the 16 event entries. The NUMVAL number of entries starting from STRTPTR are indicative of events still queued in the respective queue. The remaining entries may be read to determine which events have already been de-queued and submitted to the associated transfer controller. The EDMA3CC event queue includes watermarking/threshold logic that allows you to keep track of maximum usage of all event queues. This is useful for debugging real-time deadline violations that may result from head-of-line blocking on a given EDMA3 event queue. You can program the maximum number of events that can queue up in an event queue by programming the threshold value (between 0 to 15) in the queue watermark threshold A register (QWMTHRA). The maximum queue usage is recorded actively in the watermark (WM) field of the queue status register (QSTATn) that keeps getting updated based on a comparison of number of valid entries, which is also visible in the NUMVAL bit in QSTATn and the maximum number of entries (WM bit in QSTATn). If the queue usage is exceeded, this status is visible in the EDMA3CC registers: the QTHRXCDn bit in the channel controller error register (CCERR) and the THRXCD bit in QSTATn, where n stands for the event queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt. The main switched central resource (SCR) (see the data manual) arbitrates bus requests from all the masters (ARM, master peripherals, VPSS, and the EDMA3 transfer controllers (TC0 and TC1)) to the shared slave resources (peripherals and memories). The priorities of transfer requests (read and write commands) from the EDMA3 transfer controllers with respect to other masters within the system are programmed using the queue priority register (QUEPRI). QUEPRI programs the priority of the event queues (or indirectly, TC0 and TC1, since Queue0 transfer requests are submitted to TC0 and Queue1 transfer requests are submitted to TC1). Therefore, the priority of unloading queues has a secondary affect compared to the priority of the transfers as they are executed by the EDMA3TC (dictated by the priority set using QUEPRI). EDMA3 Architecture 56 SPRUG34–November 2008 Submit Documentation Feedback

2.11.1 Architecture Details 2.11.1.1 Command Fragmentation www.ti.com EDMA3 Transfer Controller (EDMA3TC) The EDMA3 channel controller is the user-interface of the EDMA3 and the EDMA3 transfer controller (EDMA3TC) is the data movement engine of the EDMA3. The EDMA3CC submits transfer requests (TR) to the EDMA3TC and the EDMA3TC performs the data transfers dictated by the TR; thus, the EDMA3TC is a slave to the EDMA3CC. The TC read and write controllers in conjunction with the source and destination register sets are responsible for issuing optimally-sized reads and writes to the slave endpoints. An optimally-sized command is defined by the transfer controller default burst size (DBS), which is defined in Section 2.11.4. The EDMA3TC attempts to issue the largest possible command size as limited by the DBS value or the ACNT/BCNT value of the TR. EDMA3TC obeys the following rules: • The read/write controllers always issue commands less than or equal to the DBS value. • The first command of a 1D transfer is always issued so that subsequent commands align to the DBS value. Example 2-3 shows the command fragmentation for a DBS of 32 bytes. In summary, if the ACNT value is larger than the DBS value, then the EDMA3TC breaks the ACNT array into DBS-sized commands to the source/destination addresses. Each BCNT number of arrays are then serviced in succession. Example 2-3. Command Fragmentation (DBS = 32) The pseudo code: 1. ACNT = 8, BCNT = 8, SRCBIDX = 8, DSTBIDX = 10, SRCADDR = 64, DSTADDR = 191 Read Controller: This is optimized from a 2D-transfer to a 1D-transfer such that the read side is equivalent to ACNT = 64, BCNT = 1. Cmd0 = 32 byte, Cmd0 = 32 byte Write Controller: Since DSTBIDX != ACNT, it is not optimized. Cmd0 = 8 byte, Cmd1 = 8 byte, Cmd2 = 8 byte, Cmd3 = 8 byte, Cmd4 = 8 byte, Cmd5 = 8 byte, Cmd6 = 8 byte, Cmd7 = 8 byte. 2. ACNT=64, BCNT = 1, SRCADDR = 31, DSTADDR = 513 Read Controller: Read address is not aligned. Cmd0 = 1 byte, (now the SRCADDR is aligned to 32 for the next command) Cmd1 = 32 bytes Cmd2 = 31 bytes Write Controller: The write address is also not aligned. Cmd0 = 31 bytes, (now the DSTADDR is aligned to 32 for the next command) Cmd1 = 32 bytes Cmd2 = 1 byte For BCNT arrays of ACNT bytes (that is, a 2D transfer), if the ACNT value is less than or equal to the DBS value, then the TR may be optimized into a 1D-transfer in order to maximize efficiency, as per the rules in Table 2-15. The optimization takes place if the EDMA3TC recognizes that the 2D-transfer is organized as a single dimension (SAM/DAM = INCR), BIDX = ACNT, the ACNT value is a power of 2, and the BCNT value is less than or equal to 1023. Table 2-15 lists conditions in which the optimizations are performed. SPRUG34–November 2008 EDMA3 Architecture 57 Submit Documentation Feedback

www.ti.com Table 2-15. Read/Write Command Optimization Rules SAM/DAM = ACNT ≤ DBS ACNT is power of 2 BIDX = ACNT BCNT ≤ 1023 Increment Description Yes Yes Yes Yes Yes Optimized No x x x x Not Optimized x No x x x Not Optimized x x No x x Not Optimized x x x No x Not Optimized x x x x No Not Optimized TR pipelining refers to the ability of the source active set to get ahead of the destination active set. Essentially, the reads for a given TR may already be in progress while the writes of a previous TR may not have completed. The number of outstanding TRs is limited by the number of destination FIFO register entries. A single TR must be assured to target a single source peripheral endpoint. TR pipelining is useful for maintaining throughput on back-to-back small TRs. It eliminates the read overhead because reads start in the background of a previous TR writes. By default, reads are as issued as fast as possible. In some cases, the reads issued by the EDMA3TC could fill the available command buffering for a slave, delaying other (potentially higher priority) masters from successfully submitting commands to that slave. The rate at which read commands are issued by the EDMA3TC is controlled by the RDRATE register. The RDRATE register defines the number of cycles that the EDMA3TC read controller waits before issuing subsequent commands for a given TR, thus minimizing the chance of the EDMA3TC consuming all available slave resources. The RDRATE value should be set to a relatively small value if the transfer controller is targeted for high priority transfers and to a higher value if the transfer controller is targeted for low priority transfers. In contrast, the Write Interface does not have any performance turning knobs because writes always have an interval between commands as write commands are submitted along with the associated write data. Errors are generated if enabled under three conditions: • EDMA3TC detection of an error signaled by the source or destination address. • Attempt to read or write to an invalid address in the configuration memory map. • Detection of a constant addressing mode TR violating the constant addressing mode transfer rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes). Either or all error types may be disabled. If an error bit is set and enabled, the error interrupt for the concerned transfer controller is pulsed. 58 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

2.11.4 EDMA3TC Configuration www.ti.com EDMA3 Transfer Controller (EDMA3TC) The DMA program register set, DMA source active register set, and the destination FIFO register set are used to derive a brief history of TRs serviced through the transfer controller. Additionally, the EDMA3TC status register (TCSTAT) has dedicated bit fields to indicate the ongoing activity within different parts of the transfer controller: • The SRCACTV bit indicates whether the source active set is active. • The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given instance. • The PROGBUSY bit indicates whether a valid TR is present in the DMA program set. If the TRs are in progression, caution must be used and you must realize that there is a chance that the values read from the EDMA3TC status registers will be inconsistent since the EDMA3TC may change the values of these registers due to ongoing activities. It is recommended that you ensure no additional submission of TRs to the EDMA3TC in order to facilitate ease of debug. The destination FIFO register pointer is implemented as a circular buffer with the start pointer being DFSTRTPTR and a buffer depth of usually 2 or 4. The EDMA3TC maintains two important status details in TCSTAT that may be used during advanced debugging, if necessary. The DFSTRTPTR is a start pointer, that is, the index to the head of the destination FIFO register. The DSTACTV is a counter for the number of valid (occupied) entries. These registers may be used to get a brief history of transfers. Examples of some register field values and their interpretation: • DFSTRTPTR = 0 and DSTACTV = 0 implies that no TRs are stored in the destination FIFO register. • DFSTRTPTR = 1 and DSTACTV = 2h implies that two TRs are present. The first pending TR is read from the destination FIFO register entry 1 and the second pending TR is read from the destination FIFO register entry 2. • DFSTRTPTR = 3h and DSTACTV = 2h implies that two TRs are present. The first pending TR is read from the destination FIFO register entry 3 and the second pending TR is read from the destination FIFO register entry 0. Table 2-16 provides the configuration of the individual EDMA3 transfer controllers present on the device. Table 2-16. EDMA3 Transfer Controller Configurations Name TC0 TC1 FIFOSIZE 128 bytes 256 bytes BUSWIDTH 8 bytes 8 bytes DSTREGDEPTH 4 entries 4 entries DBS 16 bytes 32 bytes SPRUG34–November 2008 EDMA3 Architecture 59 Submit Documentation Feedback

controller to the time the transfer completion code is returned. The following steps list the sequence of EDMA3CC activity: 1. Event is asserted from an external source (peripheral or external interrupt). This also is similar for a manually-triggered, chained-triggered, or QDMA-triggered event. The event is latched into the ER.En/ERH.En (or CER.En/CERH.En, ESR.En /ESRH.En, QER.En) bit. 2. Once an event is prioritized and queued into the appropriate event queue, the SER.En\SERH.En (or QSER.En) bit is set to inform the event prioritization/processing logic to disregard this event since it is already in the queue. Alternatively, if the transfer controller and the event queue are empty, then the event bypasses the queue. 3. The EDMA3CC processing and the submission logic evaluates the appropriate PaRAM set and determines whether it is a non-null and non-dummy transfer request (TR). 4. The EDMA3CC clears the ER.En/ERH.En (or CER.En/CERH.En, ESR.En/ESRH.En, QER.En) bit and the SER.En/SERH.En bit as soon as it determines the TR is non-null. In the case of a null set, the SER.En/SERH.En bit remains set. It submits the non-null/non-dummy TR to the associated transfer controller. If the TR was programmed for early completion, the EDMA3CC immediately sets the interrupt pending register (IPR.I[TCC]/IPRH.I[TCC]-32). 5. If the TR was programmed for normal completion, the EDMA3CC sets the interrupt pending register (IPR.I[TCC]/IPRH.I[TCC]) when the EDMA3TC informs the EDMA3CC about completion of the transfer (returns transfer completion codes). 6. The EDMA3CC programs the associated EDMA3TCn's Program Register Set with the TR. 7. The TR is then passed to the Source Active set and the Dst FIFO Register Set, if both the register sets are available. 8. The Read Controller processes the TR by issuing read commands to the source slave endpoint. The Read Data lands in the Data FIFO of the EDMA3TCn. 9. As soon as sufficient data is available, the Write Controller begins processing the TR by issuing write commands to the destination slave endpoint. 10. This continues until the TR completes and the EDMA3TCn then signals completion status to the EDMA3CC. 60 EDMA3 Architecture SPRUG34–November 2008 Submit Documentation Feedback

etc. The following subsections detail various arbitration details whenever there might be occurrence of concurrent activity. Figure 2-14 shows the different places EDMA3 priorities come into play. The DMA event registers (ER and ERH) capture up to 64 events; likewise, the QDMA event register (QER) captures QDMA events for all QDMA channels; therefore, it is possible for events to occur simultaneously on the DMA/QDMA event inputs. For events arriving simultaneously, the event associated with the lowest channel number is prioritized for submission to the event queues (for DMA events, channel 0 has the highest priority and channel 63 has the lowest priority; similarly, for QDMA events, channel 0 has the highest priority and channel 7 has the lowest priority). This mechanism only sorts simultaneous events for submission to the event queues. If a DMA and QDMA event occurs simultaneously, the DMA event always has prioritization against the QDMA event for submission to the event queues. Figure 2-14. EDMA3 Prioritization SPRUG34–November 2008 EDMA3 Architecture 61 Submit Documentation Feedback

2.13.3 Dequeue Priority 2.13.4 System (Transfer Controller) Priority 2.14 EDMA3 Operating Frequency (Clock Control) 2.15 Reset Considerations EDMA3 Operating Frequency (Clock Control) www.ti.com If a DMA channel is associated with more than one trigger source (event trigger, manual trigger, and chain trigger), and if multiple events are set simultaneously for the same channel (ER.En = 1, ESR.En = 1, CER.En = 1), then the EDMA3CC always services these events in the following priority order: event trigger (via ER) is higher priority than chain trigger (via CER) and chain trigger is higher priority than manual trigger (via ESR). This implies that if for channel 0, both ER.E0 = 1 and CER.E0 = 1 at the same time, then the ER.E0 event is always queued before the CER.E0 event. The priority of the associated transfer request (TR) is further mitigated by which event queue is being used for event submission (dictated by DMAQNUM and QDMAQNUM). For submission of a TR to the transfer controller, events need to be dequeued from the event queues. Q0 has higher dequeue priority then Q1. In other words, if there are multiple events in both Q0 and Q1, then the transfer requests associated with events in Q0 will get submitted to TC0 prior to any transfer requests associated with events in Q1 getting submitted to TC1. Note: If there are outstanding events in both queues, then the channel controller will always submit requests to TC0, before submitting requests to TC1, even if TC0 is busy processing earlier transfer requests and TC1 is available. This can cause delays in submission of requests on Q1. Therefore, it is recommended to reserve the higher priority Q0/TC0 for submission of urgent, small, real-time sensitive transfers and allocate Q1/TC1 for longer, nonreal-time sensitive transfers. Each transfer controller has a programmed system priority (programmed via the QUEPRI) that is implemented when multiple masters in the system are vying for the same endpoint. The priority of the associated transfer request (TR) is further mitigated by system priority setting of the transfer controller. This priority is necessary when several masters are submitting requests to the main switched central resource (SCR), which in turn has to arbitrate the requests from these masters. Note: The default priority for both TC0 and TC1 is the same, 0 or highest priority relative to other masters (like EMAC, VPSS, etc.). It is recommended that this priority be changed based on system level considerations, such as real-time deadlines for all masters including the priority of the transfer controllers with respect to each other. (The priority configuration registers for other masters are either present within the memory-map of the master or implemented as a chip level register, see the device-specific data manual). The EDMA3 channel controller and transfer controller are clocked from PLL1. The EDMA3 system runs at SYSCLK3. A hardware reset resets the EDMA3 (EDMA3CC and EDMA3TC) and the EDMA3 configuration registers. The PaRAM memory contents are undefined after device reset and you should not rely on parameters to be reset to a known state. The PaRAM set must be initialized to a desired value before it is used. EDMA3 Architecture 62 SPRUG34–November 2008 Submit Documentation Feedback

during periods of low activity. The power management of the peripheral is controlled by the device Power and Sleep Controller (PSC). The PSC acts as a master controller for power management for all peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM357 DMSoC ARM Subsystem Reference Guide (SPRUG25). The EDMA3 controller can be idled on receiving a clock stop request from the PSC. The requests to EDMA3CC and EDMA3TC are separate. In general, you should verify that there are no pending activities in the EDMA3 controller before issuing a clock stop request via PSC. The EDMA3CC checks for the following conditions: • No pending DMA/QDMA events • No outstanding events in the event queues • Transfer request processing logic is not active • No completion requests outstanding (early or normal completion) • No configuration bus requests in progress The first four conditions are software readable by the channel controller status register (CCSTAT) in the EDMA3CC. Similarly, from the EDMA3TC perspective, you should check that there are no outstanding TRs that are getting processed and essentially the read/write controller is not busy processing a TR. The activity of EDMA3TC logic is read in TCSTAT for each EDMA3TC.. It is generally recommended to first disable the EDMA3CC and then the EDMA3TC(s) to put the EDMA3 controller in reduced-power modes. Additionally, when EDMA3 is involved in servicing a peripheral and it is required to power-down both the peripheral and the EDMA, the recommended sequence is to first disable the peripheral, then disable the DMA channel associated with the peripheral (clearing the EER/EERH bit for the channel), then disable the EDMA3CC, and finally disable the EDMA3TC(s). During debug when using the emulator, the CPU(s) may be halted on an execute packet boundary for single-stepping, benchmarking, profiling, or other debug purposes. During an emulation halt, the EDMA3 channel controller and transfer controller operations continue. Events continue to be latched and processed and transfer requests continue to be submitted and serviced. Since EDMA3 is involved in servicing multiple master and slave peripherals, it is not feasible to have an independent behavior of the EDMA3 for emulation halts. EDMA3 functionality would be coupled with the peripherals it is servicing, which might have different behavior during emulation halts. For example, if a ASP is halted during an emulation access (FREE = 0 and SOFT = 0 or 1 in ASP registers), the ASP stops generating the ASP receive or transmit events (REVT or XEVT) to the EDMA. From the point of view of the ASP, the EDMA3 is suspended, but other peripherals (for example, a timer) still assert events and will be serviced by the EDMA. SPRUG34–November 2008 EDMA3 Architecture 63 Submit Documentation Feedback

The EDMA3 channel controller performs a variety of transfers depending on the parameter configuration. The following sections provides a description and PaRAM configuration for some typical use case scenarios. Topic .................................................................................................. Page 3.1 Block Move Example ................................................................. 66 3.2 Subframe Extraction Example .................................................... 68 3.3 Data Sorting Example................................................................ 70 3.4 Peripheral Servicing Example..................................................... 72 SPRUG34–November 2008 EDMA3 Transfer Examples 65 Submit Documentation Feedback

253 254 255 256 249 250 251 252 244 ... ... 245 246 247 248 ... ... 17 18 19 20 21 12 10 9 11 13 14 15 16 4 3 1 2 7 6 5 8 8000 0000h 244 252 250 249 ... 251 ... 245 246 247 253 254 255 248 256 1180 0000h 12 20 11 10 9 17 18 19 2 1 3 15 14 13 21 ... ... 5 4 7 6 16 8 Block Move Example www.ti.com The most basic transfer performed by the EDMA3 is a block move. During device operation it is often necessary to transfer a block of data from one location to another, usually between on-chip and off-chip memory. In this example, a section of data is to be copied from external memory to internal L2 SRAM. A data block of 256 words residing at address 8000 0000h (external memory ) needs to be transferred to internal address 1180 0000h (L2), as shown in Figure 3-1. Figure 3-2 shows the parameters for this transfer. The source address for the transfer is set to the start of the data block in external memory, and the destination address is set to the start of the data block in L2. If the data block is less than 64K bytes, the PaRAM configuration in Figure 3-2 holds true with the synchronization type set to A-synchronized and indexes cleared to 0. If the amount of data is greater than 64K bytes, BCNT and the B-indexes need to be set appropriately with the synchronization type set to AB-synchronized. The STATIC bit in OPT is set to prevent linking. This transfer example may also be set up using QDMA. For successive transfer submissions, of a similar nature, the number of cycles used to submit the transfer are fewer depending on the number of changing transfer parameters. You may program the QDMA trigger word to be the highest numbered offset in the PaRAM set that undergoes change. Figure 3-1. Block Move Example 66 EDMA3 Transfer Examples SPRUG34–November 2008 Submit Documentation Feedback

Figure 3-2. Block Move Example PaRAM Configuration (a) EDMA Parameters Parameter Contents Parameter 0010 0008h Channel Options Parameter (OPT) 8000 0000h Channel Source Address (SRC) 0001h 0100h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0000h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0000h FFFFh BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 1 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM SPRUG34–November 2008 EDMA3 Transfer Examples 67 Submit Documentation Feedback

0_10 0_1 0_2 0_3 0_4 0_5 0_6 0_7 0_8 0_9 0_A 0_B 0_C 0_D 0_E 0_F 1_10 1_1 1_2 1_3 1_4 1_5 1_6 1_7 1_8 1_9 1_A 1_B 1_C 1_D 1_E 1_F 2_10 2_1 2_2 2_3 2_4 2_5 2_6 2_7 2_8 2_9 2_A 2_B 2_C 2_D 2_E 2_F 3_10 3_1 3_2 3_3 3_4 3_5 3_6 3_7 3_8 3_9 3_A 3_B 3_C 3_D 3_E 3_F 4_10 4_1 4_2 4_3 4_4 4_5 4_6 4_7 4_8 4_9 4_A 4_B 4_C 4_D 4_E 4_F 5_10 5_1 5_2 5_3 5_4 5_5 5_6 5_7 5_8 5_9 5_A 5_B 5_C 5_D 5_E 5_F 6_10 6_1 6_2 6_3 6_4 6_5 6_6 6_7 6_8 6_9 6_A 6_B 6_C 6_D 6_E 6_F 7_10 7_1 7_2 7_3 7_4 7_5 7_6 7_7 7_8 7_9 7_A 7_B 7_C 7_D 7_E 7_F 8_10 8_1 8_2 8_3 8_4 8_5 8_6 8_7 8_8 8_9 8_A 8_B 8_C 8_D 8_E 8_F 9_10 9_1 9_2 9_3 9_4 9_5 9_6 9_7 9_8 9_9 9_A 9_B 9_C 9_D 9_E 9_F A_10 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_A A_B A_C A_D A_E A_F B_10 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_9 B_A B_B B_C B_D B_E B_F 0 479 0 6 3 9 8002 5580h 8000 0788h 8000 0000h 1180 0000h Subframe Extraction Example www.ti.com The EDMA3 can efficiently extract a small frame of data from a larger frame of data. By performing a 2D-to-1D transfer, the EDMA3 retrieves a portion of data for the CPU to process. In this example, a 640 × 480-pixel frame of video data is stored in external memory, DDR2. Each pixel is represented by a 16-bit halfword. The CPU extracts a 16 × 12-pixel subframe of the image for processing. To facilitate more efficient processing time by the CPU, the EDMA3 places the subframe in internal L2 SRAM. Figure 3-3 shows the transfer of a subframe from external memory to L2. Figure 3-4 shows the parameters for this transfer. The same PaRAM set options are used for QDMA channels, as well as DMA channels. The STATIC bit in OPT is set to 1 to prevent linking. For successive transfers, only changed parameters need to be programmed before triggering the channel. Figure 3-3. Subframe Extraction Example 68 EDMA3 Transfer Examples SPRUG34–November 2008 Submit Documentation Feedback

Figure 3-4. Subframe Extraction Example PaRAM Configuration (a) EDMA Parameters Parameter Contents Parameter 0010 000Ch Channel Options Parameter (OPT) 8000 0788h Channel Source Address (SRC) 000Ch 0020h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0020h 0500h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0000h FFFFh BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 1 1 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM SPRUG34–November 2008 EDMA3 Transfer Examples 69 Submit Documentation Feedback

A_1022 A_1023 A_1024 B_1022 B_1023 B_1024 D_1023 C_1023 D_1022 C_1022 D_1024 C_1024 ... ... ... ... ... ... ... ... D_2 D_1 D_3 C_2 B_2 A_2 C_1 B_1 A_1 B_3 C_3 A_3 8000 0000h D_1 D_2 D_1023 ... D_3 ... D_1022 D_1024 B_1 C_1 A_1 B_2 C_2 A_2 B_1023 C_1023 A_1023 ... ... ... B_3 C_3 A_3 ... ... ... B_1022 C_1022 A_1022 B_1024 C_1024 A_1024 1180 0000h Data Sorting Example www.ti.com Many applications require the use of multiple data arrays; it is often desirable to have the arrays arranged such that the first elements of each array are adjacent, the second elements are adjacent, and so on. Often this is not how the data is presented to the device. Either data is transferred via a peripheral with the data arrays arriving one after the other or the arrays are located in memory with each array occupying a portion of contiguous memory spaces. For these instances, the EDMA3 can reorganize the data into the desired format. Figure 3-5 shows the data sorting. In order to determine the parameter entry values, the following need to be considered: • ACNT – Program this to be the size in bytes of an element. • BCNT – Program this to be the number of elements in a frame. • CCNT – Program this to be the number of frames. • SRCBIDX – Program this to be the size of the element or ACNT. • DSTBIDX = CCNT × ACNT • SRCCDX = ACNT × BCNT • DSTCIDX = ACNT The synchronization type needs to be AB-synchronized and the STATIC bit is 0 to allow updates to the parameter set. It is advised to use normal DMA channels for sorting. It is not possible to sort this with a single trigger event. Instead, the channel can be programmed to be chained to itself. After BCNT elements get sorted, intermediate chaining could be used to trigger the channel again causing the transfer of the next BCNT elements and so on. Figure 3-6 shows the parameter set programming for this transfer, assuming channel 0 and an element size of 4 bytes. Figure 3-5. Data Sorting Example EDMA3 Transfer Examples 70 SPRUG34–November 2008 Submit Documentation Feedback

Figure 3-6. Data Sorting Example PaRAM Configuration (a) EDMA Parameters Parameter Contents Parameter 0090 0004h Channel Options Parameter (OPT) 8000 0000h Channel Source Address (SRC) 0400h 0004h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0010h 0001h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0000h FFFFh BCNT Reload (BCNTRLD) Link Address (LINK) 0001h 1000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0004h Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 1 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 1 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM SPRUG34–November 2008 EDMA3 Transfer Examples 71 Submit Documentation Feedback

3.4.1 Nonbursting Peripherals 244 252 250 249 ... 251 ... 245 246 247 253 254 255 248 256 1180 0000h 12 20 11 10 9 17 18 19 2 1 3 15 14 13 21 ... ... 5 4 7 6 16 8 RSR RBR DRR : 3 : 2 : 1 REVT 01E0 2000h Peripheral Servicing Example www.ti.com The EDMA3 channel controller also services peripherals in the background of CPU operation, without requiring any CPU intervention. Through proper initialization of the DMA channels, they can be configured to continuously service on-chip and off-chip peripherals throughout the device operation. Each event available to the EDMA3 has its own dedicated channel, and all channels operate simultaneously. The only requirements are to use the proper channel for a particular transfer and to enable the channel event in the event enable register (EER). When programming a DMA channel to service a peripheral, it is necessary to know how data is to be presented to the ARM. Data is always provided with some kind of synchronization event as either one element per event (nonbursting) or multiple elements per event (bursting). Nonbursting peripherals include the on-chip audio serial port (ASP) and many external devices, such as codecs. Regardless of the peripheral, the DMA channel configuration is the same. The ASP transmit and receive data streams are treated independently by the EDMA3. The transmit and receive data streams can have completely different counts, data sizes, and formats. Figure 3-7 shows servicing incoming ASP data. To transfer the incoming data stream to its proper location in L2 memory, the DMA channel must be set up for a 1D-to-1D transfer with A-synchronization. Since an event (REVT) is generated for every word as it arrives, it is necessary to have the EDMA3 issue the transfer request for each element individually. Figure 3-8 shows the parameters for this transfer. The source address of the DMA channel is set to the data receive register (DRR) address for ASP, and the destination address is set to the start of the data block in L2. Since the address of DRR is fixed, the source B index is cleared to 0 (no modification) and the destination B index is set to 01b (increment). Based on the premise that serial data is typically a high priority, the DMA channel should be programmed to be on queue 0. Figure 3-7. Servicing Incoming ASP Data Example EDMA3 Transfer Examples 72 SPRUG34–November 2008 Submit Documentation Feedback

Figure 3-8. Servicing Incoming ASP Data Example PaRAM (a) EDMA Parameters Parameter Contents Parameter 0010 0000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0100h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0001h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0000h FFFFh BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0004h Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM SPRUG34–November 2008 EDMA3 Transfer Examples 73 Submit Documentation Feedback

www.ti.com Higher bandwidth applications require that multiple data elements be presented to the CPU for every synchronization event. This frame of data can either be from multiple sources that are working simultaneously or from a single high-throughput peripheral that streams data to/from the CPU. In this example, a port is receiving a video frame from a camera and presenting it to the CPU one array at a time. The video image is 640 × 480 pixels, with each pixel represented by a 16-bit element. The image is to be stored in external memory. Figure 3-9 shows this example. To transfer data from an external peripheral to an external buffer one array at a time based on EVTn , channel n must be configured. Due to the nature of the data (a video frame made up of arrays of pixels) the destination is essentially a 2D entity. Figure 3-10 shows the parameters to service the incoming data with a 1D-to-2D transfer using AB-synchronization. The source address is set to the location of the video framer peripheral, and the destination address is set to the start of the data buffer. Since the input address is static, the SRCBIDX is 0 (no modification to the source address). The destination is made up of arrays of contiguous, linear elements; therefore, the DSTBIDX is set to pixel size, 2 bytes. ANCT is equal to the pixel size, 2 bytes. BCNT is set to the number of pixels in an array, 640. CCNT is equal to the total number of arrays in the block, 480. SRCCIDX is 0 since the source address undergoes no increment. The DSTCIDX is equal to the difference between the starting addresses of each array. Since a pixel is 16 bits (2 bytes), DSTCIDX is equal to 640 × 2. Figure 3-9. Servicing Peripheral Burst Example EDMA3 Transfer Examples 74 SPRUG34–November 2008 Submit Documentation Feedback

Figure 3-10. Servicing Peripheral Burst Example PaRAM (a) EDMA Parameters Parameter Contents Parameter 0010 0004h Channel Options Parameter (OPT) Channel Source Address Channel Source Address (SRC) 0280h 0002h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 8000 0000h Channel Destination Address (DST) 0002h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0000h FFFFh BCNT Reload (BCNTRLD) Link Address (LINK) 0500h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 01E0h Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 1 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM SPRUG34–November 2008 EDMA3 Transfer Examples 75 Submit Documentation Feedback

... B1i B2i B3i B4i B5i ... B8i B7i ..B5..A5..B4..A4..B3..A3..B2..A2..B1..A1 01E0 2000h 1180 0080h B6o A6o B2o B1o B9o B10o A9i A10i B5o B4o B3o B11o B12o B13o ... A11i A12i A13i ... A1o A2o A3o A4o A5o B7o B8o ... ... A8o A7o 1180 1000h 1180 1080h 01E0 2004h DXR A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 XSR XEVT Peripheral Servicing Example www.ti.com Configuring a DMA channel to receive a single frame of data is useful, and is applicable to some systems. A majority of the time, however, data is going to be continuously transmitted and received throughout the entire operation of the CPU. In this case, it is necessary to implement some form of linking such that the DMA channels continuously reload the necessary parameter sets. In this example, the ASP is configured to transmit and receive data on a array. To simplify the example, only two channels are active for both transmit and receive data streams. Each channel receives packets of 128 elements. The packets are transferred from the serial port to L2 memory and from L2 memory to the serial port, as shown in Figure 3-11. The ASP generates REVT for every element received and generates XEVT for every element transmitted. To service the data streams, DMA channels 12 and 13 must be set up for 1D-to-1D transfers with A-synchronization. Figure 3-12 shows the parameters for the parameter entries for the channel for these transfers. In order to service the ASP continuously throughout CPU operation, the channels must be linked to a duplicate PaRAM set in the PaRAM. After all frames have been transferred, the DMA channels reload and continue. Figure 3-13 shows the reload parameters for the channel. DMA channel 3 services the incoming data stream of the ASP. The source address is set to that of the data receiver register (DRR), and the destination address is set to the first element of the data block. Since there are two data channels being serviced, A and B, they are to be located separately within the L2 SRAM. In order to facilitate continuous operation, a copy of the PaRAM set for the channel is placed in PaRAM set 64. The LINK option is set and the link address is provided in the PaRAM set. Upon exhausting the channel 3 parameter set, the parameters located at the link address are loaded into the channel 3 parameter set and operation continues. This function continues throughout device operation until halted by the CPU. DMA channel 2 services the outgoing data stream of the ASP. In this case the destination address needs no update, hence, the parameter set changes accordingly. Linking is also used to allow continuous operation by the DMA channel, with duplicate PaRAM set entries at PaRAM set 65. Figure 3-11. Servicing Continuous ASP Data Example EDMA3 Transfer Examples 76 SPRUG34–November 2008 Submit Documentation Feedback

Figure 3-12. Servicing Continuous ASP Data Example PaRAM (a) EDMA Parameters for Receive Channel (PaRAM Set 3) being Linked to PaRAM Set 64 Parameter Contents Parameter 0010 0000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0001h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4800h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h FFFFh Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content for Receive Channel (PaRAM Set 3) 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM (c) EDMA Parameters for Transmit Channel (PaRAM Set 2) being Linked to PaRAM Set 65 Parameter Contents Parameter 0010 1000h Channel Options Parameter (OPT) 1180 1000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 01E0 2004h Channel Destination Address (DST) 0000h 0001h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4820h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h FFFFh Reserved Count for 3rd Dimension (CCNT) (d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 2) 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0001 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM SPRUG34–November 2008 EDMA3 Transfer Examples 77 Submit Documentation Feedback

www.ti.com Figure 3-13. Servicing Continuous ASP Data Example Reload PaRAM (a) EDMA Reload Parameters (PaRAM Set 64) for Receive Channel Parameter Contents Parameter 0010 0000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0001h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4800h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h FFFFh Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content for Receive Channel (PaRAM Set 64) 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM (c) EDMA Reload Parameters (PaRAM Set 65) for Transmit Channel Parameter Contents Parameter 0010 1000h Channel Options Parameter (OPT) 1180 1000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 01E0 2004h Channel Destination Address (DST) 0000h 0001h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4820h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h FFFFh Reserved Count for 3rd Dimension (CCNT) (d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 65) 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0001 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM EDMA3 Transfer Examples 78 SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com Peripheral Servicing Example Although the previous configuration allows the EDMA3 to service a peripheral continuously, it presents a number of restrictions to the CPU. Since the input and output buffers are continuously being filled/emptied, the CPU must match the pace of the EDMA3 very closely in order to process the data. The EDMA3 receive data must always be placed in memory before the CPU accesses it, and the CPU must provide the output data before the EDMA3 transfers it. Though not impossible, this is an unnecessary challenge. It is particularly difficult in a 2-level cache scheme. Ping-pong buffering is a simple technique that allows the CPU activity to be distanced from the EDMA3 activity. This means that there are multiple (usually two) sets of data buffers for all incoming and outgoing data streams. While the EDMA3 transfers the data into and out of the ping buffers, the CPU manipulates the data in the pong buffers. When both CPU and EDMA3 activity completes, they switch. The EDMA3 then writes over the old input data and transfers the new output data. Figure 3-14 shows the ping-pong scheme for this example. To change the continuous operation example, such that a ping-pong buffering scheme is used, the DMA channels need only a moderate change. Instead of one parameter set, there are two; one for transferring data to/from the ping buffers and one for transferring data to/from the pong buffers. As soon as one transfer completes, the channel loads the PaRAM set for the other and the data transfers continue. Figure 3-15 shows the DMA channel configuration required. Each channel has two parameter sets, ping and pong. The DMA channel is initially loaded with the ping parameters (Figure 3-15). The link address for the ping set is set to the PaRAM offset of the pong parameter set (Figure 3-16). The link address for the pong set is set to the PaRAM offset of the ping parameter set (Figure 3-17). The channel options, count values, and index values are all identical between the ping and pong parameters for each channel. The only differences are the link address provided and the address of the data buffer. In order to utilize the ping-pong buffering technique, the system must signal the CPU when to begin to access the new data set. After the CPU finishes processing an input buffer (ping), it waits for the EDMA3 to complete before switching to the alternate (pong) buffer. In this example, both channels provide their channel numbers as their report word and set the TCINTEN bit to 1 to generate an interrupt after completion. When channel 3 fills an input buffer, the E3 bit in the interrupt pending register (IPR) is set to 1; when channel 2 empties an output buffer, the E2 bit in IPR is set to 1. The CPU must manually clear these bits. With the channel parameters set, the CPU polls IPR to determine when to switch. The EDMA3 and CPU could alternatively be configured such that the channel completion interrupts the CPU. By doing this, the CPU could service a background task while waiting for the EDMA3 to complete. SPRUG34–November 2008 EDMA3 Transfer Examples 79 Submit Documentation Feedback

... A11i A12i A13i ... A1o A2o A3o A4o A5o B7o B8o ... ... A8o A7o 1180 1800h 1180 1880h A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 Pong DRR RBR RSR A11i B3o B11o B9o B10o B1o A9i B2o A10i B12o B13o ... A13i B5o B4o A12i B6o ... B11i B3i A3o A1o A2o B9i B1i B10i B2i A5o A4o A6o B13i B5i B12i B4i ... B6i ... B8o B7o ... A8o A7o ... B7i B8i A3i A11i A9i A1i A10i A2i A5i A13i A12i A4i ... A6i Ping ... A7i A8i REVT 01E0 2000h DXR XEVT XSR 01E0 2004h 1180 0000h 1180 0080h 1180 1000h 1180 1080h Peripheral Servicing Example www.ti.com Figure 3-14. Ping-Pong Buffering for ASP Data Example Figure 3-15. Ping-Pong Buffering for ASP Example PaRAM (a) EDMA Parameters for Channel 3 (Using PaRAM Set 3 Linked to Pong Set 64) Parameter Contents Parameter 0010 3000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0001h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4800h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) (b) Channel Options Parameter (OPT) Content for Channel 3 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0011 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM EDMA3 Transfer Examples 80 SPRUG34–November 2008 Submit Documentation Feedback

(c) EDMA Parameters for Channel 2 (Using PaRAM Set 2 Linked to Pong Set 65) Parameter Contents Parameter 0010 2000h Channel Options Parameter (OPT) 1180 1000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 01E0 2004h Channel Destination Address (DST) 0000h 0001h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4840h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) (d) Channel Options Parameter (OPT) Content for Channel 2 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0010 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM Figure 3-16. Ping-Pong Buffering for ASP Example Pong PaRAM (a) EDMA Pong Parameters for Channel 3 at Set 64 Linked to Set 65 Parameter Contents Parameter 0010 D000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0800h Channel Destination Address (DST) 0001h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4820h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) (b) EDMA Pong Parameters for Channel 2 at Set 66 Linked to Set 67 Parameter Contents Parameter 0010 C000h Channel Options Parameter (OPT) 1180 1800h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 01E0 2004h Channel Destination Address (DST) 0000h 0001h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4860h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) SPRUG34–November 2008 EDMA3 Transfer Examples 81 Submit Documentation Feedback

3.4.5.1 Servicing Input/Output FIFOs with a Single Event Peripheral Servicing Example www.ti.com Figure 3-17. Ping-Pong Buffering for ASP Example Ping PaRAM (a) EDMA Ping Parameters for Channel 3 at Set 65 Linked to Set 64 Parameter Contents Parameter 0010 D000h Channel Options Parameter (OPT) 01E0 2000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 1180 0000h Channel Destination Address (DST) 0001h 0000h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4800h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) (b) EDMA Ping Parameters for Channel 2 at Set 67 Linked to Set 66 Parameter Contents Parameter 0010 C000h Channel Options Parameter (OPT) 1180 1000h Channel Source Address (SRC) 0080h 0001h Count for 2nd Dimension (BCNT) Count for 1st Dimension (ACNT) 01E0 2004h Channel Destination Address (DST) 0000h 0001h Destination BCNT Index (DSTBIDX) Source BCNT Index (SRCBIDX) 0080h 4840h BCNT Reload (BCNTRLD) Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) The following examples explain the intermediate transfer complete chaining function. Many systems require the use of a pair of external FIFOs that must be serviced at the same rate. One FIFO buffers data input, and the other buffers data output. The EDMA3 channels that service these FIFOs can be set up for AB-synchronized transfers. While each FIFO is serviced with a different set of parameters, both can be signaled from a single event. For example, an external interrupt pin can be tied to the status flags of one of the FIFOs. When this event arrives, the EDMA3 needs to perform servicing for both the input and output streams. Without the intermediate transfer complete chaining feature this would require two events, and thus two external interrupt pins. The intermediate transfer complete chaining feature allows the use of a single external event (for example, a GPIO event). Figure 3-18 shows the EDMA3 setup and illustration for this example. A GPIO event (in this case, GPINT0) triggers an array transfer. Upon completion of each intermediate array transfer of channel 32, intermediate transfer complete chaining sets the E63 bit (specified by TCC of 63) in the chained event register high (CERH) and provides a synchronization event to channel 63. Upon completion of the last array transfer of channel 32, transfer complete chaining—not intermediate transfer complete chaining—sets the E63 bit in CERH (specified by TCCMODE:TCC) and provides a synchronization event to channel 63. The completion of channel 63 sets the I63 bit (specified by TCCMODE:TCC) in the interrupt pending register high (IPRH), which can generate an interrupt to the CPU, if the I63 bit in the interrupt enable register high (IERH) is set to 1. 82 EDMA3 Transfer Examples SPRUG34–November 2008 Submit Documentation Feedback

Intermediate transfer complete(A) Channel 63, array 0 Event 32 Hardwired event (tied to GPINT0, event 32) Chained event (event 63) Channel 32, array 1 Event 32 Channel 63, array 1 Intermediate transfer complete(A) Channel 63, array 3 Channel 32, array 3 Channel 32, array 2 Event 32 Event 32 Channel 63, array 2 Transfer complete(B) Intermediate transfer complete(A) (last array) Transfer complete sets IPRH.I63 = 1 If IPRH.I63 = 1, EDMACC_INT* sent Notes: (A) Intermediate transfer complete chaining synchronizes event 63 ITCCHEN = 1, TCC = 011 1111b and sets CERH.E63 = 1 (B) Transfer complete chaining synchronizes event 63 TCCHEN = 1, TCC = 011 1111b and sets CERH.E63 = 1 to CPU Enable transfer complete chaining: OPT.TCCHEN = 1 OPT.TCC = 011 1111b Enable intermediate transfer complete chaining: OPT.ITCCHEN = 1 OPT.TCC = 011 1111b Disable intermediate transfer OPT.TCINTEN = 1 OPT.ITCCHEN = 0 complete chaining: OPT.TCC = 011 1111b completion interrupt: Enable transfer Setup Channel 32 parameters for chaining for chaining Channel 63 parameters Enable channel 32 EERH.E32 = 1 Event enable register (EER) 3.4.5.2 Breaking Up Large Transfers with Intermediate Chaining www.ti.com Peripheral Servicing Example Figure 3-18. Intermediate Transfer Completion Chaining Example Another feature of intermediate transfer chaining (ITCCHEN) is for breaking up large transfers. A large transfer may lock out other transfers of the same priority level for the duration of the transfer. For example, a large transfer on queue 0 from the internal memory to the external memory using the EMIF may starve other EDMA3 transfers on the same queue. In addition, this large high-priority transfer may prevent the EMIF for a long duration to service other lower priority transfers. When a large transfer is considered to be high priority, it should be split into multiple smaller transfers. Figure 3-19 shows the EDMA3 setup and illustration of an example single large block transfer. SPRUG34–November 2008 EDMA3 Transfer Examples 83 Submit Documentation Feedback

Event 25 (CPU writes 1 to ESR.E25) ACNT = 16384 BCNT = 1 CCNT = 1 1D transfer of 16 KByte elements OPT.ITCINTEN = 0 OPT.TCC = Don’t care EDMA3 channel 25 setup 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K Event 25 (CPU writes 1 to ESR.E25) ITCCHEN=1, TCC=25 causes channel 25 to be synchronized again Time gaps allow other transfers on the same priority level to be performed ACNT = 1024 BCNT = 16 CCNT = 1 OPT.SYNCDIM = A SYNC OPT.ITCCHEN = 1 OPT.TCINTEN = 1 EDMA channel 25 setup OPT.TCC = 25 Peripheral Servicing Example www.ti.com Figure 3-19. Single Large Block Transfer Example The intermediate transfer chaining enable (ITCCHEN) provides a method to break up a large transfer into smaller transfers. For example, to move a single large block of memory (16K bytes), the EDMA3 performs an A-synchronized transfer. The element count is set to a reasonable value, where reasonable derives from the amount of time it would take to move this smaller amount of data. Assume 1 Kbyte is a reasonable small transfer in this example. The EDMA3 is set up to transfer 16 arrays of 1 Kbyte elements, for a total of 16K byte elements. The TCC field in the channel options parameter (OPT) is set to the same value as the channel number and ITCCHEN are set. In this example, DMA channel 25 is used and TCC is also set to 25. The TCINTEN may also be set to trigger interrupt 25 when the last 1 Kbyte array is transferred. The CPU starts the EDMA3 transfer by writing to the appropriate bit of the event set register (ESR.E25). The EDMA3 transfers the first 1 Kbyte array. Upon completion of the first array, intermediate transfer complete code chaining generates a synchronization event to channel 25, a value specified by the TCC field. This intermediate transfer completion chaining event causes DMA channel 25 to transfer the next 1 Kbyte array. This process continues until the transfer parameters are exhausted, at which point the EDMA3 has completed the 16K byte transfer. This method breaks up a large transfer into smaller packets, thus providing natural time slices in the transfer such that other events may be processed. Figure 3-20 shows the EDMA3 setup and illustration of the broken up smaller packet transfers. Figure 3-20. Smaller Packet Data Transfers Example 84 EDMA3 Transfer Examples SPRUG34–November 2008 Submit Documentation Feedback

Topic .................................................................................................. Page 4.1 Register Memory Maps .............................................................. 86 4.2 Parameter RAM (PaRAM) Entries ................................................ 86 4.3 EDMA3 Channel Controller Control Registers............................... 93 4.4 EDMA3 Transfer Controller Control Registers............................. 140 SPRUG34–November 2008 Registers 85 Submit Documentation Feedback

4.2 Parameter RAM (PaRAM) Entries Register Memory Maps www.ti.com See your device-specific data manual for the register memory maps. Table 4-1 lists the parameter RAM (PaRAM) entries for the EDMA3 channel controller (EDMA3CC). See the device-specific data manual for the memory address of these registers. Table 4-1. EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries Offset Acronym Parameter Section 0h OPT Channel Options Section 4.2.1 4h SRC Channel Source Address Section 4.2.2 8h A_B_CNT A Count/B Count Section 4.2.3 Ch DST Channel Destination Address Section 4.2.4 10h SRC_DST_BIDX Source B Index/Destination B Index Section 4.2.5 14h LINK_BCNTRLD Link Address/B Count Reload Section 4.2.6 18h SRC_DST_CIDX Source C Index/Destination C Index Section 4.2.7 1Ch CCNT C Count Section 4.2.8 Registers 86 SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com Parameter RAM (PaRAM) Entries The channel options parameter (OPT) is shown in Figure 4-1 and described in Table 4-2. Figure 4-1. Channel Options Parameter (OPT) 31 28 27 24 23 22 21 20 19 18 17 16 Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 15 12 11 10 8 7 4 3 2 1 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-2. Channel Options Parameters (OPT) Field Descriptions Bit Field Value Description 31-28 Reserved 0 Reserved 27-24 PRIVID 0-Fh Privilege identification for the external host/CPU/DMA that programmed this PaRAM set. This value is set with the EDMA3 master’s privilege identification value when any part of the PaRAM set is written. 23 ITCCHEN Intermediate transfer completion chaining enable. 0 Intermediate transfer complete chaining is disabled. 1 Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified. 22 TCCHEN Transfer complete chaining enable. 0 Transfer complete chaining is disabled. 1 Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified. 21 ITCINTEN Intermediate transfer completion interrupt enable. 0 Intermediate transfer complete interrupt is disabled. 1 Intermediate transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER[TCC]/IERH[TCC] bit must be set to 1. 20 TCINTEN Transfer complete interrupt enable. 0 Transfer complete interrupt is disabled. 1 Transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER[TCC]/IERH[TCC] bit must be set to 1. 19 Reserved 0 Reserved. Always write 0 to this bit. 18 Reserved 0 Reserved 17-12 TCC 0-3Fh Transfer complete code. This 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. SPRUG34–November 2008 Registers 87 Submit Documentation Feedback

www.ti.com Table 4-2. Channel Options Parameters (OPT) Field Descriptions (continued) Bit Field Value Description 11 TCCMODE Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. 0 Normal completion: A transfer is considered completed after the data has been transferred. 1 Early completion: A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered. 10-8 FWID 0-7h FIFO Width. Applies if either SAM or DAM is set to constant addressing mode. 0 FIFO width is 8-bit. 1h FIFO width is 16-bit. 2h FIFO width is 32-bit. 3h FIFO width is 64-bit. 4h FIFO width is 128-bit. 5h FIFO width is 256-bit. 6h-7h Reserved 7-4 Reserved 0 Reserved 3 STATIC Static PaRAM set. 0 PaRAM set is not static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers. 1 PaRAM set is static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers. 2 SYNCDIM Transfer synchronization dimension. 0 A-synchronized. Each event triggers the transfer of a single array of ACNT bytes. 1 AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes. 1 DAM Destination address mode. 0 Increment (INCR) mode. Destination addressing within an array increments. Destination is not a FIFO. 1 Constant addressing (CONST) mode. Destination addressing within an array wraps around upon reaching FIFO width. 0 SAM Source address mode. 0 Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO. 1 Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching FIFO width. 88 Registers SPRUG34–November 2008 Submit Documentation Feedback

4.2.3 A Count/B Count Parameter (A_B_CNT) www.ti.com Parameter RAM (PaRAM) Entries The channel source address parameter (SRC) specifies the starting byte address of the source. The SRC is shown in Figure 4-2 and described in Table 4-3. Figure 4-2. Channel Source Address Parameter (SRC) 31 16 SRC R/W-x 15 0 SRC R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 4-3. Channel Source Address Parameter (SRC) Field Descriptions Bit Field Value Description 31-0 SRC 0-FFFF FFFFh Source address. Specifies the starting byte address of the source. The A count/B count parameter (A_B_CNT) specifies the number of bytes within the 1st dimension of a transfer and the number of arrays of length ACNT. The A_B_CNT is shown in Figure 4-3 and described in Table 4-4. Figure 4-3. A Count/B Count Parameter (A_B_CNT) 31 16 BCNT R/W-x 15 0 ACNT R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 4-4. A Count/B Count Parameter (A_B_CNT) Field Descriptions Bit Field Value Description 31-16 BCNT 0-FFFFh B count. Unsigned value specifying the number of arrays in a frame, where an array is ACNT bytes. Valid values range from 1 to 65 535. 15-0 ACNT 0-FFFFh A count for 1st Dimension. Unsigned value specifying the number of contiguous bytes within an array (first dimension of the transfer). Valid values range from 1 to 65 535. SPRUG34–November 2008 Registers 89 Submit Documentation Feedback

4.2.5 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Parameter RAM (PaRAM) Entries www.ti.com The channel destination address parameter (DST) specifies the starting byte address of the source. The DST is shown in Figure 4-4 and described in Table 4-5. Figure 4-4. Channel Destination Address Parameter (DST) 31 16 DST R/W-x 15 0 DST R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 4-5. Channel Destination Address Parameter (DST) Field Descriptions Bit Field Value Description 31-0 DST 0-FFFF FFFFh Destination address. Specifies the starting byte address of the destination where data is transferred. The source B index/destination B index parameter (SRC_DST_BIDX) specifies the value (2s complement) used for source address modification between each array in the 2nd dimension and the value (2s complement) used for destination address modification between each array in the 2nd dimension. The SRC_DST_BIDX is shown in Figure 4-5 and described in Table 4-6. Figure 4-5. Source B Index/Destination B Index Parameter (SRC_DST_BIDX) 31 16 DSTBIDX R/W-x 15 0 SRCBIDX R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 4-6. Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions Bit Field Value Description 31-16 DSTBIDX 0-FFFFh Destination B index. Signed value specifying the byte address offset between destination arrays within a frame (2nd dimension). Valid values range from –32 768 and 32 767. 15-0 SRCBIDX 0-FFFFh Source B index. Signed value specifying the byte address offset between source arrays within a frame (2nd dimension). Valid values range from –32 768 and 32 767. 90 Registers SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com Parameter RAM (PaRAM) Entries The link address/B count reload parameter (LINK_BCNTRLD) specifies the byte address offset in the PaRAM from which the EDMA3CC loads/reloads the next PaRAM set during linking and the value used to reload the BCNT field in the A count/B count parameter (A_B_CNT) once the last array in the 2nd dimension is transferred. The LINK_BCNTRLD is shown in Figure 4-6 and described in Table 4-7. Figure 4-6. Link Address/B Count Reload Parameter (LINK_BCNTRLD) 31 16 BCNTRLD R/W-x 15 0 LINK R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 4-7. Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions Bit Field Value Description 31-16 BCNTRLD 0-FFFFh B count reload. The count value used to reload BCNT in the A count/B count parameter (A_B_CNT) when BCNT decrements to 0 (TR submitted for the last array in 2nd dimension). Only relevant in A-synchronized transfers. 15-0 LINK 0-FFFFh Link address. The PaRAM address containing the PaRAM set to be linked (copied from) when the current PaRAM set is exhausted. You must program the link address to point to a valid aligned 32-byte PaRAM set. The 5 LSBs of the LINK field should be cleared to 0. A value of FFFFh specifies a null link. SPRUG34–November 2008 Registers 91 Submit Documentation Feedback

4.2.8 C Count Parameter (CCNT) Parameter RAM (PaRAM) Entries www.ti.com The source C index/destination C index parameter (SRC_DST_CIDX) specifies the value (2s complement) used for source address modification between each array in the 3rd dimension and the value (2s complement) used for destination address modification between each array in the 3rd dimension. The SRC_DST_CIDX is shown in Figure 4-7 and described in Table 4-8. Figure 4-7. Source C Index/Destination C Index Parameter (SRC_DST_CIDX) 31 16 DSTCIDX R/W-x 15 0 SRCCIDX R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 4-8. Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions Bit Field Value Description 31-16 DSTCIDX 0-FFFFh Destination C index. Signed value specifying the byte address offset between frames within a block (3rd dimension). Valid values range from –32 768 and 32 767. 15-0 SRCCIDX 0-FFFFh Source C index. Signed value specifying the byte address offset between frames within a block (3rd dimension). Valid values range from –32 768 and 32 767. The C count parameter (CCNT) specifies the number of frames in a block. The CCNT is shown in Figure 4-8 and described in Table 4-9. Figure 4-8. C Count Parameter (CCNT) 31 16 Reserved R/W-x 15 0 CCNT R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 4-9. C Count Parameter (CCNT) Field Descriptions Bit Field Value Description 31-16 Reserved 0 Reserved 15-0 CCNT 0-FFFFh C counter. Unsigned value specifying the number of frames in a block, where a frame is BCNT arrays of ACNT bytes. Valid values range from 1 to 65 535. 92 Registers SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com EDMA3 Channel Controller Control Registers Table 4-10 lists the memory-mapped registers for the EDMA3 channel controller (EDMACC). See the device-specific data manual for the memory address of these registers and for the shadow region addresses. All other register offset addresses not listed in Table 4-10 should be considered as reserved locations and the register contents should not be modified. Table 4-10. EDMACC Registers Offset Acronym Register Description Section 00h PID Peripheral Identification Register Section 4.3.1.1 04h CCCFG EDMA3CC Configuration Register Section 4.3.1.2 Global Registers 0200h QCHMAP0 QDMA Channel 0 Mapping Register Section 4.3.1.3 0204h QCHMAP1 QDMA Channel 1 Mapping Register Section 4.3.1.3 0208h QCHMAP2 QDMA Channel 2 Mapping Register Section 4.3.1.3 020Ch QCHMAP3 QDMA Channel 3 Mapping Register Section 4.3.1.3 0210h QCHMAP4 QDMA Channel 4 Mapping Register Section 4.3.1.3 0214h QCHMAP5 QDMA Channel 5 Mapping Register Section 4.3.1.3 0218h QCHMAP6 QDMA Channel 6 Mapping Register Section 4.3.1.3 021Ch QCHMAP7 QDMA Channel 7 Mapping Register Section 4.3.1.3 0240h DMAQNUM0 DMA Queue Number Register 0 Section 4.3.1.4 0244h DMAQNUM1 DMA Queue Number Register 1 Section 4.3.1.4 0248h DMAQNUM2 DMA Queue Number Register 2 Section 4.3.1.4 024Ch DMAQNUM3 DMA Queue Number Register 3 Section 4.3.1.4 0250h DMAQNUM4 DMA Queue Number Register 4 Section 4.3.1.4 0254h DMAQNUM5 DMA Queue Number Register 5 Section 4.3.1.4 0258h DMAQNUM6 DMA Queue Number Register 6 Section 4.3.1.4 025Ch DMAQNUM7 DMA Queue Number Register 7 Section 4.3.1.4 0260h QDMAQNUM QDMA Queue Number Register Section 4.3.1.5 0284h QUEPRI Queue Priority Register Section 4.3.1.6 0300h EMR Event Missed Register Section 4.3.2.1 0304h EMRH Event Missed Register High Section 4.3.2.1 0308h EMCR Event Missed Clear Register Section 4.3.2.2 030Ch EMCRH Event Missed Clear Register High Section 4.3.2.2 0310h QEMR QDMA Event Missed Register Section 4.3.2.3 0314h QEMCR QDMA Event Missed Clear Register Section 4.3.2.4 0318h CCERR EDMA3CC Error Register Section 4.3.2.5 031Ch CCERRCLR EDMA3CC Error Clear Register Section 4.3.2.6 0320h EEVAL Error Evaluate Register Section 4.3.2.7 0340h DRAE0 DMA Region Access Enable Register for Region 0 Section 4.3.3.1 0344h DRAEH0 DMA Region Access Enable Register High for Region 0 Section 4.3.3.1 0348h DRAE1 DMA Region Access Enable Register for Region 1 Section 4.3.3.1 034Ch DRAEH1 DMA Region Access Enable Register High for Region 1 Section 4.3.3.1 0350h DRAE2 DMA Region Access Enable Register for Region 2 Section 4.3.3.1 0354h DRAEH2 DMA Region Access Enable Register High for Region 2 Section 4.3.3.1 0358h DRAE3 DMA Region Access Enable Register for Region 3 Section 4.3.3.1 035Ch DRAEH3 DMA Region Access Enable Register High for Region 3 Section 4.3.3.1 0380h QRAE0 QDMA Region Access Enable Register for Region 0 Section 4.3.3.2 0384h QRAE1 QDMA Region Access Enable Register for Region 1 Section 4.3.3.2 0388h QRAE2 QDMA Region Access Enable Register for Region 2 Section 4.3.3.2 SPRUG34–November 2008 Registers 93 Submit Documentation Feedback

www.ti.com Table 4-10. EDMACC Registers (continued) Offset Acronym Register Description Section 038Ch QRAE3 QDMA Region Access Enable Register for Region 3 Section 4.3.3.2 0400h-047Ch Q0E0-Q1E15 Event Queue Entry Registers Q0E0-Q1E15 Section 4.3.4.1 0600h QSTAT0 Queue 0 Status Register Section 4.3.4.2 0604h QSTAT1 Queue 1 Status Register Section 4.3.4.2 0620h QWMTHRA Queue Watermark Threshold A Register Section 4.3.4.3 0640h CCSTAT EDMA3CC Status Register Section 4.3.4.4 Global Channel Registers 1000h ER Event Register Section 4.3.5.1 1004h ERH Event Register High Section 4.3.5.1 1008h ECR Event Clear Register Section 4.3.5.2 100Ch ECRH Event Clear Register High Section 4.3.5.2 1010h ESR Event Set Register Section 4.3.5.3 1014h ESRH Event Set Register High Section 4.3.5.3 1018h CER Chained Event Register Section 4.3.5.4 101Ch CERH Chained Event Register High Section 4.3.5.4 1020h EER Event Enable Register Section 4.3.5.5 1024h EERH Event Enable Register High Section 4.3.5.5 1028h EECR Event Enable Clear Register Section 4.3.5.6 102Ch EECRH Event Enable Clear Register High Section 4.3.5.6 1030h EESR Event Enable Set Register Section 4.3.5.7 1034h EESRH Event Enable Set Register High Section 4.3.5.7 1038h SER Secondary Event Register Section 4.3.5.8 103Ch SERH Secondary Event Register High Section 4.3.5.8 1040h SECR Secondary Event Clear Register Section 4.3.5.9 1044h SECRH Secondary Event Clear Register High Section 4.3.5.9 1050h IER Interrupt Enable Register Section 4.3.6.1 1054h IERH Interrupt Enable Register High Section 4.3.6.1 1058h IECR Interrupt Enable Clear Register Section 4.3.6.2 105Ch IECRH Interrupt Enable Clear Register High Section 4.3.6.2 1060h IESR Interrupt Enable Set Register Section 4.3.6.3 1064h IESRH Interrupt Enable Set Register High Section 4.3.6.3 1068h IPR Interrupt Pending Register Section 4.3.6.4 106Ch IPRH Interrupt Pending Register High Section 4.3.6.4 1070h ICR Interrupt Clear Register Section 4.3.6.5 1074h ICRH Interrupt Clear Register High Section 4.3.6.5 1078h IEVAL Interrupt Evaluate Register Section 4.3.6.6 1080h QER QDMA Event Register Section 4.3.7.1 1084h QEER QDMA Event Enable Register Section 4.3.7.2 1088h QEECR QDMA Event Enable Clear Register Section 4.3.7.3 108Ch QEESR QDMA Event Enable Set Register Section 4.3.7.4 1090h QSER QDMA Secondary Event Register Section 4.3.7.5 1094h QSECR QDMA Secondary Event Clear Register Section 4.3.7.6 Shadow Region 0 Channel Registers 2000h ER Event Register 2004h ERH Event Register High 2008h ECR Event Clear Register 94 Registers SPRUG34–November 2008 Submit Documentation Feedback

Table 4-10. EDMACC Registers (continued) Offset Acronym Register Description Section 200Ch ECRH Event Clear Register High 2010h ESR Event Set Register 2014h ESRH Event Set Register High 2018h CER Chained Event Register 201Ch CERH Chained Event Register High 2020h EER Event Enable Register 2024h EERH Event Enable Register High 2028h EECR Event Enable Clear Register 202Ch EECRH Event Enable Clear Register High 2030h EESR Event Enable Set Register 2034h EESRH Event Enable Set Register High 2038h SER Secondary Event Register 203Ch SERH Secondary Event Register High 2040h SECR Secondary Event Clear Register 2044h SECRH Secondary Event Clear Register High 2050h IER Interrupt Enable Register 2054h IERH Interrupt Enable Register High 2058h IECR Interrupt Enable Clear Register 205Ch IECRH Interrupt Enable Clear Register High 2060h IESR Interrupt Enable Set Register 2064h IESRH Interrupt Enable Set Register High 2068h IPR Interrupt Pending Register 206Ch IPRH Interrupt Pending Register High 2070h ICR Interrupt Clear Register 2074h ICRH Interrupt Clear Register High 2078h IEVAL Interrupt Evaluate Register 2080h QER QDMA Event Register 2084h QEER QDMA Event Enable Register 2088h QEECR QDMA Event Enable Clear Register 208Ch QEESR QDMA Event Enable Set Register 2090h QSER QDMA Secondary Event Register 2094h QSECR QDMA Secondary Event Clear Register Shadow Region 1 Channel Registers 2200h ER Event Register 2204h ERH Event Register High 2208h ECR Event Clear Register 220Ch ECRH Event Clear Register High 2210h ESR Event Set Register 2214h ESRH Event Set Register High 2218h CER Chained Event Register 221Ch CERH Chained Event Register High 2220h EER Event Enable Register 2224h EERH Event Enable Register High 2228h EECR Event Enable Clear Register 222Ch EECRH Event Enable Clear Register High 2230h EESR Event Enable Set Register SPRUG34–November 2008 Registers 95 Submit Documentation Feedback

www.ti.com Table 4-10. EDMACC Registers (continued) Offset Acronym Register Description Section 2234h EESRH Event Enable Set Register High 2238h SER Secondary Event Register 223Ch SERH Secondary Event Register High 2240h SECR Secondary Event Clear Register 2244h SECRH Secondary Event Clear Register High 2250h IER Interrupt Enable Register 2254h IERH Interrupt Enable Register High 2258h IECR Interrupt Enable Clear Register 225Ch IECRH Interrupt Enable Clear Register High 2260h IESR Interrupt Enable Set Register 2264h IESRH Interrupt Enable Set Register High 2268h IPR Interrupt Pending Register 226Ch IPRH Interrupt Pending Register High 2270h ICR Interrupt Clear Register 2274h ICRH Interrupt Clear Register High 2278h IEVAL Interrupt Evaluate Register 2280h QER QDMA Event Register 2284h QEER QDMA Event Enable Register 2288h QEECR QDMA Event Enable Clear Register 228Ch QEESR QDMA Event Enable Set Register 2290h QSER QDMA Secondary Event Register 2294h QSECR QDMA Secondary Event Clear Register 2400h-2494h — Shadow Region 2 Channel Registers 2600h-2694h — Shadow Region 3 Channel Registers 4000h-4FFFh — Parameter RAM (PaRAM) Registers 96 SPRUG34–November 2008 Submit Documentation Feedback

4.3.1.2 EDMA3CC Configuration Register (CCCFG) www.ti.com EDMA3 Channel Controller Control Registers The peripheral identification register (PID) uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC. The PID is shown in Figure 4-9 and described in Table 4-11. Figure 4-9. Peripheral ID Register (PID) 31 16 PID R-4001h 15 0 PID R-1B00h LEGEND: R = Read only; -n = value after reset Table 4-11. Peripheral ID Register (PID) Field Descriptions Bit Field Value Description 31-0 PID Peripheral identifier. 4001 1B00h Uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC. The EDMA3CC configuration register (CCCFG) provides the features/resources for the EDMA3CC in a particular device. The CCCFG is shown in Figure 4-10 and described in Table 4-12. Figure 4-10. EDMA3CC Configuration Register (CCCFG) 31 26 25 24 Reserved MP_EXIST CHMAP_EXIST R-x R-0 R-0 23 22 21 20 19 18 16 Reserved NUM_REGN Reserved NUM_EVQUE R-0 R-2h R-x R-1 15 14 12 11 10 8 Reserved NUM_PAENTRY Reserved NUM_INTCH R-x R-3h R-x R-4h 7 6 4 3 2 0 Reserved NUM_QDMACH Reserved NUM_DMACH R-x R-4h R-x R-5h LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset SPRUG34–November 2008 Registers 97 Submit Documentation Feedback

www.ti.com Table 4-12. EDMA3CC Configuration Register (CCCFG) Field Descriptions Bit Field Value Description 31-26 Reserved 0-3Fh Reserved 25 MP_EXIST Memory protection existence. 0 No memory protection. 1 Reserved 24 CHMAP_EXIST Channel mapping existence 0 No channel mapping. This implies that there is fixed association for a channel number to a parameter entry number or, in other words, PaRAM entry n corresponds to channel n. 1 Reserved 23-22 Reserved 0 Reserved 21-20 NUM_REGN 0-3h Number of shadow regions. 0-1 Reserved 2h 4 regions 3h Reserved 19 Reserved 0 Reserved 18-16 NUM_EVQUE 0-7h Number of queues/number of TCs. 0 Reserved 1 2 EDMA3TC/Event Queues 2h-7h Reserved 15 Reserved 0 Reserved 14-12 NUM_PAENTRY 0-7h Number of PaRAM sets. 0-2h Reserved 3h 128 sets 4h-7h Reserved 11 Reserved 0 Reserved 10-8 NUM_INTCH 0-7h Number of interrupt channels. 0-3h Reserved 4h 64 interrupt channels 5h-7h Reserved 7 Reserved 0 Reserved 6-4 NUM_QDMACH 0-7h Number of QDMA channels. 0-3h Reserved 4h 8 QDMA channels 5h-7h Reserved 3 Reserved 0 Reserved 2-0 NUM_DMACH 0-7h Number of DMA channels. 0-4h Reserved 5h 64 DMA channels 6h-7h Reserved Registers 98 SPRUG34–November 2008 Submit Documentation Feedback

www.ti.com EDMA3 Channel Controller Control Registers Each QDMA channel in EDMA3CC can be associated with any PaRAM set available on the device. Furthermore, the specific trigger word (0-7) of the PaRAM set can be programmed. The PaRAM set association and trigger word for every QDMA channel register is configurable using the QDMA channel map n register (QCHMAPn). The QCHMAPn is shown in Figure 4-11 and described in Table 4-13. Note: At reset the QDMA channel map registers for all QDMA channels point to the PaRAM set 0. Prior to using any QDMA channel, QCHMAPn should be programmed appropriately to point to a different PaRAM set. Figure 4-11. QDMA Channel Map n Registers (QCHMAPn) 31 16 Reserved R-0 15 14 13 5 4 2 1 0 Reserved PAENTRY TRWORD Reserved R-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-13. QDMA Channel Map n Registers (QCHMAPn) Field Descriptions Bit Field Value Description 31-14 Reserved 0 Reserved 13-5 PAENTRY 0-1FFh PAENTRY points to the PaRAM set number for QDMA channel n. 0-7Fh PaRAM set number 0 through 127 80h-1FFh Reserved 4-2 TRWORD 0-7h Points to the specific PaRAM entry or the trigger word in the PaRAM set pointed to by PAENTRY. A write to the trigger word results in a QDMA event being recognized. 1-0 Reserved 0 Reserved SPRUG34–November 2008 Registers 99 Submit Documentation Feedback

EDMA3 Channel Controller Control Registers www.ti.com The DMA channel queue number register (DMAQNUMn) allows programmability of each of the 64 DMA channels in the EDMA3CC to submit its associated synchronization event to any event queue in the EDMA3CC. At reset, all channels point to event queue 0. The DMAQNUMn is shown in Figure 4-12 and described in Table 4-14. Table 4-15 shows the channels and their corresponding bits in DMAQNUMn. Note: Since the event queues in EDMA3CC have a fixed association to the transfer controllers, that is, Q0 TRs are submitted to TC0, Q1 TRs are submitted to TC1, etc., by programming DMAQNUMn for a particular DMA channel also dictates which transfer controller is utilized for the data movement (or which EDMA3TC receives the TR request). Figure 4-12. DMA Channel Queue Number Registers (DMAQNUMn) 31 30 28 27 26 24 23 22 20 19 18 16 Rsvd En Rsvd En Rsvd En Rsvd En R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 15 14 12 11 10 8 7 6 4 3 2 0 Rsvd En Rsvd En Rsvd En Rsvd En R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-14. DMA Channel Queue Number Registers (DMAQNUMn) Field Descriptions Bit Field Value Description 31-0 En 0-7h DMA queue number. Contains the event queue number to be used for the corresponding DMA channel. Programming DMAQNUMn for an event queue number to a value more then the number of queues available in the EDMA3CC results in undefined behavior. 0 Event n is queued on Q0. 1h Event n is queued on Q1. 2h-7h Reserved Table 4-15. Bits in DMAQNUMn DMAQNUMn En bit 0 1 2 3 4 5 6 7 0-2 E0 E8 E16 E24 E32 E40 E48 E56 4-6 E1 E9 E17 E25 E33 E41 E49 E57 8-10 E2 E10 E18 E26 E34 E42 E50 E58 12-14 E3 E11 E19 E27 E35 E43 E51 E59 16-18 E4 E12 E20 E28 E36 E44 E52 E60 20-22 E5 E13 E21 E29 E37 E45 E53 E61 24-26 E6 E14 E22 E30 E38 E46 E54 E62 28-30 E7 E15 E23 E31 E39 E47 E55 E63 100 Registers SPRUG34–November 2008 Submit Documentation Feedback