Dynamic Engineering PCIeBiSerialDb37-LM9 Operation & User’s Manual

DYNAMIC ENGINEERING 150 DuBois St. Suite C, Santa Cruz, CA 95060 831-457-8891 Fax 831-457-4793 http://www.dyneng.com [email protected] Est. 1988 User Manual PCIeBiSerialDb37-LM9 ARC210 IF / Parallel Port PCIe 4 lane Module Transmit and Receive Interface Protocols RS485/422 Revision A1 Corresponding Ha ...

PCIeBiSerialDb37LM9 ARC-210 and Digital Parallel Interface PCIe Module Dynamic Engineering 150 DuBois St. Suite C, Santa Cruz CA 95060 831-457-8891 831-457-4793 FAX This document contains information of proprietary interest to Dynamic Engineering. It has been supplied in confidence and the recipient, by ac ...

Table of Contents PRODUCT DESCRIPTION 6 ADDRESS MAP 12 PROGRAMMING 14 Base Register Definitions 16 LM9_BASE_BASE 16 LM9_BASE_ID 17 LM9_BASE_STATUS 18 LM9_CHAN_CNTRL 19 LM9_CHAN_STATUS 21 LM9_CHAN_TX_FIFO_COUNT 26 LM9_CHAN_RD_DMA_PNTR 26 LM9_CHAN_RX_FIFO_COUNT 27 LM9_CHAN_FIFO 27 LM9_CHAN_TX_AMT_LVL 28 LM9_C ...

Out of Warranty Repairs 41 SPECIFICATIONS 42 ORDER INFORMATION 43 ...

List of Figures FIGURE 1 PCIEBISERIALDB37LM9 BLOCK DIAGRAM 7 FIGURE 2 PCIEBISERIALDB37LM9 TIMING DIAGRAM 11 FIGURE 3 PCIEBISERIALDB37LM9 INTERNAL ADDRESS MAP BASE FUNCTIONS 12 FIGURE 4 PCIEBISERIALDB37LM9 CHANNEL ADDRESS MAP 13 FIGURE 5 PCIEBISERIALDB37LM9 CONTROL BASE REGISTER BIT MAP 16 FIGURE 6 PCI ...

Product Description In embedded systems many of the interconnections are made with differential [RS- 422/485 or LVDS] signals. Depending on the system architecture an IP, PMC or native bus card will be the right choice to make the connection. You have choices with carriers for cPCI, PCI, PCIe, VME, PC/104 ...

“LM9” is set to use the RS485/RS422 standard, and supports one Transmit and one Receive channel plus a parallel port. The transmitter and receiver are designed to interface with the ARC-210 radio. Figure 1 PCIEBISERIALDB37LM9 Block Diagram The ARC-210 will supply the “SendTiming” and “ReceiveTim ...

The number of bytes to send is programmable. The number can be stored into a secondary FIFO to allow multiple packets to be transmitted from a single larger DMA transfer. The number of bytes can also be stored into a register to cover cases where the size of each packet is consistent. The hardware waits u ...

The transmitter and receiver have 4K x 32 FIFO’s with direct access, DMA support, and loop-back capabilities. The driver/reference software includes examples of all three modes. DMA when used will keep the transmitter FIFO full and the receiver FIFO empty automatically and without overflow etc. The hardw ...

The registers are mapped as 32 bit words and support 32 bit access. Most registers are read-writeable. The Windows® and Linux compatible drivers are available to provide the system level interface for this version of the Biserial. Use standard C/C++ to control your hardware or use the Hardware manual t ...