Cypress Semiconductor CY7C1522AV18 Specification Sheet
Text of the manual
72-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
CY7C1522AV18, CY7C1529AV18
CY7C1523AV18, CY7C1524AV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 001-06981 Rev. *D
Revised June 14, 2008
Features
■72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■300 MHz clock for high bandwidth
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Document #: 001-06981 Rev. *D
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Logic Block Diagram (CY7C1522AV18)
Logic Block Diagram (CY7C1529AV18)
4M x 8 Array
CLK
A(21:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
LD
Q[7:0]
Reg.
Reg.
Reg.
8
16
8
NWS[1:0]
VREF
Write Add. Decode
Write
Data Reg
8
8
22
8
R
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Logic Block Diagram (CY7C1523AV18)
Logic Block Diagram (CY7C1524AV18)
2M x 18 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
LD
Q[17:0]
Reg.
Reg.
Reg.
18
36
18
BWS[1:0]
VREF
Write Add. Decode
Write
Data Reg
18
18
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Pin Configuration
The pin configuration for CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and CY7C1524AV18 follow. [1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1522AV18 (8M x 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
A
A
R/W
NWS1
K
NC/144M
LD
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
N
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CY7C1523AV18 (4M x 18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/144M
A
R/W
BWS1
K
NC/288M
LD
A
A
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
A
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
