Cypress Semiconductor CY7C1161V18 Specification Sheet

Architecture (2.5 Cycle Read Latency) Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-06582 Rev. *D Revised March 06, 2008 Features ■Separate independent read and write data ports ❐Supports con ...

Page 2 of 29 Logic Block Diagram (CY7C1161V18) Logic Block Diagram (CY7C1176V18) 512K x 8 Array CLK A(18:0) Gen. K K Control Logic Address Register D[7:0] Read Add. Decode Read Data Reg. RPS WPS Q[7:0] Control Logic Address Register Reg. Reg. Reg. 16 19 8 32 8 NWS[1:0] VREF ...

Page 3 of 29 Logic Block Diagram (CY7C1163V18) Logic Block Diagram (CY7C1165V18) 256K x 18 Array CLK A(17:0) Gen. K K Control Logic Address Register D[17:0] Read Add. Decode Read Data Reg. RPS WPS Q[17:0] Control Logic Address Register Reg. Reg. Reg. 36 18 18 72 18 BWS[1:0] ...

Page 4 of 29 Pin Configurations CY7C1161V18 (2M x 8) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS1 K WPS NC/144M NC NC NC NC NC TDO NC NC D5 NC NC NC TCK NC NC A NC/288M K NWS0 VSS A NC A NC VSS VSS ...

Page 5 of 29 Pin Configurations (continued) CY7C1163V18 (1M x 18) 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/144M NC/36M BWS1 K WPS NC/288M Q9 D9 NC NC NC TDO NC NC D13 NC NC NC TCK NC D10 A NC K BWS0 VSS A ...

Page 6 of 29 Pin Definitions Pin Name IO Pin Description D[x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1161V18−D[7:0] CY7C1176V18−D[8:0] CY7C1163V18−D[17:0] CY7C1165V18−D[35:0] WPS Input- ...

Page 7 of 29 CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics” on page 23. ZQ Input Output Impedance Matching Inpu ...

Page 8 of 29 Functional Overview The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are synchronous pipelined burst SRAMs equipped with both a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operation ...

Page 9 of 29 Depth Expansion The CY7C1163V18 has a port select input for each port. This enables easy depth expansion. Both port selects are only sampled on the rising edge of the positive input clock (K). Each port select input can deselect the specified port. Deselecting a ...

Page 10 of 29 Application Example Figure 1 shows four QDR-II+ used in an application. Figure 1. Application Example Truth Table The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.[3, 4, 5, 6, 7, 8] Operation K RPS WPS DQ DQ DQ DQ Write Cyc ...