Western Digital TN-55 Operation & User’s Manual

WRL Technical Note TN-55 The Memory Daughter-Card Version 1.5 User’s Manual Marc A. Viredaz d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA

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The Memory Daugh ter-Card V ersion
. User's Man ual Marc A. Viredaz July
 Abstract The memory daughter-c ar d is memory extension b oard for the Itsy p o cket c omputer dev elop ed at Compaq Computer Corp oration's Western R ese ar ch L ab or atory (WRL). It pro vides an additional bank of ash memory and up to three additional banks of DRAM. It is p ossible to b o ot from this daugh ter-card. This do cumen t describ es the arc hitecture and the lo w-lev el programming mo del of the memory daugh ter-card. R evision
.0

The Memory Daugh ter-Card V ersion
. : User's Man ual Con ten ts Disclaimer

In tro duction

.
Purp ose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   Arc hitecture  .
Memory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .
.
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .
. Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   Programmer's mo del  .
Memory daugh ter-card general-purp ose input/output signals . . . . . . . . . . . . .  . Non-v olatile memory iden tication structure . . . . . . . . . . . . . . . . . . . . . . .  References  List of Figures
Arc hitecture of the memory daugh ter-card . . . . . . . . . . . . . . . . . . . . . . . .  List of T ables
Memory daugh ter-card general-purp ose input/output signals . . . . . . . . . . . . .  WRL, Compaq iii

The Memory Daugh ter-Card V ersion
. : User's Man ual Disclaimer Compaq Computer Corp oration b eliev es the information included in this pub- lication is correct as of the date of publication. Suc h information is sub ject to c hange without notice. Compaq is not resp onsible for inadv erten t errors. Compaq mak es no represen tations that the use of its pro ducts in the man- ner describ ed in this publication will not infringe on existing or future paten t righ ts, nor do the descriptions con tained in this publication imply the gran ting of licenses to mak e, use, or sell equipmen t or soft w are in accordance with the description.
In tro duction This do cumen t describ es the arc hitecture and the programmer's mo del of the memory daughter- c ar d for the Itsy p o cket c omputer [Vir ]. It should b e considered as a guide for lo w-lev el soft w are dev elop ers. A go o d understanding of the Itsy computer [Vir ] is assumed throughout this rep ort.
.
Purp ose The design of the memory daugh ter-card w as aimed at ac hieving sev eral goals :  Pro vide additional ash memory and DRAM (memory extension).  Be usable as a \safet y daugh ter-card," i.e., it should b e p ossible to b o ot from the daugh ter- card, in order to reco v er from a corrupted mother-b oard ash memory .  Be usable as a system test and debug platform, i.e., it should b e p ossible to b o ot from the daugh ter-card and use so c k ets for the ash memory , so that it can b e programmed with an external programmer.  Pro vide a protot yping platform to in terface additional hardw are to the Itsy computer.
. History The rst printe d-cir cuit b o ar d (PCB), referred to as memory daughter-c ar d version
.0, w as com- pleted in No v em b er
. This rst protot yp e had a few minor a ws, all of whic h could b e corrected. The logic design corresp onding to a mo died (i.e., patc hed) v ersion
.0 b oard is kno wn as memory daughter-c ar d version
.
. This design corresp onds only to a set of sc hematics, no ph ysical PCB ha ving b een man ufactured. A second protot yp e, named memory daughter-c ar d version
. w as complete in July
. It corresp onds to a v ersion
.
system with a few additional features. F rom the programmer's p oin t-of-view, there are almost no dierences b et w een the v ersions
.
and
.. This do cumen t describ es the memory daugh ter-card v ersion
.. All relev an t dierences b et w een the v ersions
.
and
. are outlined in fo ot-notes. WRL, Compaq

15 Gray L. LCD 32 Processor StrongARM SA-1100 Interface Analog 32 DRAM 16 Mbyte Memory Card DRAM Daughter 9 Flash Memory 4 Mbyte 32 Telecom. Codec Points Access Memory Bus A/D GPIO SSP SDLC UART USB Figure
: Arc hitecture of the memory daugh ter-card.
. Notations In this rep ort, electrical signals are represen ted as upp er-case names in a sans-serif fon t (e.g., PWR EN ). Activ e-lo w signals are denoted b y o v er-lines (e.g., RESET OUT ), while buses and elemen t of buses are sp ecied b y subscripts (e.g., DCD 
:: 0 , DCA 0 ). In the sc hematics, the same signals are represen ted using the syn tax and con v en tions of the Windo wSIL [Tha  ] CAD to ols. F or example, the signal DCCS  app ears as ~dccs[].  Arc hitecture Figure
presen ts the arc hitecture of the memory daugh ter-card (righ t part), sho wn in resp ect to the Itsy computer (left part). The memory daugh ter-card v ersions
.
and
. are b oth compatible with b oth v ersions of the Itsy mother-b oard (i.e., v ersions
.
and
.). .
Memory system The memory daugh ter-card features a ash memory deco ded as static-memory bank  and the three dynamic r andom-ac c ess memory (DRAM) banks
, , and . Dep ending on the application's  WRL, Compaq

The Memory Daugh ter-Card V ersion
. : User's Man ual needs, only some of these banks (or ev en none) migh t b e presen t. Since this daugh ter-card is b o otable, the ash memory is also deco ded as static-memory bank 0, from whic h the StrongARM SA-

00 pro cessor [DEC  ] b o ots. .
.
Flash memory A pair of
-bit ash-memory circuits implemen t the -bit ash memory . These circuits can b e either soldered on the b oard or put in zer o insertion for c e (ZIF) so ckets . Man y dieren t devices can b e accommo dated : AMD Am L V
0BO ss P T [AMD e ] AMD Am L V00O -ss P T /Am L V00BO ss P T [AMD c , AMD d ] AMD Am L V00O -ss P T [AMD a ] AMD Am L V00O -ss P T [AMD b ] Hitac hi HN VO 00P -ss /HN WO 00P - ss [Hit c , Hit d] Motorola M F00AO P ss /M F0 0A O P ss [Mot  ] Sharp LHF00SGP -Lss [Sha ] where \O " sp ecies the in ternal sector organization, \ss " sp ecies the sp eed, \P " sp ecies the pac k age, and \T " sp ecies the temp erature range. An y other compatible parts can also b e used. F ollo wing the Itsy static-memory iden tication sc heme [Vir ], a non-v olatile memory iden ti- cation structure describ es the c haracteristics of the sp ecic parts used on a giv en daugh ter-card and hence allo ws the soft w are to congure the memory in terface correctly . The r eset/p ower-down pin of the ash-memory circuits is asserted (0) during a reset (i.e., hardw are, soft w are, or w atc h-dog reset) and during sleep mo de. When the ash memory do es not need to b e accessed, this signal can also b e asserted (0) b y setting the signal GPIO
 (DCFLF OFF) to 0 (see Section .
).
When the Itsy computer m ust b o ot from the daugh ter-card, this signal should nev er b e set to 0 during sleep mo de, since the pro cessor w ould b e unable to read the b o ot memory up on w ak e up. This can easily b e ac hiev ed b y setting bit
 of the p ower manager GPIO sle ep state r e gister PGSR of the StrongARM SA-

00 pro cessor [DEC  ] to
. The r e ady/not-busy pins of the ash-memory circuits can b e monitored using the signals GPIO
 (DCFL0RY =BY ), for the least signican t
 data bits D
 :: 0 , and GPIO
 (DCFL
RY =BY ), for the most signican t
 data bits D 
::
 (see Section .
). The hardw are write-protection mec hanism, featured b y some of the supp orted parts, is nev er used, and the corresp onding pin is alw a ys de-asserted (
). Ho w ev er, it is still p ossible to protect the ash memory against write accesses, b y using the jump er pro vided for this purp ose. The ash memory is protected when this jump er is op en and is writable when this jump er is short-circuited. .
. Dynamic RAM Three pairs of  Mbit (i.e., 
 ro ws  
0 columns 
 bits) self-refresh DRAM circuits implemen t the three -bit DRAM banks. Man y dieren t fast-p age mo de or enhanc e d data out (EDO) devices can b e accommo dated :
On the memory daugh ter-card v ersion
.
, the reset/p o w er-do wn pins are only asserted (0) during sleep mo de or when the signal GPIO
 (DCFLF OFF ) is set to 0. WRL, Compaq 

The Memory Daugh ter-Card V ersion
. : User's Man ual Signal Name F unction Dir. Def. GPIO
 DCFLF OFF Daugh ter-card ash memory f orce o O
GPIO
 DCFL0RY =BY Daugh ter-card ash memory 0 ready /busy I GPIO
 DCFL
RY =BY Daugh ter-card ash memory
ready /busy I T able
: Memory daugh ter-card general-purp ose input/output signals. Hitac hi HM

0AL TT-ss [Hit a ] Hitac hi HM

AL TT-ss [Hit b ] Samsung KM
V
00AS-Lss /KM
V
00B S-Lss [Sam a , Sam a ] Samsung KM
V
0AS-Lss /KM
V
0B S-Lss [Sam b, Sam b] T oshiba TC

AFTS-ss [T os  ] where \ss " sp ecies the sp eed. An y other compatible parts can also b e used. Since all DRAM banks m ust b e accessed at the sp eed of the slo w est one, it is b est to use the same devices as on the Itsy mother-b oard, that is, 0 ns EDO DRAM circuits (KM
V
0AS-L , KM
V
0BS-L , or TC

AFTS-0 ).  Programmer's mo del This section presen ts additional information on the mo del that the lo w-lev el soft w are has of the memory daugh ter-card hardw are. .
Memory daugh ter-card general-purp ose input/output signals T able
sho ws the general-purp ose input/output signals used on the memory daugh ter-card. Both input signals can b e used as in terrupts. After a hardw are reset (i.e., p o w er-up or push-button reset), all input/output signals are congured as input. Therefore, a pull-up resistor is used to pro vide a default v alue to the signal GPIO
 (DCFLF OFF), as sho wn in the last column of T able
. The function of all signals are : GPIO
 : DCFLF OFF : Daugh ter-card ash memory f orce o This output signal is used to con trol the reset/p o w er-do wn pin of the ash-memory circuits (see Section .
.
). When this signal is set to 0, the reset/p o w er-do wn pins are asserted (0). When it is set to
, the reset/p o w er-do wn pins are only asserted (0) during a reset (i.e., hardw are, soft w are, or w atc h-dog reset) and during sleep mo de.  A pull-up resistor sets the default v alue of this signal to
when the GPIO
 pin is congured as input (e.g., after a hardw are reset). When the Itsy computer m ust b o ot from the daugh ter-card, this signal should nev er b e set to 0 during sleep mo de, since the pro cessor w ould b e unable to read the b o ot memory up on w ak e up. This can b e easily ac hiev ed b y setting bit
 of the p ower manager GPIO sle ep state r e gister PGSR of the StrongARM SA-

00 pro cessor [DEC  ] to
.  On the memory daugh ter-card v ersion
.
, the reset/p o w er-do wn pins are only asserted (0) when this signal is set to 0 and during sleep mo de.  WRL, Compaq

The Memory Daugh ter-Card V ersion
. : User's Man ual GPIO
 : DCFL0RY =BY : Daugh ter-card ash memory 0 ready /busy This input signal is connected to the ready/not-busy pin of the ash-memory circuit used for the least signican t
 data bits D
 :: 0 (see Section .
.
). It is set to 0 when the ash- memory circuit is executing an erase or program op eration and to
when it is ready for use. GPIO
 : DCFL
RY =BY : Daugh ter-card ash memory
ready /busy This input signal is connected to the ready/not-busy pin of the ash-memory circuit used for the most signican t
 data bits D 
::
 (see Section .
.
). It is set to 0 when the ash- memory circuit is executing an erase or program op eration and to
when it is ready for use. . Non-v olatile memory iden tication structure F ollo wing the Itsy static-memory identic ation scheme, the ash memory m ust implemen t a non- volatile memory identic ation structur e [Vir ]. The class identic ation v alue is CID = 0 , the read-only bit is R = 0 , the daugh ter-card bit is D =
, and the width bit is W = 0 . The v alues of the SIZE eld and of the dieren t MSC elds dep end on the sp ecic parts used on a giv en daugh ter- card (see Section .
.
). The elds EN0 , RY =BY 0 , EN
, and RY =BY
, dening the general-purp ose input/output signals, ha v e the v alues EN0 =
 =
0
 , RY =BY 0 =
 =


 , EN
=
 =
0
 , and RY =BY
=
 =

 . References [AMD a] Adv anced Micro Devices. A m L V00T/A m L V00B :  Me gabit (,  -Bit / ,
 
-Bit ) CMOS .0 V olt-Only Se ctor A r chite ctur e Flash Memory, Ma y
. Publication no. 0
, rev. B, amendmen t +
, preliminary . [AMD b] Adv anced Micro Devices. A m L V00T/A m L V00B :  Me gabit (,
  -Bit /

,0 
-Bit) CMOS .0 V olt-Only Se ctor A r chite ctur e Flash Memory, August
. Publication no. 0
, rev. C, amendmen t +
, preliminary . [AMD c] Adv anced Micro Devices. A m L V00T/A m L V00B :  Me gabit (
,0,  -Bit / , 
-Bit ) CMOS .0 V olt-Only, Se ctor e d Flash Memory, No v em b er
. Pub- lication no. 0, rev. D, amendmen t 0, preliminary . [AMD d] Adv anced Micro Devices. A m L V00B :  Me gabit (
M  -Bit/
 K 
-Bit ) CMOS .0 V olt-Only Bo ot Se ctor Flash Memory, Decem b er
. Publication no. 
 0, rev. E, amendmen t 0, preliminary . [AMD e] Adv anced Micro Devices. A m L V
0B :
 Me gabit ( M  -Bit/
M 
-Bit ) CMOS .0 V olt-Only Bo ot Se ctor Flash Memory, Decem b er
. Publication no. 
, rev. F, amendmen t 0, preliminary . WRL, Compaq 

The Memory Daugh ter-Card V ersion
. : User's Man ual [DEC ] Digital Equipmen t Corp oration, Ma ynard, MA (USA). DIGIT AL Semic onductor SA-

00 Micr opr o c essor : T e chnic al R efer enc e Manual, Marc h
. Do cumen t no. EC-RMTC-TE. [Hit a] Hitac hi. HM

0A Series, HM

0A Series : 
0-Wor d 
-Bit Dynamic RAM, Jan uary
. Do cumen t no. ADE-0-  (Z) , rev. 0.
, preliminary . [Hit b] Hitac hi. HM

A Series, HM

A Series : 
0-Wor d 
-Bit Dynamic RAM, April
. Do cumen t no. ADE-0- (Z), rev. 0., preliminary . [Hit c] Hitac hi. HN VT00 Series, HN VB00 Series :
0-Wor d  -Bit / -Wor d 
-Bit CMOS Flash Memory, April
. Do cumen t no. ADE-0-
A (Z), rev.
.0. [Hit d] Hitac hi. HN WT00 Series, HN WB00 Series :
0-Wor d  -Bit / -Wor d 
-Bit CMOS Flash Memory, Ma y
. Do cumen t no. ADE-0-A (Z), rev.
.0. [Mot ] Motorola. M F00A, M F00A :  M CMOS Flash Memory, Octob er
. Do c- umen t no. M F00A/D , rev. . [Sam a] Samsung Electronics. KM
V000A, KM
V
00A CMOS DRAM :  M 
 Bit CMOS Dynamic RAM with F ast Page Mo de,
. [Sam b] Samsung Electronics. KM
V00A, KM
V
0A CMOS DRAM :  M 
 Bit CMOS Dynamic RAM with Extende d Data Out,
. [Sam a] Samsung Electronics. KM
V000B, KM
V
00B CMOS DRAM :  M 
 Bit CMOS Dynamic RAM with F ast Page Mo de,
. Preliminary sp ec. [Sam b] Samsung Electronics. KM
V00B, KM
V
0B CMOS DRAM :  M 
 Bit CMOS Dynamic RAM with Extende d Data Out,
. Preliminary sp ec. [Sha ] Sharp. LHF00SG :  Mbit (
 Kbit 
) SmartV oltage Flash Memory, F ebruary
. Preliminary . [Tha ] C. Thac k er. WindowSIL/WC User's Guide. SR C, Digital Equipmen t Corp oration, P alo Alto, CA (USA), F ebruary
. [T os ] T oshiba. T oshib a MOS Digital Inte gr ate d Cir cuit TC

AJS/AFTS-0 TC

AJS/AFTS-0 TC

AJS/AFTS-0 Silic on Gate CMOS : ,
,0 Wor ds 
 Bit EDO (Hyp er Page) Dynamic RAM, Octob er
. T en tativ e data. [Vir ] Marc A. Viredaz. The Itsy P o c k et Computer V ersion
. : User's Man ual. T ec hnical note TN-, WRL, Compaq, P alo Alto, CA (USA), July
. Revision
.0.  WRL, Compaq

‘‘Titan System Manual.’’ Michael J. K. Nielsen. WRL Research Report 86/1, September 1986. ‘‘Global Register Allocation at Link Time.’’ David W. Wall. WRL Research Report 86/3, October 1986. ‘‘Optimal Finned Heat Sinks.’’ William R. Hamburgen. WRL Research Report 86/4, October 1986. ‘‘The Mahler Experience: Using an Intermediate Language as the Machine Description.’’ David W. Wall and Michael L. Powell. WRL Research Report 87/1, August 1987. ‘‘The Packet Filter: An Efficient Mechanism for User-level Network Code.’’ Jeffrey C. Mogul, Richard F. Rashid, Michael J. Accetta. WRL Research Report 87/2, November 1987. ‘‘Fragmentation Considered Harmful.’’ Christopher A. Kent, Jeffrey C. Mogul. WRL Research Report 87/3, December 1987. ‘‘Cache Coherence in Distributed Systems.’’ Christopher A. Kent. WRL Research Report 87/4, December 1987. ‘‘Register Windows vs. Register Allocation.’’ David W. Wall. WRL Research Report 87/5, December 1987. ‘‘Editing Graphical Objects Using Procedural Representations.’’ Paul J. Asente. WRL Research Report 87/6, November 1987. ‘‘The USENET Cookbook: an Experiment in Electronic Publication.’’ Brian K. Reid. WRL Research Report 87/7, December 1987. ‘‘MultiTitan: Four Architecture Papers.’’ Norman P. Jouppi, Jeremy Dion, David Boggs, Michael J. K. Nielsen. WRL Research Report 87/8, April 1988. ‘‘Fast Printed Circuit Board Routing.’’ Jeremy Dion. WRL Research Report 88/1, March 1988. ‘‘Compacting Garbage Collection with Ambiguous Roots.’’ Joel F. Bartlett. WRL Research Report 88/2, February 1988. ‘‘The Experimental Literature of The Internet: An Annotated Bibliography.’’ Jeffrey C. Mogul. WRL Research Report 88/3, August 1988. ‘‘Measured Capacity of an Ethernet: Myths and Reality.’’ David R. Boggs, Jeffrey C. Mogul, Christopher A. Kent. WRL Research Report 88/4, September 1988. ‘‘Visa Protocols for Controlling Inter-Organizational Datagram Flow: Extended Description.’’ Deborah Estrin, Jeffrey C. Mogul, Gene Tsudik, Kamaljit Anand. WRL Research Report 88/5, December 1988. ‘‘SCHEME->C A Portable Scheme-to-C Compiler.’’ Joel F. Bartlett. WRL Research Report 89/1, January 1989. ‘‘Optimal Group Distribution in Carry-Skip Ad- ders.’’ Silvio Turrini. WRL Research Report 89/2, February 1989. ‘‘Precise Robotic Paste Dot Dispensing.’’ William R. Hamburgen. WRL Research Report 89/3, February 1989. ‘‘Simple and Flexible Datagram Access Controls for Unix-based Gateways.’’ Jeffrey C. Mogul. WRL Research Report 89/4, March 1989. ‘‘Spritely NFS: Implementation and Performance of Cache-Consistency Protocols.’’ V. Srinivasan and Jeffrey C. Mogul. WRL Research Report 89/5, May 1989. ‘‘Available Instruction-Level Parallelism for Super- scalar and Superpipelined Machines.’’ Norman P. Jouppi and David W. Wall. WRL Research Report 89/7, July 1989. ‘‘A Unified Vector/Scalar Floating-Point Architec- ture.’’ Norman P. Jouppi, Jonathan Bertoni, and David W. Wall. WRL Research Report 89/8, July 1989.

Design of the MultiTitan CPU.’’ Norman P. Jouppi. WRL Research Report 89/9, July 1989. ‘‘Integration and Packaging Plateaus of Processor Performance.’’ Norman P. Jouppi. WRL Research Report 89/10, July 1989. ‘‘A 20-MIPS Sustained 32-bit CMOS Microproces- sor with High Ratio of Sustained to Peak Perfor- mance.’’ Norman P. Jouppi and Jeffrey Y. F. Tang. WRL Research Report 89/11, July 1989. ‘‘The Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.’’ Norman P. Jouppi. WRL Research Report 89/13, July 1989. ‘‘Long Address Traces from RISC Machines: Generation and Analysis.’’ Anita Borg, R.E.Kessler, Georgia Lazana, and David W. Wall. WRL Research Report 89/14, Septem- ber 1989. ‘‘Link-Time Code Modification.’’ David W. Wall. WRL Research Report 89/17, September 1989. ‘‘Noise Issues in the ECL Circuit Family.’’ Jeffrey Y.F. Tang and J. Leon Yang. WRL Research Report 90/1, January 1990. ‘‘Efficient Generation of Test Patterns Using Boolean Satisfiablilty.’’ Tracy Larrabee. WRL Research Report 90/2, February 1990. ‘‘Two Papers on Test Pattern Generation.’’ Tracy Larrabee. WRL Research Report 90/3, March 1990. ‘‘Virtual Memory vs. The File System.’’ Michael N. Nelson. WRL Research Report 90/4, March 1990. ‘‘Efficient Use of Workstations for Passive Monitor- ing of Local Area Networks.’’ Jeffrey C. Mogul. WRL Research Report 90/5, July 1990. ‘‘A One-Dimensional Thermal Model for the VAX 9000 Multi Chip Units.’’ John S. Fitch. WRL Research Report 90/6, July 1990. ‘‘1990 DECWRL/Livermore Magic Release.’’ Robert N. Mayo, Michael H. Arnold, Walter S. Scott, Don Stark, Gordon T. Hamachi. WRL Research Report 90/7, September 1990. ‘‘Pool Boiling Enhancement Techniques for Water at Low Pressure.’’ Wade R. McGillis, John S. Fitch, William R. Hamburgen, Van P. Carey. WRL Research Report 90/9, December 1990. ‘‘Writing Fast X Servers for Dumb Color Frame Buf- fers.’’ Joel McCormack. WRL Research Report 91/1, February 1991. ‘‘A Simulation Based Study of TLB Performance.’’ J. Bradley Chen, Anita Borg, Norman P. Jouppi. WRL Research Report 91/2, Novem- ber 1991. ‘‘Analysis of Power Supply Networks in VLSI Cir- cuits.’’ Don Stark. WRL Research Report 91/3, April 1991. ‘‘TurboChannel T1 Adapter.’’ David Boggs. WRL Research Report 91/4, April 1991. ‘‘Procedure Merging with Instruction Caches.’’ Scott McFarling. WRL Research Report 91/5, March 1991. ‘‘Don’t Fidget with Widgets, Draw!.’’ Joel Bartlett. WRL Research Report 91/6, May 1991. ‘‘Pool Boiling on Small Heat Dissipating Elements in Water at Subatmospheric Pressure.’’ Wade R. McGillis, John S. Fitch, William R. Hamburgen, Van P. Carey. WRL Research Report 91/7, June 1991. ‘‘Incremental, Generational Mostly-Copying Gar- bage Collection in Uncooperative Environ- ments.’’ G. May Yip. WRL Research Report 91/8, June 1991. ‘‘Interleaved Fin Thermal Connectors for Multichip Modules.’’ William R. Hamburgen. WRL Research Report 91/9, August 1991. ‘‘Experience with a Software-defined Machine Ar- chitecture.’’ David W. Wall. WRL Research Report 91/10, August 1991.

Jeffrey C. Mogul. WRL Research Report 91/11, November 1991. ‘‘Cache Write Policies and Performance.’’ Norman P. Jouppi. WRL Research Report 91/12, Decem- ber 1991. ‘‘Packaging a 150 W Bipolar ECL Microprocessor.’’ William R. Hamburgen, John S. Fitch. WRL Research Report 92/1, March 1992. ‘‘Observing TCP Dynamics in Real Networks.’’ Jeffrey C. Mogul. WRL Research Report 92/2, April 1992. ‘‘Systems for Late Code Modification.’’ David W. Wall. WRL Research Report 92/3, May 1992. ‘‘Piecewise Linear Models for Switch-Level Simula- tion.’’ Russell Kao. WRL Research Report 92/5, September 1992. ‘‘A Practical System for Intermodule Code Optimiza- tion at Link-Time.’’ Amitabh Srivastava and David W. Wall. WRL Research Report 92/6, December 1992. ‘‘A Smart Frame Buffer.’’ Joel McCormack & Bob McNamara. WRL Research Report 93/1, January 1993. ‘‘Recovery in Spritely NFS.’’ Jeffrey C. Mogul. WRL Research Report 93/2, June 1993. ‘‘Tradeoffs in Two-Level On-Chip Caching.’’ Norman P. Jouppi & Steven J.E. Wilton. WRL Research Report 93/3, October 1993. ‘‘Unreachable Procedures in Object-oriented Programing.’’ Amitabh Srivastava. WRL Research Report 93/4, August 1993. ‘‘An Enhanced Access and Cycle Time Model for On-Chip Caches.’’ Steven J.E. Wilton and Nor- man P. Jouppi. WRL Research Report 93/5, July 1994. ‘‘Limits of Instruction-Level Parallelism.’’ David W. Wall. WRL Research Report 93/6, November 1993. ‘‘Fluoroelastomer Pressure Pad Design for Microelectronic Applications.’’ Alberto Makino, William R. Hamburgen, John S. Fitch. WRL Research Report 93/7, November 1993. ‘‘A 300MHz 115W 32b Bipolar ECL Microproces- sor.’’ Norman P. Jouppi, Patrick Boyle, Jeremy Dion, Mary Jo Doherty, Alan Eustace, Ramsey Haddad, Robert Mayo, Suresh Menon, Louis Monier, Don Stark, Silvio Turrini, Leon Yang, John Fitch, William Hamburgen, Rus- sell Kao, and Richard Swan. WRL Research Report 93/8, December 1993. ‘‘Link-Time Optimization of Address Calculation on a 64-bit Architecture.’’ Amitabh Srivastava, David W. Wall. WRL Research Report 94/1, February 1994. ‘‘ATOM: A System for Building Customized Program Analysis Tools.’’ Amitabh Srivastava, Alan Eustace. WRL Research Report 94/2, March 1994. ‘‘Complexity/Performance Tradeoffs with Non- Blocking Loads.’’ Keith I. Farkas, Norman P. Jouppi. WRL Research Report 94/3, March 1994. ‘‘A Better Update Policy.’’ Jeffrey C. Mogul. WRL Research Report 94/4, April 1994. ‘‘Boolean Matching for Full-Custom ECL Gates.’’ Robert N. Mayo, Herve Touati. WRL Research Report 94/5, April 1994. ‘‘Software Methods for System Address Tracing: Implementation and Validation.’’ J. Bradley Chen, David W. Wall, and Anita Borg. WRL Research Report 94/6, September 1994. ‘‘Performance Implications of Multiple Pointer Sizes.’’ Jeffrey C. Mogul, Joel F. Bartlett, Robert N. Mayo, and Amitabh Srivastava. WRL Research Report 94/7, December 1994.

fers, and Speculative Execution in Multiple Issue Processors?.’’ Keith I. Farkas, Norman P. Jouppi, and Paul Chow. WRL Research Report 94/8, December 1994. ‘‘Drip: A Schematic Drawing Interpreter.’’ Ramsey W. Haddad. WRL Research Report 95/1, March 1995. ‘‘Recursive Layout Generation.’’ Louis M. Monier, Jeremy Dion. WRL Research Report 95/2, March 1995. ‘‘Contour: A Tile-based Gridless Router.’’ Jeremy Dion, Louis M. Monier. WRL Research Report 95/3, March 1995. ‘‘The Case for Persistent-Connection HTTP.’’ Jeffrey C. Mogul. WRL Research Report 95/4, May 1995. ‘‘Network Behavior of a Busy Web Server and its Clients.’’ Jeffrey C. Mogul. WRL Research Report 95/5, October 1995. ‘‘The Predictability of Branches in Libraries.’’ Brad Calder, Dirk Grunwald, and Amitabh Srivas- tava. WRL Research Report 95/6, October 1995. ‘‘Shared Memory Consistency Models: A Tutorial.’’ Sarita V. Adve, Kourosh Gharachorloo. WRL Research Report 95/7, September 1995. ‘‘Eliminating Receive Livelock in an Interrupt-driven Kernel.’’ Jeffrey C. Mogul and K. K. Ramakrishnan. WRL Research Report 95/8, December 1995. ‘‘Memory Consistency Models for Shared-Memory Multiprocessors.’’ Kourosh Gharachorloo. WRL Research Report 95/9, December 1995. ‘‘Register File Design Considerations in Dynamically Scheduled Processors.’’ Keith I. Farkas, Nor- man P. Jouppi, Paul Chow. WRL Research Report 95/10, November 1995. ‘‘Optimization in Permutation Spaces.’’ Silvio Tur- rini. WRL Research Report 96/1, November 1996. ‘‘Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory.’’ Daniel J. Scales, Kourosh Gharachorloo, and Chandramohan A. Thekkath. WRL Research Report 96/2, November 1996. ‘‘Efficient Procedure Mapping using Cache Line Coloring.’’ Amir H. Hashemi, David R. Kaeli, and Brad Calder. WRL Research Report 96/3, October 1996. ‘‘Optimizations and Placement with the Genetic Workbench.’’ Silvio Turrini. WRL Research Report 96/4, November 1996. ‘‘Memory-system Design Considerations for Dynamically-scheduled Processors.’’ Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic. WRL Research Report 97/1, February 1997. ‘‘Performance of the Shasta Distributed Shared Memory Protocol.’’ Daniel J. Scales and Kourosh Gharachorloo. WRL Research Report 97/2, February 1997. ‘‘Fine-Grain Software Distributed Shared Memory on SMP Clusters.’’ Daniel J. Scales, Kourosh Gharachorloo, and Anshu Aggarwal. WRL Research Report 97/3, February 1997. ‘‘Potential benefits of delta encoding and data com- pression for HTTP.’’ Jeffrey C. Mogul, Fred Douglis, Anja Feldmann, and Balachander Krishnamurthy. WRL Research Report 97/4, July 1997.

‘‘TCP/IP PrintServer: Print Server Protocol.’’ Brian K. Reid and Christopher A. Kent. WRL Tech- nical Note TN-4, September 1988. ‘‘TCP/IP PrintServer: Server Architecture and Im- plementation.’’ Christopher A. Kent. WRL Technical Note TN-7, November 1988. ‘‘Smart Code, Stupid Memory: A Fast X Server for a Dumb Color Frame Buffer.’’ Joel McCormack. WRL Technical Note TN-9, September 1989. ‘‘Why Aren’t Operating Systems Getting Faster As Fast As Hardware?.’’ John Ousterhout. WRL Technical Note TN-11, October 1989. ‘‘Mostly-Copying Garbage Collection Picks Up Generations and C++.’’ Joel F. Bartlett. WRL Technical Note TN-12, October 1989. ‘‘Characterization of Organic Illumination Systems.’’ Bill Hamburgen, Jeff Mogul, Brian Reid, Alan Eustace, Richard Swan, Mary Jo Doherty, and Joel Bartlett. WRL Technical Note TN-13, April 1989. ‘‘Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers.’’ Norman P. Jouppi. WRL Technical Note TN-14, March 1990. ‘‘Limits of Instruction-Level Parallelism.’’ David W. Wall. WRL Technical Note TN-15, Decem- ber 1990. ‘‘The Effect of Context Switches on Cache Perfor- mance.’’ Jeffrey C. Mogul and Anita Borg. WRL Technical Note TN-16, December 1990. ‘‘MTOOL: A Method For Detecting Memory Bot- tlenecks.’’ Aaron Goldberg and John Hen- nessy. WRL Technical Note TN-17, December 1990. ‘‘Predicting Program Behavior Using Real or Es- timated Profiles.’’ David W. Wall. WRL Tech- nical Note TN-18, December 1990. ‘‘Cache Replacement with Dynamic Exclusion.’’ Scott McFarling. WRL Technical Note TN-22, November 1991. ‘‘Boiling Binary Mixtures at Subatmospheric Pres- sures.’’ Wade R. McGillis, John S. Fitch, Wil- liam R. Hamburgen, Van P. Carey. WRL Technical Note TN-23, January 1992. ‘‘A Comparison of Acoustic and Infrared Inspection Techniques for Die Attach.’’ John S. Fitch. WRL Technical Note TN-24, January 1992. ‘‘TurboChannel Versatec Adapter.’’ David Boggs. WRL Technical Note TN-26, January 1992. ‘‘A Recovery Protocol For Spritely NFS.’’ Jeffrey C. Mogul. WRL Technical Note TN-27, April 1992. ‘‘Electrical Evaluation Of The BIPS-0 Package.’’ Patrick D. Boyle. WRL Technical Note TN-29, July 1992. ‘‘Transparent Controls for Interactive Graphics.’’ Joel F. Bartlett. WRL Technical Note TN-30, July 1992. ‘‘Design Tools for BIPS-0.’’ Jeremy Dion & Louis Monier. WRL Technical Note TN-32, December 1992. ‘‘Link-Time Optimization of Address Calculation on a 64-Bit Architecture.’’ Amitabh Srivastava and David W. Wall. WRL Technical Note TN-35, June 1993. ‘‘Combining Branch Predictors.’’ Scott McFarling. WRL Technical Note TN-36, June 1993. ‘‘Boolean Matching for Full-Custom ECL Gates.’’ Robert N. Mayo and Herve Touati. WRL Technical Note TN-37, June 1993. ‘‘Piecewise Linear Models for Rsim.’’ Russell Kao, Mark Horowitz. WRL Technical Note TN-40, December 1993. ‘‘Speculative Execution and Instruction-Level Paral- lelism.’’ David W. Wall. WRL Technical Note TN-42, March 1994.

ware.’’ Joel F. Bartlett. WRL Technical Note TN-43, December 1994. ‘‘ATOM: A Flexible Interface for Building High Per- formance Program Analysis Tools.’’ Alan Eus- tace and Amitabh Srivastava. WRL Technical Note TN-44, July 1994. ‘‘Circuit and Process Directions for Low-Voltage Swing Submicron BiCMOS.’’ Norman P. Jouppi, Suresh Menon, and Stefanos Sidiropoulos. WRL Technical Note TN-45, March 1994. ‘‘Experience with a Wireless World Wide Web Client.’’ Joel F. Bartlett. WRL Technical Note TN-46, March 1995. ‘‘I/O Component Characterization for I/O Cache Designs.’’ Kathy J. Richardson. WRL Tech- nical Note TN-47, April 1995. ‘‘Attribute caches.’’ Kathy J. Richardson, Michael J. Flynn. WRL Technical Note TN-48, April 1995. ‘‘Operating Systems Support for Busy Internet Ser- vers.’’ Jeffrey C. Mogul. WRL Technical Note TN-49, May 1995. ‘‘The Predictability of Libraries.’’ Brad Calder, Dirk Grunwald, Amitabh Srivastava. WRL Technical Note TN-50, July 1995. ‘‘Simultaneous Multithreading: A Platform for Next- generation Processors.’’ Susan J. Eggers, Joel Emer, Henry M. Levy, Jack L. Lo, Rebecca Stamm and Dean M. Tullsen. WRL Technical Note TN-52, March 1997. ‘‘Reducing Compulsory and Capacity Misses.’’ Norman P. Jouppi. WRL Technical Note TN-53, August 1990. ‘‘The Itsy Pocket Computer Version 1.5: User’s Manual.’’ Marc A. Viredaz. WRL Technical Note TN-54, July 1998. ‘‘The Memory Daughter-Card Version 1.5: User’s Manual.’’ Marc A. Viredaz. WRL Technical Note TN-55, July 1998.

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