Intel DUAL-CORE - UPDATE REV 010 Specification

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Identification Information .................................................................................................... 15 Errata ............................................................................................................................... 17 Specification Changes ......................................................................................................... 55 Specification Clarifications ................................................................................................... 56 Documentation Changes ...................................................................................................... 57

March 2007 316515 -003 • Updated erratum AN45 • Updated Summary Table of Changes April 2007 316515 -004 • Updated Summary Table of Changes July 2007 316515 -005 • Added processors for the Mobile 965 Express Chipset Family • Added M-0 stepping errata August 2007 316515 -006 • Added Processors based on the Intel Mobile 965 series chipset. • Added M-0 Errata and Microcode in separate tables • Removed Errata AN11, AN19, AN21, AN42, AN55, AN63, AN 69, AN72, AN74, AN79, AN83, AN96, AN104, AN5S and AN11S. • Updated Errata AN45 September 2007 316515 -007 • Added AN106 – AN109 October 2007 316515 -008 • Added AN110 November 2007 316515 -009 • Updated Summary Table of Changes - Added AU - AY • Updated AN34 • Added AN111 December 2007 316515 -010 • Added AN112 November 2010 §

the following Affected Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools. Information types defined in the Nomenclature section of this document are consolidated into this update document and are no longer published in other documents. This document may also contain information that has not been previously published. Affected Documents Document Title Document Number/Location Intel® Pentium® Dual-Core Processor Mobile Processor Datasheet 316519 Intel® Pentium® Dual-Core Processor for Intel® 965 Express Chipset Family Datasheet 318125 Related Documents Document Title Document Number/Location Debug Port Design Guide for Crestline and Intel® 945PM/GM/GT and 940GML Express Chipset Systems Note Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture 253665 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference, A-M 253666 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B: Instruction Set Reference, N-Z 253667 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide 253668 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide 253669 Intel® 64 and IA-32 Architectures Optimization Reference Manual 248966 Intel® 64 and IA-32 Architectures Optimization Reference Manual Documentation Changes 252046

differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors. Errata may cause the products’ behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications. Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications. Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications. Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). §

Specification Update 7 Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Processor steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations: Codes Used in Summary Table Stepping X: Erratum, Specification Change or Clarification that applies to this stepping. (No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping. Status Doc: Document change or update that will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum. Shaded: This item is either new or modified from the previous version of the document.

8 Specification Update Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000Δ sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.80 GHz E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Dual-Core Intel® Xeon® processor 5000Δ series J = 64-bit Intel® Xeon® processor MP with 1-MB L2 cache K = Mobile Intel® Pentium® III processor L = Intel® Celeron® D processor M = Mobile Intel® Celeron® processor N = Intel ® Pentium® 4 processor O = Intel ® Xeon® processor MP P = Intel ® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm process technology R = Intel® Pentium® 4 processor on 90-nm process S = 64-bit Intel® Xeon® processor with 800-MHz system bus (1-MB and 2-MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor–M U = 64-bit Intel® Xeon® processor MP with up to 8-MB L3 cache V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA Package W= Intel® Celeron®-M processor X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel® Processors A100 and A110 with 512-kB L2 cache Y = Intel® Pentium® M processor Z = Mobile Intel® Pentium® 4 processor with 533-MHz system bus AA= Intel® Pentium® D Processor 900Δ Sequence and Intel® Pentium® processor Extreme Edition 955Δ, 965Δ AB= Intel® Pentium® 4 processor 6x1 sequence AC= Intel® Celeron® processor in 478-pin package AD = Intel® Celeron® D processor on 65-nm process AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65-nm process AF = Dual-Core™ Intel® Xeon® processor LV AG = Dual-Core Intel® Xeon® processor 5100Δ series AH= Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor technology AI = Intel® Core™2 Extreme processor X6800Δ and Intel® Core™2 Duo Desktop processor E6000Δ and E4000Δ sequence AJ = Quad-Core Intel® Xeon® processor 5300Δ series

Specification Update 9 AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6000 sequence AL = Dual-Core Intel® Xeon® processor 7100 Δ series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® Dual-Core processor AO = Quad-Core Intel® Xeon® processor 3200Δ series AP = Dual-Core Intel® Xeon® processor 3000Δ series AQ = Intel® Pentium® Dual-Core Desktop processor E2000Δ sequence AR = Intel® Celeron® Processor 500Δ series AS = Intel® Xeon® processor 7200, 7300Δ series AT = Intel® Celeron® processor 200 series AU = Mobile Value Celeron AV = Intel® Core™2 Extreme Processor QX9000 Sequence and Intel® Core™2 Quad Processor Q9000 Sequence processor AX = Quad-Core Intel® Xeon® Processor 5400 Series AY = Wolfdale DP Note: Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Errata for Intel® Pentium® Dual-Core Mobile Processors Number D0 M0 Plans ERRATA AN1 X Fixed FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect FPU Operand Pointer AN2 X X No Fix Code Segment Limit Violation May Occur on 4-Gbyte Limit Check AN3 Erratum Removed AN4 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations AN5 X Fixed Memory Aliasing with Inconsistent A and D Bits May Cause Processor Deadlock AN6 X X No Fix VM Bit Is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86) AN7 X Fixed Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated MTRR (Memory Type Range Register) Is UC (Uncacheable) May Consolidate to UC AN8 X Fixed FPU Operand Pointer May Not Be cleared following FINIT/FNINIT AN9 X Fixed LTR Instruction May Result in Unexpected Behavior AN10 X Fixed Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May Cause General Protection (#GP) Exception if the Reserved Bits are Set to One AN11 Fixed Erratum Removed

10 Specification Update Number D0 M0 Plans ERRATA AN12 X Fixed FP Inexact-Result Exception Flag May Not Be Set AN13 X Fixed A Locked Data Access that Spans Across Two Pages May Cause the System to Hang AN14 X X No Fix MOV To/From Debug Registers Causes Debug Exception AN15 X X No Fix INIT Does Not Clear Global Entries in the TLB AN16 X Fixed Use of Memory Aliasing with Inconsistent Memory Type May Cause System Hang AN17 X Fixed Machine Check Exception May Occur when Interleaving Code Between Different Memory Types AN18 Erratum removed AN19 Erratum removed AN20 X X No Fix LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly Deassert AN21 Erratum removed AN22 X X No Fix Last Branch Records (LBR) Updates May be Incorrect After a Task Switch AN23 X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single- bit L2 ECC Errors May be Incorrect AN24 X Fixed Disabling of Single-step On Branch Operation May be Delayed following a POPFD Instruction AN25 X Fixed Performance Monitoring Counters that Count External Bus Events May Report Incorrect Values after Processor Power State Transitions AN26 X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR AN27 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation Above 4-G Limit AN28 X Fixed Performance Monitoring Events for Retired Floating Point Operations (C1h) May Not be Accurate AN29 X X No Fix DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired (Event CFH) AN30 X Fixed Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction before Restoring the Architectural State from SMRAM AN31 X Fixed Data Breakpoint/Single Step on MOV SS/POP SS May be Lost after Entry into SMM AN32 X Fixed CS Limit Violation on RSM May be Serviced before Higher Priority Interrupts/Exceptions AN33 Erratum removed AN34 X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts

Specification Update 11 Number D0 M0 Plans ERRATA AN35 X X No Fix Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts AN36 Erratum removed AN37 X X No Fix The Processor May Report a #TS Instead of a #GP Fault AN38 X Fixed BTS Message May be Lost when the STPCLK# Signal is Active AN39 X Fixed Certain Performance Monitoring Counters Related to Bus, L2 Cache and Power Management are Inaccurate AN40 X X No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred AN41 X X No Fix IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly AN42 Erratum removed AN43 Erratum removed AN44 X Fixed Logical Processors May Not Detect Write-Back (WB) Memory Writes AN45 X X No Fix LER MSRs May be Incorrectly Updated. AN46 X Fixed SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers AN47 X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt AN48 X X No Fix Using 2M/4M pages When A20M# Is Asserted May Result in Incorrect Address Translations AN49 X Fixed Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural Performance Monitoring) Specification AN50 X X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation AN51 X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate AN52 X X No Fix #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute Disable Bit is Not Supported AN53 X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AN54 X Fixed SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC) Event May Cause Unexpected Behavior AN55 No Fix Erratum Removed AN56 X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware AN57 X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue

12 Specification Update Number D0 M0 Plans ERRATA AN58 X X No Fix MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data after a Machine Check Exception (MCE) AN59 X Fixed Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior AN60 X X No Fix Code Breakpoint May Be Taken after POP SS Instruction if It Is Followed by an Instruction that Faults AN61 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update AN62 X X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM AN63 No Fix Erratum Removed AN64 X X No Fix Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior AN65 X X No Fix A Thermal Interrupt is Not Generated when the Current Temperature is Invalid AN66 X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate AN67 X X No Fix The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception AN68 X X No Fix BTM/BTS Branch-From Instruction Address May Be Incorrect for Software Interrupts AN69 Erratum removed AN70 X X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled AN71 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame AN72 Erratum removed AN73 X X No Fix Unaligned Accesses to Paging Structures May Cause the Processor To Hang AN74 No Fix Erratum Removed AN75 X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete Under Certain Conditions AN76 X X No Fix Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault AN77 X Fixed Performance Monitoring Events for Hardware Prefetch Requests (4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not be Accurate AN78 X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown AN79 X No Fix Erratum Removed AN80 X X No Fix Store Ordering May be Incorrect between WC and WP Memory Types

Specification Update 13 Number D0 M0 Plans ERRATA AN81 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions AN82 X No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May Be Incorrect AN83 No Fix Erratum Removed AN84 X No Fix Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions AN85 X No Fix EIP May Be Incorrect after Shutdown in IA-32e Mode AN86 X No Fix Upper 32 bits of ‘From’ Address Reported through BTMs or BTSs May Be Incorrect AN87 X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions AN88 X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode AN89 X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early AN90 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception AN91 X No Fix PMI May Be Delayed to Next PEBS Event AN92 X No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP AN93 X No Fix B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint AN94 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values AN95 X No Fix Performance Monitoring Events for L1 and L2 Miss May Not Be Accurate AN96 No Fix Erratum Removed AN97 X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction AN98 X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI AN99 X No Fix Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF AN100 X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count AN101 X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware AN102 X No Fix A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask AN103 X No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR Information AN104 No Fix Erratum Removed

14 Specification Update Number D0 M0 Plans ERRATA AN105 X No Fix BIST Failure after Reset AN106 X X No Fix Instruction Fetch May Cause a Livelock during Snoops of the L1 Data Cache AN107 X X No Fix Use of Memory Aliasing with Inconsistent Memory Type May Cause a System Hang or a Machine Check Exception AN108 X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations AN109 X X No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations AN110 X No Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results AN111 X X Plan Fix NMIs May Not Be Blocked by a VM-Entry Failure AN112 X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results Number SPECIFICATION CHANGES There are no Specification Changes in this Specification Update revision. Number SPECIFICATION CLARIFICATIONS There are no Specification Clarifications in this Specification Update revision. Number DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision. §

Figure 1. Intel® Pentium® Dual-Core Mobile Processor on 65-nm Process (Micro- FCPGA/FCBGA) S-Spec Markings Table 1. Pentium Dual-Core Mobile Processor on 65-nm Process Identification Information QDF/S- SPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes SL9VX T2060 Micro-FCPGA D-0 06ECh 533 1.6/800 1 SL9VY T2080 Micro-FCPGA D-0 06ECh 533 1.73/800 1 SLAEC T2310 Micro-FCPGA M-0 06FDh 533 1.46/800 1 SLA4K T2330 Micro-FCPGA M-0 06FDh 533 1.60/800 1 NOTES: 1. VCC_CORE=1.2125 V-1.025 V for HFM Range/LFM.

Information for 965 Express Chipset Family QDF/S- SPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes SLAEC T2310 Micro-FCPGA M-0 06FDh 533 1.46/800 1 SLA4J T2370 Micro-FCPGA M-0 06FDh 533 1.73/800 1 SLA4K T2330 Micro-FCPGA M-0 06FDh 533 1.60/800 1 NOTES: 1. VCC_CORE=1.2125 V-1.025 V for HFM Range/LFM. §

Numeric Exception with Incorrect FPU Operand Pointer Problem: If execution of an FST (Store Floating Point Value) instruction would generate both numeric and Null segment exceptions, the numeric exceptions may be taken first and with the Null x87 FPU Instruction Operand (Data) Pointer. Implication: Due to this erratum, on an FST instruction the processor reports a numeric exception instead of reporting an exception because of a Null segment. If the numeric exception handler tries to access the FST data it will get a #GP fault. Intel has not observed this erratum with any commercially available software, or system. Workaround: The numeric exception handler should check the segment and if it is Null avoid further access to the data that caused the fault. Status: For the steppings affected, see the Summary Tables of Changes. AN2. Code Segment Limit Violation May Occur on 4-Gbyte Limit Check Problem: Code Segment limit violation may occur on 4-Gbyte limit check when the code stream wraps around in a way that one instruction ends at the last byte of the segment and the next instruction begins at 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code that wraps around segment limit. Status: For the steppings affected, see the Summary Tables of Changes.

Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data size or may observe memory ordering violations. Implication: Upon crossing the page boundary the following may occur, dependent on the new page memory type: • UC the data size of each write will now always be 8 bytes, as opposed to the original data size. • WP the data size of each write will now always be 8 bytes, as opposed to the original data size and there may be a memory ordering violation. • WT there may be a memory ordering violation. Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC, WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled. Status: For the steppings affected, see the Summary Tables of Changes. AN5. Memory Aliasing with Inconsistent A and D Bits May Cause Processor Deadlock Problem: In the event that software implements memory aliasing by having two Page Directory Entries (PDEs) point to a common Page Table Entry (PTE) and the Accessed and Dirty bits for the two PDEs are allowed to become inconsistent the processor may become deadlocked. Implication: This erratum has not been observed with commercially available software. Workaround: Software that needs to implement memory aliasing in this way should manage the consistency of the Accessed and Dirty bits. Status: For the steppings affected, see the Summary Tables of Changes.

Virtual-8086 (VM86) Problem: Following a task switch to any fault handler that was initiated while the processor was in VM86 mode, if there is an additional fault while servicing the original task switch then the VM bit will be incorrectly cleared in EFLAGS, data segments will not be pushed and the processor will not return to the correct mode upon completion of the second fault handler via IRET. Implication: When the OS recovers from the second fault handler, the processor will no longer be in VM86 mode. Normally, operating systems should prevent interrupt task switches from faulting, thus the scenario should not occur under normal circumstances. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN7. Page With PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated MTRR (Memory Type Range Register) Is UC (Uncacheable) May Consolidate to UC Problem: A page whose PAT memory type is USWC while the relevant MTRR memory type is UC, the consolidated memory type may be treated as UC (rather than WC as specified in Intel® 64 and IA-32 Architectures Software Developer's Manual). Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This may have a negative performance impact. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN8. FPU Operand Pointer May Not Be Cleared Following FINIT/FNINIT Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87 FPU Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector (both fields form the FPUDataPointer). Saving the floating point environment with FSTENV, FNSTENV, or floating point state with FSAVE, FNSAVE or FXSAVE before an intervening FP instruction may save un-initialized values for the FPUDataPointer. Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point image structure may appear to be random values. Executing any non-control FP instruction with memory operand will initialize the FPUDataPointer. Intel has not observed this erratum with any commercially available software. Workaround: After initialization, do not expect a floating point state saved memory image to be correct, until at least one non-control FP instruction with a memory operand has been executed. Status: For the steppings affected, see the Summary Tables of Changes.

Problem: Under certain circumstances an LTR (Load Task Register) instruction may result in an unexpected behavior if all the following conditions are met: 1. Invalid data selector of the TR (Task Register) resulting with either #GP (General Protection Fault) or #NP (Segment Not Present Fault). 2. GDT (Global Descriptor Table) is not 8-bytes aligned. Implication: If all conditions have been met then under certain circumstances LTR instruction may result in system hang, memory corruption or other unexpected behavior. This erratum has not been observed in commercial operating systems or software. Workaround: Operating system software should align GDT to 8-bytes, as recommended in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide. For performance reasons, GDT is typically aligned to 8-bytes. Status: For the steppings affected, see the Summary Tables of Changes. AN10. Invalid Entries In Page-Directory-Pointer-Table Register (PDPTR) May Cause General Protection (#GP) Exception If the Reserved Bits Are Set to One Problem: Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the reserved bits set to one may cause a General Protection (#GP) exception. Implication: Intel has not observed this erratum with any commercially available software. Workaround: Do not set the reserved bits to one when PDPTR entries are invalid. Status: For the steppings affected, see the Summary Tables of Changes. AN11. Erratum removed

Problem: When the result of a floating-point operation is not exactly represented in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs. However, other actions taken by the processor (invoking the software exception handler if the exception is unmasked) are not affected. This erratum can only occur if the floating-point operation which causes the precision exception is immediately followed by one of the following instructions: • FST m32real • FST m64real • FSTP m32real • FSTP m64real • FSTP m80real • FIST m16int • FIST m32int • FISTP m16int • FISTP m32int • FISTP m64int Note that even if this combination of instructions is encountered, there is also a dependency on the internal pipelining and execution state of both instructions in the processor. Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it happens frequently, and produces a rounded result acceptable to most applications. The PE bit of the FPU status word may not always be set upon receiving an inexact- result exception. Thus, if these exceptions are unmasked, a floating-point error exception handler may not recognize that a precision exception occurred. Note that this is a “sticky” bit, i.e., once set by an inexact-result condition, it remains set until cleared by software. Workaround: This condition can be avoided by inserting either three NOPs or three non-floating- point non-Jcc instructions between the two floating-point instructions. Status: For the steppings affected, see the Summary Tables of Changes.

System to Hang Problem: An instruction with lock data access that spans across two pages may, given some rare internal conditions, hang the system. Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available software or system. Workaround: A locked data access should always be aligned. Status: For the steppings affected, see the Summary Tables of Changes. AN14. MOV To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is executed to/from a debug register, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead. Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to execute a MOV on debug registers in V86 mode, a debug exception will be generated instead of the expected general-protection fault. Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally set and used by debuggers. The debug exception handler should check that the exception did not occur in V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed to the general-protection exception handler. Status: For the steppings affected, see the Summary Tables of Changes. AN15. INIT Does Not Clear Global Entries in the TLB Problem: INIT may not flush a TLB entry when: 1. The processor is in protected mode with paging enabled and the page global enable flag is set (PGE bit of CR4 register) 2. G bit for the page table entry is set 3. TLB entry is present in TLB when INIT occurs Implication: Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left in TLB after INIT. Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE) registers before writing to memory early in BIOS code to clear all the global entries from TLB. Status: For the steppings affected, see the Summary Tables of Changes.

System Hang Problem: Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang. This would occur if one of the addresses is non-cacheable used in code segment and the other a cacheable address. If the cacheable address finds its way in instruction cache, and non-cacheable address is fetched in IFU, the processor may invalidate the non-cacheable address from the fetch unit. Any micro-architectural event that causes instruction restart will expect this instruction to still be in fetch unit and lack of it will cause system hang. Implication: This erratum has not been observed with commercially available software. Workaround: Although it is possible to have a single physical page mapped by two different linear addresses with different memory types, Intel has strongly discouraged this practice as it may lead to undefined results. Software that needs to implement memory aliasing should manage the memory type consistency. Status: For the steppings affected, see the Summary Tables of Changes. AN17. Machine Check Exception May Occur When Interleaving Code between Different Memory Types Problem: A small window of opportunity exists where code fetches interleaved between different memory types may cause a machine check exception. A complex set of micro- architectural boundary conditions is required to expose this window. Implication: Interleaved instruction fetches between different memory types may result in a machine check exception. The system may hang if machine check exceptions are disabled. Intel has not observed the occurrence of this erratum while running commercially available applications or operating systems. Workaround: Software can avoid this erratum by placing a serializing instruction between code fetches between different memory types. Status: For the steppings affected, see the Summary Tables of Changes.

Unexpectedly Deassert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly deassert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially available systems or software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN21. Erratum removed. AN22. Last Branch Records (LBR) Updates May Be Incorrect after a Task Switch Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to the LBR_TO value. Implication: The LBR_FROM will have the incorrect address of the Branch Instruction. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN23. Address Reported By Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May Be Incorrect Problem: When correctable single-bit ECC errors occur in the L2 cache the address is logged in the MCA address register (MCi_ADDR). Under some scenarios, the address reported may be incorrect. Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2 ECC errors Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

following a POPFD Instruction Problem: Disabling of Single-step On Branch Operation may be delayed, if the following conditions are met: “Single Step On Branch Mode” is enabled (DebugCtlMSR.BTF and EFLAGS.TF are set) POPFD used to clear EFLAGS.TF A jump instruction (JMP, Jcc, etc.) is executed immediately after POPFD Implication: Single-step On Branch mode may remain in effect for one instruction after the POPFD instruction disables it by clearing the EFLAGS.TF bit. Workaround: There is no workaround for Single-Step operation in commercially available software. The workaround for custom software is to execute at least one instruction following POPFD before issuing a JMP instruction. Status: For the steppings affected, see the Summary Tables of Changes. AN25. Performance Monitoring Counters That Count External Bus Events May Report Incorrect Values after Processor Power State Transitions Problem: Performance monitoring counters that count external bus events operate when the processor is in the Active state (C0). If a processor transitions to a new power state, these Performance monitoring counters will stop counting, even if the event being counted remains active. Implication: After transitioning between processor power states, software may observe incorrect counts in Performance monitoring counters that count external bus events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Last Exception Record (LER) MSR Problem: The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is zero after executing the following instructions: VERR (ZF=0 indicates unsuccessful segment read verification) VERW (ZF=0 indicates unsuccessful segment write verification) LAR (ZF=0 indicates unsuccessful access rights load) LSL (ZF=0 indicates unsuccessful segment limit load) Implication: The value of the LER MSR may be inaccurate if VERW/VERR/LSL/LAR instructions are executed after the occurrence of an exception. Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR before executing VERW/VERR/LSL/LAR instructions. Status: For the steppings affected, see the Summary Tables of Changes. AN27. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4G limit (0ffffffffh) may not signal a #GP fault. Implication: When such memory accesses occur, the system may not issue a #GP fault. Workaround: Software should ensure that memory accesses do not occur above the 4G limit (0ffffffffh). Status: For the steppings affected, see the Summary Tables of Changes. AN28. Performance Monitoring Events for Retired Floating Point Operations (C1h) May Not Be Accurate Problem: Performance monitoring events that count retired floating point operations may be too high. Implication: The Performance Monitoring Event may have an inaccurate count. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired (Event CFh) Problem: Performance monitoring for Event CFH normally increments on saturating SIMD instruction retired. Regardless of DR7 programming, if the linear address of a retiring memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in DR3, the CFH counter may be incorrectly incremented. Implication: The value observed for performance monitoring count for saturating SIMD instructions retired may be too high. The size of error is dependent on the number of occurrences of the conditions described above, while the counter is active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN30. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM Instruction before Restoring the Architectural State from SMRAM Problem: The Resume from System Management Mode (RSM) instruction does not flush global pages from the Data Translation Look-Aside Buffer (DTLB) prior to reloading the saved architectural state. Implication: If SMM turns on paging with global paging enabled and then maps any of linear addresses of SMRAM using global pages, RSM load may load data from the wrong location. Workaround: Do not use global pages in system management mode. Status: For the steppings affected, see the Summary Tables of Changes.

Entry into SMM Problem: Data Breakpoint/Single Step exceptions are normally blocked for one instruction following MOV SS/POP SS instructions. Immediately after executing these instructions, if the processor enters SMM (System Management Mode), upon RSM (resume from SMM) operation, normal processing of Data Breakpoint/Single Step exceptions is restored. Because of this erratum, Data Breakpoints/Single step exceptions on MOVSS/POPSS instructions may be lost under one of the following conditions. • Following SMM entry and after RSM, the next instruction to be executed is HLT or MWAIT • SMM entry after executing MOV SS/POP SS is the result of executing an I/O instruction that triggers a synchronous SMI (System Management Interrupt). Implication: Data Breakpoints/Single step operation on MOV SS/POP SS instructions may be unreliable in the presence of SMI. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. AN32. CS Limit Violation on RSM May Be Serviced before Higher Priority Interrupts/Exceptions Problem: When the processor encounters a CS (Code Segment) limit violation, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced. Because of this erratum, if RSM (Resume from System Management Mode) returns to execution flow where a CS limit violation occurs, the #GP fault may be serviced before a higher priority Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc). Implication: Operating systems may observe a #GP fault being serviced before higher priority interrupts and Exceptions. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. AN33. Erratum removed

before Higher Priority Interrupts Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are serviced immediately after the STI instruction is executed. Because of this erratum, if following STI, an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel SpeedStep® Technology transitions or Intel® Thermal Monitor 1 events occur, the pending #MF may be serviced before higher priority interrupts. Implication: Software may observe #MF being serviced before higher priority interrupts. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN35. Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts Problem: Software can enable DTS thermal interrupts by programming the thermal threshold and setting the respective thermal interrupt enable bit. When programming DTS value, the previous DTS threshold may be crossed. This will generate an unexpected thermal interrupt. Implication: Software may observe an unexpected thermal interrupt occur after reprogramming the thermal threshold. Workaround: In the ACPI/OS implement a workaround by temporarily disabling the DTS threshold interrupt before updating the DTS threshold value. Status: For the steppings affected, see the Summary Tables of Changes. AN36. Erratum removed AN37. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some circumstances, when STPCLK# becomes active, a pending BTS (Branch Trace Store) message may be either lost and not written or written with corrupted branch address to the Debug Store area. Implication: BTS messages may be lost in the presence of STPCLK# assertions. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN39. Certain Performance Monitoring Counters Related to Bus, L2 Cache and Power Management Are Inaccurate Problem: All Performance Monitoring Counters in the ranges 21H-3DH and 60H-7FH may have inaccurate results up to ±7. Implication: There may be a small error in the affected counts. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN40. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory- based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g., CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered. This may cause interrupts whose priority is lower than the initial TPR, but higher than the final TPR, to not be serviced until the interrupt enabled flag is finally set, i.e., by STI instruction. Interrupts will remain pending and are not lost. Implication: In this example the processor may allow interrupts to be accepted but may delay their service. Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC register write. This will force the store to the APIC register before any subsequent instructions are executed. No commercial operating system is known to be impacted by this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

Problem: The IO_SMI bit in SMRAM’s location 7FA4H is set to 1 by the CPU to indicate a System Management Interrupt (SMI) occurred as the result of executing an instruction that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by: • A non-I/O instruction. • SMI is pending while a lower priority event interrupts • A REP I/O read • An I/O read that redirects to MWAIT. • In systems supporting Intel® Virtualization Technology a fault in the middle of an IO operation that causes a VM Exit Implication: SMM handlers may get false IO_SMI indication. Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I/O port. The SMM handler must not restart an I/O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I/O port address. Status: For the steppings affected, see the Summary Tables of Changes. AN42. Erratum removed AN43. Erratum removed. AN44. Logical Processors May Not Detect Write-Back (WB) Memory Writes Problem: Multiprocessor systems may use polling of memory semaphores to synchronize software activity. Because of this erratum, if a logical processor is polling a WB memory location while it is being updated by another logical processor, the update may not be detected. Implication: System may livelock due to polling loop and undetected semaphore change. Intel has not observed this erratum on commercially available systems. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AN45. Erratum removed

Selector” to SS and CS Registers Problem: According to the processor specification, attempting to load a Null segment selector into the CS and SS segment registers should generate a General Protection Fault (#GP). Although loading a Null segment selector to the other segment registers is allowed, the processor will generate an exception when the segment register holding a Null selector is used to access memory. However, the SYSENTER instruction can implicitly load a Null value to the SS segment selector. This can occur if the value in SYSENTER_CS_MSR is between FFF8h and FFFBh when the SYSENTER instruction is executed. This behavior is part of the SYSENTER/SYSEXIT instruction definition; the content of the SYSTEM_CS_MSR is always incremented by 8 before it is loaded into the SS. This operation will set the Null bit in the segment selector if a Null result is generated, but it does not generate a #GP on the SYSENTER instruction itself. An exception will be generated as expected when the SS register is used to access memory, however. The SYSEXIT instruction will also exhibit this behavior for both CS and SS when executed with the value in SYSENTER_CS_MSR between FFF0h and FFF3h, or between FFE8h and FFEBh, inclusive. Implication: These instructions are intended for operating system use. If this erratum occurs (and the OS does not ensure that the processor never has a Null segment selector in the SS or CS segment registers), the processor’s behavior may become unpredictable, possibly resulting in system failure. Workaround: Do not initialize the SYSTEM_CS_MSR with the values between FFF8h and FFFBh, FFF0h and FFF3h, or FFE8h and FFEBh before executing SYSENTER or SYSEXIT. Status: For the steppings affected, see the Summary Tables of Changes. AN47. Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious vector should not be used when writing the LVT. Status: For the steppings affected, see the Summary Tables of Changes.

Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte. However, if all of the following conditions are met, address bit 20 may not be masked. • paging is enabled • a linear address has bit 20 set • the address references a large page • A20M# is enabled Implication: When A20M# is enabled and an address references a large page the resulting translated physical address may be incorrect. This erratum has not been observed with any commercially available operating system. Workaround: Operating systems should not allow A20M# to be enabled if the masking of address bit 20 could be applied to an address that references a large page. A20M# is normally only used with the first megabyte of memory. Status: For the steppings affected, see the Summary Tables of Changes. AN49. Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural Performance Monitoring) Specification Problem: According to the Architectural Performance Monitoring specification the two PerfMon counters can be disabled/enabled through the corresponding Counter Enable bit [22] of IA32_CR_PerfEvtSel0/1. Due to this erratum the following occurs: 1. bit [22] of IA32_CR_PerfEvtSel0 enables/disables both counters 2. bit [22] of IA32_CR_PerfEvtSel1 doesn't function Implication: Software cannot enable/disable only one of the two PerfMon counters through the corresponding Counter Enable bit [22] of IA32_CR_PerfEvtSel0/1. Workaround: Software should enable/disable both PerfMon counters together through Counter Enable bit [22] of IA32_CR_PerfEvtSel0 only. Alternatively, Software can effectively disable any one of the counters by clearing both Kernel and App bits [17:16] in the corresponding IA32_CR_PerfEvtSel0/1. Status: For the steppings affected, see the Summary Tables of Changes.

Invocation Problem: If any of the below circumstances occur it is possible that the load portion of the instruction will have executed before the exception handler is entered. 1. If an instruction that performs a memory load causes a code segment limit violation 2. If a waiting X87 floating-point instruction or MMX™ technology (MMX) instruction that performs a memory load has a floating-point exception pending 3. If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending Implication: In normal code execution where the target of the load operation is to write back memory there is no impact from the load being prematurely executed, nor from the restart and subsequent re-execution of that instruction by the exception handler. If the target of the load is to uncached memory that has a system side-effect, restarting the instruction may cause unexpected system behavior due to the repetition of the side-effect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may issue a memory load before getting the DNA exception. Workaround: Code which performs loads from memory that has side-effects can effectively workaround this behavior by using simple integer-based load instructions when accessing side-effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect memory. Status: For the steppings affected, see the Summary Tables of Changes. AN51. Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate Problem: The INST_RETIRED performance monitor may miscount retired instructions as follows: • Repeat string and repeat I/O operations are not counted when a hardware interrupt is received during or after the last iteration of the repeat flow. • VMLAUNCH and VMRESUME instructions are not counted. • HLT and MWAIT instructions are not counted. The following instructions, if executed during HLT or MWAIT events, are also not counted: a) RSM from a C-state SMI during an MWAIT instruction. b) RSM from an SMI during a HLT instruction. Implication: There may be a smaller than expected value in the INST_RETIRED performance monitoring counter. The extent to which this value is smaller than expected is determined by the frequency of the above cases. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

When Execute Disable Bit Is Not Supported Problem: #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor which does not support Execute Disable Bit functionality. Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN53. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB May Cause Unexpected Processor Behavior Problem: Updating a page table entry by changing R/W, U/S or P bits without TLB shootdown (as defined by the 4 step procedure in Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide), in conjunction with a complex sequence of internal processor micro-architectural events, may lead to unexpected processor behavior. Implication: This erratum may lead to livelock, shutdown or other unexpected processor behavior. Intel has not observed this erratum with any commercially available system. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN54. SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC) Event May Cause Unexpected Behavior Problem: An SSE or SSE2 streaming store that results in a Self-Modifying Code (SMC) event may cause unexpected behavior. The SMC event occurs on a full address match of code contained in L1 cache. Implication: Due to this erratum, any of the following events may occur: 1. A data access break point may be incorrectly reported on the instruction pointer (IP) just before the store instruction. 2. A non-cacheable store can appear twice on the external bus (the first time it will write only 8 bytes, the second time it will write the entire 16 bytes). Note: Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Problem: Logical processors normally resume program execution following the MWAIT, when another logical processor performs a write access to a WB cacheable address within the address range used to perform the MONITOR operation. Due to this erratum, a logical processor may not resume execution until the next targeted interrupt event or O/S timer tick following a locked store that spans across cache lines within the monitored address range. Implication: The logical processor that executed the MWAIT instruction may not resume execution until the next targeted interrupt event or O/S timer tick in the case where the monitored address is written by a locked store which is split across cache lines. Workaround: Do not use locked stores that span cache lines in the monitored address range. Status: For the steppings affected, see the Summary Tables of Changes. AN57. Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system. Workaround: Software should ensure at least one of the following is true when modifying shared data by multiple agents: • The shared data is aligned • Proper semaphores or barriers are used in order to prevent concurrent data accesses Status: For the steppings affected, see the Summary Tables of Changes.

Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data after a Machine Check Exception (MCE) Problem: When an MCE occurs during execution of a RDMSR instruction for MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock Count (IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may contain incorrect data. Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may return incorrect data. A subsequent reset will clear this condition. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN59. Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior Problem: Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses, each with different memory type. Memory type aliasing with the memory types WB and WT may cause the processor to perform incorrect operations leading to unpredictable behavior. Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable behavior. Intel chipset-based platforms are not affected by this erratum. Workaround: None identified. Intel does not support the use of WB and WT page memory type aliasing. Status: For the steppings affected, see the Summary Tables of Changes. AN60. Code Breakpoint May be Taken after POP SS Instruction If It Is followed by an Instruction That Faults Problem: A POP SS instruction should inhibit all interrupts including Code Breakpoints until after execution of the following instruction. This allows sequential execution of POP SS and MOV eSP, eBP instructions without having an invalid stack during interrupt handling. However, a code breakpoint may be taken after POP SS if it is followed by an instruction that faults, this results in a code breakpoint being reported on an unexpected instruction boundary since both instructions should be atomic. Implication: This can result in a mismatched Stack Segment and SP. Intel has not observed this erratum with any commercially available software, or system. Workaround: As recommended in the Intel® 64 and IA-32 Architectures Software Developer's Manual, the use "POP SS" in conjunction with "MOV eSP, eBP" will avoid the failure since the "MOV" will not fault. Status: For the steppings affected, see the Summary Tables of Changes.

Image Leads to Partial Memory Update Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32-bit mode. Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected but the memory state may be only partially saved or restored. Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and 32-bit mode memory limits. Status: For the steppings affected, see the Summary Tables of Changes. AN62. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM Problem: After a return from SMM (system management mode), the CPU will incorrectly update the LBR (last branch record) and the BTS (branch trace store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect. Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used. Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN63. Erratum removed. AN64. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior Problem: Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM. Status: For the steppings affected, see the Summary Tables of Changes.

Is Invalid Problem: When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of the programmed thresholds is crossed and the corresponding log bits become set. Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is crossed. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN66. Performance Monitoring Event FP_ASSIST May Not Be Accurate Problem: Performance monitoring event FP_ASSIST (11H) may be inaccurate as assist events will be counted twice per actual assist in the following specific cases: • FADD and FMUL instructions with a not a Number (NaN) operand and a memory operand. • FDIV instruction with zero operand value in memory In addition, an assist event may be counted when DAZ (Denormals-Are-Zeros) and FTZ (Flush-To-Zero) flags are turned on even though no actual assist occurs. Implication: The counter value for performance monitoring event FP_ASSIST (11H) may be larger than expected. The size of the error is dependent on the number of occurrences of the above condition while the event is active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN67. The BS Flag in DR6 May Be Set for Non-Single-Step #DB Exception Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8) of the EFLAGS Register is set and a #DB (Debug Exception) occurs due to one of the following: • DR7 GD (General Detect, bit 13) being bit set; • INT1 instruction; • Code breakpoint Implication: The BS flag may be incorrectly set for non-single-step #DB exception. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Incorrect for Software Interrupts Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software interrupt may result in the overwriting of BTM/BTS branch-from instruction address by the LBR (Last Branch Record) branch-from instruction address. Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN69. Erratum removed AN70. Single Step Interrupts with Floating Point Exception Pending May Be Mishandled Problem: In certain circumstances, when a floating point exception (#MF) is pending during single-step execution, processing of the single-step debug exception (#DB) may be mishandled. Implication: When this erratum occurs, #DB will be incorrectly handled as follows • #DB is signaled before the pending higher priority #MF (Interrupt 16) • #DB is generated twice on the same instruction Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes. AN71. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e. residual stack data as a result of processing the fault). Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction. Please refer to “Procedure Calls For Block-Structured Languages” in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture, for information on the usage of ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially-available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Hang Problem: When an unaligned access is performed on paging structure entries, accessing a portion of two different entries simultaneously, the processor may livelock. Implication: When this erratum occurs, the processor may live lock causing a system hang. Workaround: Do not perform unaligned access on paging structure entries. Status: For the steppings affected, see the Summary Tables of Changes. AN74. Erratum removed AN75. INVLPG Operations for Large (2M/4M) Pages May Be Incomplete under Certain Conditions Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer (TLB) entries for large pages (2M/4M) when both of the following conditions exist: • Address range of the page being invalidated spans several Memory Type Range Registers (MTRRs) with different memory types specified • INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an access that results in either A or D bits being set in a Page table Entry (PTE)) Implication: Stale Translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure that the memory type specified in the MTRRs is the same for the entire address range of the large page. Status: For the steppings affected, see the Summary Tables of Changes. AN76. Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A Bit) may be set for the subsequent page prior to general protection fault on code segment limit. Implication: When this erratum occurs, a non-accessed page, which is present in memory and follows a page that contains the code segment limit may be tagged as accessed. Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable page) as the last page of the segment or after the page that includes the code segment limit. Status: For the steppings affected, see the Summary Tables of Changes.

(4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not Be Accurate Problem: Performance monitoring events that count hardware prefetch requests and prefetch misses may not be accurate. Implication: This erratum may cause inaccurate counting for Hardware Prefetch Requests and Hardware Prefetch Request Cache Misses. Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable page) as the last page of the segment or after the page that includes the code segment limit. Status: For the steppings affected, see the Summary Tables of Changes. AN78. EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after Shutdown Problem: When the processor is going into shutdown due to an RSM inconsistency failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal may still be asserted. This may be observed if the processor is taken out of shutdown by NMI# Implication: A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0 and CR4. In addition the EXF4 signal may still be asserted. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN79. Erratum removed. AN80. Store Ordering May Be Incorrect between WC and WP Memory Types Problem: According to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do. Due to this erratum, WP stores may not drain the WC buffers. Implication: Memory ordering may be violated between WC and WP stores. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes.

Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if only a small number of MMX instructions (including EMMS) are executed immediately after the last FP instruction, a FP to MMX transition may not be counted. Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software. Workaround: None Identified Status: For the steppings affected, see the Summary Tables of Changes. AN82. Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May Be Incorrect Problem: Performance-Monitoring Counter PMH_PAGE_WALK is used to count the number of page walks resulting from Data Translation Look-Aside Buffer (DTLB) and Instruction Translation Look-Aside (ITLB) misses. Under certain conditions, this counter may be incorrect. Implication: There may be small errors in the accuracy of the counter. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN83. Erratum removed

Events under Certain Conditions Problem: Many Performance Monitoring Events require core-specificity, which specifies which core’s events are to be counted (local core, other core, or both cores). Due to this erratum, some Bus Performance Monitoring events may not count when the core- specificity is set to the local core. The following Bus Transaction Performance Monitor events are supposed to count all local transactions: • BUS_TRANS_ IO (Event: 6CH) – Will not count I/O level reads resulting from package resolved C-state • BUS_TRANS_ANY (Event: 70H) – Will not count Stop-Grants Implication: The count values for the affected events may be lower than expected. The degree of under count depends on the occurrence of erratum conditions while the affected events are active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN85. EIP May Be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be incorrect. This may be observed if the processor is taken out of shutdown state by NMI#. Implication: A processor that has been taken out of the shutdown state may have an incorrect EIP. The only software which would be affected is diagnostic software that relies on a valid EIP. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN86. Upper 32 bits of 'From' Address Reported through BTMs or BTSs May Be Incorrect Problem: When a far transfer switches the processor from 32-bit mode to IA-32e mode, the upper 32 bits of the 'From' (source) addresses reported through the BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may be incorrect. Implication: The upper 32 bits of the 'From' address debug information reported through BTMs or BTSs may be incorrect during this transition. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Higher Priority Interrupts/Exceptions Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume from System Management Mode) returns to execution flow that results in a Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher priority Interrupt or Exception (for example NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), etc.) Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. AN88. LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1’s. Subsequent BTS and BTM operations which report the LBR will also be incorrect. Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/interrupt. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN89. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early Problem: In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count greater than or equal to 248 may terminate early. Early termination may result in one of the following. • The last iteration not being executed • Signaling of a canonical limit fault (#GP) on the last iteration Implication: While in 64-bit mode, with count greater or equal to 248, repeat string operations CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel has not observed this erratum with any commercially available software. Workaround: Do not use repeated string operations with RCX greater than or equal to 248. Status: For the steppings affected, see the Summary Tables of Changes.

Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing the stack frame. Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame. Workaround: Software should not generate misaligned stack frames for use with IRET. Status: For the steppings affected, see the Summary Tables of Changes. AN91. PMI May Be Delayed to Next PEBS Event Problem: After a PEBS (Precise Event-Based Sampling) event, the PEBS index is compared with the PEBS threshold, and the index is incremented with every event. If PEBS index is equal to the PEBS threshold, a PMI (Performance Monitoring Interrupt) should be issued. Due to this erratum, the PMI may be delayed by one PEBS event. Implication: Debug Store Interrupt Service Routines may observe delay of PMI occurrence by one PEBS event. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN92. An Asynchronous MCE during a Far Transfer May Corrupt ESP Problem: If an asynchronous machine check occurs during an interrupt, call through gate, FAR RET or IRET and in the presence of certain internal conditions, ESP may be corrupted. Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a triple fault will occur due to the corrupted stack pointer, resulting in a processor shutdown. If the MCE is called with a stack switch, for example when the CPL (Current Privilege Level) was changed or when going through an interrupt task gate, then the corrupted ESP will be saved on the stack or in the TSS (Task State Segment), and will not be used. Workaround: Use an interrupt task gate for the machine check handler. Status: For the steppings affected, see the Summary Tables of Changes.

Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following sequence happens: 1. POP instruction to SS (Stack Segment) selector. 2. Next instruction is FP (Floating Point) that gets FP assist followed by code breakpoint. Implication: B0-B3 bits in DR6 may not be properly cleared. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN94. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: The SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may also count other types of instructions resulting in values higher than the number of actual retired SSE instructions. Implication: The event monitor instruction SIMD_INST_RETIRED may report count higher than expected. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN95. Performance Monitoring Events for L1 and L2 Miss May Not Be Accurate Problem: Performance monitoring events 0CBh with an event mask value of 02h or 08h (MEM_LOAD_RETIRED.L1_LINE_MISS or MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss events. Implication: These performance monitoring events may show a count which is lower than expected; the amount by which the count is lower is dependent on other conditions occurring on the same load that missed the cache. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes.

Counted Incorrectly for PMULUDQ Instruction Problem: Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select 0B3H, Umask 01H) counts the number of SIMD packed multiply micro-ops executed. The count for PMULUDQ micro-ops might be lower than expected. No other instruction is affected. Implication: The count value returned by the performance monitoring event SIMD_UOP_TYPE_EXEC.MUL may be lower than expected. The degree of undercount depends on actual occurrences of PMULUDQ instructions, while the counter is active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN98. Storage of PEBS Record Delayed Following Execution of MOV SS or STI Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow. Due to this erratum, if the counter overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is delayed by one instruction. Implication: When this erratum occurs, software may observe storage of the PEBS record being delayed by one instruction following execution of MOV SS or STI. The state information in the PEBS record will also reflect the one instruction delay. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes.

May Result in Improper Handling of Code #PF Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of the following conditions are met: • A PDE (Page Directory Entry) is modified without invalidating the corresponding TLB (Translation Look-aside Buffer) entry • Code execution transitions to a different code page such that both  The target linear address corresponds to the modified PDE  The PTE (Page Table Entry) for the target linear address has an A (Accessed) bit that is clear • One of the following simultaneous exception conditions is present following the code transition  Code #DB and code #PF  Code Segment Limit Violation #GP and code #PF Implication: Software may observe either incorrect processing of code #PF before code Segment Limit Violation #GP or processing of code #PF in lieu of code #DB. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AN100. Performance Monitoring Event MISALIGN_MEM_REF May Over Count Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the number of memory accesses that cross an 8-byte boundary and are blocked until retirement. Due to this erratum, the performance monitoring event MISALIGN_MEM_REF also counts other memory accesses. Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The extent of the over counting depends on the number of memory accesses retiring while the counter is active. Workaround: None Identified Status: For the steppings affected, see the Summary Tables of Changes.

Prevent Triggering of the Monitoring Hardware Problem: The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction. The hardware is triggered on subsequent memory store operations to the monitored address range. Due to this erratum, REP STOS/MOVS fast string operations to the monitored address range may prevent the actual triggering store to be propagated to the monitoring hardware. Implication: A logical processor executing an MWAIT instruction may not immediately continue program execution if a REP STOS/MOVS targets the monitored address range. Workaround: Software can avoid this erratum by not using REP STOS/MOVS store operations within the monitored address range. Status: For the steppings affected, see the Summary Tables of Changes. AN102. A Memory Access May Get a Wrong Memory Type Following a #GP Due to WRMSR to an MTRR Mask Problem: The TLB (Translation Lookaside Buffer) may indicate a wrong memory type on a memory access to a large page (2M/4M Byte) following the recovery from a #GP (General Protection Fault) due to a WRMSR to one of the IA32_MTRR_PHYSMASKn MSRs with reserved bits set. Implication: When this erratum occurs, a memory access may get an incorrect memory type leading to unexpected system operation. As an example, an access to a memory mapped I/O device may be incorrectly marked as cacheable, become cached, and never make it to the I/O device. Intel has not observed this erratum with any commercially available software. Workaround: Software should not attempt to set reserved bits of IA32_MTRR_PHYSMASKn MSRs. Status: For the steppings affected, see the Summary Tables of Changes. AN103. PMI While LBR Freeze Enabled May Result in Old/Out-of-Date LBR Information Problem: When Precise Event-Based Sampling (PEBS) is configured with Performance Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch Record (LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag (bit 11) to 1 in IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon the occurrence of a hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e. before the hardware PMI request). Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date LBR information that does not describe the last few branches before the PEBS sample that triggered the PMI. Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes.

Problem: The processor may show an erroneous BIST (built-in self test) result in bit [17] of EAX register when coming out of reset. Implication: When this erratum occurs, an erroneous BIST failure will be reported in EAX bit [17]. This failure can be ignored since it is not accurate. Workaround: It is possible for BIOS to workaround this erratum by masking off bit [17] of the EAX register after coming out of reset. Status: For the steppings affected, see the Summary Tables of Changes. AN106. Instruction Fetch May Cause a Livelock during Snoops of the L1 Data Cache Problem: A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

System Hang or a Machine Check Exception Problem: Software that implements memory aliasing by having more than one linear addresses mapped to the same physical page with different cache types may cause the system to hang or to report a machine check exception (MCE). This would occur if one of the addresses is non-cacheable and used in a code segment and the other is a cacheable address. If the cacheable address finds its way into the instruction cache, and the non-cacheable address is fetched in the IFU, the processor may invalidate the non- cacheable address from the fetch unit. Any micro-architectural event that causes instruction restart will be expecting this instruction to still be in the fetch unit and lack of it will cause a system hang or an MCE. Implication: This erratum has not been observed with commercially available software. Workaround: Although it is possible to have a single physical page mapped by two different linear addresses with different memory types, Intel has strongly discouraged this practice as it may lead to undefined results. Software that needs to implement memory aliasing should manage the memory type consistency Status: For the steppings affected, see the Summary Tables of Changes. AN108. A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations Problem: Under certain conditions, as described in the Software Developers Manual section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors", the processor may perform REP MOVS or REP STOS as write combining stores (referred to as “fast strings”) for optimal performance. FXSAVE may also be internally implemented using write combining stores. Due to this erratum, stores of a WB (write back) memory type to a cache line previously written by a preceding fast string/FXSAVE instruction may be observed before string/FXSAVE stores. Implication: A write-back store may be observed before a previous string or FXSAVE related store. Intel has not observed this erratum with any commercially available software. Workaround: Software desiring strict ordering of string/FXSAVE operations relative to subsequent write-back stores should add an MFENCE or SFENCE instruction between the string/FXSAVE operation and following store-order sensitive code such as that used for synchronization. Status: For the steppings affected, see the Summary Tables of Changes.

May Lead to Memory Ordering Violations Problem: Memory type aliasing occurs when a single physical page is mapped to two or more different linear addresses, each with different memory types. Memory type aliasing with a cacheable memory type and WC (write combining) may cause the processor to perform incorrect operations leading to memory ordering violations for WC operations. Implication: Software that uses aliasing between cacheable and WC memory types may observe memory ordering errors within WC memory operations. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered. Status: For the steppings affected, see the Summary Tables of Changes. AN110 RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a complex sequence of internal processor micro-architectural events, may lead to processor hang, or unexpected instruction execution results. Implication: In the above sequence, the processor may live lock or hang, or RSM instruction may restart the interrupted processor context through a nondeterministic EIP offset in the code segment, resulting in unexpected instruction execution, unexpected exceptions or system hang. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Please contact your Intel sales representative for availability. Status: For the steppings affected, see the Summary Tables of Changes. AN111 NMIs May Not Be Blocked by a VM-Entry Failure Problem: The Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 specifies that, following a VM-entry failure during or after loading guest state, “the state of blocking by NMI is what it was before VM entry.” If non-maskable interrupts (NMIs) are blocked and the “virtual NMIs” VM- execution control set to 1, this erratum may result in NMIs not being blocked after a VM-entry failure during or after loading guest state. Implication: VM-entry failures that cause NMIs to become unblocked may cause the processor to deliver an NMI to software that is not prepared for it. Workaround: VMM software should configure the virtual-machine control structure (VMCS) so that VM-entry failures do not occur. Status: For the steppings affected, see the Summary Tables of Changes.

Results Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IP- relative instruction result may be incorrect Implication: A register IP-relative instruction result may be incorrect and could cause software to read from or write to an incorrect memory location. This may result in an unexpected page fault or unpredictable system behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. §

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Documentation changes for the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volumes 1, 2A, 2B, 3A and 3B will be posted in a separate document, Intel® 64 and IA-32 Architectures Optimization Reference Manual Documentation Changes. §