Analog Devices ADuC7026 Reference Manual

Specifications

Brand:	Analog Devices
Category:	Motherboard
Model:	ADuC7026 (Reference Manual)
File Type:	PDF
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Pages:	12

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One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com

TABLE OF CONTENTS Evaluation Board Overview.......................................... 1 Evaluation Board Features........................................... 1 DIP Switch Link Options............................................... 2 External Connectors.................................................... 3 External Memory Interface.......................................... 5 Potentiometer Demonstration Circuit ......................... 6 Schematic.................................................................... 7 Parts List ..................................................................... 9 OVERVIEW The ADuC7026 evaluation board has the following features: • 2-Layer PCB (4”  5” form factor) • 9 V power supply regulated to 3.3 V on board • 4-pin UART header to connect to RS-232 interface cable • 20-pin standard JTAG connector to connect to ULINK emulator • Demonstration circuit • 32.768 kHz watch crystal to drive the PLL clock • ADR291 2.5 V external reference chip • Reset/Download/IRQ0 push-buttons • Power indicator/general-purpose LEDs • Access to all ADC inputs and DAC output from external header. All device ports are brought out to external header pins. • Surface-mount and through hole general-purpose prototype area • External memory and latch footprint Notes 1. This document refers to the MicroConverter ADuC7026 Eval Board, Rev. A1. 2. All references in this document to physical orientation of components on the board are made with respect to a component side view of the board with the prototype area appearing in the bottom of the board. 3. The board is laid out to minimize coupling between the analog and digital sections of the board. To this end, the ground plane is split with the analog section on the left- ADuC7026 Evaluation Board Reference Guide by Aude Richard hand side and a digital plane on the right-hand side of the board. The regulated 3.3 V power supply is routed directly to the digital section and is filtered before being routed into the analog section of the board. FEATURES Power Supply The user should connect the 9 V power supply via the 2.1 mm input power socket (J5). The input connector is configured as CENTER NEGATIVE, i.e., GND on the center pin and +9 V on the outer shield. This 9 V supply is regulated via a linear voltage regulator (U5). The 3.3 V regulator output is used to drive the digital side of the board directly. The 3.3 V supply is also filtered and then used to supply the analog side of the board. When on, the red LED (D3) indicates that a valid 3.3 V supply is being driven from the regulator circuit. All active components are decoupled with 0.1 F at device supply pins to ground. RS-232 Interface The ADuC7026 (U1) P1.1 and P1.0 lines are connected to the RS-232 interface cable via connector (J1). The interface cable generates the required level shifting to allow direct connection to a PC serial port. Ensure that the cable supplied is connected to the board correctly, i.e., DVDD is connected to DVDD and DGND is connected to DGND. Emulation Interface Nonintrusive emulation and download are possible on the ADuC7026 via JTAG by connecting the ULINK emulator to the J4 connector. Crystal Circuit The board is fitted with a 32.768 kHz crystal, from which the on-chip PLL circuit can generate a 45 MHz clock. External Reference (ADR291) The external 2.5 V reference chip (U2) has two functions. It is provided on the evaluation board to demonstrate the external reference option of the ADuC7026, but its main purpose is to generate the VOCM voltage of the differential amplifier, if required. Reset/Download/IRQ0 Push-buttons A RESET push-button is provided to allow the user to manually reset the part. When inserted, the RESET pin of the ADuC7026 will be pulled to DGND. Because the REV. 0

RESET pin on the ADuC7026 is Schmitt-triggered inter-

nally there is no need to use an external Schmitt trigger on this pin. When inserted the IRQ0 push-button switch drives P0.4/IRQ0 high. This can be used to initiate an external interrupt 0. To enter serial download mode the user must pull the P0.0/BM pin low while reset is toggled. On the evalua- tion board, serial download mode can be easily initiated by holding down the serial download push-button (S2) while inserting and releasing the reset button (S3) as illustrated in Figure 1. �� Figure 1. Entering Serial Download Mode on the Evaluation Board Power Indicator/General-Purpose LEDs A red power LED (D3) is used to indicate that a sufficient supply is available on the board. A general-purpose LED (D2) is directly connected to P4.2 of the ADuC7026. When P4.2 is cleared the LED will be turned on, and when P4.2 is set, the LED will be turned off. Analog I/O Connections All analog I/O are brought out on header J3. ADC0 and ADC1 are buffered using an AD8606 to evaluate single-ended and pseudo differential mode. A potentiometer can be connected to ADC0 buffered. ADC3 and ADC4 can be buffered with a single-ended to differential op amp on board, the AD8132, used to evalu- ate the ADC in fully differential mode. ADC2 and ADC5 to ADC11 are not buffered. Be sure to follow the data sheet recommendation when connecting signals to these inputs. DAC1 can be used to control the brightness of the green LED D1, when connected via the S1 switch. General-Purpose Prototype Area General-purpose prototype areas are provided at the bottom of the evaluation board for adding external components as required in the user’s application. As can be seen from the layout AVDD, AGND, VDDIO, and DGND tracks are provided in this prototype area. External Memory and Latch Footprint Footprint for a 32 kB  16 static RAM (CY7C1020CV33) and 16-bit latch is also on board. See External Memory Interface section. DIP SWITCH LINK OPTIONS S1-1 VREF Function: Connects the output of the 2.5 V external refer- ence (ADR291) to the VREF pin (Pin 55) of the ADuC7026. Use: Slide S1-1 to the on position to connect the external reference to the ADuC7026. Slide S1-1 to the off position to use the internal 2.5 V reference or a different external reference on VREF pin of J3 header. S1-2 VOCM Function: Connects 1.67 V to the VOCM pin of the AD8132. No extra dc voltage is required on the board to use the ADC in differential mode. Use: Slide S1-2 to the on position to connect VOCM of the differential amplifier to 1.67 V, divided output of the ADR291 reference. Slide S1-2 to the off position to use a different voltage for VOCM by connecting a dc voltage to the VOCM pin of J3 header. Note that VOCM value is dependent on reference value as shown in Table 1. Table 1. VOCM Range VREF VOCM min VOCM max 2.5 V 1.25 V 2.05 V 2.048 V 1.024 V 2.276 V 1.25 V 0.75 V 2.55 V S1-3 POT Function: Connects the potentiometer output to ADC0. This input is buffered by an AD8606. This is for demonstration purposes. Use: Slide S1-3 to the on position to connect the potentiometer to the op amp of ADC0 input channel. Slide S1-3 to the off position to use ADC0 input on J3 header. S1-4 ADC3 Function: Brings out ADC3 (Pin 64) on J3 header. Use: Slide S1-6 to the on position to connect directly ADC3 of J3 header to ADC3 pin (Pin 64) of the ADuC7026. Slide S1-6 to the off position to disconnect ADC3 of J3 header from ADC3 pin (Pin 64) of the ADuC7026. REV. 0

Function: Connects –OUT of the single-ended to

differential op amp (AD8132) to ADC3. S1- 5 and S1-6 must be used together, when VIN– is in the on position, VIN+ must also be in the on position to use the differential op amp on channel ADC3 and ADC4. Use: Slide S1-5 to the on position to connect –OUT of the AD8132 to ADC3. Slide S1-5 to the off position to use ADC3 without the AD8132. S1-6 VIN+ Function: Connects +OUT of the single-ended to differ- ential op amp (AD8132) to ADC4. When VIN+ is in the on position, VIN– must also be in the on position to use the differential op amp on channel ADC3 and ADC4. Use: Slide S1-6 to the on position to connect +OUT of AD8132 to ADC4. Slide S1-6 to the off position to use ADC4 without the AD8132. S1-7 ADC4 Use: Slide S1-6 to the on position to connect directly ADC4 of J3 header to ADC4 pin (Pin 1) of the ADuC7026. Slide S1-6 to the off position to disconnect ADC4 of J3 header from ADC4 pin (Pin 1) of the ADuC7026. S1-8 LED Function: Connects the DAC1 output to the green LED of the demo circuit, D1. Use: Slide S1-7 to the on position to connect the DAC1 output to D1. Slide S1-7 to the off position to use DAC1 output on J3 header. EXTERNAL CONNECTORS J3 Analog I/O Connector The analog I/O connector J3 provides external connections for all ADC inputs, reference inputs, and DAC outputs. The pinout of the connector is shown in Table 2. Table 2. Pin Functions for Analog I/O Connector J3 Pin Number Pin Description J3-1 AVDD J3-2 AGND J3-3 VREF J3-4 DACREF J3-5 ADC0 J3-6 ADC1 J3-7 ADC2 J3-8 ADC3 J3-9 ADC4 J3-10 ADC5 J3-11 ADC6 J3-12 ADC7 J3-13 ADC8 J3-14 ADC9 J3-15 ADC10 J3-16 ADC11 J3-17 VDIFF J3-18 VOCM J3-19 DAC0 J3-20 DAC1 J3-21 DAC2 J3-22 DAC3 J3-23 ADCNEG J3-24 AGND J5 Power Supply Connections J5 allows for the connection between the evaluation board and the 9 V power supply provided in the ADuC7026 Development System. J4 Emulation Connector J4 provides a connection of the evaluation board to the PC via a USB cable and ULINK provided in the ADuC7026 Development System. J1 Serial Interface Connector J1 provides a simple connection of the evaluation board to the PC via a PC serial port cable provided with the ADuC7026 Development System. J2 Digital I/O Connector The digital I/O connector J2 provides external connec- tions for all GPIOs. The pinout of the connector is shown in Table 3, with details of the pin functions. REV. 0

Table 3. Pin Functions for Digital I/O Connector J2

Pin Number Pin Description J2-1 DGND J2-2 P4.5 AD13/PLAO[13] J2-3 P4.4 AD12/PLAO[12] J2-4 P4.3 AD11/PLAO[11] J2-5 P4.2 AD10/PLAO[10] J2-6 P1.0 SIN/SCL0/PLAI[0] J2-7 P1.1 SOUT/SDA0/PLAI[1] J2-8 P1.2 RTS/SCL1/PLAI[2] J2-9 P1.3 CTS/SDA1/PLAI[3] J2-10 P1.4 RI/CLK/PLAI[4] J2-11 P1.5 DCD/MISO/PLAI[5] J2-12 P4.1 AD9/PLAO[9] J2-13 P4.0 AD8/PLAO[8] J2-14 P1.6 DSR/MOSI/PLAI[6] J2-15 P1.7 DTR/CSL/PLAO[0] J2-16 P2.2 RS/PLAO[7] J2-17 P2.1 WS/PLAO[6] J2-18 P2.7 PWM1L/MS3 J2-19 P3.7 PWMSYNC/AD7/PLAI[15] J2-20 P3.6 PWMTRIP/AD6/PLAI[14] J2-21 P0.7 ECLK/SIN/PLAO[4] Pin Number Pin Description J2-22 P2.0 CONV/SOUT/PLAO[5] J2-23 P0.5 IRQ1/ADCBUSY/MS0/PLAO[2] J2-24 P0.4 IRQ0/PWMTRIP/MS1/PLAO[1] J2-25 P3.5 PWM2L/AD5/PLAI[13] J2-26 P3.4 PWM2H/AD4/PLAI[12] J2-27 P2.6 PWM1H/MS2 J2-28 P2.5 PWM0L/MS1 J2-29 P0.3 TRST/A[16]/ADCBUSY J2-30 P2.4 PWM0H/MS0 J2-31 P3.3 PWM1L/AD3/PLAI[11] J2-32 P3.2 PWM1H/AD2/PLAI[10] J2-33 P3.1 PWM0L/AD1/PLAI[9] J2-34 P3.0 PWM0H/AD0/PLAI[8] J2-35 P0.2 TDO/PWM2L/BEL J2-36 P0.6 T2CLK/MRST/AE/PLAO[3] J2-37 P0.0 CMPOUT/MS2/PLAI[7] J2-38 P4.7 AD15/PLAO[15] J2-39 P4.6 AD14/PLAO[14] J2-40 P2.3 AE J2-41 P0.1 TDI/PWM2H/BEH J2-42 DGND REV. 0

EXTERNAL MEMORY INTERFACE

A footprint for a 32 kB  16 SRAM is provided on board as well as a footprint for a 16-bit D-latch since address and data are multiplexed on the external bus. The memory footprint is for a CY7C1020CV33 and the latch footprint is for a 74LVT16373AGG. Note that you can use different versions of the CY7C1020CV33 memory, with different access times. Wait states can be added in the XMxPAR register to allow interfacing a slower memory if required. Connections Controls: RS, WS, and AE are the minimum control signals of any memory interface. MSO, memory select is connected to CE to enable the memory only when necessary. BHE and BLE allow the user to select the high or low byte of the 16-bit memory. Data: 16 bits of data AD[15-0] are directly con- nected from the ADuC7026 to the memory. Addresses: To address 32 kB, only a 14-bit address is required. There are two ways of addressing a 16-bit memory: 1. Connecting AD[14-0] to A[14-0]. To enable it requires dynamic addressing (set Bit 11 in XMxPAR) to address in 16-bit mode instead of 8-bit mode. 2. Connecting AD[15-1] of the ADuC702x to A[14-0] of the memory, without using dynamic addressing. On the evaluation board, AD[14-0] are connected. In software, dynamic addressing must be enabled. �� Figure 2. External Memory Connections REV. 0

POTENTIOMETER DEMONSTRATION CIRCUIT

�� Figure 3. Circuit Diagram of the RTD Circuit Using the sample code in \adc\pot.c, the variation in the potentiometer resistance can be seen on the output LED. Note that the internal and external references are 2.5 V, which gives an ADC input range of 0 V to 2.5 V in single- ended mode. The potentiometer can give a voltage between 0 V and AVDD = 3.3 V. REV. 0

Analog Devices ADuC7026 Reference Manual

Specifications

Download

Read Online

Text of the manual

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com

RESET pin on the ADuC7026 is Schmitt-triggered inter-

Function: Connects –OUT of the single-ended to

Table 3. Pin Functions for Digital I/O Connector J2

EXTERNAL MEMORY INTERFACE

POTENTIOMETER DEMONSTRATION CIRCUIT

��

Table 4. ADuC7026 Evaluation Board Parts List

Table 4. ADuC7026 Evaluation Board Parts List (Continued)

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

Other Motherboard Manuals

Analog Devices ADuC7026 Reference Manual

Specifications

Download

Read Online

Text of the manual

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com

RESET pin on the ADuC7026 is Schmitt-triggered inter-

Function: Connects –OUT of the single-ended to

Table 3. Pin Functions for Digital I/O Connector J2

EXTERNAL MEMORY INTERFACE

POTENTIOMETER DEMONSTRATION CIRCUIT

�� ��� ���

Table 4. ADuC7026 Evaluation Board Parts List

Table 4. ADuC7026 Evaluation Board Parts List (Continued)

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

Other Motherboard Manuals

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